diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-05 03:22:39 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-05 03:22:39 -0400 |
| commit | 80cd107e51ceb5aac262ec7dd82870e48d345b43 (patch) | |
| tree | 4bb545ae29522161963a8028f34ca850c98a3403 /tests/long | |
| parent | 2847d5f5177304236dcdbab112a0369f0bd96aea (diff) | |
| download | gem5-80cd107e51ceb5aac262ec7dd82870e48d345b43.tar.xz | |
stats: Update stats to reflect cache changes
Diffstat (limited to 'tests/long')
57 files changed, 18564 insertions, 18099 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 421497f85..9af3017c0 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.887184 # Nu sim_ticks 1887184463000 # Number of ticks simulated final_tick 1887184463000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 275099 # Simulator instruction rate (inst/s) -host_op_rate 275099 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9249537203 # Simulator tick rate (ticks/s) -host_mem_usage 373576 # Number of bytes of host memory used -host_seconds 204.03 # Real time elapsed on the host +host_inst_rate 272052 # Simulator instruction rate (inst/s) +host_op_rate 272052 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9147074399 # Simulator tick rate (ticks/s) +host_mem_usage 373996 # Number of bytes of host memory used +host_seconds 206.32 # Real time elapsed on the host sim_insts 56128524 # Number of instructions simulated sim_ops 56128524 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -46,12 +46,12 @@ system.physmem.readBursts 404899 # Nu system.physmem.writeBursts 159652 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 25907328 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue -system.physmem.bytesWritten 8556800 # Total number of bytes written to DRAM +system.physmem.bytesWritten 8555840 # Total number of bytes written to DRAM system.physmem.bytesReadSys 25913536 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 10217728 # Total written bytes from the system interface side system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 25922 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 157 # Number of requests that are neither read nor write +system.physmem.mergedWrBursts 25937 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 159 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25492 # Per bank write bursts system.physmem.perBankRdBursts::1 25732 # Per bank write bursts system.physmem.perBankRdBursts::2 25844 # Per bank write bursts @@ -70,22 +70,22 @@ system.physmem.perBankRdBursts::14 25834 # Pe system.physmem.perBankRdBursts::15 25739 # Per bank write bursts system.physmem.perBankWrBursts::0 8904 # Per bank write bursts system.physmem.perBankWrBursts::1 8550 # Per bank write bursts -system.physmem.perBankWrBursts::2 9125 # Per bank write bursts -system.physmem.perBankWrBursts::3 8822 # Per bank write bursts +system.physmem.perBankWrBursts::2 9134 # Per bank write bursts +system.physmem.perBankWrBursts::3 8817 # Per bank write bursts system.physmem.perBankWrBursts::4 8179 # Per bank write bursts system.physmem.perBankWrBursts::5 8016 # Per bank write bursts system.physmem.perBankWrBursts::6 7555 # Per bank write bursts -system.physmem.perBankWrBursts::7 7379 # Per bank write bursts +system.physmem.perBankWrBursts::7 7380 # Per bank write bursts system.physmem.perBankWrBursts::8 8271 # Per bank write bursts system.physmem.perBankWrBursts::9 7751 # Per bank write bursts system.physmem.perBankWrBursts::10 8147 # Per bank write bursts -system.physmem.perBankWrBursts::11 7873 # Per bank write bursts -system.physmem.perBankWrBursts::12 8188 # Per bank write bursts -system.physmem.perBankWrBursts::13 9058 # Per bank write bursts +system.physmem.perBankWrBursts::11 7871 # Per bank write bursts +system.physmem.perBankWrBursts::12 8181 # Per bank write bursts +system.physmem.perBankWrBursts::13 9046 # Per bank write bursts system.physmem.perBankWrBursts::14 9003 # Per bank write bursts -system.physmem.perBankWrBursts::15 8879 # Per bank write bursts +system.physmem.perBankWrBursts::15 8880 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 49 # Number of times write queue was full causing retry +system.physmem.numWrRetry 48 # Number of times write queue was full causing retry system.physmem.totGap 1887175688500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) @@ -149,66 +149,66 @@ system.physmem.wrQLenPdf::12 1 # Wh system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 1116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 764 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 161 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 54 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 64790 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 531.935916 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 325.040765 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.485108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 531.921099 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 325.032687 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.479352 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 14695 22.68% 22.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10955 16.91% 39.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10956 16.91% 39.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 5460 8.43% 48.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3097 4.78% 52.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2483 3.83% 56.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1877 2.90% 59.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1493 2.30% 61.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1431 2.21% 64.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3096 4.78% 52.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2482 3.83% 56.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1882 2.90% 59.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1491 2.30% 61.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1429 2.21% 64.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 23299 35.96% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 64790 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4900 # Reads before turning the bus around for writes @@ -220,36 +220,36 @@ system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4900 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4900 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.285714 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.337905 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 63.692079 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.282653 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.334547 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 63.863816 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::0-31 4662 95.14% 95.14% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-63 56 1.14% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-95 11 0.22% 96.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-127 6 0.12% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-159 26 0.53% 97.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-191 25 0.51% 97.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-223 16 0.33% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-255 2 0.04% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-287 6 0.12% 98.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 12 0.24% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 6 0.12% 96.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 26 0.53% 97.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 25 0.51% 97.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 16 0.33% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-255 3 0.06% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 4 0.08% 98.16% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::288-319 8 0.16% 98.33% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::320-351 21 0.43% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-383 21 0.43% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-415 2 0.04% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-479 6 0.12% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-511 7 0.14% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-543 9 0.18% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-575 5 0.10% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-383 20 0.41% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-415 2 0.04% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-479 6 0.12% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-511 7 0.14% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-543 9 0.18% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-575 6 0.12% 99.78% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::672-703 3 0.06% 99.84% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::704-735 7 0.14% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::1088-1119 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4900 # Writes before turning the bus around for reads -system.physmem.totQLat 2145870750 # Total ticks spent queuing -system.physmem.totMemAccLat 9735908250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2145936500 # Total ticks spent queuing +system.physmem.totMemAccLat 9735974000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2024010000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5301.04 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5301.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24051.04 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24051.20 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.53 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s @@ -261,46 +261,46 @@ system.physmem.busUtilWrite 0.04 # Da system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 25.13 # Average write queue length when enqueuing system.physmem.readRowHits 363622 # Number of row buffer hits during reads -system.physmem.writeRowHits 110090 # Number of row buffer hits during writes +system.physmem.writeRowHits 110075 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads system.physmem.writeRowHitRate 82.32 # Row buffer hit rate for writes system.physmem.avgGap 3342790.44 # Average gap between requests system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 238971600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 130391250 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 238979160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 130395375 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 1577557800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 431114400 # Energy for write commands per rank (pJ) +system.physmem_0.writeEnergy 431146800 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 60578040195 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1079167578750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1265384866875 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.517315 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1795079554966 # Time in different power states +system.physmem_0.actBackEnergy 60577818750 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1079167773000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1265384883765 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.517324 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1795079851716 # Time in different power states system.physmem_0.memoryStateTime::REF 63016980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 29080496284 # Time in different power states +system.physmem_0.memoryStateTime::ACT 29080199534 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 250840800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136867500 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 250833240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136863375 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1579897800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 435261600 # Energy for write commands per rank (pJ) +system.physmem_1.writeEnergy 435132000 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61601133195 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1078270137000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1265535350775 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.597050 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1793586337716 # Time in different power states +system.physmem_1.actBackEnergy 61600331205 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1078270840500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1265535111000 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.596923 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1793587329216 # Time in different power states system.physmem_1.memoryStateTime::REF 63016980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30573727284 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30572735784 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 15007831 # Number of BP lookups +system.cpu.branchPred.lookups 15007833 # Number of BP lookups system.cpu.branchPred.condPredicted 13016266 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 375462 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9968114 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 9968116 # Number of BTB lookups system.cpu.branchPred.BTBHits 5203851 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 52.204971 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 52.204960 # BTB Hit Percentage system.cpu.branchPred.usedRAS 809053 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 32834 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -308,15 +308,15 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9242509 # DTB read hits +system.cpu.dtb.read_hits 9242504 # DTB read hits system.cpu.dtb.read_misses 17824 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations system.cpu.dtb.read_accesses 766347 # DTB read accesses -system.cpu.dtb.write_hits 6385998 # DTB write hits +system.cpu.dtb.write_hits 6386002 # DTB write hits system.cpu.dtb.write_misses 2322 # DTB write misses system.cpu.dtb.write_acv 159 # DTB write access violations system.cpu.dtb.write_accesses 298454 # DTB write accesses -system.cpu.dtb.data_hits 15628507 # DTB hits +system.cpu.dtb.data_hits 15628506 # DTB hits system.cpu.dtb.data_misses 20146 # DTB misses system.cpu.dtb.data_acv 370 # DTB access violations system.cpu.dtb.data_accesses 1064801 # DTB accesses @@ -336,15 +336,15 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 180833283 # number of cpu cycles simulated +system.cpu.numCycles 180833533 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 56128524 # Number of instructions committed system.cpu.committedOps 56128524 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2493053 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2493054 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 5493 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3593535643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.221772 # CPI: cycles per instruction +system.cpu.quiesceCycles 3593535393 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.221776 # CPI: cycles per instruction system.cpu.ipc 0.310388 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed @@ -359,10 +359,10 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.41% # nu system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73432 49.32% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 148896 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1834551091000 97.21% 97.21% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1834551053500 97.21% 97.21% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 80458000 0.00% 97.22% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 676198500 0.04% 97.25% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 51875728000 2.75% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 51875765500 2.75% 100.00% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::total 1887183475500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl @@ -427,17 +427,17 @@ system.cpu.kern.mode_switch_good::kernel 0.324536 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.079943 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.392949 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36591764000 1.94% 1.94% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4134630500 0.22% 2.16% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1846457071000 97.84% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 36591863000 1.94% 1.94% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4134622500 0.22% 2.16% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1846456980000 97.84% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4171 # number of times the context was actually changed -system.cpu.tickCycles 84552258 # Number of cycles that the object actually ticked -system.cpu.idleCycles 96281025 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1395325 # number of replacements +system.cpu.tickCycles 84552243 # Number of cycles that the object actually ticked +system.cpu.idleCycles 96281290 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1395323 # number of replacements system.cpu.dcache.tags.tagsinuse 511.981737 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13774282 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1395837 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.868116 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 13774277 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1395835 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.868127 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 90985250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.981737 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999964 # Average percentage of cache occupancy @@ -447,52 +447,52 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63660758 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63660758 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7815437 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7815437 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 63660728 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63660728 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7815432 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7815432 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 5576995 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 5576995 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 182818 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 182818 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 198995 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 198995 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13392432 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13392432 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13392432 # number of overall hits -system.cpu.dcache.overall_hits::total 13392432 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1201539 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201539 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 13392427 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13392427 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13392427 # number of overall hits +system.cpu.dcache.overall_hits::total 13392427 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1201537 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201537 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 573249 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 573249 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 17197 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17197 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1774788 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1774788 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1774788 # number of overall misses -system.cpu.dcache.overall_misses::total 1774788 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32999838250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32999838250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22461596052 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22461596052 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1774786 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1774786 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1774786 # number of overall misses +system.cpu.dcache.overall_misses::total 1774786 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32999736250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32999736250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22461890056 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22461890056 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 230671750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 230671750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 55461434302 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 55461434302 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 55461434302 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 55461434302 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9016976 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9016976 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 55461626306 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 55461626306 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 55461626306 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 55461626306 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9016969 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9016969 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6150244 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6150244 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200015 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 200015 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 198995 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 198995 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15167220 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15167220 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15167220 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15167220 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 15167213 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15167213 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15167213 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15167213 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133253 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.133253 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093208 # miss rate for WriteReq accesses @@ -503,16 +503,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.117015 system.cpu.dcache.demand_miss_rate::total 0.117015 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.117015 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.117015 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27464.641805 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27464.641805 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39182.965957 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39182.965957 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27464.602630 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27464.602630 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39183.478830 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39183.478830 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.487818 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.487818 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31249.610828 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31249.610828 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31249.610828 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31249.610828 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31249.754227 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31249.754227 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31249.754227 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31249.754227 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -533,32 +533,38 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 396104 system.cpu.dcache.demand_mshr_hits::total 396104 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 396104 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 396104 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074431 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074431 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074429 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074429 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304253 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 304253 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17194 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 17194 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378684 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378684 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378684 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378684 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29341442500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29341442500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11237495843 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11237495843 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1378682 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1378682 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1378682 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378682 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9619 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 9619 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16549 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 16549 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29341393000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29341393000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11237642841 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11237642841 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204691750 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204691750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40578938343 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 40578938343 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40578938343 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 40578938343 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40579035841 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 40579035841 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40579035841 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 40579035841 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1433304500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1433304500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2018255500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2018255500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3451560000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3451560000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2018260000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2018260000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3451564500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3451564500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119156 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119156 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049470 # mshr miss rate for WriteReq accesses @@ -569,22 +575,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090899 system.cpu.dcache.demand_mshr_miss_rate::total 0.090899 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090899 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.090899 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27308.819738 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27308.819738 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36934.708427 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36934.708427 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27308.824501 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27308.824501 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36935.191571 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36935.191571 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11904.835989 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.835989 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29433.095868 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29433.095868 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29433.095868 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29433.095868 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29433.209283 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29433.209283 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29433.209283 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29433.209283 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206826.046176 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206826.046176 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209820.147624 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209820.147624 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208566.348420 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208566.348420 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1459080 # number of replacements system.cpu.icache.tags.tagsinuse 509.440068 # Cycle average of tags in use @@ -614,12 +620,12 @@ system.cpu.icache.demand_misses::cpu.inst 1459769 # n system.cpu.icache.demand_misses::total 1459769 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1459769 # number of overall misses system.cpu.icache.overall_misses::total 1459769 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20155087658 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20155087658 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20155087658 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20155087658 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20155087658 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20155087658 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20155075408 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20155075408 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20155075408 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20155075408 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20155075408 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20155075408 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 20428067 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 20428067 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 20428067 # number of demand (read+write) accesses @@ -632,12 +638,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.071459 system.cpu.icache.demand_miss_rate::total 0.071459 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.071459 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.071459 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13807.039099 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13807.039099 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13807.039099 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13807.039099 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13807.039099 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13807.039099 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13807.030707 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13807.030707 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13807.030707 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13807.030707 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13807.030707 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13807.030707 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -652,33 +658,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1459769 system.cpu.icache.demand_mshr_misses::total 1459769 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1459769 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1459769 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17958185842 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17958185842 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17958185842 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17958185842 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17958185842 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17958185842 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17958174092 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17958174092 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17958174092 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17958174092 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17958174092 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17958174092 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071459 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071459 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071459 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.071459 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071459 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.071459 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12302.073713 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12302.073713 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12302.073713 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12302.073713 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12302.073713 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12302.073713 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12302.065664 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12302.065664 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12302.065664 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12302.065664 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12302.065664 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12302.065664 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 339394 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65314.689309 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2982707 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65314.689332 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2982705 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 404554 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.372828 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.372823 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 6335415750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 54416.774547 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5825.207065 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 54416.774568 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5825.207067 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 5072.707697 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.830334 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088886 # Average percentage of cache occupancy @@ -691,52 +697,52 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5172 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2816 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55531 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994263 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 30259084 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 30259084 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 30259068 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 30259068 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 1443260 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 819387 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2262647 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 819385 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2262645 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 838171 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 838171 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187599 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187599 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187597 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187597 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 1443260 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1006986 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2450246 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1006982 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2450242 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1443260 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1006986 # number of overall hits -system.cpu.l2cache.overall_hits::total 2450246 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1006982 # number of overall hits +system.cpu.l2cache.overall_hits::total 2450242 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 16444 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 272210 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 288654 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 20 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 20 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116658 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116658 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 116660 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116660 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 16444 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388868 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405312 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388870 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 405314 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 16444 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388868 # number of overall misses -system.cpu.l2cache.overall_misses::total 405312 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1322916250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19744352250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21067268500 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.data 388870 # number of overall misses +system.cpu.l2cache.overall_misses::total 405314 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1322904500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19744325250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21067229750 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 253997 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 253997 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8959337611 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8959337611 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1322916250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 28703689861 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30026606111 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1322916250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 28703689861 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30026606111 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8959505609 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8959505609 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1322904500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 28703830859 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30026735359 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1322904500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 28703830859 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30026735359 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1459704 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1091597 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2551301 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1091595 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2551299 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 838171 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 838171 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 24 # number of UpgradeReq accesses(hits+misses) @@ -744,37 +750,37 @@ system.cpu.l2cache.UpgradeReq_accesses::total 24 system.cpu.l2cache.ReadExReq_accesses::cpu.data 304257 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 304257 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 1459704 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1395854 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2855558 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1395852 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2855556 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 1459704 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1395854 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2855558 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1395852 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2855556 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.011265 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.249369 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.113140 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.833333 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.833333 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383419 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383419 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383426 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383426 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011265 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.278588 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.141938 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.278590 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.141939 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011265 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.278588 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.141938 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80449.784116 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72533.530179 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72984.502207 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.278590 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.141939 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80449.069569 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72533.430991 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72984.367963 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12699.850000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12699.850000 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76800.027525 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76800.027525 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80449.784116 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73813.453051 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74082.697061 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80449.784116 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73813.453051 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74082.697061 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76800.150943 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76800.150943 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80449.069569 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73813.436004 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74082.650387 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80449.069569 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73813.436004 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74082.650387 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -790,102 +796,108 @@ system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 272210 system.cpu.l2cache.ReadReq_mshr_misses::total 288654 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 20 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 20 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116658 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116658 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116660 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116660 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 16444 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388868 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 405312 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388870 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 405314 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 16444 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388868 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 405312 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1116961750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16343103250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17460065000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 388870 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 405314 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9619 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9619 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16549 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16549 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1116950000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16343076250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17460026250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 455517 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 455517 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7500878889 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7500878889 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1116961750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23843982139 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24960943889 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1116961750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23843982139 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24960943889 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7501019891 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7501019891 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1116950000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23844096141 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24961046141 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1116950000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23844096141 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24961046141 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336266500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336266500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893208000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893208000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229474500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229474500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893212500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893212500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229479000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229479000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.249369 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113140 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.833333 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.833333 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383419 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383419 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383426 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383426 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278588 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141938 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278590 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141939 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278588 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141938 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67925.185478 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60038.585100 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60487.867828 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278590 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141939 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67924.470932 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60038.485912 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60487.733584 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22775.850000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22775.850000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64298.024045 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64298.024045 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67925.185478 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61316.390495 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61584.517332 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67925.185478 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61316.390495 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61584.517332 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64298.130387 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64298.130387 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67924.470932 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61316.368300 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61584.465725 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67924.470932 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61316.368300 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61584.465725 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192823.448773 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192823.448773 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196820.095644 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196820.095644 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195146.474107 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195146.474107 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2558469 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2558436 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2558467 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2558434 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 838171 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41593 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41592 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 304257 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 304257 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2919473 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663181 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6582654 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663177 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6582650 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93421056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143030876 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 236451932 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41987 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3735584 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.011181 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.105146 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143030748 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 236451804 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 41986 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3752130 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.011131 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.104915 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3693818 98.88% 98.88% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41766 1.12% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3710365 98.89% 98.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41765 1.11% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3735584 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2698164499 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3752130 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2698163499 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2193277658 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2193277408 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2194690407 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2194687409 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -958,7 +970,7 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 242093194 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 242092694 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) @@ -990,8 +1002,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8777958811 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 8777958811 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8775999311 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8775999311 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles @@ -1014,17 +1026,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211252.378008 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 211252.378008 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211205.220230 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 211205.220230 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 73082 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 73059 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10004 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10002 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.305278 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.304439 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1040,8 +1052,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 173 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6617254811 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6617254811 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6615295311 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6615295311 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles @@ -1056,8 +1068,8 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159252.378008 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159252.378008 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159205.220230 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159205.220230 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency @@ -1070,18 +1082,18 @@ system.membus.trans_dist::WriteResp 9619 # Tr system.membus.trans_dist::Writeback 118100 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 159 # Transaction distribution -system.membus.trans_dist::UpgradeResp 159 # Transaction distribution +system.membus.trans_dist::UpgradeReq 161 # Transaction distribution +system.membus.trans_dist::UpgradeResp 161 # Transaction distribution system.membus.trans_dist::ReadExReq 116519 # Transaction distribution system.membus.trans_dist::ReadExResp 116519 # Transaction distribution system.membus.trans_dist::BadAddressError 16 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 886945 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 886949 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920075 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920079 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1044879 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1044883 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30814208 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30858524 # Cumulative packet size per connected master and slave (bytes) @@ -1089,24 +1101,24 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 36175580 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) -system.membus.snoop_fanout::samples 565206 # Request fanout histogram +system.membus.snoop_fanout::samples 581756 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 565206 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 581756 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 565206 # Request fanout histogram -system.membus.reqLayer0.occupancy 30238000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 581756 # Request fanout histogram +system.membus.reqLayer0.occupancy 30242500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1230315562 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1230317312 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160768093 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160772841 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 5574bfb2b..dad37454b 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.904438 # Nu sim_ticks 1904437574000 # Number of ticks simulated final_tick 1904437574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 143053 # Simulator instruction rate (inst/s) -host_op_rate 143053 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4814720142 # Simulator tick rate (ticks/s) -host_mem_usage 313028 # Number of bytes of host memory used -host_seconds 395.54 # Real time elapsed on the host +host_inst_rate 149880 # Simulator instruction rate (inst/s) +host_op_rate 149880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5044505517 # Simulator tick rate (ticks/s) +host_mem_usage 380636 # Number of bytes of host memory used +host_seconds 377.53 # Real time elapsed on the host sim_insts 56583768 # Number of instructions simulated sim_ops 56583768 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -780,6 +780,12 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 1280444 system.cpu0.dcache.demand_mshr_misses::total 1280444 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 1280444 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 1280444 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7039 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7039 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10032 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10032 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17071 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17071 # number of overall MSHR uncacheable misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28982142208 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28982142208 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11887451669 # number of WriteReq MSHR miss cycles @@ -822,12 +828,12 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31918.298557 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208007.813610 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208007.813610 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 212295.504187 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212295.504187 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 210527.531955 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 210527.531955 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 911417 # number of replacements system.cpu0.icache.tags.tagsinuse 509.418391 # Cycle average of tags in use @@ -1377,6 +1383,12 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 111358 system.cpu1.dcache.demand_mshr_misses::total 111358 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 111358 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 111358 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 158 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 158 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2893 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2893 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3051 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3051 # number of overall MSHR uncacheable misses system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 815361518 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_latency::total 815361518 # number of ReadReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1580599049 # number of WriteReq MSHR miss cycles @@ -1419,12 +1431,12 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21515.836913 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185632.911392 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185632.911392 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218110.266160 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 218110.266160 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 216428.384136 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 216428.384136 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 211356 # number of replacements system.cpu1.icache.tags.tagsinuse 472.195820 # Cycle average of tags in use @@ -1914,6 +1926,15 @@ system.l2c.overall_mshr_misses::cpu0.data 385876 # n system.l2c.overall_mshr_misses::cpu1.inst 1677 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 11762 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 413037 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7039 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 158 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 7197 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10032 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2893 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 12925 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17071 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3051 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 20122 # number of overall MSHR uncacheable misses system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 974652500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16545106250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122062750 # number of ReadReq MSHR miss cycles @@ -1995,15 +2016,15 @@ system.l2c.overall_avg_mshr_miss_latency::cpu0.data 65174.151113 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194007.671544 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171632.911392 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 193516.465194 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 199279.057018 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 204473.902523 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 200441.818182 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 197105.471267 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 202773.189118 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 197964.839479 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 296650 # Transaction distribution system.membus.trans_dist::ReadResp 296572 # Transaction distribution @@ -2032,17 +2053,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 37110021 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 10437 # Total snoops (count) -system.membus.snoop_fanout::samples 594010 # Request fanout histogram +system.membus.snoop_fanout::samples 614132 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 594010 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 614132 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 594010 # Request fanout histogram +system.membus.snoop_fanout::total 614132 # Request fanout histogram system.membus.reqLayer0.occupancy 36342500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 1279237311 # Layer occupancy (ticks) @@ -2076,19 +2097,19 @@ system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 135 system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10962579 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 213083141 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 72565 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3405571 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012264 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.110061 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 3425693 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.012192 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.109741 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3363806 98.77% 98.77% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41765 1.23% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3383928 98.78% 98.78% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41765 1.22% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3405571 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3425693 # Request fanout histogram system.toL2Bus.reqLayer0.occupancy 2521355915 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 80e8bf1d4..038a204b1 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.861006 # Nu sim_ticks 1861005569500 # Number of ticks simulated final_tick 1861005569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145313 # Simulator instruction rate (inst/s) -host_op_rate 145313 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5108711594 # Simulator tick rate (ticks/s) -host_mem_usage 309496 # Number of bytes of host memory used -host_seconds 364.28 # Real time elapsed on the host +host_inst_rate 152837 # Simulator instruction rate (inst/s) +host_op_rate 152837 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5373256396 # Simulator tick rate (ticks/s) +host_mem_usage 376300 # Number of bytes of host memory used +host_seconds 346.35 # Real time elapsed on the host sim_insts 52934565 # Number of instructions simulated sim_ops 52934565 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -51,7 +51,7 @@ system.physmem.bytesReadSys 25845824 # To system.physmem.bytesWrittenSys 10176576 # Total written bytes from the system interface side system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 25870 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 187 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 189 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25748 # Per bank write bursts system.physmem.perBankRdBursts::1 25559 # Per bank write bursts system.physmem.perBankRdBursts::2 25508 # Per bank write bursts @@ -261,8 +261,8 @@ system.physmem.wrPerTurnAround::688-703 2 0.04% 99.96% # Wr system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::720-735 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4847 # Writes before turning the bus around for reads -system.physmem.totQLat 3741903500 # Total ticks spent queuing -system.physmem.totMemAccLat 11312066000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3741904500 # Total ticks spent queuing +system.physmem.totMemAccLat 11312067000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2018710000 # Total ticks spent in databus transfers system.physmem.avgQLat 9268.06 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst @@ -399,15 +399,15 @@ system.cpu.decode.DecodedInsts 68295720 # Nu system.cpu.decode.SquashedInsts 134238 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 584855 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 24961940 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 51456366 # Number of cycles rename is blocking +system.cpu.rename.BlockCycles 51456440 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 20841952 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10391329 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8777565 # Number of cycles rename is unblocking +system.cpu.rename.RunCycles 10391328 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8777492 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 65857652 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 204161 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2078785 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 153522 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4578544 # Number of times rename has blocked due to SQ full +system.cpu.rename.SQFullEvents 4578470 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 43917673 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 79850033 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 79669145 # Number of integer rename lookups @@ -416,11 +416,11 @@ system.cpu.rename.CommittedMaps 38142428 # Nu system.cpu.rename.UndoneMaps 5775237 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 1690640 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 240974 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13460569 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 13460579 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 10430513 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 6961741 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1496363 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1107330 # Number of conflicting stores. +system.cpu.memDep0.conflictingStores 1107333 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 58622970 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 2136022 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 57539781 # Number of instructions issued @@ -432,13 +432,13 @@ system.cpu.iq.issued_per_cycle::samples 117014009 # Nu system.cpu.iq.issued_per_cycle::mean 0.491734 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.229968 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 93391036 79.81% 79.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10179391 8.70% 88.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 93391037 79.81% 79.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10179390 8.70% 88.51% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 4310458 3.68% 92.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3008330 2.57% 94.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3008329 2.57% 94.77% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 3082993 2.63% 97.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1515378 1.30% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1001152 0.86% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1515380 1.30% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1001151 0.86% 99.55% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 403458 0.34% 99.90% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 121813 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle @@ -476,7 +476,7 @@ system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.84% # at system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.84% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 537781 48.22% 67.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 367353 32.94% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 367354 32.94% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued @@ -515,15 +515,15 @@ system.cpu.iq.FU_type_0::IprAccess 948942 1.65% 100.00% # Ty system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 57539781 # Type of FU issued system.cpu.iq.rate 0.469435 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1115222 # FU busy when requested +system.cpu.iq.fu_busy_cnt 1115223 # FU busy when requested system.cpu.iq.fu_busy_rate 0.019382 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 232558247 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 232558248 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 68266797 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 55883323 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 713260 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 336497 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 329169 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58264568 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 58264569 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 383149 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 636979 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -534,18 +534,18 @@ system.cpu.iew.lsq.thread0.squashedStores 587155 # N system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 18243 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 442852 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 442853 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 584855 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 48003305 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1105801 # Number of cycles IEW is unblocking +system.cpu.iew.iewUnblockCycles 1105875 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 64465821 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 144286 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 10430513 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 6961741 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 1886655 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 45598 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 856378 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 856452 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 20302 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 189944 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 410798 # Number of branches that were predicted not taken incorrectly @@ -576,13 +576,13 @@ system.cpu.commit.committed_per_cycle::stdev 1.428292 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 95814381 82.90% 82.90% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 7848857 6.79% 89.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4272054 3.70% 93.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4272055 3.70% 93.39% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 2211253 1.91% 95.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1764307 1.53% 96.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1764306 1.53% 96.83% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 615369 0.53% 97.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 473670 0.41% 97.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 473669 0.41% 97.77% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 490996 0.42% 98.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2085445 1.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2085446 1.80% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle @@ -632,8 +632,8 @@ system.cpu.commit.op_class_0::MemWrite 6380538 11.37% 98.31% # Cl system.cpu.commit.op_class_0::IprAccess 948942 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 56123349 # Class of committed instruction -system.cpu.commit.bw_lim_events 2085445 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 177593269 # The number of ROB reads +system.cpu.commit.bw_lim_events 2085446 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 177593268 # The number of ROB reads system.cpu.rob.rob_writes 130137832 # The number of ROB writes system.cpu.timesIdled 572499 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 5558352 # Total number of cycles that the CPU has spent unscheduled due to idling @@ -692,16 +692,16 @@ system.cpu.dcache.overall_misses::cpu.data 3751566 # system.cpu.dcache.overall_misses::total 3751566 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 41841354315 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 41841354315 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 80890671511 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 80890671511 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 80890725520 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 80890725520 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376182249 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 376182249 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 455005 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 455005 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 122732025826 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 122732025826 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 122732025826 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 122732025826 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 122732079835 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 122732079835 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 122732079835 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 122732079835 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 9063784 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 9063784 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6144148 # number of WriteReq accesses(hits+misses) @@ -728,21 +728,21 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.246685 system.cpu.dcache.overall_miss_rate::total 0.246685 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23287.658005 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 23287.658005 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41379.519794 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41379.519794 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41379.547423 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41379.547423 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16166.670205 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16166.670205 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16852.037037 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16852.037037 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32714.878487 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32714.878487 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32714.878487 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32714.878487 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4477815 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32714.892883 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32714.892883 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32714.892883 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32714.892883 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4477894 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 2036 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 123579 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.234433 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.235072 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 88.521739 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -770,18 +770,24 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1386351 system.cpu.dcache.demand_mshr_misses::total 1386351 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1386351 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1386351 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9597 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 9597 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16527 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 16527 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29996933023 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 29996933023 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12482487876 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12482487876 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12482529124 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12482529124 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 214354001 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 214354001 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 414495 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 414495 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42479420899 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 42479420899 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42479420899 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 42479420899 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42479462147 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 42479462147 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42479462147 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 42479462147 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1433706500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1433706500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011966000 # number of WriteReq MSHR uncacheable cycles @@ -802,22 +808,22 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091160 system.cpu.dcache.overall_mshr_miss_rate::total 0.091160 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27380.506576 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27380.506576 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42925.682104 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42925.682104 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42925.823950 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42925.823950 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11910.540701 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11910.540701 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 15351.666667 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 15351.666667 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30641.173050 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30641.173050 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30641.173050 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30641.173050 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30641.202803 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30641.202803 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30641.202803 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30641.202803 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206884.054834 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206884.054834 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209645.305825 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209645.305825 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208487.475041 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208487.475041 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1032757 # number of replacements system.cpu.icache.tags.tagsinuse 509.197301 # Cycle average of tags in use @@ -941,14 +947,14 @@ system.cpu.l2cache.UpgradeReq_hits::cpu.data 31 system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 186339 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 186339 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 186337 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 186337 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 1018225 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1015065 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2033290 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1015063 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2033288 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1018225 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1015065 # number of overall hits -system.cpu.l2cache.overall_hits::total 2033290 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1015063 # number of overall hits +system.cpu.l2cache.overall_hits::total 2033288 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 15127 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 273931 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 289058 # number of ReadReq misses @@ -956,14 +962,14 @@ system.cpu.l2cache.UpgradeReq_misses::cpu.data 48 system.cpu.l2cache.UpgradeReq_misses::total 48 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 115274 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 115274 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 115276 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 115276 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 15127 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389205 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404332 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 389207 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404334 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 15127 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389205 # number of overall misses -system.cpu.l2cache.overall_misses::total 404332 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 389207 # number of overall misses +system.cpu.l2cache.overall_misses::total 404334 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1264836999 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20020012000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 21284848999 # number of ReadReq miss cycles @@ -971,14 +977,14 @@ system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 395995 system.cpu.l2cache.UpgradeReq_miss_latency::total 395995 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 62498 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 62498 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10271336364 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10271336364 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10271399612 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10271399612 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 1264836999 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 30291348364 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31556185363 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 30291411612 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31556248611 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 1264836999 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 30291348364 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31556185363 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 30291411612 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31556248611 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1033352 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1102657 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 2136009 # number of ReadReq accesses(hits+misses) @@ -1003,14 +1009,14 @@ system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.607595 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.607595 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.185185 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.185185 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382192 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.382192 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382198 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.382198 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014639 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.277158 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.165871 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.277160 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.165872 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014639 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.277158 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.165871 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.277160 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.165872 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83614.530244 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73084.141627 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 73635.218534 # average ReadReq miss latency @@ -1018,14 +1024,14 @@ system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8249.895833 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8249.895833 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 12499.600000 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 12499.600000 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89103.669206 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89103.669206 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89102.671953 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89102.671953 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83614.530244 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77828.774975 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78045.233528 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77828.537544 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78045.003910 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83614.530244 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77828.774975 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78045.233528 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77828.537544 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78045.003910 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1049,14 +1055,20 @@ system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 48 system.cpu.l2cache.UpgradeReq_mshr_misses::total 48 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115274 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115274 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115276 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115276 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 15126 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389205 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404331 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389207 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404333 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 15126 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389205 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404331 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389207 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404333 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9597 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9597 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16527 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16527 # number of overall MSHR uncacheable misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1075826749 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16607896000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17683722749 # number of ReadReq MSHR miss cycles @@ -1064,14 +1076,14 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1000544 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1000544 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 89005 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 89005 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8861608136 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8861608136 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8861643888 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8861643888 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1075826749 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25469504136 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26545330885 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25469539888 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26545366637 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1075826749 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25469504136 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26545330885 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25469539888 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26545366637 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336686500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336686500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1887182500 # number of WriteReq MSHR uncacheable cycles @@ -1085,14 +1097,14 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.607595 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.607595 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.185185 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.185185 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382192 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382192 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382198 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382198 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277158 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.165871 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277160 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.165872 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277158 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.165871 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277160 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.165872 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71124.338821 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60628.026766 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61177.285964 # average ReadReq mshr miss latency @@ -1100,20 +1112,20 @@ system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20844.666667 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20844.666667 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 17801 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17801 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76874.300675 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76874.300675 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76873.277074 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76873.277074 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65439.817412 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65652.475039 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65439.572998 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65652.238717 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65439.817412 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65652.475039 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65439.572998 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65652.238717 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192884.054834 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192884.054834 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196642.961342 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196642.961342 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195066.799782 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195066.799782 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 2143279 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2143168 # Transaction distribution @@ -1134,24 +1146,24 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143814956 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 209949484 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 42097 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3321757 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.012576 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.111435 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 3338284 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.012514 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.111162 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3279983 98.74% 98.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41774 1.26% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3296510 98.75% 98.75% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41774 1.25% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3321757 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3338284 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2495140999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1554402947 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2190379384 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2190379636 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1336,19 +1348,19 @@ system.membus.trans_dist::WriteResp 9597 # Tr system.membus.trans_dist::Writeback 117457 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 185 # Transaction distribution +system.membus.trans_dist::UpgradeReq 187 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.membus.trans_dist::UpgradeResp 190 # Transaction distribution +system.membus.trans_dist::UpgradeResp 192 # Transaction distribution system.membus.trans_dist::ReadExReq 115137 # Transaction distribution system.membus.trans_dist::ReadExResp 115137 # Transaction distribution system.membus.trans_dist::BadAddressError 94 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884248 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884252 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 188 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917490 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917494 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1042294 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1042298 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30705344 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30749484 # Cumulative packet size per connected master and slave (bytes) @@ -1356,24 +1368,24 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 36066540 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 435 # Total snoops (count) -system.membus.snoop_fanout::samples 563651 # Request fanout histogram +system.membus.snoop_fanout::samples 580180 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 563651 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 580180 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 563651 # Request fanout histogram +system.membus.snoop_fanout::total 580180 # Request fanout histogram system.membus.reqLayer0.occupancy 29181000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1226048062 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1226050062 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) system.membus.reqLayer2.occupancy 118000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2139454565 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2139458813 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 42497997 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 438fcc2e5..e143de192 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.841539 # Nu sim_ticks 1841538755500 # Number of ticks simulated final_tick 1841538755500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 221247 # Simulator instruction rate (inst/s) -host_op_rate 221247 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5777125497 # Simulator tick rate (ticks/s) -host_mem_usage 308008 # Number of bytes of host memory used -host_seconds 318.76 # Real time elapsed on the host +host_inst_rate 221997 # Simulator instruction rate (inst/s) +host_op_rate 221997 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5796715531 # Simulator tick rate (ticks/s) +host_mem_usage 374488 # Number of bytes of host memory used +host_seconds 317.69 # Real time elapsed on the host sim_insts 70525499 # Number of instructions simulated sim_ops 70525499 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -681,6 +681,15 @@ system.cpu0.dcache.demand_mshr_misses::total 506836 system.cpu0.dcache.overall_mshr_misses::cpu1.data 140963 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu2.data 365873 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 506836 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 1102 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1563 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2665 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 1382 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 2131 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3513 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2484 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3694 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6178 # number of overall MSHR uncacheable misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2114965000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4270329509 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6385294509 # number of ReadReq MSHR miss cycles @@ -741,15 +750,15 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21873.285524 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 26925.029901 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19926.957037 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21873.285524 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201881.578947 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 211980.806142 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 207804.690432 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 212719.971056 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 209384.795870 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 210696.840307 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 207911.634461 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 210483.216026 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 209449.255422 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 964809 # number of replacements system.cpu0.icache.tags.tagsinuse 510.919385 # Cycle average of tags in use @@ -1734,6 +1743,15 @@ system.l2c.overall_mshr_misses::cpu1.data 33612 # n system.l2c.overall_mshr_misses::cpu2.inst 4814 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.data 41256 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 81979 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 1102 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2.data 1563 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 2665 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 1382 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2.data 2131 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 3513 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 2484 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2.data 3694 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 6178 # number of overall MSHR uncacheable misses system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 158665250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.data 968947500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 340372000 # number of ReadReq MSHR miss cycles @@ -1809,15 +1827,15 @@ system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62698.783470 system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 70704.611550 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70320.426823 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 67183.160187 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187881.578947 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 197980.806142 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 193804.690432 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 199719.971056 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 196384.795870 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 197696.840307 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 194467.995169 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 197060.097455 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 196017.886047 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 295002 # Transaction distribution system.membus.trans_dist::ReadResp 294996 # Transaction distribution @@ -1846,17 +1864,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5323648 system.membus.pkt_size_system.iocache.mem_side::total 5323648 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 36001472 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 157 # Total snoops (count) -system.membus.snoop_fanout::samples 562136 # Request fanout histogram +system.membus.snoop_fanout::samples 579090 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 562136 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 579090 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 562136 # Request fanout histogram +system.membus.snoop_fanout::total 579090 # Request fanout histogram system.membus.reqLayer0.occupancy 11072500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 412860298 # Layer occupancy (ticks) @@ -1886,17 +1904,17 @@ system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 617 system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142733184 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 204523392 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 41934 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3236737 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012895 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112822 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 3253691 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012828 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112532 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3194999 98.71% 98.71% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 41738 1.29% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3211953 98.72% 98.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 41738 1.28% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3236737 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3253691 # Request fanout histogram system.toL2Bus.reqLayer0.occupancy 1080719000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 82500 # Layer occupancy (ticks) diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index c733baa00..bb4196597 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,160 +1,164 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.846097 # Number of seconds simulated -sim_ticks 2846097440000 # Number of ticks simulated -final_tick 2846097440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.846145 # Number of seconds simulated +sim_ticks 2846145040000 # Number of ticks simulated +final_tick 2846145040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101530 # Simulator instruction rate (inst/s) -host_op_rate 122947 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2278332577 # Simulator tick rate (ticks/s) -host_mem_usage 584920 # Number of bytes of host memory used -host_seconds 1249.20 # Real time elapsed on the host -sim_insts 126830911 # Number of instructions simulated -sim_ops 153585651 # Number of ops (including micro ops) simulated +host_inst_rate 162017 # Simulator instruction rate (inst/s) +host_op_rate 196203 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3671761280 # Simulator tick rate (ticks/s) +host_mem_usage 648900 # Number of bytes of host memory used +host_seconds 775.14 # Real time elapsed on the host +sim_insts 125586921 # Number of instructions simulated +sim_ops 152085297 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 9344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1671232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1335292 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8458880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 217280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 606496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 432576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 8320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1497984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1248876 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8305216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 2560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 388800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 684240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 582144 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12733532 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1671232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 217280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1888512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8840256 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory +system.physmem.bytes_read::total 12719228 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1497984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 388800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1886784 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8861888 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8858000 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 146 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26113 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21389 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 132170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9500 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6759 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8879452 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 130 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 23406 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20035 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 129769 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 40 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6075 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10711 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 9096 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 199510 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138129 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory +system.physmem.num_reads::total 199279 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138467 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142565 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3283 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 587201 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 469166 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2972098 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 76343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 213097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 151989 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 142858 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 526320 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 438796 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2918058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 136606 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 240409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 204538 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4474032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 587201 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 76343 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 663544 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3106097 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6220 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4468932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 526320 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 136606 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 662926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3113646 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6157 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3112332 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3106097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3283 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 587201 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 475386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2972098 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 76343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 213111 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 151989 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3119817 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3113646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 526320 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 444953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2918058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 136606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 240423 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 204538 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7586364 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 199510 # Number of read requests accepted -system.physmem.writeReqs 178789 # Number of write requests accepted -system.physmem.readBursts 199510 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 178789 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12761024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue -system.physmem.bytesWritten 9911424 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12733532 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11176336 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23895 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14191 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12377 # Per bank write bursts -system.physmem.perBankRdBursts::1 12507 # Per bank write bursts -system.physmem.perBankRdBursts::2 12921 # Per bank write bursts -system.physmem.perBankRdBursts::3 12944 # Per bank write bursts -system.physmem.perBankRdBursts::4 15059 # Per bank write bursts -system.physmem.perBankRdBursts::5 12345 # Per bank write bursts -system.physmem.perBankRdBursts::6 13163 # Per bank write bursts -system.physmem.perBankRdBursts::7 13279 # Per bank write bursts -system.physmem.perBankRdBursts::8 12255 # Per bank write bursts -system.physmem.perBankRdBursts::9 12304 # Per bank write bursts -system.physmem.perBankRdBursts::10 12058 # Per bank write bursts -system.physmem.perBankRdBursts::11 11233 # Per bank write bursts -system.physmem.perBankRdBursts::12 11543 # Per bank write bursts -system.physmem.perBankRdBursts::13 12301 # Per bank write bursts -system.physmem.perBankRdBursts::14 11677 # Per bank write bursts -system.physmem.perBankRdBursts::15 11425 # Per bank write bursts -system.physmem.perBankWrBursts::0 9896 # Per bank write bursts -system.physmem.perBankWrBursts::1 10159 # Per bank write bursts -system.physmem.perBankWrBursts::2 10174 # Per bank write bursts -system.physmem.perBankWrBursts::3 9995 # Per bank write bursts -system.physmem.perBankWrBursts::4 9156 # Per bank write bursts -system.physmem.perBankWrBursts::5 9568 # Per bank write bursts -system.physmem.perBankWrBursts::6 10283 # Per bank write bursts -system.physmem.perBankWrBursts::7 10373 # Per bank write bursts -system.physmem.perBankWrBursts::8 9590 # Per bank write bursts -system.physmem.perBankWrBursts::9 9571 # Per bank write bursts -system.physmem.perBankWrBursts::10 9719 # Per bank write bursts -system.physmem.perBankWrBursts::11 9542 # Per bank write bursts -system.physmem.perBankWrBursts::12 9254 # Per bank write bursts -system.physmem.perBankWrBursts::13 9350 # Per bank write bursts -system.physmem.perBankWrBursts::14 9412 # Per bank write bursts -system.physmem.perBankWrBursts::15 8824 # Per bank write bursts +system.physmem.bw_total::total 7588749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 199279 # Number of read requests accepted +system.physmem.writeReqs 179082 # Number of write requests accepted +system.physmem.readBursts 199279 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 179082 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12747712 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue +system.physmem.bytesWritten 9932032 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12719228 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11197788 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23866 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14978 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12467 # Per bank write bursts +system.physmem.perBankRdBursts::1 12549 # Per bank write bursts +system.physmem.perBankRdBursts::2 12590 # Per bank write bursts +system.physmem.perBankRdBursts::3 12626 # Per bank write bursts +system.physmem.perBankRdBursts::4 14976 # Per bank write bursts +system.physmem.perBankRdBursts::5 12125 # Per bank write bursts +system.physmem.perBankRdBursts::6 13379 # Per bank write bursts +system.physmem.perBankRdBursts::7 13505 # Per bank write bursts +system.physmem.perBankRdBursts::8 12274 # Per bank write bursts +system.physmem.perBankRdBursts::9 12440 # Per bank write bursts +system.physmem.perBankRdBursts::10 11813 # Per bank write bursts +system.physmem.perBankRdBursts::11 11246 # Per bank write bursts +system.physmem.perBankRdBursts::12 11354 # Per bank write bursts +system.physmem.perBankRdBursts::13 11924 # Per bank write bursts +system.physmem.perBankRdBursts::14 11833 # Per bank write bursts +system.physmem.perBankRdBursts::15 12082 # Per bank write bursts +system.physmem.perBankWrBursts::0 9603 # Per bank write bursts +system.physmem.perBankWrBursts::1 9871 # Per bank write bursts +system.physmem.perBankWrBursts::2 10084 # Per bank write bursts +system.physmem.perBankWrBursts::3 9904 # Per bank write bursts +system.physmem.perBankWrBursts::4 9385 # Per bank write bursts +system.physmem.perBankWrBursts::5 9666 # Per bank write bursts +system.physmem.perBankWrBursts::6 10609 # Per bank write bursts +system.physmem.perBankWrBursts::7 10482 # Per bank write bursts +system.physmem.perBankWrBursts::8 9764 # Per bank write bursts +system.physmem.perBankWrBursts::9 9386 # Per bank write bursts +system.physmem.perBankWrBursts::10 9428 # Per bank write bursts +system.physmem.perBankWrBursts::11 9248 # Per bank write bursts +system.physmem.perBankWrBursts::12 9294 # Per bank write bursts +system.physmem.perBankWrBursts::13 9689 # Per bank write bursts +system.physmem.perBankWrBursts::14 9592 # Per bank write bursts +system.physmem.perBankWrBursts::15 9183 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 38 # Number of times write queue was full causing retry -system.physmem.totGap 2846096933500 # Total gap between requests +system.physmem.numWrRetry 107 # Number of times write queue was full causing retry +system.physmem.totGap 2846144533500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 559 # Read request sizes (log2) +system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 198923 # Read request sizes (log2) +system.physmem.readPktSize::6 198700 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 4436 # Write request sizes (log2) +system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 174353 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 98295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 47940 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7837 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5336 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4702 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 765 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 174691 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 98289 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 47643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7835 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4763 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 766 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 286 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -184,160 +188,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1868 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90716 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 249.927069 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.222601 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 310.362875 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47359 52.21% 52.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17889 19.72% 71.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6289 6.93% 78.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3581 3.95% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2839 3.13% 85.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1568 1.73% 87.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 985 1.09% 88.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1019 1.12% 89.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9187 10.13% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90716 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6524 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.562538 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 556.578248 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6523 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 536 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 91273 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 248.481807 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 139.408554 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 309.811796 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47817 52.39% 52.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18099 19.83% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6231 6.83% 79.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3556 3.90% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2836 3.11% 86.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1554 1.70% 87.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 946 1.04% 88.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1020 1.12% 89.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9214 10.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 91273 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6574 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.298296 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 554.918828 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6572 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6524 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6524 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.737891 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.670801 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 40.283485 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 6175 94.65% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 90 1.38% 96.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 23 0.35% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 12 0.18% 96.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 26 0.40% 96.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 32 0.49% 97.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 26 0.40% 97.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 10 0.15% 98.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 20 0.31% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 5 0.08% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 20 0.31% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 23 0.35% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 7 0.11% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 7 0.11% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 1 0.02% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 3 0.05% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 2 0.03% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 5 0.08% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 4 0.06% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 4 0.06% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 14 0.21% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 2 0.03% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.05% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6524 # Writes before turning the bus around for reads -system.physmem.totQLat 5679096455 # Total ticks spent queuing -system.physmem.totMemAccLat 9417677705 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 996955000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28482.21 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6574 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6574 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.606328 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.587470 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 41.316435 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 6233 94.81% 94.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 88 1.34% 96.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 20 0.30% 96.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 23 0.35% 96.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 27 0.41% 97.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 26 0.40% 97.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 23 0.35% 97.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 19 0.29% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 11 0.17% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 6 0.09% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 17 0.26% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 19 0.29% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 5 0.08% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 3 0.05% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.03% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.03% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 3 0.05% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 5 0.08% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 6 0.09% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 6 0.09% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 9 0.14% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 2 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.05% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.03% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 3 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 2 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6574 # Writes before turning the bus around for reads +system.physmem.totQLat 5766362365 # Total ticks spent queuing +system.physmem.totMemAccLat 9501043615 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 995915000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28950.07 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47232.21 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 47700.07 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.48 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 3.49 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.47 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.18 # Average write queue length when enqueuing -system.physmem.readRowHits 166067 # Number of row buffer hits during reads -system.physmem.writeRowHits 97473 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.93 # Row buffer hit rate for writes -system.physmem.avgGap 7523405.91 # Average gap between requests -system.physmem.pageHitRate 74.39 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 359115120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 195945750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 815841000 # Energy for read commands per rank (pJ) +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.19 # Average write queue length when enqueuing +system.physmem.readRowHits 165729 # Number of row buffer hits during reads +system.physmem.writeRowHits 97368 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.20 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.73 # Row buffer hit rate for writes +system.physmem.avgGap 7522298.90 # Average gap between requests +system.physmem.pageHitRate 74.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 359432640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 196119000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 812892600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 515833920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185892919680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83249453610 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1634629745250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1905658854330 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.570214 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2719227401175 # Time in different power states -system.physmem_0.memoryStateTime::REF 95037280000 # Time in different power states +system.physmem_0.refreshEnergy 185895971040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83250586485 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634656782000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1905687617685 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.569329 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2719272584266 # Time in different power states +system.physmem_0.memoryStateTime::REF 95038840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31827968825 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31827943234 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 326697840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 178257750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 739401000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 487697760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185892919680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82096607520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1635641013750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1905362595300 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.466120 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2720918284391 # Time in different power states -system.physmem_1.memoryStateTime::REF 95037280000 # Time in different power states +system.physmem_1.actEnergy 330591240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 180382125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 740727000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 489784320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185895971040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82231883055 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1635550381500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1905419720280 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.475203 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2720770086744 # Time in different power states +system.physmem_1.memoryStateTime::REF 95038840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30141762609 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30336000256 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory @@ -363,15 +371,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 20630955 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13593557 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1040069 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 13124579 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 9315197 # Number of BTB hits +system.cpu0.branchPred.lookups 33812647 # Number of BP lookups +system.cpu0.branchPred.condPredicted 16331756 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1585484 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 19439562 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 14041669 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 70.975206 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3367508 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 204886 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.232435 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 10663467 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 792082 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -402,59 +410,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 69457 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 69457 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46535 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22922 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 69457 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 69457 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 69457 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6849 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 9469.922616 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 8283.824538 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6457.338241 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6642 96.98% 96.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 191 2.79% 99.77% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 7 0.10% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6849 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 65253 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 65253 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 42795 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22458 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 65253 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 65253 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 65253 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6648 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 9627.369284 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 8488.785540 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6159.752779 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6446 96.96% 96.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 188 2.83% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 4 0.06% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 7 0.11% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6648 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 328505000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 328505000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 328505000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5259 76.78% 76.78% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1590 23.22% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6849 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 69457 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5136 77.26% 77.26% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1512 22.74% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6648 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65253 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 69457 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6849 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65253 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6648 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6849 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 76306 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6648 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 71901 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17312533 # DTB read hits -system.cpu0.dtb.read_misses 63301 # DTB read misses -system.cpu0.dtb.write_hits 14536158 # DTB write hits -system.cpu0.dtb.write_misses 6156 # DTB write misses +system.cpu0.dtb.read_hits 22995822 # DTB read hits +system.cpu0.dtb.read_misses 59685 # DTB read misses +system.cpu0.dtb.write_hits 17147924 # DTB write hits +system.cpu0.dtb.write_misses 5568 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3522 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1254 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1942 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1156 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1615 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17375834 # DTB read accesses -system.cpu0.dtb.write_accesses 14542314 # DTB write accesses +system.cpu0.dtb.perms_faults 564 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 23055507 # DTB read accesses +system.cpu0.dtb.write_accesses 17153492 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31848691 # DTB hits -system.cpu0.dtb.misses 69457 # DTB misses -system.cpu0.dtb.accesses 31918148 # DTB accesses +system.cpu0.dtb.hits 40143746 # DTB hits +system.cpu0.dtb.misses 65253 # DTB misses +system.cpu0.dtb.accesses 40208999 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -484,38 +491,39 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3833 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3833 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3526 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3833 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3833 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3833 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2419 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 9485.117817 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 8378.584027 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 4911.792845 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 918 37.95% 37.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1466 60.60% 98.55% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 5 0.21% 98.76% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 29 1.20% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 3866 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3866 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 306 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3560 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3866 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3866 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3866 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2421 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 9944.030566 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 8839.286720 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5045.849413 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 802 33.13% 33.13% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1572 64.93% 98.06% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 10 0.41% 98.47% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.45% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2419 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2421 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 328041000 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 328041000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 328041000 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2119 87.60% 87.60% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 300 12.40% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2419 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2122 87.65% 87.65% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 299 12.35% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2421 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3833 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3833 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3866 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3866 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2419 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2419 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6252 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 38694088 # ITB inst hits -system.cpu0.itb.inst_misses 3833 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2421 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2421 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6287 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 68390761 # ITB inst hits +system.cpu0.itb.inst_misses 3866 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -524,131 +532,131 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2222 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2224 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7309 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7604 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 38697921 # ITB inst accesses -system.cpu0.itb.hits 38694088 # DTB hits -system.cpu0.itb.misses 3833 # DTB misses -system.cpu0.itb.accesses 38697921 # DTB accesses -system.cpu0.numCycles 164664294 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 68394627 # ITB inst accesses +system.cpu0.itb.hits 68390761 # DTB hits +system.cpu0.itb.misses 3866 # DTB misses +system.cpu0.itb.accesses 68394627 # DTB accesses +system.cpu0.numCycles 225488562 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 79545676 # Number of instructions committed -system.cpu0.committedOps 95726645 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 5037895 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1845 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5527555817 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.070060 # CPI: cycles per instruction -system.cpu0.ipc 0.483078 # IPC: instructions per cycle +system.cpu0.committedInsts 104715622 # Number of instructions committed +system.cpu0.committedOps 126599996 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 8092675 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 2098 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5466839701 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.153342 # CPI: cycles per instruction +system.cpu0.ipc 0.464394 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1847 # number of quiesce instructions executed -system.cpu0.tickCycles 127989646 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 36674648 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 713904 # number of replacements -system.cpu0.dcache.tags.tagsinuse 500.482804 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 30358451 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 714416 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 42.494080 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 348749500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.482804 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977505 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.977505 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 2103 # number of quiesce instructions executed +system.cpu0.tickCycles 187544415 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 37944147 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 678004 # number of replacements +system.cpu0.dcache.tags.tagsinuse 485.290770 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 38699274 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 678516 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 57.035168 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 346166500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.290770 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947834 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.947834 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63703980 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63703980 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15781686 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15781686 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 13418199 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 13418199 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 321521 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 321521 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365596 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365596 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361488 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361488 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 29199885 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 29199885 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 29521406 # number of overall hits -system.cpu0.dcache.overall_hits::total 29521406 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 463568 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 463568 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 577310 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 577310 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 136519 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 136519 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21073 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21073 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20283 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20283 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1040878 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1040878 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1177397 # number of overall misses -system.cpu0.dcache.overall_misses::total 1177397 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6134841542 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6134841542 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9140419725 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 9140419725 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 317623227 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 317623227 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 453858268 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 453858268 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 454500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 454500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 15275261267 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 15275261267 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 15275261267 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 15275261267 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16245254 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16245254 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 13995509 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 13995509 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 458040 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 458040 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386669 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386669 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381771 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381771 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 30240763 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 30240763 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30698803 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30698803 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028536 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.028536 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041250 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.041250 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.298050 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.298050 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054499 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054499 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053129 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053129 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034420 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.034420 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038353 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.038353 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13233.962530 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13233.962530 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15832.775675 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15832.775675 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15072.520619 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15072.520619 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22376.288912 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22376.288912 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 80249956 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 80249956 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 21509384 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 21509384 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 16060534 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 16060534 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307394 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 307394 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 357644 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 357644 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352742 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 352742 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 37569918 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 37569918 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 37877312 # number of overall hits +system.cpu0.dcache.overall_hits::total 37877312 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 441440 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 441440 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 555221 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 555221 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131923 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 131923 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20844 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20844 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21317 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 21317 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 996661 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 996661 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1128584 # number of overall misses +system.cpu0.dcache.overall_misses::total 1128584 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5848521453 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5848521453 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8885926805 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8885926805 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 320729731 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 320729731 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 481626159 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 481626159 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 602000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 602000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 14734448258 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 14734448258 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 14734448258 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 14734448258 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 21950824 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 21950824 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 16615755 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 16615755 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 439317 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 439317 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378488 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 378488 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 374059 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 374059 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 38566579 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 38566579 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 39005896 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 39005896 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.020110 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.020110 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033415 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.033415 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300291 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300291 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055072 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055072 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056988 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056988 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025843 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.025843 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028934 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.028934 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13248.734716 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13248.734716 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16004.306042 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 16004.306042 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15387.148868 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15387.148868 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22593.524370 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22593.524370 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14675.361826 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14675.361826 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12973.755893 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12973.755893 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14783.811404 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14783.811404 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13055.694798 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13055.694798 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -657,143 +665,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 513522 # number of writebacks -system.cpu0.dcache.writebacks::total 513522 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 72271 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 72271 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 253439 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 253439 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14656 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14656 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 325710 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 325710 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 325710 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 325710 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 391297 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 391297 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323871 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 323871 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 103394 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 103394 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6417 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6417 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20283 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20283 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 715168 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 715168 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 818562 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 818562 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4428376943 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4428376943 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4906976685 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4906976685 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1616801678 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1616801678 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 95832009 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95832009 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 422721232 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 422721232 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 436500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 436500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9335353628 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9335353628 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10952155306 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10952155306 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4276481750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4276481750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3261665000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3261665000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7538146750 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7538146750 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024087 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024087 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023141 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023141 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225731 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225731 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016596 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016596 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053129 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053129 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023649 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023649 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026664 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026664 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11317.175810 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11317.175810 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15151.022120 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15151.022120 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15637.287251 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15637.287251 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14934.082749 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14934.082749 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20841.159197 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20841.159197 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 490183 # number of writebacks +system.cpu0.dcache.writebacks::total 490183 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 69583 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 69583 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 243174 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 243174 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14803 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14803 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 312757 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 312757 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 312757 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 312757 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 371857 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 371857 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312047 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 312047 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99536 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 99536 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6041 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6041 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21317 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 21317 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 683904 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 683904 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 783440 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 783440 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29433 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29433 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26165 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26165 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 55598 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 55598 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4208861714 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4208861714 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4793451106 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4793451106 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1567109691 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1567109691 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 90045006 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90045006 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 448833841 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 448833841 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 579500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 579500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9002312820 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9002312820 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10569422511 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10569422511 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5627001499 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5627001499 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4261635500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4261635500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9888636999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9888636999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016940 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016940 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018780 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018780 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226570 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226570 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.015961 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.015961 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056988 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056988 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017733 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.017733 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020085 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.020085 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11318.495319 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11318.495319 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15361.311296 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15361.311296 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15744.149765 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15744.149765 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14905.645754 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14905.645754 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21055.206689 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21055.206689 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13053.371555 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13053.371555 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13379.750472 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13379.750472 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13163.123509 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13163.123509 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13491.042723 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13491.042723 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191180.018992 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191180.018992 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162875.425186 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162875.425186 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177859.581262 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177859.581262 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1969157 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.783924 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 36716761 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1969669 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 18.641082 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6455779250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.783924 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999578 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1884730 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.784347 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 66497574 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1885242 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 35.272699 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6453364250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.784347 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999579 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999579 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 79342579 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 79342579 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 36716761 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 36716761 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 36716761 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 36716761 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 36716761 # number of overall hits -system.cpu0.icache.overall_hits::total 36716761 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1969686 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1969686 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1969686 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1969686 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1969686 # number of overall misses -system.cpu0.icache.overall_misses::total 1969686 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18594001543 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18594001543 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18594001543 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18594001543 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18594001543 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18594001543 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 38686447 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 38686447 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 38686447 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 38686447 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 38686447 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 38686447 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050914 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050914 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050914 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050914 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050914 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050914 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9440.084127 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9440.084127 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9440.084127 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9440.084127 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9440.084127 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9440.084127 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 138650918 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 138650918 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 66497574 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 66497574 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 66497574 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 66497574 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 66497574 # number of overall hits +system.cpu0.icache.overall_hits::total 66497574 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1885257 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1885257 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1885257 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1885257 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1885257 # number of overall misses +system.cpu0.icache.overall_misses::total 1885257 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17590953808 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 17590953808 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 17590953808 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 17590953808 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 17590953808 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 17590953808 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 68382831 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 68382831 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 68382831 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 68382831 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 68382831 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 68382831 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.027569 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.027569 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.027569 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.027569 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.027569 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.027569 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9330.798829 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9330.798829 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9330.798829 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9330.798829 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9330.798829 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9330.798829 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -802,424 +816,436 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1969686 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1969686 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1969686 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1969686 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1969686 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1969686 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16614994457 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 16614994457 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16614994457 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 16614994457 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16614994457 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 16614994457 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 312159000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 312159000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 312159000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 312159000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050914 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050914 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050914 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.050914 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050914 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.050914 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8435.351857 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8435.351857 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8435.351857 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8435.351857 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8435.351857 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8435.351857 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1885257 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1885257 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1885257 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1885257 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1885257 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1885257 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3367 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 3367 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3367 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 3367 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 15697482196 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 15697482196 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 15697482196 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 15697482196 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 15697482196 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 15697482196 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 310652000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 310652000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 310652000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 310652000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027569 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027569 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027569 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.027569 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027569 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.027569 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8326.441539 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8326.441539 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8326.441539 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8326.441539 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8326.441539 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8326.441539 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92263.736264 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92263.736264 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1838342 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1838481 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 119 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1754468 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1754508 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 35 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 233119 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 300411 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16152.844833 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2914098 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 316661 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 9.202579 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2826281697500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6746.773874 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 56.784036 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.060323 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5767.067703 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1954.184068 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1627.974828 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.411790 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003466 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.351994 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.119274 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.099364 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.985891 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1019 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15218 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 323 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 417 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 268 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4291 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7836 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2805 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062195 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.928833 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 55319704 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 55319704 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 80908 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4161 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1898400 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 400606 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 2384075 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 513519 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 513519 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28702 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 28702 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1838 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 1838 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 223052 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 223052 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 80908 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4161 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1898400 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 623658 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 2607127 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 80908 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4161 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1898400 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 623658 # number of overall hits -system.cpu0.l2cache.overall_hits::total 2607127 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 892 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 113 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 71286 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 100496 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 172787 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26801 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26801 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18444 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18444 # number of SCUpgradeReq misses +system.cpu0.l2cache.prefetcher.pfSpanPage 221228 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 285273 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16083.611278 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2784455 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 301530 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 9.234421 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 8638.017947 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 60.519313 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.077213 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4655.233239 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1567.458030 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1162.305536 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.527223 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003694 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.284133 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.095670 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.070942 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.981666 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1030 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15217 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 322 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 428 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 273 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4109 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7718 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3035 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062866 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.928772 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 52971740 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 52971740 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77753 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4353 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1821437 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 376273 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 2279816 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 490181 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 490181 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28296 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 28296 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1798 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 1798 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 212312 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 212312 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77753 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4353 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1821437 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 588585 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 2492128 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77753 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4353 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1821437 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 588585 # number of overall hits +system.cpu0.l2cache.overall_hits::total 2492128 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 788 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 123 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 63820 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 101159 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 165890 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 28131 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 28131 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19518 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 19518 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45324 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 45324 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 892 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 113 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 71286 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 145820 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 218111 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 892 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 113 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 71286 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 145820 # number of overall misses -system.cpu0.l2cache.overall_misses::total 218111 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 31644248 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2618496 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 3281889931 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 3018329920 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 6334482595 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 498950782 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 498950782 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 372929796 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 372929796 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 423999 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 423999 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2226350926 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2226350926 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 31644248 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2618496 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3281889931 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 5244680846 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 8560833521 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 31644248 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2618496 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3281889931 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 5244680846 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 8560833521 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 81800 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4274 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1969686 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 501102 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 2556862 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 513519 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 513519 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55503 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 55503 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20282 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 20282 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43311 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 43311 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 788 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 123 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 63820 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 144470 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 209201 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 788 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 123 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 63820 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 144470 # number of overall misses +system.cpu0.l2cache.overall_misses::total 209201 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 27073496 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2775500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2907382734 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2926155686 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 5863387416 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 516960426 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 516960426 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 396286408 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 396286408 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 563999 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 563999 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2178252172 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 2178252172 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 27073496 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2775500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2907382734 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 5104407858 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 8041639588 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 27073496 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2775500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2907382734 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 5104407858 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 8041639588 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78541 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4476 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1885257 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 477432 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 2445706 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 490181 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 490181 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56427 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 56427 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21316 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 21316 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 268376 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 268376 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 81800 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4274 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1969686 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 769478 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 2825238 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 81800 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4274 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1969686 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 769478 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 2825238 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010905 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.026439 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.036192 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.200550 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.067578 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.482875 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.482875 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.909378 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.909378 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 255623 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 255623 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78541 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4476 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1885257 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 733055 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 2701329 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78541 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4476 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1885257 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 733055 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 2701329 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010033 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.027480 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.033852 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.211881 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.067829 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.498538 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.498538 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.915650 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.915650 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.168882 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.168882 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010905 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.026439 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.036192 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.189505 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.077201 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010905 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.026439 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.036192 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.189505 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.077201 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35475.614350 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23172.530973 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46038.351584 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 30034.328929 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36660.643422 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18616.871833 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18616.871833 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20219.572544 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20219.572544 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 423999 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 423999 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49120.795296 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49120.795296 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35475.614350 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23172.530973 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46038.351584 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35966.814196 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 39249.893499 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35475.614350 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23172.530973 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46038.351584 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35966.814196 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 39249.893499 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 13 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.169433 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.169433 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010033 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.027480 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.033852 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.197079 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.077444 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010033 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.027480 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.033852 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.197079 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.077444 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34357.228426 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22565.040650 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 45555.981416 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 28926.301031 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 35345.032347 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18376.894742 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18376.894742 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20303.638078 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20303.638078 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 563999 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 563999 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50293.278197 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50293.278197 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34357.228426 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22565.040650 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 45555.981416 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35331.957209 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 38439.776043 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34357.228426 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22565.040650 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 45555.981416 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35331.957209 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 38439.776043 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 200740 # number of writebacks -system.cpu0.l2cache.writebacks::total 200740 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 77 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 418 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 495 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3009 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 3009 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 77 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3427 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 3504 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 77 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3427 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 3504 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 892 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 113 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 71209 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 100078 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 172292 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 246246 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 246246 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26801 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26801 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18444 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18444 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.writebacks::writebacks 196267 # number of writebacks +system.cpu0.l2cache.writebacks::total 196267 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 50 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 373 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 423 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 2918 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 2918 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 50 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3291 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 3341 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 50 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3291 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 3341 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 788 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 123 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 63770 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 100786 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 165467 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 233242 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 233242 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 28131 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 28131 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19518 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19518 # number of SCUpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42315 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 42315 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 892 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 113 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 71209 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142393 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 214607 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 892 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 113 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 71209 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142393 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 246246 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 460853 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 25830750 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1882000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2808366569 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2341826150 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 5177905469 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14395344158 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 14395344158 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 540640009 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 540640009 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 270568831 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 270568831 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 345999 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 345999 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1615514460 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1615514460 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 25830750 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1882000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2808366569 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3957340610 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 6793419929 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 25830750 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1882000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2808366569 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3957340610 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14395344158 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 21188764087 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 283536500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4113067750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4396604250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3117904500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3117904500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 283536500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7230972250 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7514508750 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010905 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.026439 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.036152 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.199716 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.067384 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40393 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 40393 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 788 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 123 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 63770 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 141179 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 205860 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 788 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 123 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 63770 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 141179 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 233242 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 439102 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3367 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29433 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 32800 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 26165 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 26165 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3367 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 55598 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 58965 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 21938500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1976000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2484151766 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2249231613 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4757297879 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14218858632 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 14218858632 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 550871371 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 550871371 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 288938194 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 288938194 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 466499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 466499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1582913137 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1582913137 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 21938500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1976000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2484151766 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3832144750 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 6340211016 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 21938500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1976000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2484151766 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3832144750 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14218858632 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 20559069648 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 282144500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5391279750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5673424250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4065113000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4065113000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 282144500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9456392750 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9738537250 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010033 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.027480 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.033826 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.211100 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.067656 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.482875 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.482875 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.909378 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.909378 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.498538 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.498538 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.915650 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.915650 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.157671 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.157671 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010905 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.026439 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.036152 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.185051 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075961 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010905 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.026439 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036152 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.185051 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158018 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158018 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010033 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.027480 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.033826 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.192590 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.076207 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010033 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.027480 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.033826 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192590 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163120 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28958.239910 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16654.867257 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39438.365502 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23400.009493 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30053.081217 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58459.199979 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58459.199979 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20172.381963 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20172.381963 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14669.747940 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14669.747940 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 345999 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 345999 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38178.292804 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38178.292804 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28958.239910 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16654.867257 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39438.365502 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27791.679436 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31655.164692 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28958.239910 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16654.867257 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39438.365502 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27791.679436 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58459.199979 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45977.272768 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.162550 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27840.736041 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16065.040650 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 38954.865391 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22316.905255 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28750.735065 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60961.827767 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60961.827767 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19582.360065 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19582.360065 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14803.678348 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14803.678348 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 466499 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 466499 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39187.808209 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39187.808209 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27840.736041 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16065.040650 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38954.865391 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27143.872318 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30798.654503 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27840.736041 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16065.040650 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38954.865391 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27143.872318 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60961.827767 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46820.715114 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183171.261849 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172970.251524 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155364.532773 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155364.532773 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 170085.124465 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 165157.928432 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 2703667 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2643606 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19130 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19130 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 513519 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 304285 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 88848 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42983 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 113085 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 297594 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284124 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3946133 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2385460 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11633 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 174179 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6517405 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126276224 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86385120 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17096 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 327200 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 213005640 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 651207 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3963380 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 3.135029 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.341755 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 2622296 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2539595 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26165 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 490181 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 288086 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36278 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 93335 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43761 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 114801 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 284088 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 269989 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3777247 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2323391 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11902 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 166252 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6278792 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 120871872 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82524675 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17904 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 314164 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 203728615 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 661406 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3889209 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.165588 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.371711 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 3428208 86.50% 86.50% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 535172 13.50% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 3245202 83.44% 83.44% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 644007 16.56% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3963380 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2258643996 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 3889209 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2173439238 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 116241999 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 113551498 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2965047043 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2837827806 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1230256203 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1188833142 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7364491 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7429994 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 92392742 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 87720745 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 18842889 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6205402 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 629106 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 9920552 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 7177439 # Number of BTB hits +system.cpu1.branchPred.lookups 5430284 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3355584 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 331008 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 3397877 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 2268406 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 72.349190 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 8245946 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 413041 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 66.759509 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 972543 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 68492 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1249,60 +1275,60 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 26188 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 26188 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19132 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7056 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 26188 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 26188 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 26188 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2719 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 9780.159618 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 8826.212048 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5631.617808 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 919 33.80% 33.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1662 61.13% 94.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 68 2.50% 97.43% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 62 2.28% 99.71% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.11% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::90112-98303 2 0.07% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2719 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1631340764 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1631340764 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1631340764 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 2011 73.96% 73.96% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 708 26.04% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2719 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26188 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 30040 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 30040 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 22353 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7687 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 30040 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 30040 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 30040 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2702 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 9799.871947 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8761.915074 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6575.386381 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 913 33.79% 33.79% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1652 61.14% 94.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 67 2.48% 97.41% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.07% 99.48% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.56% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 5 0.19% 99.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 6 0.22% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2702 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1622459264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1622459264 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1622459264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 2019 74.72% 74.72% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 683 25.28% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2702 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30040 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26188 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2719 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30040 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2702 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2719 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 28907 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2702 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 32742 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 11112548 # DTB read hits -system.cpu1.dtb.read_misses 24192 # DTB read misses -system.cpu1.dtb.write_hits 6961122 # DTB write hits -system.cpu1.dtb.write_misses 1996 # DTB write misses +system.cpu1.dtb.read_hits 5155380 # DTB read hits +system.cpu1.dtb.read_misses 27847 # DTB read misses +system.cpu1.dtb.write_hits 4232538 # DTB write hits +system.cpu1.dtb.write_misses 2193 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2061 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 148 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 422 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2049 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 312 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 511 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 278 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 11136740 # DTB read accesses -system.cpu1.dtb.write_accesses 6963118 # DTB write accesses +system.cpu1.dtb.perms_faults 285 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 5183227 # DTB read accesses +system.cpu1.dtb.write_accesses 4234731 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 18073670 # DTB hits -system.cpu1.dtb.misses 26188 # DTB misses -system.cpu1.dtb.accesses 18099858 # DTB accesses +system.cpu1.dtb.hits 9387918 # DTB hits +system.cpu1.dtb.misses 30040 # DTB misses +system.cpu1.dtb.accesses 9417958 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1332,41 +1358,40 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 2252 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2252 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2071 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2252 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2252 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2252 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1119 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 9763.181412 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 8935.720507 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4528.605471 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 139 12.42% 12.42% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 170 15.19% 27.61% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 525 46.92% 74.53% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 253 22.61% 97.14% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 2 0.18% 97.32% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 1.88% 99.20% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 7 0.63% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1119 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1630766264 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1630766264 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1630766264 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 951 84.99% 84.99% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 168 15.01% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1119 # Table walker page sizes translated +system.cpu1.itb.walker.walks 2268 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2268 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 178 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2090 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2268 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2268 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2268 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1115 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 9869.507623 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 8954.185655 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5421.941384 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 302 27.09% 27.09% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 778 69.78% 96.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 3 0.27% 97.13% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 27 2.42% 99.55% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 1 0.09% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 3 0.27% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1115 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1621868264 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1621868264 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1621868264 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 950 85.20% 85.20% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 165 14.80% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1115 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2252 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2252 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2268 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2268 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1119 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1119 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3371 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 39781680 # ITB inst hits -system.cpu1.itb.inst_misses 2252 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1115 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1115 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3383 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 10199097 # ITB inst hits +system.cpu1.itb.inst_misses 2268 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1375,130 +1400,130 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1157 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1153 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1899 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1907 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 39783932 # ITB inst accesses -system.cpu1.itb.hits 39781680 # DTB hits -system.cpu1.itb.misses 2252 # DTB misses -system.cpu1.itb.accesses 39783932 # DTB accesses -system.cpu1.numCycles 114623988 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 10201365 # ITB inst accesses +system.cpu1.itb.hits 10199097 # DTB hits +system.cpu1.itb.misses 2268 # DTB misses +system.cpu1.itb.accesses 10201365 # DTB accesses +system.cpu1.numCycles 54377537 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 47285235 # Number of instructions committed -system.cpu1.committedOps 57859006 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 5005620 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2776 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5576963738 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.424097 # CPI: cycles per instruction -system.cpu1.ipc 0.412525 # IPC: instructions per cycle +system.cpu1.committedInsts 20871299 # Number of instructions committed +system.cpu1.committedOps 25485301 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 1815368 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2715 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5637293692 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.605374 # CPI: cycles per instruction +system.cpu1.ipc 0.383822 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2776 # number of quiesce instructions executed -system.cpu1.tickCycles 97884766 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 16739222 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 194739 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.948438 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 17633406 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 195100 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 90.381374 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 90504077500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.948438 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923727 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.923727 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 361 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 55 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.705078 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 36178407 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 36178407 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 10725883 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 10725883 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6668052 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6668052 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49984 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 49984 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80051 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 80051 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71499 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71499 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 17393935 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 17393935 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 17443919 # number of overall hits -system.cpu1.dcache.overall_hits::total 17443919 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 157968 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 157968 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 144726 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 144726 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30816 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30816 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16919 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16919 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23678 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23678 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 302694 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 302694 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 333510 # number of overall misses -system.cpu1.dcache.overall_misses::total 333510 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2315952429 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2315952429 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3861386324 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3861386324 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 316030492 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 316030492 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 557062155 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 557062155 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 124000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 124000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6177338753 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6177338753 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6177338753 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6177338753 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 10883851 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 10883851 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6812778 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6812778 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80800 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 80800 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96970 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96970 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95177 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95177 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 17696629 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 17696629 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 17777429 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 17777429 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.014514 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.014514 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021243 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.021243 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381386 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381386 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174477 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174477 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248779 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248779 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.017105 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.017105 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018760 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.018760 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14660.896061 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14660.896061 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26680.667772 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 26680.667772 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18679.029021 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18679.029021 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23526.571290 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23526.571290 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2716 # number of quiesce instructions executed +system.cpu1.tickCycles 38719894 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 15657643 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 231595 # number of replacements +system.cpu1.dcache.tags.tagsinuse 482.666397 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 8898721 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 231963 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 38.362674 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 90493998000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 482.666397 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.942708 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.942708 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 368 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 53 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.718750 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 18845353 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 18845353 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 4715534 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4715534 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3905905 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3905905 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65439 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 65439 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88128 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 88128 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80091 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 80091 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 8621439 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 8621439 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 8686878 # number of overall hits +system.cpu1.dcache.overall_hits::total 8686878 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 182965 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 182965 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 168408 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 168408 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35586 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 35586 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17713 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17713 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23494 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23494 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 351373 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 351373 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 386959 # number of overall misses +system.cpu1.dcache.overall_misses::total 386959 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2670008756 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2670008756 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4196907972 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4196907972 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325609985 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 325609985 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 550485715 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 550485715 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 359500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 359500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6866916728 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6866916728 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6866916728 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6866916728 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4898499 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4898499 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4074313 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4074313 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 101025 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 101025 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105841 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 105841 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 103585 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 103585 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 8972812 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 8972812 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 9073837 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 9073837 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037351 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.037351 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.041334 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.041334 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.352249 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.352249 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.167355 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.167355 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.226809 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.226809 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.039160 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.039160 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.042646 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.042646 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14593.002793 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14593.002793 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24921.072467 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 24921.072467 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18382.543047 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18382.543047 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23430.906402 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23430.906402 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20407.866535 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20407.866535 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18522.199493 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18522.199493 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19543.097301 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19543.097301 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17745.850925 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17745.850925 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1507,142 +1532,148 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 119475 # number of writebacks -system.cpu1.dcache.writebacks::total 119475 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16075 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 16075 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52265 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 52265 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12035 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12035 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 68340 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 68340 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 68340 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 68340 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 141893 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 141893 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92461 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 92461 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29935 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29935 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4884 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4884 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23678 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23678 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 234354 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 234354 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 264289 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 264289 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1871458583 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1871458583 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2300176813 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2300176813 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 487265761 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 487265761 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79878753 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 79878753 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 520207345 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 520207345 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 119500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 119500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4171635396 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4171635396 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4658901157 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4658901157 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2322015751 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2322015751 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1843986000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1843986000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4166001751 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4166001751 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013037 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013037 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013572 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013572 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.370483 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.370483 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050366 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050366 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248779 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248779 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013243 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.013243 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014867 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.014867 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13189.224155 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13189.224155 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24877.265150 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24877.265150 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16277.459863 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16277.459863 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16355.191032 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16355.191032 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21970.071163 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21970.071163 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 138038 # number of writebacks +system.cpu1.dcache.writebacks::total 138038 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18091 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 18091 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62532 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 62532 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12272 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12272 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 80623 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 80623 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 80623 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 80623 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164874 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 164874 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105876 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 105876 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 34136 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 34136 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5441 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5441 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23494 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23494 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 270750 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 270750 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 304886 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 304886 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5716 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5716 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5010 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5010 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10726 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10726 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2161886054 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2161886054 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2482626291 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2482626291 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 533136002 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 533136002 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89692006 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89692006 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 513974285 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 513974285 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 347500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 347500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4644512345 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4644512345 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5177648347 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5177648347 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 978236749 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 978236749 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 848797501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 848797501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1827034250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1827034250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033658 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033658 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025986 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025986 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.337897 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.337897 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051407 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051407 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.226809 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.226809 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030174 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030174 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033601 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033601 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13112.352791 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13112.352791 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23448.432988 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23448.432988 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15617.998652 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15617.998652 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16484.470869 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16484.470869 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21876.831744 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21876.831744 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17800.572621 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17800.572621 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17628.055488 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17628.055488 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17154.246888 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17154.246888 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16982.243681 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16982.243681 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171140.089048 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171140.089048 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169420.658882 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169420.658882 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170336.961589 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170336.961589 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 947666 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.322678 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 38831450 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 948178 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.953756 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 72138919500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.322678 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975240 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975240 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 1038832 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.324542 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 9157675 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 1039344 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 8.811014 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 72123856500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.324542 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975243 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975243 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 459 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 53 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 80507434 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 80507434 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 38831450 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 38831450 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 38831450 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 38831450 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 38831450 # number of overall hits -system.cpu1.icache.overall_hits::total 38831450 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 948178 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 948178 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 948178 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 948178 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 948178 # number of overall misses -system.cpu1.icache.overall_misses::total 948178 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8186316171 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8186316171 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8186316171 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8186316171 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8186316171 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8186316171 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 39779628 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 39779628 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 39779628 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 39779628 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 39779628 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 39779628 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023836 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023836 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023836 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023836 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023836 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023836 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8633.733509 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8633.733509 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8633.733509 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8633.733509 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8633.733509 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8633.733509 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 21433382 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 21433382 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 9157675 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 9157675 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 9157675 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 9157675 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 9157675 # number of overall hits +system.cpu1.icache.overall_hits::total 9157675 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 1039344 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 1039344 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 1039344 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 1039344 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 1039344 # number of overall misses +system.cpu1.icache.overall_misses::total 1039344 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9221968883 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 9221968883 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 9221968883 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 9221968883 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 9221968883 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 9221968883 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 10197019 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 10197019 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 10197019 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 10197019 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 10197019 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 10197019 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.101926 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.101926 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.101926 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.101926 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.101926 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.101926 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8872.874508 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8872.874508 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8872.874508 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8872.874508 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8872.874508 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8872.874508 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1651,415 +1682,415 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 948178 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 948178 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 948178 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 948178 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 948178 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 948178 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7236829829 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7236829829 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7236829829 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7236829829 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7236829829 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7236829829 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10429000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10429000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10429000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10429000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023836 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023836 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023836 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.023836 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023836 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.023836 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7632.353660 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7632.353660 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7632.353660 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7632.353660 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7632.353660 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7632.353660 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 1039344 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 1039344 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 1039344 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 1039344 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 1039344 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 1039344 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable +system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable +system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses +system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8180244117 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8180244117 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8180244117 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8180244117 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8180244117 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8180244117 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10330000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10330000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10330000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10330000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.101926 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.101926 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.101926 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.101926 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.101926 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.101926 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7870.583865 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7870.583865 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7870.583865 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7870.583865 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7870.583865 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7870.583865 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92232.142857 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92232.142857 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92232.142857 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92232.142857 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 198185 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 198250 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 56 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 272919 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 272954 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 58438 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 54866 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15346.205956 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1177923 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 69767 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 16.883670 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 68790 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 69865 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15664.735857 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1313161 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 84814 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 15.482833 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 7899.614060 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 43.616627 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.093163 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4379.239024 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2180.842140 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 842.800943 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.482154 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002662 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.267288 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.133108 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051440 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.936658 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1047 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 51 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13803 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 662 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 384 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6041 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7452 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.063904 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.842468 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 22495354 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 22495354 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28402 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2611 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 927201 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 105616 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 1063830 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 119475 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 119475 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1556 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1556 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 974 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 974 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28114 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 28114 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 28402 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2611 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 927201 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 133730 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 1091944 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 28402 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2611 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 927201 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 133730 # number of overall hits -system.cpu1.l2cache.overall_hits::total 1091944 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 655 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 221 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 20977 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 71094 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 92947 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28365 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28365 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22703 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22703 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34428 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 34428 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 655 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 221 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 20977 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 105522 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 127375 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 655 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 221 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 20977 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 105522 # number of overall misses -system.cpu1.l2cache.overall_misses::total 127375 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 15088235 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4439998 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 733507240 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1569643994 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 2322679467 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536973358 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 536973358 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 458518574 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 458518574 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 116500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 116500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1375727201 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1375727201 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 15088235 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4439998 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 733507240 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2945371195 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3698406668 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 15088235 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4439998 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 733507240 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2945371195 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3698406668 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29057 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2832 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 948178 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 176710 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 1156777 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 119475 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 119475 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29921 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29921 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23677 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23677 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62542 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 62542 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29057 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2832 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 948178 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 239252 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1219319 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29057 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2832 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 948178 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 239252 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1219319 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022542 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.078037 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.022123 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.402320 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.080350 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.947996 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.947996 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.958863 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.958863 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.550478 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.550478 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022542 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.078037 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.022123 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.441050 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.104464 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022542 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.078037 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.022123 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.441050 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.104464 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23035.473282 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20090.488688 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34967.213615 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22078.431288 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24989.289240 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18930.842870 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18930.842870 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20196.386997 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20196.386997 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 116500 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 116500 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39959.544586 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39959.544586 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23035.473282 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20090.488688 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34967.213615 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27912.389786 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 29035.577374 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23035.473282 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20090.488688 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34967.213615 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27912.389786 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 29035.577374 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 66 # number of cycles access was blocked +system.cpu1.l2cache.tags.occ_blocks::writebacks 6115.525293 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 60.132908 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.972099 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5626.461246 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2273.619533 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1588.024777 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.373262 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003670 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000059 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.343412 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.138771 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.096925 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.956100 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1163 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 63 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13723 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 666 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 493 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6148 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7266 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.070984 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.837585 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 25009138 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 25009138 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 33079 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2665 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 1011889 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 130945 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 1178578 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 138038 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 138038 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1986 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1986 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1041 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 1041 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 38169 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 38169 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 33079 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2665 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 1011889 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 169114 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 1216747 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 33079 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2665 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 1011889 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 169114 # number of overall hits +system.cpu1.l2cache.overall_hits::total 1216747 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 706 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 219 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 27455 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 73504 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 101884 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29526 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 29526 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22453 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22453 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 36197 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 36197 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 706 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 219 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 27455 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 109701 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 138081 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 706 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 219 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 27455 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 109701 # number of overall misses +system.cpu1.l2cache.overall_misses::total 138081 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 17675980 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4473998 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1080327485 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1722703491 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 2825180954 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 558586766 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 558586766 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449048470 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449048470 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 339500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 339500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1429113805 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1429113805 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 17675980 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4473998 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1080327485 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 3151817296 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 4254294759 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 17675980 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4473998 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1080327485 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 3151817296 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 4254294759 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 33785 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2884 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 1039344 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 204449 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 1280462 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 138038 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 138038 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31512 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 31512 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23494 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23494 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 74366 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 74366 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 33785 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2884 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 1039344 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 278815 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 1354828 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 33785 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2884 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 1039344 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 278815 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 1354828 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020897 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.075936 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026416 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.359522 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.079568 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.936976 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.936976 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.955691 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.955691 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.486741 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.486741 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020897 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.075936 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026416 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.393454 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.101918 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020897 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.075936 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026416 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.393454 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.101918 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25036.798867 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20429.214612 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 39349.025132 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 23436.867259 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27729.387872 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18918.470704 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18918.470704 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19999.486483 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19999.486483 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39481.553858 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39481.553858 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25036.798867 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20429.214612 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39349.025132 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28730.980538 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 30810.138679 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25036.798867 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20429.214612 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39349.025132 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28730.980538 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 30810.138679 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 82 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 33 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 20.500000 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 32095 # number of writebacks -system.cpu1.l2cache.writebacks::total 32095 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 29 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 84 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 230 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 230 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 29 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 314 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 343 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 29 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 314 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 343 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 655 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 221 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 20948 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 71010 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 92834 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 23894 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 23894 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28365 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28365 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22703 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22703 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34198 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 34198 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 655 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 221 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 20948 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 105208 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 127032 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 655 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 221 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 20948 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 105208 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 23894 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 150926 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 10825243 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3002500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 595509510 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1105908750 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1715246003 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1009576164 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1009576164 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 452138519 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 452138519 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 342402748 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 342402748 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 97000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 97000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1121062806 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1121062806 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 10825243 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3002500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 595509510 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2226971556 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2836308809 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 10825243 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3002500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 595509510 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2226971556 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1009576164 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 3845884973 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9469000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2205184749 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2214653749 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1754353500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1754353500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9469000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3959538249 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3969007249 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022542 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.078037 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.022093 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.401845 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.080252 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.writebacks::writebacks 37239 # number of writebacks +system.cpu1.l2cache.writebacks::total 37239 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 26 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 127 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 153 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 350 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 350 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 26 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 477 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 503 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 26 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 477 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 503 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 706 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 219 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 27429 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 73377 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 101731 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 35271 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 35271 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29526 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29526 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22453 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22453 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35847 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 35847 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 706 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 219 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 27429 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 109224 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 137578 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 706 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 219 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 27429 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 109224 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 35271 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 172849 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5716 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5828 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5010 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5010 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10726 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10838 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 13073996 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3049500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 898741765 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1240067767 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 2154933028 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1274079828 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1274079828 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 492031029 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 492031029 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 337561796 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 337561796 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 287500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 287500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1155906813 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1155906813 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 13073996 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3049500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 898741765 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2395974580 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3310839841 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 13073996 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3049500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 898741765 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2395974580 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1274079828 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4584919669 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9388000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 932474750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 941862750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 811133499 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 811133499 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9388000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1743608249 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1752996249 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020897 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.075936 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.026391 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.358901 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.079449 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.947996 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.947996 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.958863 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.958863 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.546801 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.546801 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022542 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.078037 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.022093 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.439737 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.104183 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022542 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.078037 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.022093 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.439737 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.936976 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.936976 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.955691 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.955691 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.482035 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.482035 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020897 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.075936 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026391 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.391744 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.101546 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020897 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.075936 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026391 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.391744 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.123779 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16527.088550 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13585.972851 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28427.988829 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15573.986058 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18476.484941 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42252.287771 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 42252.287771 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15940.014772 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15940.014772 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15081.828305 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15081.828305 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 97000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 97000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32781.531259 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32781.531259 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16527.088550 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13585.972851 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28427.988829 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21167.321458 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22327.514398 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16527.088550 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13585.972851 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28427.988829 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21167.321458 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42252.287771 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25481.924738 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.127580 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 32766.114878 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 16899.951851 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 21182.658462 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36122.588756 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36122.588756 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16664.330725 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16664.330725 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15034.151160 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15034.151160 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32245.566240 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32245.566240 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32766.114878 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21936.337984 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24065.183685 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32766.114878 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21936.337984 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36122.588756 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26525.578216 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83821.428571 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163134.141008 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161609.943377 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161902.894012 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161902.894012 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83821.428571 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162559.038691 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161745.363443 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1546268 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1215347 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11936 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11936 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 119475 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 29668 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 76508 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42110 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86467 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 85086 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 67037 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1896584 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 833808 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7155 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62301 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2799848 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60690688 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25792980 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11328 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 116228 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 86611224 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 603822 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1920664 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 3.272089 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.445035 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1679463 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1332654 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5010 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 138038 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 44141 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36278 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 76606 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42998 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 89660 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 97798 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 80302 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2078912 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 908693 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7242 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 71512 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3066359 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66525184 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29710243 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11536 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 135140 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 96382103 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 669363 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2146516 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.290923 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.454188 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 1398073 72.79% 72.79% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 522591 27.21% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 1522045 70.91% 70.91% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 624471 29.09% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1920664 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 837814982 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 2146516 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 922622470 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80458500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 87676498 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1423116171 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1560397383 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 410915491 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 459276108 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4323500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4359499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 33252737 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 37739490 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31003 # Transaction distribution -system.iobus.trans_dist::ReadResp 31003 # Transaction distribution +system.iobus.trans_dist::ReadReq 30987 # Transaction distribution +system.iobus.trans_dist::ReadResp 30987 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution system.iobus.trans_dist::WriteResp 23198 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution @@ -2068,7 +2099,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2084,16 +2115,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72906 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72906 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180818 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2109,10 +2140,10 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2483972 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2483858 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) @@ -2123,7 +2154,7 @@ system.iobus.reqLayer3.occupancy 12000 # La system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 504000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2153,52 +2184,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198973953 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198858516 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36786758 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36733518 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36449 # number of replacements -system.iocache.tags.tagsinuse 14.479940 # Cycle average of tags in use +system.iocache.tags.replacements 36403 # number of replacements +system.iocache.tags.tagsinuse 1.010559 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36419 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270378265000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.479940 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.904996 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.904996 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270375766000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.010559 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.063160 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.063160 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328203 # Number of tag accesses -system.iocache.tags.data_accesses 328203 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses -system.iocache.ReadReq_misses::total 243 # number of ReadReq misses +system.iocache.tags.tag_accesses 328077 # Number of tag accesses +system.iocache.tags.data_accesses 328077 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 229 # number of ReadReq misses +system.iocache.ReadReq_misses::total 229 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses -system.iocache.demand_misses::total 243 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 243 # number of overall misses -system.iocache.overall_misses::total 243 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31380127 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31380127 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6638963068 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6638963068 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31380127 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31380127 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31380127 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31380127 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 229 # number of demand (read+write) misses +system.iocache.demand_misses::total 229 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 229 # number of overall misses +system.iocache.overall_misses::total 229 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 29476377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29476377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6677842621 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6677842621 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29476377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29476377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29476377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29476377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 229 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 229 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 229 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 229 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 229 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 229 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses @@ -2207,40 +2238,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129136.325103 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129136.325103 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183275.261374 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183275.261374 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 129136.325103 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 129136.325103 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 129136.325103 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 129136.325103 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22458 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128717.803493 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128717.803493 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 184348.570589 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 184348.570589 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128717.803493 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128717.803493 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128717.803493 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128717.803493 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 23020 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3415 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3484 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.576281 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.607348 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36206 # number of writebacks -system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 36174 # number of writebacks +system.iocache.writebacks::total 36174 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 229 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 229 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18685627 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18685627 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4755299084 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4755299084 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18685627 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18685627 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18685627 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18685627 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 229 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 229 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 229 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 229 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17561377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17561377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4794158657 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4794158657 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17561377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17561377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17561377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17561377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2249,561 +2280,593 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76895.584362 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76895.584362 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131274.820119 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131274.820119 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76895.584362 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76895.584362 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76895.584362 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76895.584362 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76687.235808 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76687.235808 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 132347.577766 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 132347.577766 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76687.235808 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76687.235808 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76687.235808 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76687.235808 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 135638 # number of replacements -system.l2c.tags.tagsinuse 64035.864385 # Cycle average of tags in use -system.l2c.tags.total_refs 380564 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 200114 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.901736 # Average number of references to valid blocks. +system.l2c.tags.replacements 136197 # number of replacements +system.l2c.tags.tagsinuse 64163.282922 # Cycle average of tags in use +system.l2c.tags.total_refs 379817 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 200471 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.894623 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12087.017372 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 77.160254 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.033685 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8509.496822 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2877.165248 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35676.414678 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 13.500349 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2186.391247 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 567.991773 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2040.692959 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.184433 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001177 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.129845 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043902 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.544379 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000206 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.033362 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008667 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.031139 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.977110 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 30037 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 48 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 34391 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 135 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4776 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 25126 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 12850.317421 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 69.201711 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.031095 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 6628.601764 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1957.826461 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32727.538139 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 28.180445 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.851989 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4115.294958 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1518.513926 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4266.925013 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.196080 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001056 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.101144 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.029874 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.499383 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000430 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.062794 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.023171 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.065108 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.979054 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 30066 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 34130 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 141 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5589 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 24336 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 78 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3317 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 30762 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.458328 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.524765 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5287806 # Number of tag accesses -system.l2c.tags.data_accesses 5287806 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 444 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 48461 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 49558 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 47653 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 127 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 25 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 17654 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 9320 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 5533 # number of ReadReq hits -system.l2c.ReadReq_hits::total 178838 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 232835 # number of Writeback hits -system.l2c.Writeback_hits::total 232835 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 3130 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 650 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3780 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 173 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 165 # number of SCUpgradeReq hits +system.l2c.tags.age_task_id_blocks_1024::3 3041 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 30776 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.458771 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.001190 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.520782 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5295828 # Number of tag accesses +system.l2c.tags.data_accesses 5295828 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 375 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 73 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 43717 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 47365 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 45781 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 167 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 27 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 21454 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 10985 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 8059 # number of ReadReq hits +system.l2c.ReadReq_hits::total 178003 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 233506 # number of Writeback hits +system.l2c.Writeback_hits::total 233506 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2927 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 947 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3874 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 249 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 89 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 338 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4192 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1733 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5925 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 444 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 48461 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 53750 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 47653 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 127 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 25 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 17654 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 11053 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5533 # number of demand (read+write) hits -system.l2c.demand_hits::total 184763 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 444 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits -system.l2c.overall_hits::cpu0.inst 48461 # number of overall hits -system.l2c.overall_hits::cpu0.data 53750 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 47653 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 127 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 25 # number of overall hits -system.l2c.overall_hits::cpu1.inst 17654 # number of overall hits -system.l2c.overall_hits::cpu1.data 11053 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5533 # number of overall hits -system.l2c.overall_hits::total 184763 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 146 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 22747 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 9845 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 132327 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 21 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3294 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1096 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 6759 # number of ReadReq misses -system.l2c.ReadReq_misses::total 176237 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 9250 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2916 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12166 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 671 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1253 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1924 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11244 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8399 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19643 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 146 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 22747 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 21089 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 132327 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 21 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3294 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 9495 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 6759 # number of demand (read+write) misses -system.l2c.demand_misses::total 195880 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 146 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 22747 # number of overall misses -system.l2c.overall_misses::cpu0.data 21089 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 132327 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 21 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3294 # number of overall misses -system.l2c.overall_misses::cpu1.data 9495 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 6759 # number of overall misses -system.l2c.overall_misses::total 195880 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 13322250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 165000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 1836389560 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 869862901 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 13647658866 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1878250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 273761254 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 100369500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 908948741 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 17652356322 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 7104776 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 3030406 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 10135182 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1032472 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1498952 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2531424 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 1028146684 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 690374730 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1718521414 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 13322250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 165000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1836389560 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1898009585 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13647658866 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1878250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 273761254 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 790744230 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 908948741 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 19370877736 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 13322250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 165000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1836389560 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1898009585 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13647658866 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1878250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 273761254 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 790744230 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 908948741 # number of overall miss cycles -system.l2c.overall_miss_latency::total 19370877736 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 590 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 65 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 71208 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 59403 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 179980 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 148 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 25 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 20948 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 10416 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 12292 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 355075 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 232835 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 232835 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 12380 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3566 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 15946 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 844 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1418 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2262 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 15436 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 10132 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 25568 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 590 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 65 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 71208 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 74839 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179980 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 148 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 20948 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 20548 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 12292 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 380643 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 590 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 65 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 71208 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 74839 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179980 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 148 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 20948 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 20548 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 12292 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 380643 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.247458 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.030769 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.319444 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.165732 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.735232 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.141892 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.157247 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.105223 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.549870 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.496337 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.747173 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.817723 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.762950 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.795024 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.883639 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.850575 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.728427 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.828958 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.768265 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.247458 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.030769 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.319444 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.281792 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.735232 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.141892 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.157247 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.462089 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.549870 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.514603 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.247458 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.030769 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.319444 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.281792 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.735232 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.141892 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.157247 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.462089 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.549870 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.514603 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 91248.287671 # average ReadReq miss latency +system.l2c.ReadExReq_hits::cpu0.data 4056 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 2216 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 6272 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 375 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 73 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 43717 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 51421 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 45781 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 167 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 27 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 21454 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 13201 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 8059 # number of demand (read+write) hits +system.l2c.demand_hits::total 184275 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 375 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 73 # number of overall hits +system.l2c.overall_hits::cpu0.inst 43717 # number of overall hits +system.l2c.overall_hits::cpu0.data 51421 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 45781 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 167 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 27 # number of overall hits +system.l2c.overall_hits::cpu1.inst 21454 # number of overall hits +system.l2c.overall_hits::cpu1.data 13201 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 8059 # number of overall hits +system.l2c.overall_hits::total 184275 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 130 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 20052 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 8676 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 129939 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 40 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 5975 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 2283 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 9112 # number of ReadReq misses +system.l2c.ReadReq_misses::total 176209 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 8724 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4132 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 12856 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 807 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1210 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2017 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11072 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8457 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 19529 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 130 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 20052 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 19748 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 129939 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 40 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 5975 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10740 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 9112 # number of demand (read+write) misses +system.l2c.demand_misses::total 195738 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 130 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu0.inst 20052 # number of overall misses +system.l2c.overall_misses::cpu0.data 19748 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 129939 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 40 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 5975 # number of overall misses +system.l2c.overall_misses::cpu1.data 10740 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 9112 # number of overall misses +system.l2c.overall_misses::total 195738 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 10973000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 1610371008 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 763651868 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 13522119331 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 3426000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 83000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 494933758 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 205725771 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 1117904049 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 17729270285 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 8986748 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 6209345 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 15196093 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1132469 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1093465 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2225934 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 1027113188 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 693883201 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1720996389 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 10973000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 82500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1610371008 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1790765056 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13522119331 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 3426000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 83000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 494933758 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 899608972 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1117904049 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 19450266674 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 10973000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 82500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1610371008 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1790765056 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13522119331 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 3426000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 83000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 494933758 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 899608972 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1117904049 # number of overall miss cycles +system.l2c.overall_miss_latency::total 19450266674 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 505 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 74 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 63769 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 56041 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 175720 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 207 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 28 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 27429 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 13268 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 17171 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 354212 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 233506 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 233506 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 11651 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5079 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 16730 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 1056 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1299 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2355 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 15128 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 10673 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 25801 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 505 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 74 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 63769 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 71169 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 175720 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 207 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 28 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 27429 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 23941 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 17171 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 380013 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 505 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 74 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 63769 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 71169 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 175720 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 207 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 28 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 27429 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 23941 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 17171 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 380013 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.257426 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.013514 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.314447 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.154815 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.739466 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.193237 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.035714 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.217835 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.172068 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.530662 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.497468 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.748777 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.813546 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.768440 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.764205 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.931486 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.856476 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.731888 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.792373 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.756909 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.257426 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.013514 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.314447 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.277480 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.739466 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.193237 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.035714 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.217835 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.448603 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.530662 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.515082 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.257426 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.013514 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.314447 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.277480 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.739466 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.193237 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.035714 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.217835 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.448603 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.530662 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.515082 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 84407.692308 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80731.066075 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 88355.805079 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 103135.859394 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89440.476190 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83109.063145 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 91578.010949 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 134479.766386 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 100162.601054 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 768.083892 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1039.233882 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 833.074305 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1538.706408 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1196.290503 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1315.708940 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91439.584134 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82197.253244 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 87487.726620 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 91248.287671 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80309.745063 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 88018.887506 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 104065.133109 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 85650 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 83000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 82834.101757 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 90112.032852 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 122684.816615 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 100615.009931 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1030.117836 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1502.745644 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1182.023413 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1403.307311 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 903.690083 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1103.586515 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 92766.725795 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82048.386071 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 88125.167136 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 84407.692308 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 80731.066075 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 89999.980321 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 103135.859394 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89440.476190 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 83109.063145 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 83280.066351 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134479.766386 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 98891.554707 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 91248.287671 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 80309.745063 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 90680.831274 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 104065.133109 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85650 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 82834.101757 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 83762.474115 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 122684.816615 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 99368.884294 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 84407.692308 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 80731.066075 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 89999.980321 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 103135.859394 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89440.476190 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 83109.063145 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 83280.066351 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 134479.766386 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 98891.554707 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.overall_avg_miss_latency::cpu0.inst 80309.745063 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 90680.831274 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 104065.133109 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85650 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 82834.101757 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 83762.474115 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 122684.816615 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 99368.884294 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 17 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 17 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 101923 # number of writebacks -system.l2c.writebacks::total 101923 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 146 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 22742 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 9845 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 132327 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 21 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 3293 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1095 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 6759 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 176230 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 9250 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 2916 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 12166 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 671 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1253 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1924 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 11244 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 8399 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 19643 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 146 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 22742 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 21089 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 132327 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 21 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 3293 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 9494 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6759 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 195873 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 146 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 22742 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 21089 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 132327 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 21 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 3293 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 9494 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6759 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 195873 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 11489750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 140000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1551174190 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 746786599 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12016886672 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1614750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 232356996 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 86604500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 826146057 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 15473199514 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 164200724 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 51784907 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 215985631 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12008669 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 22268252 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 34276921 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 889143316 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 585339270 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1474482586 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 11489750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 140000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1551174190 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 1635929915 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12016886672 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1614750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 232356996 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 671943770 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 826146057 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16947682100 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 11489750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 140000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1551174190 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 1635929915 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12016886672 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1614750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 232356996 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 671943770 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 826146057 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16947682100 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 205778000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3714619750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6850000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919856251 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5847104001 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2763444000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1533087000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4296531000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 205778000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6478063750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6850000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3452943251 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10143635001 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.247458 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.319374 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.165732 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735232 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.141892 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.157199 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.105127 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.549870 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.496318 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.747173 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.817723 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.762950 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.795024 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.883639 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.850575 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.728427 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.828958 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.768265 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.247458 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.319374 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.281792 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735232 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.141892 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.157199 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.462040 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.549870 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.514585 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.247458 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.319374 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.281792 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735232 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.141892 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.157199 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.462040 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.549870 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.514585 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 78696.917808 # average ReadReq mshr miss latency +system.l2c.writebacks::writebacks 102293 # number of writebacks +system.l2c.writebacks::total 102293 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 130 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 20049 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 8676 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 129939 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 40 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 5975 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 2283 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 9112 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 176206 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8724 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 4132 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 12856 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 807 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1210 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2017 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 11072 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 8457 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 19529 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 130 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 20049 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 19748 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 129939 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 40 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 5975 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 10740 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 9112 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 195735 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 130 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 20049 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 19748 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 129939 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 40 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 5975 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 10740 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 9112 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 195735 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3367 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 29433 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5712 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 38624 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 26165 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5010 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 31175 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3367 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 55598 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10722 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 69799 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 9340000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 70000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1359057992 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 655200132 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11920664281 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 2921500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 70500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 420043242 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 177097729 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1006174503 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 15550639879 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 155599187 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 74220106 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 229819293 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 14429805 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 21503704 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 35933509 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 890221812 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 588134799 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1478356611 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 9340000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 70000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1359057992 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1545421944 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11920664281 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 2921500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 70500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 420043242 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 765232528 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1006174503 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 17028996490 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 9340000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 70000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1359057992 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1545421944 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11920664281 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 2921500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 70500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 420043242 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 765232528 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1006174503 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 17028996490 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 204708000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4816468250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6816000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 820420250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5848412500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3580583500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 717922501 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4298506001 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 204708000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8397051750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6816000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1538342751 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10146918501 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.257426 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013514 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.314400 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.154815 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739466 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.193237 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035714 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.217835 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.172068 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.530662 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.497459 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.748777 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.813546 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.768440 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.764205 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.931486 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.856476 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.731888 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.792373 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.756909 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.257426 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.013514 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.314400 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.277480 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739466 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.193237 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.035714 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.217835 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.448603 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.530662 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.515074 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.257426 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.013514 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.314400 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.277480 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739466 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.193237 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.035714 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.217835 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.448603 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.530662 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.515074 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71846.153846 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68207.465922 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75854.403149 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90812.054018 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76892.857143 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70560.885515 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 79090.867580 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122229.036396 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 87801.166169 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17751.429622 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17758.884431 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17753.216423 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17896.675112 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17771.948923 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17815.447505 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79077.135895 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69691.543041 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 75064.022094 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78696.917808 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67786.821886 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75518.687414 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91740.464995 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73037.500000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70300.124184 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77572.373631 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110423.013938 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 88252.612732 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17835.761921 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17962.271539 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17876.422915 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17880.799257 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17771.656198 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17815.324244 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80402.981575 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69544.140830 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 75700.579190 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71846.153846 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68207.465922 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77572.664185 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90812.054018 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76892.857143 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70560.885515 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70775.623552 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122229.036396 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 86523.829726 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78696.917808 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67786.821886 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78257.137128 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91740.464995 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73037.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70300.124184 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71250.700931 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110423.013938 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 87000.263060 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71846.153846 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68207.465922 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77572.664185 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90812.054018 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76892.857143 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70560.885515 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70775.623552 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122229.036396 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 86523.829726 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67786.821886 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78257.137128 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91740.464995 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73037.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70300.124184 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71250.700931 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110423.013938 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 87000.263060 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 163641.771141 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60857.142857 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143630.996148 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 151419.130592 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 136846.302312 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143297.904391 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 137883.111500 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151031.543401 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60857.142857 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 143475.354505 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 145373.407943 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 214962 # Transaction distribution -system.membus.trans_dist::ReadResp 214962 # Transaction distribution -system.membus.trans_dist::WriteReq 31066 # Transaction distribution -system.membus.trans_dist::WriteResp 31066 # Transaction distribution -system.membus.trans_dist::Writeback 138129 # Transaction distribution +system.membus.trans_dist::ReadReq 215059 # Transaction distribution +system.membus.trans_dist::ReadResp 215059 # Transaction distribution +system.membus.trans_dist::WriteReq 31175 # Transaction distribution +system.membus.trans_dist::WriteResp 31175 # Transaction distribution +system.membus.trans_dist::Writeback 138467 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 76255 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40796 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14193 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 40018 # Transaction distribution -system.membus.trans_dist::ReadExResp 19540 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 78265 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 41611 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15010 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution +system.membus.trans_dist::ReadExReq 39963 # Transaction distribution +system.membus.trans_dist::ReadExResp 19392 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661851 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 783963 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 892875 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14788 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 665413 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 788151 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108866 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108866 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 897017 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28316 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19273388 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19465716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24102196 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123912 # Total snoops (count) -system.membus.snoop_fanout::samples 507941 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19282584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19476170 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4634432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4634432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24110602 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 126068 # Total snoops (count) +system.membus.snoop_fanout::samples 580884 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 507941 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 580884 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 507941 # Request fanout histogram -system.membus.reqLayer0.occupancy 88612000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 580884 # Request fanout histogram +system.membus.reqLayer0.occupancy 88642500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12528499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 13073499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1167691410 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1170162100 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1172073016 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1173257543 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37476242 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 37390482 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2836,44 +2899,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 516720 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 516705 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31066 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31066 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 232835 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 79932 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41134 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 121066 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51762 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51762 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1083099 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 338756 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1421855 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34093856 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5618324 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 39712180 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 288702 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 920160 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.039660 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.195160 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 519203 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 519188 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31175 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 233506 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36278 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 82002 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41949 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 123951 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51897 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51897 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1081118 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 347519 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1428637 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32891255 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6822675 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 39713930 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 293844 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 996034 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.036652 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.187907 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 883666 96.03% 96.03% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36494 3.97% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 959527 96.33% 96.33% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36507 3.67% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 920160 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 787000770 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 996034 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 791138952 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 342000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 321000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 681574777 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 673122022 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 259216519 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 273051412 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 46452a5a5..d6c8679c7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.852832 # Number of seconds simulated -sim_ticks 2852831758500 # Number of ticks simulated -final_tick 2852831758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.852840 # Number of seconds simulated +sim_ticks 2852839554500 # Number of ticks simulated +final_tick 2852839554500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111123 # Simulator instruction rate (inst/s) -host_op_rate 134357 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2834419538 # Simulator tick rate (ticks/s) -host_mem_usage 554504 # Number of bytes of host memory used -host_seconds 1006.50 # Real time elapsed on the host -sim_insts 111845135 # Number of instructions simulated -sim_ops 135229426 # Number of ops (including micro ops) simulated +host_inst_rate 169032 # Simulator instruction rate (inst/s) +host_op_rate 204382 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4294589830 # Simulator tick rate (ticks/s) +host_mem_usage 620820 # Number of bytes of host memory used +host_seconds 664.29 # Real time elapsed on the host +sim_insts 112285680 # Number of instructions simulated +sim_ops 135768245 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 7744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1669888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9170532 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 7680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1672128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9190636 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10849188 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1669888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1669888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7971008 # Number of bytes written to this memory +system.physmem.bytes_read::total 10871532 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1672128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1672128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7983360 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7988532 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 121 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26092 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143809 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8000884 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 120 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26127 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144125 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170038 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124547 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170389 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124740 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128928 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 585344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3214537 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 129121 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 586128 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3221575 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3802954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 585344 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 585344 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2794069 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3810776 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 586128 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 586128 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2798391 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2800211 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2794069 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 585344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3220679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2804533 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2798391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 586128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3227717 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6603165 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170038 # Number of read requests accepted -system.physmem.writeReqs 165152 # Number of write requests accepted -system.physmem.readBursts 170038 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 165152 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10876672 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5760 # Total number of bytes read from write queue -system.physmem.bytesWritten 9051328 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10849188 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10306868 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 90 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23701 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4591 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10711 # Per bank write bursts -system.physmem.perBankRdBursts::1 10418 # Per bank write bursts -system.physmem.perBankRdBursts::2 10743 # Per bank write bursts -system.physmem.perBankRdBursts::3 10617 # Per bank write bursts -system.physmem.perBankRdBursts::4 13557 # Per bank write bursts -system.physmem.perBankRdBursts::5 10851 # Per bank write bursts -system.physmem.perBankRdBursts::6 10986 # Per bank write bursts -system.physmem.perBankRdBursts::7 10951 # Per bank write bursts -system.physmem.perBankRdBursts::8 10335 # Per bank write bursts -system.physmem.perBankRdBursts::9 10516 # Per bank write bursts -system.physmem.perBankRdBursts::10 10068 # Per bank write bursts -system.physmem.perBankRdBursts::11 9192 # Per bank write bursts -system.physmem.perBankRdBursts::12 10325 # Per bank write bursts -system.physmem.perBankRdBursts::13 10893 # Per bank write bursts -system.physmem.perBankRdBursts::14 9864 # Per bank write bursts -system.physmem.perBankRdBursts::15 9921 # Per bank write bursts -system.physmem.perBankWrBursts::0 8907 # Per bank write bursts -system.physmem.perBankWrBursts::1 8809 # Per bank write bursts -system.physmem.perBankWrBursts::2 9307 # Per bank write bursts -system.physmem.perBankWrBursts::3 9147 # Per bank write bursts -system.physmem.perBankWrBursts::4 8787 # Per bank write bursts -system.physmem.perBankWrBursts::5 9076 # Per bank write bursts -system.physmem.perBankWrBursts::6 9209 # Per bank write bursts -system.physmem.perBankWrBursts::7 9123 # Per bank write bursts -system.physmem.perBankWrBursts::8 9054 # Per bank write bursts -system.physmem.perBankWrBursts::9 9064 # Per bank write bursts -system.physmem.perBankWrBursts::10 8553 # Per bank write bursts -system.physmem.perBankWrBursts::11 8266 # Per bank write bursts -system.physmem.perBankWrBursts::12 8846 # Per bank write bursts -system.physmem.perBankWrBursts::13 9045 # Per bank write bursts -system.physmem.perBankWrBursts::14 8063 # Per bank write bursts -system.physmem.perBankWrBursts::15 8171 # Per bank write bursts +system.physmem.bw_total::total 6615309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170389 # Number of read requests accepted +system.physmem.writeReqs 165345 # Number of write requests accepted +system.physmem.readBursts 170389 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 165345 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10897024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7872 # Total number of bytes read from write queue +system.physmem.bytesWritten 9054784 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10871532 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10319220 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 123 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23835 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4587 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10917 # Per bank write bursts +system.physmem.perBankRdBursts::1 10861 # Per bank write bursts +system.physmem.perBankRdBursts::2 10721 # Per bank write bursts +system.physmem.perBankRdBursts::3 10725 # Per bank write bursts +system.physmem.perBankRdBursts::4 13339 # Per bank write bursts +system.physmem.perBankRdBursts::5 10813 # Per bank write bursts +system.physmem.perBankRdBursts::6 11142 # Per bank write bursts +system.physmem.perBankRdBursts::7 10985 # Per bank write bursts +system.physmem.perBankRdBursts::8 10153 # Per bank write bursts +system.physmem.perBankRdBursts::9 10280 # Per bank write bursts +system.physmem.perBankRdBursts::10 10274 # Per bank write bursts +system.physmem.perBankRdBursts::11 9203 # Per bank write bursts +system.physmem.perBankRdBursts::12 10314 # Per bank write bursts +system.physmem.perBankRdBursts::13 10760 # Per bank write bursts +system.physmem.perBankRdBursts::14 10035 # Per bank write bursts +system.physmem.perBankRdBursts::15 9744 # Per bank write bursts +system.physmem.perBankWrBursts::0 9017 # Per bank write bursts +system.physmem.perBankWrBursts::1 9225 # Per bank write bursts +system.physmem.perBankWrBursts::2 9344 # Per bank write bursts +system.physmem.perBankWrBursts::3 9210 # Per bank write bursts +system.physmem.perBankWrBursts::4 8591 # Per bank write bursts +system.physmem.perBankWrBursts::5 8923 # Per bank write bursts +system.physmem.perBankWrBursts::6 9235 # Per bank write bursts +system.physmem.perBankWrBursts::7 9154 # Per bank write bursts +system.physmem.perBankWrBursts::8 8919 # Per bank write bursts +system.physmem.perBankWrBursts::9 8830 # Per bank write bursts +system.physmem.perBankWrBursts::10 8770 # Per bank write bursts +system.physmem.perBankWrBursts::11 8263 # Per bank write bursts +system.physmem.perBankWrBursts::12 8824 # Per bank write bursts +system.physmem.perBankWrBursts::13 8884 # Per bank write bursts +system.physmem.perBankWrBursts::14 8238 # Per bank write bursts +system.physmem.perBankWrBursts::15 8054 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 51 # Number of times write queue was full causing retry -system.physmem.totGap 2852831352500 # Total gap between requests +system.physmem.numWrRetry 37 # Number of times write queue was full causing retry +system.physmem.totGap 2852839149500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 541 # Read request sizes (log2) +system.physmem.readPktSize::2 543 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169483 # Read request sizes (log2) +system.physmem.readPktSize::6 169832 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 160771 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6460 # What read queue length does an incoming req see +system.physmem.writePktSize::6 160964 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6336 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -159,159 +159,160 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 157 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61712 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 322.918330 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.336942 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 338.461853 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22238 36.04% 36.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14509 23.51% 59.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6552 10.62% 70.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3615 5.86% 76.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2651 4.30% 80.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1538 2.49% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1136 1.84% 84.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1152 1.87% 86.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8321 13.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61712 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5883 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.886962 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 584.019916 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5882 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 43 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61975 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 321.932134 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.780856 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 337.844354 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22404 36.15% 36.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14558 23.49% 59.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6628 10.69% 70.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3590 5.79% 76.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2633 4.25% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1568 2.53% 82.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1136 1.83% 84.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1187 1.92% 86.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8271 13.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61975 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5903 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.841945 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 583.033382 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5902 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5883 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5883 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.039946 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.374321 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 43.145306 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 5549 94.32% 94.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 83 1.41% 95.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 21 0.36% 96.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 19 0.32% 96.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 30 0.51% 96.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 24 0.41% 97.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 22 0.37% 97.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 15 0.25% 97.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 11 0.19% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 3 0.05% 98.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 21 0.36% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 13 0.22% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 9 0.15% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 6 0.10% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.03% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 2 0.03% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 4 0.07% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 7 0.12% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 3 0.05% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 2 0.03% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 6 0.10% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 9 0.15% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 2 0.03% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 3 0.05% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 2 0.03% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 2 0.03% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 1 0.02% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 5 0.08% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 2 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 5 0.08% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5883 # Writes before turning the bus around for reads -system.physmem.totQLat 1723441444 # Total ticks spent queuing -system.physmem.totMemAccLat 4909966444 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 849740000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10140.99 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5903 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5903 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.967644 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.368451 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 42.492651 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5572 94.39% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 86 1.46% 95.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 22 0.37% 96.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 13 0.22% 96.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 26 0.44% 96.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 23 0.39% 97.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 23 0.39% 97.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 20 0.34% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 7 0.12% 98.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 2 0.03% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 23 0.39% 98.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 13 0.22% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 11 0.19% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 2 0.03% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.03% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.05% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.03% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 6 0.10% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 7 0.12% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 5 0.08% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 2 0.03% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 15 0.25% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 4 0.07% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 3 0.05% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 2 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5903 # Writes before turning the bus around for reads +system.physmem.totQLat 1723482630 # Total ticks spent queuing +system.physmem.totMemAccLat 4915970130 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 851330000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10122.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28890.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28872.29 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.82 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.62 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.38 # Average write queue length when enqueuing -system.physmem.readRowHits 140236 # Number of row buffer hits during reads -system.physmem.writeRowHits 109426 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.36 # Row buffer hit rate for writes -system.physmem.avgGap 8511087.30 # Average gap between requests -system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 243129600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132660000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 692905200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 468925200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186332824080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83554754445 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1638403001250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1909828199775 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.450935 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2725489926444 # Time in different power states -system.physmem_0.memoryStateTime::REF 95262180000 # Time in different power states +system.physmem.avgWrQLen 25.62 # Average write queue length when enqueuing +system.physmem.readRowHits 140451 # Number of row buffer hits during reads +system.physmem.writeRowHits 109320 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.49 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.25 # Row buffer hit rate for writes +system.physmem.avgGap 8497319.75 # Average gap between requests +system.physmem.pageHitRate 80.11 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 245019600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 133691250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 698123400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 471089520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186333332640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83679210810 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1638298500750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1909858967970 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.459893 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2725317218918 # Time in different power states +system.physmem_0.memoryStateTime::REF 95262440000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32075649806 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32255883582 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 223413120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 121902000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 632681400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 447521760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186332824080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82328316795 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1639478823750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1909565482905 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.358845 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2727297379194 # Time in different power states -system.physmem_1.memoryStateTime::REF 95262180000 # Time in different power states +system.physmem_1.actEnergy 223511400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 121955625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 629943600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 445707360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186333332640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82264054140 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1639539866250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1909558371015 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.354525 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2727396126418 # Time in different power states +system.physmem_1.memoryStateTime::REF 95262440000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30272102306 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30180892082 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -331,15 +332,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31016169 # Number of BP lookups -system.cpu.branchPred.condPredicted 16821620 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2509164 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18454178 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13299317 # Number of BTB hits +system.cpu.branchPred.lookups 31043514 # Number of BP lookups +system.cpu.branchPred.condPredicted 16869099 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2536489 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18574786 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13386311 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.066699 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7885459 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1501288 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.067108 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7804422 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1529182 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -370,58 +371,59 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 66365 # Table walker walks requested -system.cpu.dtb.walker.walksShort 66365 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43579 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22786 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 66365 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 66365 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 66365 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7796 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 11013.949461 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 8730.002722 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7624.437396 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 6093 78.16% 78.16% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 1696 21.75% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 65823 # Table walker walks requested +system.cpu.dtb.walker.walksShort 65823 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43117 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22706 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 65823 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 65823 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 65823 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7829 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 10980.553072 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8717.816397 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7451.711579 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 6121 78.18% 78.18% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 1701 21.73% 99.91% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-81919 1 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.97% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::229376-245759 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7796 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7829 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples 262515000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 262515000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 262515000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6406 82.17% 82.17% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1390 17.83% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7796 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66365 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 6444 82.31% 82.31% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1385 17.69% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7829 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 65823 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66365 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7796 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 65823 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7829 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7796 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 74161 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7829 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 73652 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24709745 # DTB read hits -system.cpu.dtb.read_misses 59626 # DTB read misses -system.cpu.dtb.write_hits 19412201 # DTB write hits -system.cpu.dtb.write_misses 6739 # DTB write misses +system.cpu.dtb.read_hits 24809902 # DTB read hits +system.cpu.dtb.read_misses 58990 # DTB read misses +system.cpu.dtb.write_hits 19469042 # DTB write hits +system.cpu.dtb.write_misses 6833 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4351 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1292 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1782 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1238 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1767 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 733 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24769371 # DTB read accesses -system.cpu.dtb.write_accesses 19418940 # DTB write accesses +system.cpu.dtb.perms_faults 748 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24868892 # DTB read accesses +system.cpu.dtb.write_accesses 19475875 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44121946 # DTB hits -system.cpu.dtb.misses 66365 # DTB misses -system.cpu.dtb.accesses 44188311 # DTB accesses +system.cpu.dtb.hits 44278944 # DTB hits +system.cpu.dtb.misses 65823 # DTB misses +system.cpu.dtb.accesses 44344767 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -451,37 +453,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 5448 # Table walker walks requested -system.cpu.itb.walker.walksShort 5448 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 319 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5129 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5448 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5448 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5448 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3189 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 11214.016933 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 8947.518192 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7056.251032 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1295 40.61% 40.61% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1177 36.91% 77.52% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 716 22.45% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 5435 # Table walker walks requested +system.cpu.itb.walker.walksShort 5435 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 321 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5114 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5435 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5435 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5435 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3183 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 11172.007540 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 8898.591631 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7073.724538 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1308 41.09% 41.09% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1159 36.41% 77.51% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 715 22.46% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3189 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3183 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 262109500 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 262109500 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 262109500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2879 90.28% 90.28% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 310 9.72% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3189 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 2873 90.26% 90.26% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 310 9.74% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3183 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5448 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5448 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5435 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5435 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3189 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3189 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 8637 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57588649 # ITB inst hits -system.cpu.itb.inst_misses 5448 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3183 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3183 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 8618 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57700454 # ITB inst hits +system.cpu.itb.inst_misses 5435 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -490,268 +492,274 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2978 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2972 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8467 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8445 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57594097 # ITB inst accesses -system.cpu.itb.hits 57588649 # DTB hits -system.cpu.itb.misses 5448 # DTB misses -system.cpu.itb.accesses 57594097 # DTB accesses -system.cpu.numCycles 315565701 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57705889 # ITB inst accesses +system.cpu.itb.hits 57700454 # DTB hits +system.cpu.itb.misses 5435 # DTB misses +system.cpu.itb.accesses 57705889 # DTB accesses +system.cpu.numCycles 315730000 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 111845135 # Number of instructions committed -system.cpu.committedOps 135229426 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7692999 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 112285680 # Number of instructions committed +system.cpu.committedOps 135768245 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7761547 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5390158471 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.821452 # CPI: cycles per instruction -system.cpu.ipc 0.354427 # IPC: instructions per cycle +system.cpu.quiesceCycles 5390009685 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.811846 # CPI: cycles per instruction +system.cpu.ipc 0.355638 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed -system.cpu.tickCycles 227544928 # Number of cycles that the object actually ticked -system.cpu.idleCycles 88020773 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 842581 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.947861 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42538360 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 843093 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.455122 # Average number of references to valid blocks. +system.cpu.tickCycles 227805023 # Number of cycles that the object actually ticked +system.cpu.idleCycles 87924977 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 842413 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.947858 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42688411 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 842925 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.643190 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 313221250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.947861 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.947858 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999898 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999898 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 175914832 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 175914832 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23018220 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23018220 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18257083 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18257083 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 356514 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 356514 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443429 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443429 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460179 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460179 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41275303 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41275303 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41631817 # number of overall hits -system.cpu.dcache.overall_hits::total 41631817 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 492255 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 492255 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 547766 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 547766 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 169911 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 169911 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22569 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22569 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 176513094 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 176513094 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23118388 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23118388 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18306742 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18306742 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 356409 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 356409 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443709 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443709 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460231 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460231 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41425130 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41425130 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41781539 # number of overall hits +system.cpu.dcache.overall_hits::total 41781539 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 491811 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 491811 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 547829 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 547829 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 170067 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 170067 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22347 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22347 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 1040021 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1040021 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1209932 # number of overall misses -system.cpu.dcache.overall_misses::total 1209932 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7281770758 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7281770758 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23432647284 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23432647284 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 285921000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 285921000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30714418042 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30714418042 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30714418042 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30714418042 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23510475 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23510475 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18804849 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18804849 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 526425 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 526425 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465998 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465998 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460181 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460181 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42315324 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42315324 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42841749 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42841749 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020938 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020938 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029129 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029129 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322764 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.322764 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048432 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048432 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 1039640 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1039640 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1209707 # number of overall misses +system.cpu.dcache.overall_misses::total 1209707 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7276171447 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7276171447 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23463335520 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23463335520 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 282730000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 282730000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 167000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30739506967 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30739506967 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30739506967 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30739506967 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23610199 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23610199 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18854571 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18854571 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 526476 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 526476 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466056 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 466056 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460233 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460233 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42464770 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42464770 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42991246 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42991246 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020830 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020830 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029056 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029056 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.323029 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.323029 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047949 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.047949 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024578 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024578 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.028242 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.028242 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14792.680131 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14792.680131 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42778.572025 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42778.572025 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12668.749169 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12668.749169 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29532.497942 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29532.497942 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25385.243172 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25385.243172 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 240 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.024482 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024482 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.028138 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.028138 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14794.649666 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14794.649666 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42829.670426 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42829.670426 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12651.810086 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12651.810086 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83500 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83500 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29567.453125 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29567.453125 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25410.704383 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25410.704383 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 271 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.318182 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 698329 # number of writebacks -system.cpu.dcache.writebacks::total 698329 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75041 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 75041 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249041 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 249041 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14319 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14319 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 324082 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 324082 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 324082 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 324082 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417214 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 417214 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298725 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298725 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121762 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 121762 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8250 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8250 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 697807 # number of writebacks +system.cpu.dcache.writebacks::total 697807 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74753 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 74753 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249005 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 249005 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14114 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14114 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 323758 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 323758 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 323758 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 323758 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417058 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 417058 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298824 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298824 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121668 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 121668 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8233 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8233 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 715939 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 715939 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 837701 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 837701 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5703446143 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5703446143 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12331014162 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12331014162 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562604290 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562604290 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 106206750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 106206750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18034460305 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18034460305 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19597064595 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19597064595 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5836567000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5836567000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4510270500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4510270500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346837500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346837500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017746 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017746 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015886 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015886 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.231300 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.231300 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017704 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017704 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 715882 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 715882 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 837550 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 837550 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 31128 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5703692140 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5703692140 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12347213418 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12347213418 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562689830 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562689830 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 105383000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 105383000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 164000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18050905558 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18050905558 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19613595388 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19613595388 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5837245750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5837245750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4509635000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4509635000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346880750 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346880750 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017664 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017664 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015849 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015849 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.231099 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.231099 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017665 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017665 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016919 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016919 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019553 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019553 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13670.313419 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13670.313419 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41278.815506 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41278.815506 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12833.267276 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12833.267276 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12873.545455 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12873.545455 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81250 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81250 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25189.939792 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25189.939792 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23393.865586 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23393.865586 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016858 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016858 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019482 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019482 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13676.016621 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13676.016621 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41319.349912 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41319.349912 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12843.885245 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12843.885245 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12800.072877 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12800.072877 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25214.917484 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25214.917484 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23417.820295 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23417.820295 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187523.957530 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187523.957530 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163493.274843 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163493.274843 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176234.108600 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176234.108600 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2897467 # number of replacements -system.cpu.icache.tags.tagsinuse 511.399907 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 54681814 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2897979 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.868948 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2897053 # number of replacements +system.cpu.icache.tags.tagsinuse 511.399913 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 54794053 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2897565 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.910379 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 15532087250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.399907 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.399913 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998828 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998828 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 196 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60477795 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60477795 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 54681814 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54681814 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54681814 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54681814 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 54681814 # number of overall hits -system.cpu.icache.overall_hits::total 54681814 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 2897991 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 2897991 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 2897991 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 2897991 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 2897991 # number of overall misses -system.cpu.icache.overall_misses::total 2897991 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39294300362 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39294300362 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39294300362 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39294300362 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39294300362 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39294300362 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 57579805 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 57579805 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 57579805 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 57579805 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 57579805 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 57579805 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050330 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.050330 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.050330 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.050330 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.050330 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.050330 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13559.151965 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13559.151965 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13559.151965 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13559.151965 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13559.151965 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13559.151965 # average overall miss latency +system.cpu.icache.tags.tag_accesses 60589206 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60589206 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 54794053 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 54794053 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 54794053 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 54794053 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 54794053 # number of overall hits +system.cpu.icache.overall_hits::total 54794053 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 2897577 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 2897577 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 2897577 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 2897577 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 2897577 # number of overall misses +system.cpu.icache.overall_misses::total 2897577 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39289899153 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39289899153 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39289899153 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39289899153 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39289899153 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39289899153 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 57691630 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 57691630 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 57691630 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 57691630 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 57691630 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 57691630 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050225 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.050225 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.050225 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.050225 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.050225 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.050225 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13559.570342 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13559.570342 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13559.570342 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13559.570342 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13559.570342 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13559.570342 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -760,196 +768,200 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897991 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 2897991 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 2897991 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 2897991 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 2897991 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 2897991 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34937740638 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 34937740638 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34937740638 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 34937740638 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34937740638 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 34937740638 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897577 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 2897577 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 2897577 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2897577 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 2897577 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2897577 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3172 # number of ReadReq MSHR uncacheable +system.cpu.icache.ReadReq_mshr_uncacheable::total 3172 # number of ReadReq MSHR uncacheable +system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3172 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 3172 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34933961847 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 34933961847 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34933961847 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 34933961847 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34933961847 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 34933961847 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 247386750 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 247386750 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 247386750 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 247386750 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050330 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050330 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050330 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.050330 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050330 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.050330 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12055.848565 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12055.848565 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12055.848565 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12055.848565 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12055.848565 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12055.848565 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050225 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050225 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050225 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.050225 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050225 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.050225 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12056.266959 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12056.266959 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12056.266959 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12056.266959 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12056.266959 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12056.266959 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77990.778689 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77990.778689 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77990.778689 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77990.778689 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 96766 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65065.875064 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4045925 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 162028 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.970530 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 97102 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65057.867689 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4043768 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 162361 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 24.906030 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 47500.722639 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 67.826977 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000383 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 12189.076144 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5308.248921 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.724804 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 47470.110176 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 67.851294 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.009474 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 12225.097724 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5294.799022 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.724336 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001035 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.185991 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.080997 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.992826 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 44 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65218 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 44 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186540 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.080792 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.992704 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65201 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 58 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2302 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6937 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55861 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995148 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 36601578 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 36601578 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 70583 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4448 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 2875013 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 532926 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3482970 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 698329 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 698329 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 53 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 53 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 164703 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 164703 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 70583 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 4448 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 2875013 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 697629 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3647673 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 70583 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 4448 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 2875013 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 697629 # number of overall hits -system.cpu.l2cache.overall_hits::total 3647673 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 121 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 22948 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 14295 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 37365 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2778 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2778 # number of UpgradeReq misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6944 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55834 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000885 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994888 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 36586462 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 36586462 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69776 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4408 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 2874567 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 532630 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 3481381 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 697807 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 697807 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 52 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 52 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 164524 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 164524 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 69776 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 4408 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 2874567 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 697154 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3645905 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 69776 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 4408 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 2874567 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 697154 # number of overall hits +system.cpu.l2cache.overall_hits::total 3645905 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 120 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 22985 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 14324 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 37431 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2777 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2777 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 131196 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 131196 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 121 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 22948 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 145491 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 168561 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 121 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 22948 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 145491 # number of overall misses -system.cpu.l2cache.overall_misses::total 168561 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 10389500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 82500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1838002000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1203040290 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3051514290 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1092965 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 1092965 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10205321187 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10205321187 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 10389500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 82500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1838002000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11408361477 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13256835477 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 10389500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 82500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1838002000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11408361477 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13256835477 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 70704 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4449 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 2897961 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 547221 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 3520335 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 698329 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 698329 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2831 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2831 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 131476 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 131476 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 120 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 22985 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 145800 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 168907 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 120 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 22985 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 145800 # number of overall misses +system.cpu.l2cache.overall_misses::total 168907 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 10600250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 179750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1839480250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1206111580 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3056371830 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1094965 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 1094965 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10223101190 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10223101190 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 10600250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 179750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1839480250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11429212770 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13279473020 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 10600250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 179750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1839480250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11429212770 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13279473020 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69896 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4410 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 2897552 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 546954 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 3518812 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 697807 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 697807 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2829 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2829 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 295899 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 295899 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 70704 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 4449 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 2897961 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 843120 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 3816234 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 70704 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 4449 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2897961 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 843120 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 3816234 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001711 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000225 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.007919 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026123 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.010614 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.981279 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.981279 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 296000 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 296000 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69896 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 4410 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 2897552 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 842954 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 3814812 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69896 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 4410 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 2897552 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 842954 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 3814812 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001717 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000454 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.007933 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026189 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.010637 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.981619 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.981619 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.443381 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.443381 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001711 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000225 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007919 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.172563 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.044169 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001711 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000225 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007919 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.172563 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.044169 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85863.636364 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80094.213003 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84158.117524 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 81667.718185 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 393.435925 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 393.435925 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80250 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80250 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77786.831817 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77786.831817 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85863.636364 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80094.213003 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78412.832938 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78647.109812 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85863.636364 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80094.213003 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78412.832938 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78647.109812 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.444176 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.444176 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001717 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000454 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007933 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.172963 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.044277 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001717 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000454 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007933 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.172963 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.044277 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88335.416667 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89875 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80029.595388 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84202.148841 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 81653.491224 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 394.297803 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 394.297803 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 81000 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 81000 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77756.405656 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77756.405656 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88335.416667 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89875 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80029.595388 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78389.662346 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78620.027708 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88335.416667 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89875 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80029.595388 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78389.662346 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78620.027708 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -958,164 +970,170 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 88357 # number of writebacks -system.cpu.l2cache.writebacks::total 88357 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 18 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 143 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 161 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 18 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 143 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 161 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 18 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 143 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 161 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 121 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 22930 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14152 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 37204 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2778 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2778 # number of UpgradeReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 88550 # number of writebacks +system.cpu.l2cache.writebacks::total 88550 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 20 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 140 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 160 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 20 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 140 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 160 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 20 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 140 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 160 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 120 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 22965 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14184 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 37271 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2777 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2777 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131196 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 131196 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 121 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 22930 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 145348 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 168400 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 121 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 22930 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 145348 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 168400 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 8873000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 70000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1549821750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1015754460 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2574519210 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 49350278 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 49350278 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 136000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 136000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8563537813 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8563537813 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8873000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 70000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1549821750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9579292273 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11138057023 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8873000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 70000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1549821750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9579292273 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11138057023 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131476 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 131476 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 120 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 22965 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 145660 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 168747 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 120 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 22965 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 145660 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 168747 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3172 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34300 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3172 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61883 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 9096750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 154250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1550905750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1018516170 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2578672920 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 49510277 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 49510277 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 137000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 137000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8577805310 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8577805310 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 9096750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 154250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1550905750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9596321480 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11156478230 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 9096750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 154250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1550905750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9596321480 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11156478230 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 191729750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5400289500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5592019250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151564500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151564500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5400947000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5592676750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4150934000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4150934000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 191729750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9551854000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9743583750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001711 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000225 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025862 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010568 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.981279 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9551881000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9743610750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000454 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007926 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025933 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010592 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.981619 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.981619 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.443381 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443381 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001711 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000225 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172393 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.044127 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001711 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000225 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172393 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.044127 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73330.578512 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67589.260794 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71774.622668 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69200.064778 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17764.678906 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17764.678906 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65272.857503 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65272.857503 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73330.578512 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67589.260794 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65905.910456 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66140.481134 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73330.578512 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67589.260794 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65905.910456 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66140.481134 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.444176 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.444176 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000454 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007926 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172797 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.044235 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000454 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007926 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172797 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.044235 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75806.250000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 77125 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67533.453081 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71807.400592 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69187.113842 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17828.691754 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17828.691754 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65242.365983 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65242.365983 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75806.250000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 77125 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67533.453081 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65881.652341 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66113.638939 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75806.250000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 77125 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67533.453081 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65881.652341 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66113.638939 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60444.435687 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173507.677975 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163051.800292 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150488.851829 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150488.851829 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60444.435687 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162693.209109 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157452.139521 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3579472 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3579378 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3578143 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3578049 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 698329 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2831 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 697807 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2829 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2833 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295899 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295899 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5802295 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2507794 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15026 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159855 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8484970 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185672448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98844821 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17796 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 282816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 284817881 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 61238 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4578493 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.007970 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.088920 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2831 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296000 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296000 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5801472 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506940 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14959 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 158425 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8481796 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185646272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98800797 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 279584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 284744293 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 61425 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4638617 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.029225 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.168438 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4542001 99.20% 99.20% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 36492 0.80% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4503052 97.08% 97.08% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 135565 2.92% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4578493 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3014061750 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4638617 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3012663750 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 211500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4357263112 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4356641403 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1342100655 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1341917112 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10577000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 10549250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 89155750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 88533000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution @@ -1212,23 +1230,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198870981 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198836241 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36810507 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36810509 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.031296 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.031382 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270543128000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.031296 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064456 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064456 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270536492000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.031382 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064461 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064461 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1242,14 +1260,14 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29239875 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29239875 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6646548599 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6646548599 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29239875 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29239875 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29239875 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29239875 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29235877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29235877 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6642330855 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6642330855 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29235877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29235877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29235877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29235877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1266,19 +1284,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124956.730769 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124956.730769 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183484.667596 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183484.667596 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124956.730769 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124956.730769 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124956.730769 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124956.730769 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22676 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124939.645299 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124939.645299 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183368.232525 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183368.232525 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124939.645299 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124939.645299 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124939.645299 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124939.645299 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22431 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3466 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3441 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.542412 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.518745 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1292,14 +1310,14 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16928877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16928877 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4762888611 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4762888611 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16928877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16928877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16928877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16928877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16926877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16926877 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4758664873 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4758664873 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16926877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16926877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16926877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16926877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1308,66 +1326,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72345.628205 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72345.628205 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131484.336655 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131484.336655 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72345.628205 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72345.628205 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72345.628205 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72345.628205 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72337.081197 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72337.081197 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131367.736114 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131367.736114 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72337.081197 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72337.081197 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72337.081197 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72337.081197 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 71736 # Transaction distribution -system.membus.trans_dist::ReadResp 71736 # Transaction distribution +system.membus.trans_dist::ReadReq 71805 # Transaction distribution +system.membus.trans_dist::ReadResp 71805 # Transaction distribution system.membus.trans_dist::WriteReq 27583 # Transaction distribution system.membus.trans_dist::WriteResp 27583 # Transaction distribution -system.membus.trans_dist::Writeback 124547 # Transaction distribution +system.membus.trans_dist::Writeback 124740 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4591 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4587 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4593 # Transaction distribution -system.membus.trans_dist::ReadExReq 129383 # Transaction distribution -system.membus.trans_dist::ReadExResp 129383 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4589 # Transaction distribution +system.membus.trans_dist::ReadExReq 129666 # Transaction distribution +system.membus.trans_dist::ReadExResp 129666 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446633 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554193 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447521 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 555081 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 663080 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 663968 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16520600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16684309 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16555296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16719005 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21319765 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 505 # Total snoops (count) -system.membus.snoop_fanout::samples 332236 # Request fanout histogram +system.membus.pkt_size::total 21354461 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 506 # Total snoops (count) +system.membus.snoop_fanout::samples 394644 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 332236 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 394644 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 332236 # Request fanout histogram -system.membus.reqLayer0.occupancy 90365500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 394644 # Request fanout histogram +system.membus.reqLayer0.occupancy 90290000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1715000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1707500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1025055153 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1026254667 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 997764949 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 999643493 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37471493 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 37473491 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 6373b7480..7a207cc8a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.827616 # Nu sim_ticks 2827616186000 # Number of ticks simulated final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73888 # Simulator instruction rate (inst/s) -host_op_rate 89625 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1846444734 # Simulator tick rate (ticks/s) -host_mem_usage 556020 # Number of bytes of host memory used -host_seconds 1531.38 # Real time elapsed on the host +host_inst_rate 70271 # Simulator instruction rate (inst/s) +host_op_rate 85238 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1756065639 # Simulator tick rate (ticks/s) +host_mem_usage 621588 # Number of bytes of host memory used +host_seconds 1610.20 # Real time elapsed on the host sim_insts 113151083 # Number of instructions simulated sim_ops 137250963 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -16,9 +16,9 @@ system.clk_domain.clock 1000 # Cl system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1325344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9769956 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9769960 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11098052 # Number of bytes read from this memory +system.physmem.bytes_read::total 11098056 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1325344 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1325344 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 8387584 # Number of bytes written to this memory @@ -27,18 +27,18 @@ system.physmem.bytes_written::total 8405108 # Nu system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 22954 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 153175 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 153176 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 176172 # Number of read requests responded to by this memory +system.physmem.num_reads::total 176173 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 131056 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::total 135437 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 468714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3455192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3455193 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3924879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3924881 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 468714 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 468714 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 2966309 # Write bandwidth from this memory (bytes/s) @@ -48,19 +48,19 @@ system.physmem.bw_total::writebacks 2966309 # To system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 468714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3461389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3461391 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6897386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 176173 # Number of read requests accepted +system.physmem.bw_total::total 6897387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 176174 # Number of read requests accepted system.physmem.writeReqs 171661 # Number of write requests accepted -system.physmem.readBursts 176173 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 176174 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 171661 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 11266304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue +system.physmem.bytesReadWrQ 8832 # Total number of bytes read from write queue system.physmem.bytesWritten 9457344 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11098116 # Total read bytes from the system interface side +system.physmem.bytesReadSys 11098120 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 10723444 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 138 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 23861 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4579 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 11334 # Per bank write bursts @@ -100,7 +100,7 @@ system.physmem.numWrRetry 58 # Nu system.physmem.totGap 2827615975000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 541 # Read request sizes (log2) +system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 2994 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) @@ -265,12 +265,12 @@ system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Wr system.physmem.wrPerTurnAround::752-767 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 6252 # Writes before turning the bus around for reads -system.physmem.totQLat 2104910750 # Total ticks spent queuing -system.physmem.totMemAccLat 5405585750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2104913750 # Total ticks spent queuing +system.physmem.totMemAccLat 5405588750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 880180000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11957.27 # Average queueing delay per DRAM burst +system.physmem.avgQLat 11957.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30707.27 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30707.29 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.34 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s @@ -285,35 +285,35 @@ system.physmem.readRowHits 145058 # Nu system.physmem.writeRowHits 112529 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes -system.physmem.avgGap 8129210.99 # Average gap between requests +system.physmem.avgGap 8129187.62 # Average gap between requests system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 260517600 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 142147500 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 718356600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 486693360 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 81488168145 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625088669750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1892870659755 # Total energy per rank (pJ) +system.physmem_0.actBackEnergy 81488169855 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625088668250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1892870659965 # Total energy per rank (pJ) system.physmem_0.averagePower 669.422846 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2703351125494 # Time in different power states +system.physmem_0.memoryStateTime::IDLE 2703351122494 # Time in different power states system.physmem_0.memoryStateTime::REF 94420300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 29844453256 # Time in different power states +system.physmem_0.memoryStateTime::ACT 29844456256 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 240098040 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 131005875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 654716400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 470862720 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 80123989140 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1626285318000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1892592096975 # Total energy per rank (pJ) +system.physmem_1.actBackEnergy 80123990850 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626285316500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1892592097185 # Total energy per rank (pJ) system.physmem_1.averagePower 669.324331 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2705354979994 # Time in different power states +system.physmem_1.memoryStateTime::IDLE 2705354976994 # Time in different power states system.physmem_1.memoryStateTime::REF 94420300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27840892506 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27840895506 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory @@ -570,7 +570,7 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7962 system.cpu.dtb.walker.walkRequestOrigin::total 80333 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25461870 # DTB read hits +system.cpu.dtb.read_hits 25461869 # DTB read hits system.cpu.dtb.read_misses 62291 # DTB read misses system.cpu.dtb.write_hits 19915387 # DTB write hits system.cpu.dtb.write_misses 10080 # DTB write misses @@ -583,12 +583,12 @@ system.cpu.dtb.align_faults 348 # Nu system.cpu.dtb.prefetch_faults 2290 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 1335 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25524161 # DTB read accesses +system.cpu.dtb.read_accesses 25524160 # DTB read accesses system.cpu.dtb.write_accesses 19925467 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45377257 # DTB hits +system.cpu.dtb.hits 45377256 # DTB hits system.cpu.dtb.misses 72371 # DTB misses -system.cpu.dtb.accesses 45449628 # DTB accesses +system.cpu.dtb.accesses 45449627 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -730,15 +730,15 @@ system.cpu.decode.SquashedInsts 3690202 # Nu system.cpu.rename.SquashCycles 2601803 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 83861883 # Number of cycles rename is idle system.cpu.rename.BlockCycles 10277178 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 74822970 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 74822964 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 62634848 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 22677863 # Number of cycles rename is unblocking +system.cpu.rename.UnblockCycles 22677869 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 146804130 # Number of instructions processed by rename system.cpu.rename.SquashedInsts 949467 # Number of squashed instructions processed by rename system.cpu.rename.ROBFullEvents 441862 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 64017 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 17858 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 19908146 # Number of times rename has blocked due to SQ full +system.cpu.rename.SQFullEvents 19908152 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 150492299 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 678751292 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 164435882 # Number of integer rename lookups @@ -754,7 +754,7 @@ system.cpu.memDep0.conflictingLoads 1687720 # Nu system.cpu.memDep0.conflictingStores 2166938 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 143540852 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143328299 # Number of instructions issued +system.cpu.iq.iqInstsIssued 143328298 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 8409052 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph @@ -763,8 +763,8 @@ system.cpu.iq.issued_per_cycle::samples 256876545 # Nu system.cpu.iq.issued_per_cycle::mean 0.557966 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 0.879925 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 168573863 65.62% 65.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45206233 17.60% 83.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 168573864 65.62% 65.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45206232 17.60% 83.22% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 31980064 12.45% 95.67% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 10303635 4.01% 99.68% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 812717 0.32% 100.00% # Number of insts issued each cycle @@ -840,21 +840,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 8586 0.01% 67.07% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26193107 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26193106 18.27% 85.34% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 21007096 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143328299 # Type of FU issued +system.cpu.iq.FU_type_0::total 143328298 # Type of FU issued system.cpu.iq.rate 0.544758 # Inst issue rate system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 566346239 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 566346237 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 154074171 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 13216 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165879209 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 165879208 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 323617 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -864,7 +864,7 @@ system.cpu.iew.lsq.thread0.memOrderViolation 18357 system.cpu.iew.lsq.thread0.squashedStores 705133 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 87835 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 87833 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 6849 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 2601803 # Number of cycles IEW is squashing @@ -881,16 +881,16 @@ system.cpu.iew.memOrderViolationEvents 18357 # Nu system.cpu.iew.predictedTakenIncorrect 317506 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 471434 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 788940 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142382518 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25789726 # Number of load instructions executed +system.cpu.iew.iewExecutedInsts 142382517 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25789725 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 873528 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 201053 # number of nop insts executed -system.cpu.iew.exec_refs 46667575 # number of memory reference insts executed +system.cpu.iew.exec_refs 46667574 # number of memory reference insts executed system.cpu.iew.exec_branches 26530134 # Number of branches executed system.cpu.iew.exec_stores 20877849 # Number of stores executed system.cpu.iew.exec_rate 0.541163 # Inst execution rate -system.cpu.iew.wb_sent 141996043 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent 141996041 # cumulative count of insts sent to commit system.cpu.iew.wb_count 140222490 # cumulative count of insts written-back system.cpu.iew.wb_producers 63271750 # num instructions producing a value system.cpu.iew.wb_consumers 95823649 # num instructions consuming a value @@ -975,13 +975,13 @@ system.cpu.cpi 2.325250 # CP system.cpu.cpi_total 2.325250 # CPI: Total CPI of All Threads system.cpu.ipc 0.430061 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.430061 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155826637 # number of integer regfile reads +system.cpu.int_regfile_reads 155826636 # number of integer regfile reads system.cpu.int_regfile_writes 88633022 # number of integer regfile writes system.cpu.fp_regfile_reads 9606 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502981884 # number of cc regfile reads +system.cpu.cc_regfile_reads 502981881 # number of cc regfile reads system.cpu.cc_regfile_writes 53178096 # number of cc regfile writes -system.cpu.misc_regfile_reads 446088161 # number of misc regfile reads +system.cpu.misc_regfile_reads 446088160 # number of misc regfile reads system.cpu.misc_regfile_writes 1519760 # number of misc regfile writes system.cpu.dcache.tags.replacements 839617 # number of replacements system.cpu.dcache.tags.tagsinuse 511.954240 # Cycle average of tags in use @@ -1029,16 +1029,16 @@ system.cpu.dcache.overall_misses::cpu.data 4478306 # system.cpu.dcache.overall_misses::total 4478306 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 10273111663 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 10273111663 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502760344 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 149502760344 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502808344 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 149502808344 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365521996 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 365521996 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 209000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 209000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 159775872007 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 159775872007 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 159775872007 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 159775872007 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 159775920007 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 159775920007 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 159775920007 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 159775920007 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 24021805 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 24021805 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19156176 # number of WriteReq accesses(hits+misses) @@ -1069,16 +1069,16 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.102475 system.cpu.dcache.overall_miss_rate::total 0.102475 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14556.964202 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 14556.964202 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.568194 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.568194 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.581546 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.581546 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13607.400640 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13607.400640 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.680485 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37149.680485 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.747793 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35677.747793 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.691645 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37149.691645 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.758511 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35677.758511 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 582483 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 7397 # number of cycles access was blocked @@ -1113,26 +1113,32 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 714916 system.cpu.dcache.demand_mshr_misses::total 714916 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 834525 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 834525 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5660697158 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 5660697158 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235278165 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235278165 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235281165 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235281165 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562991253 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562991253 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 123125251 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 123125251 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895975323 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18895975323 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458966576 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20458966576 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831900750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831900750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895978323 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18895978323 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458969576 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20458969576 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831942750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831942750 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4511868951 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4511868951 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343769701 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343769701 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343811701 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343811701 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017261 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017261 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015675 # mshr miss rate for WriteReq accesses @@ -1149,24 +1155,24 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019096 system.cpu.dcache.overall_mshr_miss_rate::total 0.019096 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13652.043956 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13652.043956 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.189793 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.189793 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.199784 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.199784 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13067.505397 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13067.505397 # average SoftPFReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14692.750716 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14692.750716 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40300 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40300 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.042700 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.042700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.702437 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.702437 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.046896 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.046896 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.706032 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.706032 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187359.615446 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187359.615446 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163568.334941 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163568.334941 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176181.834767 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176181.834767 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1892540 # number of replacements system.cpu.icache.tags.tagsinuse 511.345997 # Cycle average of tags in use @@ -1241,6 +1247,10 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1893071 system.cpu.icache.demand_mshr_misses::total 1893071 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1893071 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1893071 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable +system.cpu.icache.ReadReq_mshr_uncacheable::total 3002 # number of ReadReq MSHR uncacheable +system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 3002 # number of overall MSHR uncacheable misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23219754000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 23219754000 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23219754000 # number of demand (read+write) MSHR miss cycles @@ -1263,10 +1273,10 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12265.654062 system.cpu.icache.demand_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75071.952032 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75071.952032 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 103160 # number of replacements system.cpu.l2cache.tags.tagsinuse 65071.102218 # Cycle average of tags in use @@ -1350,18 +1360,18 @@ system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 966469 system.cpu.l2cache.UpgradeReq_miss_latency::total 966469 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 165000 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 165000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197750141 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11197750141 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197753141 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 11197753141 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1759750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 789750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 1637862750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12425243891 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14065656141 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12425246891 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14065659141 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1759750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 789750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 1637862750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12425243891 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14065656141 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12425246891 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14065659141 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 56051 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12594 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 1893036 # number of ReadReq accesses(hits+misses) @@ -1415,18 +1425,18 @@ system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 355.319485 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 355.319485 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82500 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82500 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.605529 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.605529 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.626875 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.626875 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80430.790095 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80430.807250 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80430.790095 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80430.807250 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1467,6 +1477,14 @@ system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 system.cpu.l2cache.overall_mshr_misses::cpu.inst 19963 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 154754 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 174745 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34129 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61713 # number of overall MSHR uncacheable misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1495250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 701750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1386544250 # number of ReadReq MSHR miss cycles @@ -1476,26 +1494,26 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48397220 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48397220 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440466859 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440466859 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440469859 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440469859 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1495250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 701750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1386544250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482081359 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11870822609 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482084359 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11870825609 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1495250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 701750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1386544250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482081359 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11870822609 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482084359 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11870825609 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 181832000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395641750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577473750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395669750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577501750 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151610000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151610000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 181832000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547251750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729083750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547279750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729111750 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for ReadReq accesses @@ -1526,29 +1544,29 @@ system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17793.095588 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17793.095588 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.811008 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.811008 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.832354 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.832354 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173343.712854 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163424.118785 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150507.903132 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150507.903132 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162614.837935 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157650.928492 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2564423 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2564403 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2564424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2564404 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 696320 # Transaction distribution @@ -1559,38 +1577,34 @@ system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # system.cpu.toL2Bus.trans_dist::ReadExReq 297641 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 297641 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3792109 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499775 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499777 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 131034 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6455012 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6455014 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121202208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530841 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530845 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50376 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224204 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 220007629 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 220007633 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 62589 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3563285 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.010244 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.100691 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 3624998 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.036134 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.186622 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3526784 98.98% 98.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 36501 1.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3494014 96.39% 96.39% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 130984 3.61% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3563285 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2504368234 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3624998 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2504368734 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 2847443747 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1338895897 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1338896897 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 19507738 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) @@ -1796,8 +1810,8 @@ system.iocache.demand_avg_mshr_miss_latency::total 70600.330472 system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 68566 # Transaction distribution -system.membus.trans_dist::ReadResp 68565 # Transaction distribution +system.membus.trans_dist::ReadReq 68567 # Transaction distribution +system.membus.trans_dist::ReadResp 68566 # Transaction distribution system.membus.trans_dist::WriteReq 27584 # Transaction distribution system.membus.trans_dist::WriteResp 27584 # Transaction distribution system.membus.trans_dist::Writeback 131056 # Transaction distribution @@ -1811,40 +1825,40 @@ system.membus.trans_dist::ReadExResp 138681 # Tr system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465380 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572944 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465382 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572946 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108886 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108886 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 681830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 681832 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349433 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186044 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349437 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21984889 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21984893 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 497 # Total snoops (count) -system.membus.snoop_fanout::samples 345038 # Request fanout histogram +system.membus.snoop_fanout::samples 406751 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 345038 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 406751 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 345038 # Request fanout histogram +system.membus.snoop_fanout::total 406751 # Request fanout histogram system.membus.reqLayer0.occupancy 83856500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 1725500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1057991143 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1057992643 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1020411671 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1020413671 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 37506490 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 444c7dd71..f9cde53a3 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,166 +1,166 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.625396 # Number of seconds simulated -sim_ticks 2625395606000 # Number of ticks simulated -final_tick 2625395606000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.625378 # Number of seconds simulated +sim_ticks 2625378187500 # Number of ticks simulated +final_tick 2625378187500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93034 # Simulator instruction rate (inst/s) -host_op_rate 112875 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2029681489 # Simulator tick rate (ticks/s) -host_mem_usage 651304 # Number of bytes of host memory used -host_seconds 1293.50 # Real time elapsed on the host -sim_insts 120339436 # Number of instructions simulated -sim_ops 146004136 # Number of ops (including micro ops) simulated +host_inst_rate 94574 # Simulator instruction rate (inst/s) +host_op_rate 114754 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2065319127 # Simulator tick rate (ticks/s) +host_mem_usage 650700 # Number of bytes of host memory used +host_seconds 1271.17 # Real time elapsed on the host +sim_insts 120220550 # Number of instructions simulated +sim_ops 145872273 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 1792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1180896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1238652 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8338496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1156128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1193576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8234944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 327120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 750304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 683328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 336832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 657616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 605504 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12522572 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1180896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 327120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1508016 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8921792 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory +system.physmem.bytes_read::total 12188376 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1156128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 336832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1492960 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8634432 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8939536 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 28 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8651996 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 20697 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 19879 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 130289 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 20310 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 19170 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 128671 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5178 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 11747 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 10677 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5329 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10295 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 9461 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198526 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 139403 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory +system.physmem.num_reads::total 193295 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 134913 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143839 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 683 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 139304 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 658 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 449797 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 471796 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3176091 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 440366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 454630 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3136670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 268 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 124598 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 285787 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 260276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 128298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 250484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 230635 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4769785 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 449797 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 124598 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 574396 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3398266 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6743 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4642522 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 440366 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 128298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 568665 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3288834 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6675 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3405024 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3398266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 683 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3295524 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3288834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 658 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 449797 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 478540 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3176091 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 440366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 461305 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3136670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 268 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 124598 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 285802 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 260276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 128298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 250500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 230635 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 8174809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198527 # Number of read requests accepted -system.physmem.writeReqs 180063 # Number of write requests accepted -system.physmem.readBursts 198527 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 180063 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12696000 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9728 # Total number of bytes read from write queue -system.physmem.bytesWritten 10018560 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12522636 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11257872 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23492 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14407 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12827 # Per bank write bursts -system.physmem.perBankRdBursts::1 12491 # Per bank write bursts -system.physmem.perBankRdBursts::2 12947 # Per bank write bursts -system.physmem.perBankRdBursts::3 12890 # Per bank write bursts -system.physmem.perBankRdBursts::4 14947 # Per bank write bursts -system.physmem.perBankRdBursts::5 12185 # Per bank write bursts -system.physmem.perBankRdBursts::6 12844 # Per bank write bursts -system.physmem.perBankRdBursts::7 12385 # Per bank write bursts -system.physmem.perBankRdBursts::8 12025 # Per bank write bursts -system.physmem.perBankRdBursts::9 12120 # Per bank write bursts -system.physmem.perBankRdBursts::10 11888 # Per bank write bursts -system.physmem.perBankRdBursts::11 11181 # Per bank write bursts -system.physmem.perBankRdBursts::12 11694 # Per bank write bursts -system.physmem.perBankRdBursts::13 12452 # Per bank write bursts -system.physmem.perBankRdBursts::14 11831 # Per bank write bursts -system.physmem.perBankRdBursts::15 11668 # Per bank write bursts -system.physmem.perBankWrBursts::0 10196 # Per bank write bursts -system.physmem.perBankWrBursts::1 10156 # Per bank write bursts -system.physmem.perBankWrBursts::2 10450 # Per bank write bursts -system.physmem.perBankWrBursts::3 10103 # Per bank write bursts -system.physmem.perBankWrBursts::4 9839 # Per bank write bursts -system.physmem.perBankWrBursts::5 9619 # Per bank write bursts -system.physmem.perBankWrBursts::6 10216 # Per bank write bursts -system.physmem.perBankWrBursts::7 9774 # Per bank write bursts -system.physmem.perBankWrBursts::8 9494 # Per bank write bursts -system.physmem.perBankWrBursts::9 9611 # Per bank write bursts -system.physmem.perBankWrBursts::10 9445 # Per bank write bursts -system.physmem.perBankWrBursts::11 9199 # Per bank write bursts -system.physmem.perBankWrBursts::12 9616 # Per bank write bursts -system.physmem.perBankWrBursts::13 9900 # Per bank write bursts -system.physmem.perBankWrBursts::14 9667 # Per bank write bursts -system.physmem.perBankWrBursts::15 9255 # Per bank write bursts +system.physmem.bw_total::total 7938046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 193296 # Number of read requests accepted +system.physmem.writeReqs 175528 # Number of write requests accepted +system.physmem.readBursts 193296 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 175528 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12362624 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue +system.physmem.bytesWritten 9724800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12188440 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10970332 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23562 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14506 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12287 # Per bank write bursts +system.physmem.perBankRdBursts::1 11514 # Per bank write bursts +system.physmem.perBankRdBursts::2 12472 # Per bank write bursts +system.physmem.perBankRdBursts::3 12180 # Per bank write bursts +system.physmem.perBankRdBursts::4 14590 # Per bank write bursts +system.physmem.perBankRdBursts::5 12444 # Per bank write bursts +system.physmem.perBankRdBursts::6 12518 # Per bank write bursts +system.physmem.perBankRdBursts::7 12466 # Per bank write bursts +system.physmem.perBankRdBursts::8 11679 # Per bank write bursts +system.physmem.perBankRdBursts::9 12089 # Per bank write bursts +system.physmem.perBankRdBursts::10 11915 # Per bank write bursts +system.physmem.perBankRdBursts::11 11053 # Per bank write bursts +system.physmem.perBankRdBursts::12 11299 # Per bank write bursts +system.physmem.perBankRdBursts::13 11450 # Per bank write bursts +system.physmem.perBankRdBursts::14 11880 # Per bank write bursts +system.physmem.perBankRdBursts::15 11330 # Per bank write bursts +system.physmem.perBankWrBursts::0 9713 # Per bank write bursts +system.physmem.perBankWrBursts::1 9189 # Per bank write bursts +system.physmem.perBankWrBursts::2 10054 # Per bank write bursts +system.physmem.perBankWrBursts::3 9647 # Per bank write bursts +system.physmem.perBankWrBursts::4 9435 # Per bank write bursts +system.physmem.perBankWrBursts::5 9608 # Per bank write bursts +system.physmem.perBankWrBursts::6 10036 # Per bank write bursts +system.physmem.perBankWrBursts::7 9866 # Per bank write bursts +system.physmem.perBankWrBursts::8 9192 # Per bank write bursts +system.physmem.perBankWrBursts::9 9471 # Per bank write bursts +system.physmem.perBankWrBursts::10 9539 # Per bank write bursts +system.physmem.perBankWrBursts::11 9209 # Per bank write bursts +system.physmem.perBankWrBursts::12 9294 # Per bank write bursts +system.physmem.perBankWrBursts::13 9108 # Per bank write bursts +system.physmem.perBankWrBursts::14 9699 # Per bank write bursts +system.physmem.perBankWrBursts::15 8890 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 63 # Number of times write queue was full causing retry -system.physmem.totGap 2625395343000 # Total gap between requests +system.physmem.numWrRetry 46 # Number of times write queue was full causing retry +system.physmem.totGap 2625377925000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 559 # Read request sizes (log2) +system.physmem.readPktSize::2 550 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) -system.physmem.readPktSize::4 3083 # Read request sizes (log2) +system.physmem.readPktSize::4 3082 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 194857 # Read request sizes (log2) +system.physmem.readPktSize::6 189636 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 4436 # Write request sizes (log2) +system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 175627 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 60901 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 71603 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 16635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12571 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6473 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1315 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 741 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 171137 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 58646 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7467 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5177 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4683 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 715 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 259 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -188,161 +188,158 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 224 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 91717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 247.658515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 138.206739 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 311.047088 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 48645 53.04% 53.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18050 19.68% 72.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5879 6.41% 79.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3418 3.73% 82.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2896 3.16% 86.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1497 1.63% 87.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 939 1.02% 88.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1042 1.14% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9351 10.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 91717 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6649 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.834862 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 569.193500 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6647 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1075 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 82 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 87477 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 252.493341 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.519371 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 314.341475 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 45925 52.50% 52.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16983 19.41% 71.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5819 6.65% 78.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3357 3.84% 82.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2775 3.17% 85.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1460 1.67% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 948 1.08% 88.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 995 1.14% 89.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9215 10.53% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 87477 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6395 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.205629 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 580.308341 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6393 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6649 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6649 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.543390 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.659302 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 38.965105 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 6283 94.50% 94.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 92 1.38% 95.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 34 0.51% 96.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 12 0.18% 96.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 28 0.42% 96.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 36 0.54% 97.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 35 0.53% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 13 0.20% 98.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 17 0.26% 98.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 4 0.06% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 17 0.26% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 15 0.23% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 12 0.18% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.03% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 5 0.08% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 5 0.08% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 1 0.02% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 2 0.03% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 5 0.08% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 4 0.06% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 13 0.20% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 1 0.02% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 3 0.05% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6649 # Writes before turning the bus around for reads -system.physmem.totQLat 7005041065 # Total ticks spent queuing -system.physmem.totMemAccLat 10724572315 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 991875000 # Total ticks spent in databus transfers -system.physmem.avgQLat 35312.12 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6395 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6395 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.760751 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.753987 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 37.694415 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 6028 94.26% 94.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 95 1.49% 95.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 28 0.44% 96.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 10 0.16% 96.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 24 0.38% 96.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 40 0.63% 97.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 30 0.47% 97.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 13 0.20% 98.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 18 0.28% 98.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 5 0.08% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 23 0.36% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 21 0.33% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 7 0.11% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 3 0.05% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.03% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 5 0.08% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 3 0.05% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 2 0.03% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 3 0.05% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 7 0.11% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 6 0.09% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 11 0.17% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6395 # Writes before turning the bus around for reads +system.physmem.totQLat 6824061250 # Total ticks spent queuing +system.physmem.totMemAccLat 10445923750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 965830000 # Total ticks spent in databus transfers +system.physmem.avgQLat 35327.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 54062.12 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.84 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.77 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.29 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 54077.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.71 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.70 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.64 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.18 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.07 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.13 # Average write queue length when enqueuing -system.physmem.readRowHits 165504 # Number of row buffer hits during reads -system.physmem.writeRowHits 97693 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.40 # Row buffer hit rate for writes -system.physmem.avgGap 6934666.38 # Average gap between requests -system.physmem.pageHitRate 74.15 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 361050480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 197001750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 807424800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 520687440 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 75248496990 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1509227374500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1757839822440 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.553437 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2510629171267 # Time in different power states -system.physmem_0.memoryStateTime::REF 87667580000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 27.24 # Average write queue length when enqueuing +system.physmem.readRowHits 161531 # Number of row buffer hits during reads +system.physmem.writeRowHits 96107 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 63.24 # Row buffer hit rate for writes +system.physmem.avgGap 7118240.48 # Average gap between requests +system.physmem.pageHitRate 74.65 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 340124400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 185583750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 783673800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 502511040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 171476769360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 74898468540 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1509525073500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1757712204390 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.508799 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2511124862587 # Time in different power states +system.physmem_0.memoryStateTime::REF 87667060000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27094642483 # Time in different power states +system.physmem_0.memoryStateTime::ACT 26583898663 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 332330040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 181330875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 739892400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 493691760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 74790166545 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1509629418750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1757644616850 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.479084 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2511304272827 # Time in different power states -system.physmem_1.memoryStateTime::REF 87667580000 # Time in different power states +system.physmem_1.actEnergy 321201720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 175258875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 723013200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 482124960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 171476769360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 74441693340 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1509925753500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1757545814955 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.445422 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2511799542258 # Time in different power states +system.physmem_1.memoryStateTime::REF 87667060000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 26423733173 # Time in different power states +system.physmem_1.memoryStateTime::ACT 25911565742 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory @@ -368,15 +365,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 51768532 # Number of BP lookups -system.cpu0.branchPred.condPredicted 23412360 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 919881 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 31255966 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 23302169 # Number of BTB hits +system.cpu0.branchPred.lookups 22612465 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14651481 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 907853 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 13732961 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 10133003 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 74.552708 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15318582 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 29481 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 73.786003 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3723828 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29274 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -407,86 +404,80 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 62660 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 62660 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 24194 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18908 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 19558 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 43102 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 433.564568 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 2585.553866 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-4095 41662 96.66% 96.66% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::4096-8191 436 1.01% 97.67% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-12287 432 1.00% 98.67% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::12288-16383 320 0.74% 99.42% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-20479 76 0.18% 99.59% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::20480-24575 60 0.14% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-28671 79 0.18% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::28672-32767 9 0.02% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-36863 4 0.01% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::36864-40959 3 0.01% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-45055 16 0.04% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::45056-49151 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-53247 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-61439 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 43102 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 15681 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 9053.791276 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 7430.926564 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 8773.860990 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 14744 94.02% 94.02% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 873 5.57% 99.59% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 41 0.26% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.03% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::114688-131071 1 0.01% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-212991 10 0.06% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::212992-229375 7 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 15681 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 91363987860 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.449877 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.503999 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 91318747860 99.95% 99.95% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 34013000 0.04% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 5422000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 3241000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 1011500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 587500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 452000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 501000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 12000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 91363987860 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5167 76.75% 76.75% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1565 23.25% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6732 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 62660 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 61748 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 61748 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 23984 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18764 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 19000 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 42748 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 436.289417 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 2694.039371 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 41732 97.62% 97.62% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 726 1.70% 99.32% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 177 0.41% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 77 0.18% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 11 0.03% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 19 0.04% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-57343 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 42748 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 15024 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 8664.869276 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 7136.607726 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7119.581025 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 14229 94.71% 94.71% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 745 4.96% 99.67% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 26 0.17% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.03% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-147455 16 0.11% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 15024 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 87051634064 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.443285 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.503059 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 87007241564 99.95% 99.95% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 33256500 0.04% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 5843000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 2996500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 874000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 581000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 581000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 249500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 11000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 87051634064 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5088 77.48% 77.48% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1479 22.52% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6567 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 61748 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 62660 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6732 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 61748 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6567 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6732 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 69392 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6567 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 68315 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 22710900 # DTB read hits -system.cpu0.dtb.read_misses 53664 # DTB read misses -system.cpu0.dtb.write_hits 16914206 # DTB write hits -system.cpu0.dtb.write_misses 8996 # DTB write misses +system.cpu0.dtb.read_hits 16748968 # DTB read hits +system.cpu0.dtb.read_misses 52995 # DTB read misses +system.cpu0.dtb.write_hits 13907664 # DTB write hits +system.cpu0.dtb.write_misses 8753 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3521 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 84 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1885 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3489 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 88 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2047 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 828 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 22764564 # DTB read accesses -system.cpu0.dtb.write_accesses 16923202 # DTB write accesses +system.cpu0.dtb.perms_faults 843 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 16801963 # DTB read accesses +system.cpu0.dtb.write_accesses 13916417 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 39625106 # DTB hits -system.cpu0.dtb.misses 62660 # DTB misses -system.cpu0.dtb.accesses 39687766 # DTB accesses +system.cpu0.dtb.hits 30656632 # DTB hits +system.cpu0.dtb.misses 61748 # DTB misses +system.cpu0.dtb.accesses 30718380 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -516,59 +507,56 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 9923 # Table walker walks requested -system.cpu0.itb.walker.walksShort 9923 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3743 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6075 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 105 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 9818 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 399.113872 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 2107.706971 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-4095 9439 96.14% 96.14% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-8191 239 2.43% 98.57% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-12287 79 0.80% 99.38% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-16383 28 0.29% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-20479 10 0.10% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-24575 11 0.11% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::28672-32767 5 0.05% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-36863 3 0.03% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 9818 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2687 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 10340.528470 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 8874.826622 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6037.575177 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 928 34.54% 34.54% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1618 60.22% 94.75% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 45 1.67% 96.43% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 85 3.16% 99.59% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 7 0.26% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 9874 # Table walker walks requested +system.cpu0.itb.walker.walksShort 9874 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3715 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6056 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 103 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 9771 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 366.390339 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 1951.164851 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 9421 96.42% 96.42% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 224 2.29% 98.71% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 80 0.82% 99.53% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 17 0.17% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 13 0.13% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 5 0.05% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::28672-32767 6 0.06% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-36863 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 9771 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2691 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 9965.812709 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 8554.132900 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5681.325139 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 1024 38.05% 38.05% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1554 57.75% 95.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 43 1.60% 97.40% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 63 2.34% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 4 0.15% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.07% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2687 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 18349502828 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.974755 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.157116 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 463854500 2.53% 2.53% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 17885129828 97.47% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 423500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 95000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 18349502828 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2262 87.61% 87.61% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 320 12.39% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2582 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 2691 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 18106130328 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.976227 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.152552 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 430953000 2.38% 2.38% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 17674714828 97.62% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 401500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 61000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 18106130328 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2271 87.75% 87.75% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 317 12.25% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2588 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 9923 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 9923 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 9874 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 9874 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2582 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2582 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 12505 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 70918524 # ITB inst hits -system.cpu0.itb.inst_misses 9923 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2588 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 12462 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 35678798 # ITB inst hits +system.cpu0.itb.inst_misses 9874 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -577,1005 +565,1020 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2361 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2368 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1943 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1932 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 70928447 # ITB inst accesses -system.cpu0.itb.hits 70918524 # DTB hits -system.cpu0.itb.misses 9923 # DTB misses -system.cpu0.itb.accesses 70928447 # DTB accesses -system.cpu0.numCycles 192710246 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 35688672 # ITB inst accesses +system.cpu0.itb.hits 35678798 # DTB hits +system.cpu0.itb.misses 9874 # DTB misses +system.cpu0.itb.accesses 35688672 # DTB accesses +system.cpu0.numCycles 121733824 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 19172907 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 190300440 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 51768532 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 38620751 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 166603353 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 5605830 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 133760 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 54794 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 348448 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 420234 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 74628 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 70919147 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 257234 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 4157 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 189611039 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.227807 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.311092 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 17621783 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 106366119 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 22612465 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 13856831 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 98711813 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2650530 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 130938 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 54154 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 345087 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 416739 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 73296 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 35679429 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 256075 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 4180 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 118679075 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.081251 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.263308 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 87830492 46.32% 46.32% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 29214542 15.41% 61.73% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 14106780 7.44% 69.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 58459225 30.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 59721044 50.32% 50.32% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 20146281 16.98% 67.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 8259650 6.96% 74.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 30552100 25.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 189611039 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.268634 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.987495 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 24427882 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 101305691 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 56642715 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4754811 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2479940 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 2942193 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 327073 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 148781526 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3762312 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 2479940 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 32842566 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 11912016 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 79322122 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 52855770 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 10198625 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 132285921 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1008096 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1377906 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 148604 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 51873 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 6170558 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 135790293 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 611071310 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 146878490 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 9376 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 124889963 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 10900327 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 2656202 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 2518524 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 22032615 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 23644678 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 18416726 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1638849 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2450280 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 129422072 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1660998 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 127592349 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 453825 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10488941 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 21267672 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 117222 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 189611039 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.672916 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 0.964306 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 118679075 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.185753 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.873760 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 18470879 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 55646585 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 38814384 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4744194 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1003033 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 2910392 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 326287 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 104430369 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3709386 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1003033 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 23916141 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 11897059 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 33727750 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 37986661 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 10148431 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 99624170 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 979348 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1380369 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 148421 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 51935 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 6127142 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 103189966 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 455330287 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 114159594 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 9381 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 92428419 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 10761544 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1188796 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1051388 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11830283 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 17680232 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 15386939 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1636462 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2175060 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 96814528 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1636038 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 95024919 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 451413 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 8911325 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 20849804 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 116309 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 118679075 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.800688 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.033122 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 115784330 61.06% 61.06% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 32509497 17.15% 78.21% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 29946391 15.79% 94.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 10293248 5.43% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1077539 0.57% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 34 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 65546472 55.23% 55.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 22156727 18.67% 73.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 21116341 17.79% 91.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 8802658 7.42% 99.11% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1056849 0.89% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 28 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 189611039 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 118679075 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 10302435 44.02% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 127 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 44.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5400760 23.08% 67.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 7700326 32.90% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 8808229 40.49% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 130 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5336848 24.53% 65.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 7610455 34.98% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2272 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 86139109 67.51% 67.51% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 105637 0.08% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 7185 0.01% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.60% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 23381898 18.33% 85.93% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 17956248 14.07% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 62565826 65.84% 65.84% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 87588 0.09% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 7159 0.01% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.94% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 17417081 18.33% 84.27% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 14944992 15.73% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 127592349 # Type of FU issued -system.cpu0.iq.rate 0.662094 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 23403648 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.183425 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 468620138 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 141579564 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 124128658 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 33072 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 11274 # Number of floating instruction queue writes +system.cpu0.iq.FU_type_0::total 95024919 # Type of FU issued +system.cpu0.iq.rate 0.780596 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 21755662 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.228947 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 330903688 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 107369307 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 93061278 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 32300 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 11278 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 9724 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 150972031 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 21694 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 349342 # Number of loads that had data forwarded from stores +system.cpu0.iq.int_alu_accesses 116757282 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 21027 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 347087 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1883137 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2543 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18891 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 974261 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1857425 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2513 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18755 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 953252 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 112825 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 327783 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 101364 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 327888 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2479940 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1553148 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 173644 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 131254258 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 1003033 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1539075 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 172884 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 98621711 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 23644678 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 18416726 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 851019 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 24728 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 127466 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18891 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 275684 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 374727 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 650411 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 126563046 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 22955767 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 966765 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 17680232 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 15386939 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 849096 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 24467 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 126834 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18755 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 265533 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 373430 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 638963 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 94008948 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 16992930 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 954343 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 171188 # number of nop insts executed -system.cpu0.iew.exec_refs 40733276 # number of memory reference insts executed -system.cpu0.iew.exec_branches 24565455 # Number of branches executed -system.cpu0.iew.exec_stores 17777509 # Number of stores executed -system.cpu0.iew.exec_rate 0.656753 # Inst execution rate -system.cpu0.iew.wb_sent 126045909 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 124138382 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 63204033 # num instructions producing a value -system.cpu0.iew.wb_consumers 102166760 # num instructions consuming a value +system.cpu0.iew.exec_nop 171145 # number of nop insts executed +system.cpu0.iew.exec_refs 31760151 # number of memory reference insts executed +system.cpu0.iew.exec_branches 15805524 # Number of branches executed +system.cpu0.iew.exec_stores 14767221 # Number of stores executed +system.cpu0.iew.exec_rate 0.772250 # Inst execution rate +system.cpu0.iew.wb_sent 93501427 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 93071002 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 48393961 # num instructions producing a value +system.cpu0.iew.wb_consumers 79995949 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.644171 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.618636 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.764545 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.604955 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 9496881 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1543776 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 596906 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 186488308 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.647310 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.345681 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 7948634 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1519729 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 585621 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 117035605 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.766100 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.480781 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 128655160 68.99% 68.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 31929494 17.12% 86.11% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 12238036 6.56% 92.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3079239 1.65% 94.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 4650991 2.49% 96.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 2566190 1.38% 98.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1394957 0.75% 98.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 526048 0.28% 99.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1448193 0.78% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 75174289 64.23% 64.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 23319780 19.93% 84.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 7849886 6.71% 90.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3044520 2.60% 93.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 3180912 2.72% 96.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 1406827 1.20% 97.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1102407 0.94% 98.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 520278 0.44% 98.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1436706 1.23% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 186488308 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 99634335 # Number of instructions committed -system.cpu0.commit.committedOps 120715819 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 117035605 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 74499569 # Number of instructions committed +system.cpu0.commit.committedOps 89660931 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 39204006 # Number of memory references committed -system.cpu0.commit.loads 21761541 # Number of loads committed -system.cpu0.commit.membars 628761 # Number of memory barriers committed -system.cpu0.commit.branches 23967170 # Number of branches committed +system.cpu0.commit.refs 30256494 # Number of memory references committed +system.cpu0.commit.loads 15822807 # Number of loads committed +system.cpu0.commit.membars 627513 # Number of memory barriers committed +system.cpu0.commit.branches 15208996 # Number of branches committed system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 105564175 # Number of committed integer instructions. -system.cpu0.commit.function_calls 4749359 # Number of function calls committed. +system.cpu0.commit.int_insts 77458658 # Number of committed integer instructions. +system.cpu0.commit.function_calls 1847857 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 81401150 67.43% 67.43% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 103478 0.09% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 7185 0.01% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 21761541 18.03% 85.55% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 17442465 14.45% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 59311896 66.15% 66.15% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 85382 0.10% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 7159 0.01% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.25% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 15822807 17.65% 83.90% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 14433687 16.10% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 120715819 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1448193 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 292184577 # The number of ROB reads -system.cpu0.rob.rob_writes 263546817 # The number of ROB writes -system.cpu0.timesIdled 122559 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3099207 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5058081346 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 99512641 # Number of Instructions Simulated -system.cpu0.committedOps 120594125 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.936540 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.936540 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.516385 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.516385 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 137143613 # number of integer regfile reads -system.cpu0.int_regfile_writes 78685231 # number of integer regfile writes -system.cpu0.fp_regfile_reads 8206 # number of floating regfile reads +system.cpu0.commit.op_class_0::total 89660931 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1436706 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 209187674 # The number of ROB reads +system.cpu0.rob.rob_writes 196861250 # The number of ROB writes +system.cpu0.timesIdled 121559 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 3054749 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5129022957 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 74377875 # Number of Instructions Simulated +system.cpu0.committedOps 89539237 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.636694 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.636694 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.610988 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.610988 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 104549028 # number of integer regfile reads +system.cpu0.int_regfile_writes 56469550 # number of integer regfile writes +system.cpu0.fp_regfile_reads 8161 # number of floating regfile reads system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes -system.cpu0.cc_regfile_reads 446712527 # number of cc regfile reads -system.cpu0.cc_regfile_writes 47224279 # number of cc regfile writes -system.cpu0.misc_regfile_reads 373664445 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1193481 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 673244 # number of replacements -system.cpu0.dcache.tags.tagsinuse 484.859625 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 36215686 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 673756 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 53.751931 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 278115000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.859625 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946991 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.946991 # Average percentage of cache occupancy +system.cpu0.cc_regfile_reads 331224109 # number of cc regfile reads +system.cpu0.cc_regfile_writes 38421528 # number of cc regfile writes +system.cpu0.misc_regfile_reads 233358199 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1191250 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 674914 # number of replacements +system.cpu0.dcache.tags.tagsinuse 486.328727 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 27281228 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 675426 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 40.391143 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 277646000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 486.328727 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.949861 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.949861 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 77975696 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 77975696 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 20636575 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 20636575 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 14390339 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 14390339 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 296451 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 296451 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 354772 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 354772 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 351523 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 351523 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 35026914 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 35026914 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35323365 # number of overall hits -system.cpu0.dcache.overall_hits::total 35323365 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 606585 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 606585 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1800589 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1800589 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141770 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 141770 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24267 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 24267 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21226 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 21226 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2407174 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2407174 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2548944 # number of overall misses -system.cpu0.dcache.overall_misses::total 2548944 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8152337496 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 8152337496 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26333386263 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 26333386263 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 385690944 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 385690944 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 485736540 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 485736540 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 421500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 421500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 34485723759 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 34485723759 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 34485723759 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 34485723759 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 21243160 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 21243160 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16190928 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16190928 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 438221 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 438221 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379039 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 379039 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 372749 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 372749 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 37434088 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 37434088 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 37872309 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 37872309 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028554 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.028554 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.111210 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.111210 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323513 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323513 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064022 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064022 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056944 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056944 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.064304 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.064304 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.067304 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.067304 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13439.728144 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13439.728144 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14624.873451 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 14624.873451 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15893.639263 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15893.639263 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22884.035617 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22884.035617 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 60112887 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 60112887 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 14700771 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 14700771 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 11392924 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 11392924 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 295732 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 295732 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 354072 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 354072 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 350987 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 350987 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 26093695 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 26093695 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 26389427 # number of overall hits +system.cpu0.dcache.overall_hits::total 26389427 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 607182 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 607182 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1803068 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1803068 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141599 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 141599 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24346 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 24346 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21181 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 21181 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2410250 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2410250 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2551849 # number of overall misses +system.cpu0.dcache.overall_misses::total 2551849 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8154354688 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 8154354688 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26135736531 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 26135736531 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 384171142 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 384171142 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 484170513 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 484170513 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 824000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 824000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 34290091219 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 34290091219 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 34290091219 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 34290091219 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 15307953 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 15307953 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 13195992 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 13195992 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 437331 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 437331 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378418 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 378418 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 372168 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 372168 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 28503945 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 28503945 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 28941276 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 28941276 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039664 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.039664 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136638 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.136638 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323780 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323780 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064336 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064336 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056912 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056912 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084558 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.084558 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088173 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.088173 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13429.836010 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13429.836010 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14495.147455 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 14495.147455 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15779.641091 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15779.641091 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22858.718332 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22858.718332 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14326.228083 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14326.228083 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13529.416009 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13529.416009 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 842 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3715311 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 190617 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.541667 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 19.490974 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14226.777811 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14226.777811 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13437.351199 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13437.351199 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 781 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3670700 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 43 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 191761 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.162791 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 19.142057 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 491598 # number of writebacks -system.cpu0.dcache.writebacks::total 491598 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 240080 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 240080 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1488537 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1488537 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18067 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18067 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1728617 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1728617 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1728617 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1728617 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 366505 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 366505 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312052 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 312052 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98413 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 98413 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6200 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6200 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21226 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 21226 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 678557 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 678557 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 776970 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 776970 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4125978302 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4125978302 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5242118761 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5242118761 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1570027702 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1570027702 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 93210251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 93210251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 452955960 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 452955960 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 405000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 405000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9368097063 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9368097063 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10938124765 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10938124765 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5613897000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5613897000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4260937012 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4260937012 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9874834012 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9874834012 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017253 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017253 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019273 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019273 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224574 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224574 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016357 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016357 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056944 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056944 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018127 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.018127 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020516 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.020516 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11257.631689 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11257.631689 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16798.862885 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16798.862885 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15953.458405 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15953.458405 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15033.911452 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15033.911452 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21339.675869 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21339.675869 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 492000 # number of writebacks +system.cpu0.dcache.writebacks::total 492000 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 239081 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 239081 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1490741 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1490741 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18153 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18153 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1729822 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1729822 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1729822 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1729822 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 368101 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 368101 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312327 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 312327 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98325 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 98325 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6193 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6193 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21181 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 21181 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 680428 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 680428 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 778753 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 778753 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17965 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17965 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16714 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16714 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34679 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34679 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4128121038 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4128121038 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5207818329 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5207818329 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1570971031 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1570971031 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 91940502 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 91940502 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 451443987 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 451443987 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 794000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 794000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9335939367 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9335939367 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10906910398 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10906910398 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3693380750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3693380750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2688166013 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2688166013 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6381546763 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6381546763 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024046 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024046 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023668 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023668 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224830 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224830 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016366 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016366 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056912 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056912 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023871 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023871 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026908 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026908 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11214.642280 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11214.642280 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16674.249517 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16674.249517 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15977.330598 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15977.330598 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14845.874697 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14845.874697 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21313.629526 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21313.629526 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13805.910282 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13805.910282 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14077.924199 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14077.924199 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13720.686637 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13720.686637 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14005.609478 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14005.609478 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 205587.573059 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205587.573059 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 160833.194508 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 160833.194508 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184017.611898 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184017.611898 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1204763 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.748349 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 69666497 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1205275 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 57.801329 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6415532250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.748349 # Average occupied blocks per requestor +system.cpu0.icache.tags.replacements 1200530 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.748320 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 34431245 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1201042 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 28.667811 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6414143250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.748320 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999508 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999508 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 143036633 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 143036633 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 69666497 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 69666497 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 69666497 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 69666497 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 69666497 # number of overall hits -system.cpu0.icache.overall_hits::total 69666497 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1249171 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1249171 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1249171 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1249171 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1249171 # number of overall misses -system.cpu0.icache.overall_misses::total 1249171 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12316352733 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12316352733 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12316352733 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12316352733 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12316352733 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12316352733 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 70915668 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 70915668 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 70915668 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 70915668 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 70915668 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 70915668 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017615 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.017615 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017615 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.017615 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017615 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.017615 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9859.621087 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9859.621087 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9859.621087 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9859.621087 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9859.621087 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9859.621087 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1363430 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 975 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 105819 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 72552920 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 72552920 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 34431245 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 34431245 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 34431245 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 34431245 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 34431245 # number of overall hits +system.cpu0.icache.overall_hits::total 34431245 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1244682 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1244682 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1244682 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1244682 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1244682 # number of overall misses +system.cpu0.icache.overall_misses::total 1244682 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12221339030 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12221339030 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12221339030 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12221339030 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12221339030 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12221339030 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 35675927 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 35675927 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 35675927 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 35675927 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 35675927 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 35675927 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034889 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.034889 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034889 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.034889 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034889 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.034889 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9818.844516 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9818.844516 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9818.844516 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9818.844516 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9818.844516 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9818.844516 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1349229 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 432 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 105227 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.884548 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 88.636364 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.822080 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 39.272727 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43872 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 43872 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 43872 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 43872 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 43872 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 43872 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1205299 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1205299 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1205299 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1205299 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1205299 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1205299 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10580120186 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10580120186 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10580120186 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10580120186 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10580120186 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10580120186 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43614 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 43614 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 43614 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 43614 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 43614 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 43614 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1201068 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1201068 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1201068 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1201068 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1201068 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1201068 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3002 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 3002 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3002 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 3002 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10504795288 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10504795288 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10504795288 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10504795288 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10504795288 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10504795288 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265434748 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 265434748 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 265434748 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 265434748 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016996 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016996 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016996 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016996 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016996 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016996 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8778.004616 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8778.004616 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8778.004616 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8778.004616 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8778.004616 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8778.004616 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033666 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033666 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033666 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.033666 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033666 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.033666 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8746.211945 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8746.211945 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8746.211945 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8746.211945 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8746.211945 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8746.211945 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88419.303131 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88419.303131 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88419.303131 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88419.303131 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1762691 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1767870 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 4580 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1764126 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1768652 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 4013 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 220490 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 265715 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16040.758095 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2094535 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 281946 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 7.428852 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2609861933500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 9327.683600 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 17.267794 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.026625 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4039.749605 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1610.171801 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1044.858671 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.569317 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001054 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000063 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.246567 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.098277 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063773 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.979050 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1077 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15140 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 37 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 322 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 401 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 317 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id +system.cpu0.l2cache.prefetcher.pfSpanPage 220332 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 264213 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16022.712569 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2093032 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 280442 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 7.463333 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 9357.549400 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.830885 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.990255 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3887.194071 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1642.708300 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1121.439658 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.571139 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000783 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000060 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.237255 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.100263 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.068447 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.977949 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1027 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15194 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 39 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 304 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 426 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 258 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 423 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4738 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7052 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2870 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.065735 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.924072 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 41668980 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 41668980 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 50191 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 11923 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1155240 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 372543 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1589897 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 491596 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 491596 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28444 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 28444 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1603 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 1603 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 210600 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 210600 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 50191 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 11923 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1155240 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 583143 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1800497 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 50191 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 11923 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1155240 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 583143 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1800497 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 425 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 170 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 50043 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 98477 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 149115 # number of ReadReq misses -system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses -system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27382 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 27382 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19621 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19621 # number of SCUpgradeReq misses +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 450 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4677 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7327 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2684 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062683 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.927368 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 41624222 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 41624222 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 49855 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 11685 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1152127 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 374018 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1587685 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 491993 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 491993 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28477 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 28477 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1602 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 1602 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 210193 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 210193 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 49855 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 11685 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1152127 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 584211 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1797878 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 49855 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 11685 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1152127 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 584211 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1797878 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 397 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 143 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 48926 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 98504 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 147970 # number of ReadReq misses +system.cpu0.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses +system.cpu0.l2cache.Writeback_misses::total 2 # number of Writeback misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27483 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 27483 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19577 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 19577 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45870 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 45870 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 425 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 170 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 50043 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 144347 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 194985 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 425 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 170 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 50043 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 144347 # number of overall misses -system.cpu0.l2cache.overall_misses::total 194985 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11462248 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4075246 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2454493202 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2862988088 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 5333018784 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 502169231 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 502169231 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 396029410 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 396029410 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 393499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 393499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2652639758 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2652639758 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11462248 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4075246 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2454493202 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 5515627846 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 7985658542 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11462248 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4075246 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2454493202 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 5515627846 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 7985658542 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 50616 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12093 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1205283 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 471020 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1739012 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 491597 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 491597 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55826 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 55826 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21224 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 21224 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 46426 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 46426 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 397 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 143 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 48926 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 144930 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 194396 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 397 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 143 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 48926 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 144930 # number of overall misses +system.cpu0.l2cache.overall_misses::total 194396 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 10907493 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3478500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2401346947 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2853426397 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 5269159337 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 505786782 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 505786782 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 394596383 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 394596383 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 773499 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 773499 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2617489063 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 2617489063 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 10907493 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3478500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2401346947 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 5470915460 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 7886648400 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 10907493 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3478500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2401346947 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 5470915460 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 7886648400 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 50252 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 11828 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1201053 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 472522 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 1735655 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 491995 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 491995 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55960 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 55960 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21179 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 21179 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 256470 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 256470 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 50616 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12093 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1205283 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 727490 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1995482 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 50616 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12093 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1205283 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 727490 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1995482 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.008397 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.014058 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.041520 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.209072 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.085747 # miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.490488 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.490488 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.924472 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.924472 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 256619 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 256619 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 50252 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 11828 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1201053 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 729141 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1992274 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 50252 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 11828 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1201053 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 729141 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1992274 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007900 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.012090 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040736 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.208464 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.085253 # miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000004 # miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_miss_rate::total 0.000004 # miss rate for Writeback accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.491119 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.491119 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.924359 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.924359 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.178851 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.178851 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.008397 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.014058 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.041520 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.198418 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.097713 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.008397 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.014058 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.041520 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.198418 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.097713 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26969.995294 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23972.035294 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 49047.683033 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29072.657453 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 35764.468927 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18339.391973 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18339.391973 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20183.956475 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20183.956475 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 196749.500000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 196749.500000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 57829.512928 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 57829.512928 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26969.995294 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23972.035294 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49047.683033 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38210.893514 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 40955.245491 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26969.995294 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23972.035294 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49047.683033 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38210.893514 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 40955.245491 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 152 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.180914 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.180914 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007900 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.012090 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040736 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.198768 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.097575 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007900 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.012090 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040736 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.198768 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.097575 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27474.793451 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24325.174825 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 49081.203184 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 28967.619559 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 35609.646124 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18403.623404 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18403.623404 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20156.121112 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20156.121112 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 386749.500000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 386749.500000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 56379.810085 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 56379.810085 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27474.793451 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24325.174825 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49081.203184 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37748.674947 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 40570.013786 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27474.793451 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24325.174825 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49081.203184 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37748.674947 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 40570.013786 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 227 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 30.400000 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32.428571 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 193170 # number of writebacks -system.cpu0.l2cache.writebacks::total 193170 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 192333 # number of writebacks +system.cpu0.l2cache.writebacks::total 192333 # number of writebacks system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 27 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 699 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 728 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6075 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 6075 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 30 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 734 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 766 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5918 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 5918 # number of ReadExReq MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 27 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6774 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 6803 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 30 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6652 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 6684 # number of demand (read+write) MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 27 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6774 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 6803 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 424 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 169 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 50016 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 97778 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 148387 # number of ReadReq MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 232167 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 232167 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27382 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27382 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19621 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19621 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 30 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6652 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 6684 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 396 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 142 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 48896 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 97770 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 147204 # number of ReadReq MSHR misses +system.cpu0.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses +system.cpu0.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 231819 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 231819 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27483 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27483 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19577 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19577 # number of SCUpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 39795 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 39795 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 424 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 169 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 50016 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 137573 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 188182 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 424 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 169 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 50016 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 137573 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 232167 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 420349 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 8681250 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2961750 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2122401548 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2188318454 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4322363002 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15144909271 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15144909271 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 533487187 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 533487187 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 293580560 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 293580560 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 321999 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 321999 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1622773486 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1622773486 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 8681250 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2961750 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2122401548 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3811091940 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 5945136488 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 8681250 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2961750 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2122401548 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3811091940 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15144909271 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 21090045759 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40508 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 40508 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 396 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 142 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 48896 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 138278 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 187712 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 396 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 142 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 48896 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 138278 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 231819 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 419531 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3002 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 17965 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 20967 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16714 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16714 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3002 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34679 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 37681 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 8304499 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2542000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2076482303 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2175990950 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4263319752 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15030655008 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15030655008 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 535907154 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 535907154 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 292472580 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 292472580 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 643499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 643499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1596975176 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1596975176 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 8304499 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2542000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2076482303 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3772966126 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 5860294928 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 8304499 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2542000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2076482303 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3772966126 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15030655008 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 20890949936 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 241524750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5378380500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5619905250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4060847435 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4060847435 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3549350250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 3790875000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2559965955 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2559965955 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 241524750 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9439227935 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9680752685 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008377 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013975 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.041497 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.207588 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.085328 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6109316205 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6350840955 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007880 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012005 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.040711 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.206911 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.084812 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000004 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000004 # mshr miss rate for Writeback accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.490488 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.490488 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.924472 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.924472 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.491119 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.491119 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.924359 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.924359 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155164 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155164 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008377 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.013975 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041497 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.189106 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.094304 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008377 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.013975 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041497 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.189106 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.157853 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.157853 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007880 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.012005 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040711 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.189645 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.094220 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007880 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.012005 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040711 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.189645 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210650 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20474.646226 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17525.147929 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42434.451935 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22380.478778 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29128.987054 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65232.824954 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65232.824954 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19483.134431 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19483.134431 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14962.568676 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14962.568676 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 160999.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 160999.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40778.326071 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40778.326071 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20474.646226 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17525.147929 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42434.451935 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27702.324875 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31592.482214 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20474.646226 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17525.147929 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42434.451935 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27702.324875 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65232.824954 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50172.703537 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210579 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42467.324587 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22256.223279 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28961.983044 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64837.890803 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 64837.890803 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19499.587163 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19499.587163 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14939.601573 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14939.601573 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 321749.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 321749.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39423.698430 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39423.698430 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42467.324587 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27285.368070 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31219.607313 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42467.324587 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27285.368070 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64837.890803 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49795.962482 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80454.613591 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197570.289452 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 180801.974531 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153162.974453 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153162.974453 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80454.613591 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176167.600133 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 168542.261485 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1908189 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1835262 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 26172 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26172 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 491597 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 299764 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 91875 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43573 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 114693 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 284602 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 270315 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2416584 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2311982 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27986 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 112626 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4869178 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 77186016 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82205272 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 48372 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 202464 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 159642124 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 659500 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3123483 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 3.174208 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.379288 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 1907833 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1820754 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 16714 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 491995 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 299768 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36263 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 92116 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43624 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 114864 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 284068 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 270286 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2408123 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2274201 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27655 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 111764 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4821743 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 76915296 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82255660 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 47312 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 201008 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 159419276 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 687931 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3186793 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.203876 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.402878 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 2579348 82.58% 82.58% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 544135 17.42% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2537081 79.61% 79.61% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 649712 20.39% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3123483 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1823730646 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 3186793 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1807599924 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 112580498 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 112679999 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1815085939 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1808718407 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1180413157 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1166698241 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 15906731 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 15837483 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 62058933 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 61547958 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 6179090 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3881916 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 362855 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 3346788 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 2458848 # Number of BTB hits +system.cpu1.branchPred.lookups 35319893 # Number of BP lookups +system.cpu1.branchPred.condPredicted 12619406 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 374072 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 19615876 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 15617711 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.468890 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 1048082 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 10606 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 79.617709 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 12648833 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 10709 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1605,91 +1608,89 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 24514 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 24514 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11457 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6002 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 7055 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 17459 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 393.464689 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 2513.400268 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 16937 97.01% 97.01% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 156 0.89% 97.90% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 187 1.07% 98.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 85 0.49% 99.46% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 23 0.13% 99.59% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 6 0.03% 99.63% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 44 0.25% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 3 0.02% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 14 0.08% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 24259 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 24259 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11332 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6025 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 6902 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 17357 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 400.040330 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 2564.899375 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 16829 96.96% 96.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 181 1.04% 98.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 173 1.00% 99.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 71 0.41% 99.41% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 28 0.16% 99.57% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 5 0.03% 99.60% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 45 0.26% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 6 0.03% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 14 0.08% 99.97% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::40960-45055 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 17459 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5476 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 9377.190285 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 8039.034346 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5934.391980 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 2488 45.43% 45.43% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2481 45.31% 90.74% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 381 6.96% 97.70% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 96 1.75% 99.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 6 0.11% 99.56% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 20 0.37% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::90112-98303 4 0.07% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5476 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 69614954880 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.366193 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.484439 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 44157971700 63.43% 63.43% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 25439149180 36.54% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2 11249000 0.02% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::3 3199000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4 940000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::5 768000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6 744500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::7 290500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8 107000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::9 122500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10 85500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::11 64000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12 71500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::13 26500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14 31000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::15 135000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 69614954880 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1964 73.78% 73.78% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 698 26.22% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2662 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24514 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::total 17357 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5295 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 9383.568650 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 7860.112601 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 8293.617199 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 5259 99.32% 99.32% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 29 0.55% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 3 0.06% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 3 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5295 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 69596834880 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.389063 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.490087 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 42554298056 61.14% 61.14% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 27024786824 38.83% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2 11219000 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::3 3252000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4 913000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::5 701500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6 719000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::7 299000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8 99500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::9 182000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10 50000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::11 63500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12 106500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::13 34000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14 15000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::15 96000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 69596834880 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1939 74.63% 74.63% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 659 25.37% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2598 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24259 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24514 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2662 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24259 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2598 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2662 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 27176 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2598 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 26857 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 5241297 # DTB read hits -system.cpu1.dtb.read_misses 21288 # DTB read misses -system.cpu1.dtb.write_hits 4318497 # DTB write hits -system.cpu1.dtb.write_misses 3226 # DTB write misses +system.cpu1.dtb.read_hits 11166498 # DTB read hits +system.cpu1.dtb.read_misses 21069 # DTB read misses +system.cpu1.dtb.write_hits 7306223 # DTB write hits +system.cpu1.dtb.write_misses 3190 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2042 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 72 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 621 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2022 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 70 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 623 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 379 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 5262585 # DTB read accesses -system.cpu1.dtb.write_accesses 4321723 # DTB write accesses +system.cpu1.dtb.perms_faults 374 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 11187567 # DTB read accesses +system.cpu1.dtb.write_accesses 7309413 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 9559794 # DTB hits -system.cpu1.dtb.misses 24514 # DTB misses -system.cpu1.dtb.accesses 9584308 # DTB accesses +system.cpu1.dtb.hits 18472721 # DTB hits +system.cpu1.dtb.misses 24259 # DTB misses +system.cpu1.dtb.accesses 18496980 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1719,67 +1720,63 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 6863 # Table walker walks requested -system.cpu1.itb.walker.walksShort 6863 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4096 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2697 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 70 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 6793 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 193.655233 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 1558.039702 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-2047 6647 97.85% 97.85% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::2048-4095 36 0.53% 98.38% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-6143 28 0.41% 98.79% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::6144-8191 24 0.35% 99.15% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-10239 16 0.24% 99.38% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::10240-12287 12 0.18% 99.56% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-14335 8 0.12% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::14336-16383 5 0.07% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-18431 3 0.04% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::18432-20479 3 0.04% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::20480-22527 2 0.03% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::22528-24575 4 0.06% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::26624-28671 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::30720-32767 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 6793 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1235 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 10095.547368 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 8796.441001 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5908.625766 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 181 14.66% 14.66% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 175 14.17% 28.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 552 44.70% 73.52% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 256 20.73% 94.25% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 7 0.57% 94.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 7 0.57% 95.38% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.27% 97.65% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 18 1.46% 99.11% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.24% 99.35% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.40% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.16% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 6817 # Table walker walks requested +system.cpu1.itb.walker.walksShort 6817 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4075 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2679 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 63 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 6754 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 138.510512 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 1194.021921 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-2047 6631 98.18% 98.18% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::2048-4095 35 0.52% 98.70% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-6143 28 0.41% 99.11% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::6144-8191 28 0.41% 99.53% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-10239 11 0.16% 99.69% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::10240-12287 8 0.12% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-14335 4 0.06% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::14336-16383 2 0.03% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-22527 2 0.03% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::22528-24575 2 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::26624-28671 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 6754 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1229 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 9949.958503 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 8666.714001 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5833.930601 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 208 16.92% 16.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 175 14.24% 31.16% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 520 42.31% 73.47% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 258 20.99% 94.47% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 10 0.81% 95.28% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.24% 95.52% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 30 2.44% 97.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.30% 99.27% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.16% 99.43% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.41% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.08% 99.92% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.08% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1235 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 18043801328 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.988843 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.105174 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 201557764 1.12% 1.12% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 17842013064 98.88% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 213500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 17000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 18043801328 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 995 85.41% 85.41% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 170 14.59% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1165 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 1229 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 18026373328 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.989122 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.103762 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 196149764 1.09% 1.09% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 17830158064 98.91% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 65500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 18026373328 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 995 85.33% 85.33% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 171 14.67% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1166 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6863 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6863 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6817 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6817 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1165 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1165 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 8028 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 10532607 # ITB inst hits -system.cpu1.itb.inst_misses 6863 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1166 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1166 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 7983 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 45723303 # ITB inst hits +system.cpu1.itb.inst_misses 6817 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1788,98 +1785,98 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1195 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1199 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 530 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 537 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 10539470 # ITB inst accesses -system.cpu1.itb.hits 10532607 # DTB hits -system.cpu1.itb.misses 6863 # DTB misses -system.cpu1.itb.accesses 10539470 # DTB accesses -system.cpu1.numCycles 43132973 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 45730120 # ITB inst accesses +system.cpu1.itb.hits 45723303 # DTB hits +system.cpu1.itb.misses 6817 # DTB misses +system.cpu1.itb.accesses 45730120 # DTB accesses +system.cpu1.numCycles 113567718 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 9545781 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 31669827 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 6179090 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 3506930 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 31408441 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 995212 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 85708 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 38872 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 217286 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 331419 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 27804 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 10531999 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 133008 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2352 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 42152917 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.913975 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.225517 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 11092326 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 115445294 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 35319893 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 28266544 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 98824380 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3951464 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 84431 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 39920 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 219438 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 325443 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 27387 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 45722696 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 133886 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2307 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 112589057 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.268755 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.334526 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 24362526 57.80% 57.80% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 6315176 14.98% 72.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2214119 5.25% 78.03% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 9261096 21.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 52059388 46.24% 46.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 15346880 13.63% 59.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 8047278 7.15% 67.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 37135511 32.98% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 42152917 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.143257 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.734237 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 8274124 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 20645023 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 11553748 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1337865 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 342157 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 880050 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 158552 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 30233981 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1392367 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 342157 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 10058392 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2609511 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 14923378 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11073163 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3146316 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 28748329 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 284293 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 329352 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 50565 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 19779 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1931384 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 29150261 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 132893523 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 32973401 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 1672 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 25705063 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 3445198 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 453540 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 375844 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 3445196 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 5586646 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 4747027 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 699100 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 721726 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 27759685 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 627473 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 27258527 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 145234 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2977146 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 6943190 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 53970 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 42152917 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.646658 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.966330 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 112589057 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.311003 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.016533 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 14201102 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 65884249 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 29361473 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1323272 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1818961 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 906595 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 159892 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 74422628 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1448245 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1818961 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 18946447 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2582249 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 60294532 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 25904145 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3042723 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 61245605 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 312742 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 326990 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 51393 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 18938 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1837973 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 61569183 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 287884146 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 65513638 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 1660 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 58022651 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 3546532 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1914472 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1838523 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 13613893 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 11512865 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7756589 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 697877 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 945772 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 60208856 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 646860 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 59677362 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 148586 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 4522679 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 7282133 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 53722 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 112589057 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.530046 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.866401 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 26379254 62.58% 62.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 7348926 17.43% 80.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 5684884 13.49% 93.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2419597 5.74% 99.24% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 320238 0.76% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 76211299 67.69% 67.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 17665370 15.69% 83.38% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 14473056 12.85% 96.23% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3891466 3.46% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 347848 0.31% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::5 18 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -1887,874 +1884,900 @@ system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 42152917 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 112589057 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2004888 32.52% 32.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 611 0.01% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 32.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1891782 30.69% 63.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 2267092 36.78% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3478019 44.85% 44.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 614 0.01% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1940620 25.03% 69.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 2334930 30.11% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 67 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 17154225 62.93% 62.93% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 35391 0.13% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4079 0.01% 63.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.08% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 5491685 20.15% 83.22% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 4573079 16.78% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 40635841 68.09% 68.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 52797 0.09% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4119 0.01% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 11419177 19.13% 87.32% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7565361 12.68% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 27258527 # Type of FU issued -system.cpu1.iq.rate 0.631965 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 6164373 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.226145 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 102973934 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 31372858 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 26623969 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 5644 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 2050 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 1785 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 33419259 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 3574 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 107638 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 59677362 # Type of FU issued +system.cpu1.iq.rate 0.525478 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7754183 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.129935 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 239840869 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 65386915 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 57545759 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 5681 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 2046 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 1784 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 67427880 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 3598 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 109848 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 606025 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 849 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 10642 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 402770 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 624171 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 851 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 10604 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 419293 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 45923 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 97906 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 57328 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 95447 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 342157 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 666539 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 117242 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 28442190 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 1818961 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 659321 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 119824 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 60910908 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 5586646 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 4747027 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 329140 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 12736 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 94970 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 10642 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 72014 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 152187 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 224201 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 26920844 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 5360548 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 313188 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 11512865 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7756589 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 325462 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 12815 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 97459 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 10604 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 81282 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 152799 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 234081 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59327650 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 11286961 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 325473 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 55032 # number of nop insts executed -system.cpu1.iew.exec_refs 9857010 # number of memory reference insts executed -system.cpu1.iew.exec_branches 4125375 # Number of branches executed -system.cpu1.iew.exec_stores 4496462 # Number of stores executed -system.cpu1.iew.exec_rate 0.624136 # Inst execution rate -system.cpu1.iew.wb_sent 26746276 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 26625754 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 13483465 # num instructions producing a value -system.cpu1.iew.wb_consumers 21315020 # num instructions consuming a value +system.cpu1.iew.exec_nop 55192 # number of nop insts executed +system.cpu1.iew.exec_refs 18774109 # number of memory reference insts executed +system.cpu1.iew.exec_branches 12866831 # Number of branches executed +system.cpu1.iew.exec_stores 7487148 # Number of stores executed +system.cpu1.iew.exec_rate 0.522399 # Inst execution rate +system.cpu1.iew.wb_sent 59146208 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 57547543 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 28211344 # num instructions producing a value +system.cpu1.iew.wb_consumers 43350974 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.617295 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.632580 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.506724 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.650766 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 2680688 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 573503 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 207406 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 41589167 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.611775 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.358099 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 4198450 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 593138 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 217301 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 110549070 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.509875 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.177384 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 29454101 70.82% 70.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 7064012 16.99% 87.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2119517 5.10% 92.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 873586 2.10% 95.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 770133 1.85% 96.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 442153 1.06% 97.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 274514 0.66% 98.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 148169 0.36% 98.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 442982 1.07% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 82464476 74.60% 74.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 15679600 14.18% 88.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6499039 5.88% 94.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 896756 0.81% 95.47% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 2234307 2.02% 97.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 1661965 1.50% 98.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 498497 0.45% 99.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 155172 0.14% 99.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 459258 0.42% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 41589167 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 20860008 # Number of instructions committed -system.cpu1.commit.committedOps 25443224 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 110549070 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 45875888 # Number of instructions committed +system.cpu1.commit.committedOps 56366249 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 9324878 # Number of memory references committed -system.cpu1.commit.loads 4980621 # Number of loads committed -system.cpu1.commit.membars 230323 # Number of memory barriers committed -system.cpu1.commit.branches 3917567 # Number of branches committed +system.cpu1.commit.refs 18225990 # Number of memory references committed +system.cpu1.commit.loads 10888694 # Number of loads committed +system.cpu1.commit.membars 231720 # Number of memory barriers committed +system.cpu1.commit.branches 12659864 # Number of branches committed system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 22363157 # Number of committed integer instructions. -system.cpu1.commit.function_calls 552505 # Number of function calls committed. +system.cpu1.commit.int_insts 50354679 # Number of committed integer instructions. +system.cpu1.commit.function_calls 3453612 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 16079933 63.20% 63.20% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 34334 0.13% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 63.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4079 0.02% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 4980621 19.58% 82.93% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 4344257 17.07% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 38084418 67.57% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 51722 0.09% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.66% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4119 0.01% 67.67% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.67% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.67% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.67% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 10888694 19.32% 86.98% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 7337296 13.02% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 25443224 # Class of committed instruction -system.cpu1.commit.bw_lim_events 442982 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 68115809 # The number of ROB reads -system.cpu1.rob.rob_writes 56808236 # The number of ROB writes -system.cpu1.timesIdled 67589 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 980056 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5207108948 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 20826795 # Number of Instructions Simulated -system.cpu1.committedOps 25410011 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.071033 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.071033 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.482851 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.482851 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 30054591 # number of integer regfile reads -system.cpu1.int_regfile_writes 16942565 # number of integer regfile writes -system.cpu1.fp_regfile_reads 1393 # number of floating regfile reads -system.cpu1.fp_regfile_writes 518 # number of floating regfile writes -system.cpu1.cc_regfile_reads 96178951 # number of cc regfile reads -system.cpu1.cc_regfile_writes 9490884 # number of cc regfile writes -system.cpu1.misc_regfile_reads 81077063 # number of misc regfile reads -system.cpu1.misc_regfile_writes 422777 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 228827 # number of replacements -system.cpu1.dcache.tags.tagsinuse 478.548130 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 8439386 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 229141 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 36.830537 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 103436351500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.548130 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.934664 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.934664 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id +system.cpu1.commit.op_class_0::total 56366249 # Class of committed instruction +system.cpu1.commit.bw_lim_events 459258 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 150434096 # The number of ROB reads +system.cpu1.rob.rob_writes 123166009 # The number of ROB writes +system.cpu1.timesIdled 67345 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 978661 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5136638072 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 45842675 # Number of Instructions Simulated +system.cpu1.committedOps 56333036 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.477336 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.477336 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.403659 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.403659 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 62490093 # number of integer regfile reads +system.cpu1.int_regfile_writes 39068646 # number of integer regfile writes +system.cpu1.fp_regfile_reads 1381 # number of floating regfile reads +system.cpu1.fp_regfile_writes 516 # number of floating regfile writes +system.cpu1.cc_regfile_reads 211116899 # number of cc regfile reads +system.cpu1.cc_regfile_writes 18233735 # number of cc regfile writes +system.cpu1.misc_regfile_reads 220514092 # number of misc regfile reads +system.cpu1.misc_regfile_writes 421035 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 227457 # number of replacements +system.cpu1.dcache.tags.tagsinuse 483.345523 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 17322126 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 227768 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 76.051623 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 89024511500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 483.345523 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.944034 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.944034 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.613281 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 18658844 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 18658844 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 4567362 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 4567362 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3580643 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3580643 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 63652 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 63652 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87547 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 87547 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79571 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 79571 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 8148005 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 8148005 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 8211657 # number of overall hits -system.cpu1.dcache.overall_hits::total 8211657 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 253908 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 253908 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 480072 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 480072 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 36130 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 36130 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19184 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 19184 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23489 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23489 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 733980 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 733980 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 770110 # number of overall misses -system.cpu1.dcache.overall_misses::total 770110 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4026677920 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 4026677920 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11127636122 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 11127636122 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 374723986 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 374723986 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 547048827 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 547048827 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1003000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1003000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 15154314042 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 15154314042 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 15154314042 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 15154314042 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 4821270 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 4821270 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4060715 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4060715 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 99782 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 99782 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 106731 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 106731 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 103060 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 103060 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 8881985 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 8881985 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 8981767 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 8981767 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.052664 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.052664 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.118224 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.118224 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.362089 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.362089 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.179742 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.179742 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.227916 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.227916 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.082637 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.082637 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.085741 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.085741 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15858.806812 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15858.806812 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23179.098389 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 23179.098389 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19533.151897 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19533.151897 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23289.574993 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23289.574993 # average StoreCondReq miss latency +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 29 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 36423981 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 36423981 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 10467087 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 10467087 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6561195 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6561195 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65021 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 65021 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88659 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 88659 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80691 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 80691 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 17028282 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 17028282 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 17093303 # number of overall hits +system.cpu1.dcache.overall_hits::total 17093303 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 254533 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 254533 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 479063 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 479063 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35844 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 35844 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19098 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 19098 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23509 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23509 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 733596 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 733596 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 769440 # number of overall misses +system.cpu1.dcache.overall_misses::total 769440 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3958996431 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3958996431 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10579018157 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 10579018157 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 370185734 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 370185734 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 549251321 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 549251321 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 798500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 798500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 14538014588 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 14538014588 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 14538014588 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 14538014588 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 10721620 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 10721620 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 7040258 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 7040258 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 100865 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 100865 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 107757 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 107757 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 104200 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 104200 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 17761878 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 17761878 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 17862743 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 17862743 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023740 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023740 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.068046 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.068046 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.355366 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.355366 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177232 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177232 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225614 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225614 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.041302 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.041302 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043075 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043075 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15553.961298 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15553.961298 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22082.728487 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22082.728487 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19383.481726 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19383.481726 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23363.448934 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23363.448934 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20646.766999 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20646.766999 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19678.116168 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 19678.116168 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 375 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1600979 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 33 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 49143 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.363636 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 32.577966 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19817.467091 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19817.467091 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18894.279720 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18894.279720 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 393 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1480475 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 42 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 48784 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.357143 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 30.347552 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 137785 # number of writebacks -system.cpu1.dcache.writebacks::total 137785 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 90105 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 90105 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 375217 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 375217 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13775 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13775 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 465322 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 465322 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 465322 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 465322 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163803 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 163803 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104855 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 104855 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32523 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 32523 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5409 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5409 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23489 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23489 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 268658 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 268658 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 301181 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 301181 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2171865461 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2171865461 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2612489394 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2612489394 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 519825898 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 519825898 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 98469253 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 98469253 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 510672173 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 510672173 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 974500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 974500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4784354855 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4784354855 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5304180753 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5304180753 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 979094500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 979094500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 848774501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 848774501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1827869001 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1827869001 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033975 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033975 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025822 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025822 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.325941 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.325941 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050679 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050679 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.227916 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.227916 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030248 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030248 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033532 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033532 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13259.009060 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13259.009060 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24915.258157 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24915.258157 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15983.331734 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15983.331734 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18204.705676 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18204.705676 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21740.907361 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21740.907361 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 138868 # number of writebacks +system.cpu1.dcache.writebacks::total 138868 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 91268 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 91268 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 375164 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 375164 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13545 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13545 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 466432 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 466432 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 466432 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 466432 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163265 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 163265 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103899 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 103899 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32275 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 32275 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5553 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5553 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23509 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23509 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 267164 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 267164 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 299439 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 299439 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17059 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17059 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14341 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31400 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31400 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2133861458 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2133861458 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2484196176 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2484196176 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 503074190 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 503074190 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 95947255 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 95947255 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 512832179 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 512832179 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 777500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 777500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4618057634 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4618057634 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5121131824 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5121131824 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2900210250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2900210250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2419067503 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2419067503 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5319277753 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5319277753 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015228 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.015228 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014758 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014758 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.319982 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.319982 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051533 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051533 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225614 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225614 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.015041 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.015041 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016763 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.016763 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13069.925936 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13069.925936 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23909.721711 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23909.721711 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15587.116654 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15587.116654 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17278.453989 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17278.453989 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21814.291505 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21814.291505 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17808.346876 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17808.346876 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17611.272799 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17611.272799 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17285.478710 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17285.478710 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17102.420940 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17102.420940 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170010.566270 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170010.566270 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 168681.926156 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168681.926156 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 169403.750096 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 169403.750096 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 667401 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.527528 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 9840970 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 667913 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 14.733910 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 78865217000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.527528 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973687 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973687 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 671809 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.529348 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 45027049 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 672321 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 66.972546 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 78856865000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.529348 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973690 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973690 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 21731377 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 21731377 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 9840970 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 9840970 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 9840970 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 9840970 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 9840970 # number of overall hits -system.cpu1.icache.overall_hits::total 9840970 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 690756 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 690756 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 690756 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 690756 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 690756 # number of overall misses -system.cpu1.icache.overall_misses::total 690756 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6328356335 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6328356335 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6328356335 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6328356335 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6328356335 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6328356335 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 10531726 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 10531726 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 10531726 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 10531726 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 10531726 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 10531726 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.065588 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.065588 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.065588 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.065588 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.065588 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.065588 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9161.493110 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9161.493110 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9161.493110 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9161.493110 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9161.493110 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9161.493110 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 590927 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 92117192 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 92117192 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 45027049 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 45027049 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 45027049 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 45027049 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 45027049 # number of overall hits +system.cpu1.icache.overall_hits::total 45027049 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 695384 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 695384 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 695384 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 695384 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 695384 # number of overall misses +system.cpu1.icache.overall_misses::total 695384 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6371214084 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6371214084 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6371214084 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6371214084 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6371214084 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6371214084 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 45722433 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 45722433 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 45722433 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 45722433 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 45722433 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 45722433 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.015209 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.015209 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.015209 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.015209 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.015209 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.015209 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9162.152255 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9162.152255 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9162.152255 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9162.152255 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9162.152255 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9162.152255 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 596666 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 49303 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 49414 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.985620 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.074837 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets 27 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22831 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 22831 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 22831 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 22831 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 22831 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 22831 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 667925 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 667925 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 667925 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 667925 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 667925 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 667925 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5443930957 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5443930957 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5443930957 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5443930957 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5443930957 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5443930957 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8774500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8774500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8774500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8774500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.063420 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.063420 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.063420 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.063420 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.063420 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.063420 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8150.512343 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8150.512343 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8150.512343 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8150.512343 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8150.512343 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8150.512343 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 23058 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 23058 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 23058 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 23058 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 23058 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 23058 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 672326 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 672326 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 672326 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 672326 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 672326 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 672326 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 100 # number of ReadReq MSHR uncacheable +system.cpu1.icache.ReadReq_mshr_uncacheable::total 100 # number of ReadReq MSHR uncacheable +system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 100 # number of overall MSHR uncacheable misses +system.cpu1.icache.overall_mshr_uncacheable_misses::total 100 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5482686465 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5482686465 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5482686465 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5482686465 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5482686465 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5482686465 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8677000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8677000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8677000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8677000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014705 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014705 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014705 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.014705 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014705 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.014705 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8154.803570 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8154.803570 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8154.803570 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8154.803570 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8154.803570 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8154.803570 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86770 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86770 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86770 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86770 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 270002 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 271052 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 936 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 264317 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 265106 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 699 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 67932 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 66588 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15581.068012 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 931760 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 81198 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.475159 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 68110 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 61852 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15537.791452 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 937119 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 76426 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 12.261783 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 6676.895279 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 16.747734 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.010823 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4682.837977 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2664.181165 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1538.395034 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.407525 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001022 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.285818 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.162609 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.093896 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.950993 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1283 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13300 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 906 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 364 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 471 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8616 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4213 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078308 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001648 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.811768 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 18862163 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 18862163 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 19502 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7394 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 645640 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 128208 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 800744 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 137784 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 137784 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2324 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 2324 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1121 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1121 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 38121 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 38121 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 19502 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7394 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 645640 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 166329 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 838865 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 19502 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7394 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 645640 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 166329 # number of overall hits -system.cpu1.l2cache.overall_hits::total 838865 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 440 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 275 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 22267 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 73501 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 96483 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29168 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29168 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22368 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22368 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35878 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 35878 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 440 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 275 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 22267 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 109379 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 132361 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 440 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 275 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 22267 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 109379 # number of overall misses -system.cpu1.l2cache.overall_misses::total 132361 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9737996 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5511500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 907046728 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1743519842 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 2665816066 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 555344240 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 555344240 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449490983 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449490983 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 955500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 955500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1553872219 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1553872219 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9737996 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5511500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 907046728 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3297392061 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 4219688285 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9737996 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5511500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 907046728 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3297392061 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 4219688285 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 19942 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7669 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 667907 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 201709 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 897227 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 137784 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 137784 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31492 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 31492 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23489 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23489 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 73999 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 73999 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 19942 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7669 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 667907 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 275708 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 971226 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 19942 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7669 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 667907 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 275708 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 971226 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022064 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.035859 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.033338 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.364391 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.107535 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.926203 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.926203 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.952276 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.952276 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.484844 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.484844 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022064 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.035859 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.033338 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.396720 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.136282 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022064 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.035859 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.033338 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.396720 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.136282 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22131.809091 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20041.818182 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 40735.021691 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 23721.035659 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27629.904398 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19039.503566 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19039.503566 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20095.269269 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20095.269269 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43309.889598 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43309.889598 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22131.809091 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20041.818182 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40735.021691 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30146.482058 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 31880.148118 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22131.809091 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20041.818182 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40735.021691 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30146.482058 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 31880.148118 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 235 # number of cycles access was blocked +system.cpu1.l2cache.tags.occ_blocks::writebacks 6612.049075 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 15.719968 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.202712 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4939.798550 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2550.027939 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1417.993208 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.403567 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000959 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000134 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.301501 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.155641 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.086547 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.948352 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1249 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 36 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13289 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 16 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 878 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 355 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 11 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8497 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4330 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.076233 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002197 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.811096 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 18910778 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 18910778 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 19107 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7219 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 650283 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 128648 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 805257 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 138868 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 138868 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1925 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1925 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1050 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 1050 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 38271 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 38271 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 19107 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7219 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 650283 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 166919 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 843528 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 19107 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7219 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 650283 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 166919 # number of overall hits +system.cpu1.l2cache.overall_hits::total 843528 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 427 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 276 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 22038 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 72420 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 95161 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29112 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 29112 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22458 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22458 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35228 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 35228 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 427 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 276 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 22038 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 107648 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 130389 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 427 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 276 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 22038 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 107648 # number of overall misses +system.cpu1.l2cache.overall_misses::total 130389 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9785994 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5538750 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 913296236 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1683125409 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 2611746389 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 548231087 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 548231087 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449027944 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449027944 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 763500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 763500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1429440182 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1429440182 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9785994 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5538750 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 913296236 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 3112565591 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 4041186571 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9785994 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5538750 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 913296236 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 3112565591 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 4041186571 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 19534 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7495 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 672321 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 201068 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 900418 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 138868 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 138868 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31037 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 31037 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23508 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23508 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 73499 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 73499 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 19534 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7495 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 672321 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 274567 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 973917 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 19534 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7495 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 672321 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 274567 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 973917 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021859 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.036825 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.032779 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.360177 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.105685 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.937977 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.937977 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.955334 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.955334 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.479299 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.479299 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021859 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.036825 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.032779 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.392065 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.133881 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021859 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.036825 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.032779 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.392065 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.133881 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22918.018735 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20067.934783 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 41441.883837 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 23241.168310 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27445.554261 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18831.790567 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18831.790567 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19994.119868 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19994.119868 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 763500 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 763500 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40576.819064 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40576.819064 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22918.018735 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20067.934783 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 41441.883837 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28914.290939 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 30993.309029 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22918.018735 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20067.934783 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 41441.883837 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28914.290939 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 30993.309029 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 61 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 26.111111 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 12.200000 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 39082 # number of writebacks -system.cpu1.l2cache.writebacks::total 39082 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 35144 # number of writebacks +system.cpu1.l2cache.writebacks::total 35144 # number of writebacks system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 13 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 18 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 149 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 181 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 867 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 867 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 16 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 141 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 171 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 736 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 736 # number of ReadExReq MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 13 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 18 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1016 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 1048 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 877 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 907 # number of demand (read+write) MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 13 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 18 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1016 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 1048 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 439 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 262 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 22249 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 73352 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 96302 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 37405 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 37405 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29168 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29168 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22368 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22368 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35011 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 35011 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 439 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 262 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 22249 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 108363 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 131313 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 439 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 262 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 22249 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 108363 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 37405 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 168718 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6861500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3646000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 759958022 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1259838411 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 2030303933 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1619373742 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1619373742 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 484903709 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 484903709 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 334604857 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 334604857 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 832000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 832000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1217604967 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1217604967 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6861500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3646000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 759958022 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2477443378 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 3247908900 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6861500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3646000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 759958022 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2477443378 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1619373742 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 4867282642 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7975000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 934007000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 941982000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 811858998 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 811858998 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7975000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1745865998 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1753840998 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022014 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.034164 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.033312 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.363653 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.107333 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 877 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 907 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 426 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 263 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 22022 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 72279 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 94990 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 36425 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 36425 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29112 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29112 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22458 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22458 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34492 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 34492 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 426 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 263 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 22022 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 106771 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 129482 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 426 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 263 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 22022 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 106771 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 36425 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 165907 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 100 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 17059 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 17159 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 14341 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 100 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 31400 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 31500 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6994000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3664750 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 767719764 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1208019590 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1986398104 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1404338548 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1404338548 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 484116716 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 484116716 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 336604833 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 336604833 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 672500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 672500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1121552915 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1121552915 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6994000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3664750 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 767719764 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2329572505 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3107951019 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6994000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3664750 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 767719764 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2329572505 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1404338548 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4512289567 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7885000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2763450750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2771335750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2311397498 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2311397498 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7885000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5074848248 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5082733248 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021808 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035090 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.032755 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.359475 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.105495 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.926203 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.926203 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.952276 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.952276 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.473128 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.473128 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022014 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.034164 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.033312 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.393035 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.135203 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022014 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.034164 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.033312 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.393035 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.937977 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.937977 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.955334 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.955334 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.469285 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.469285 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021808 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.035090 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.032755 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.388870 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132950 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021808 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.035090 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.032755 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.388870 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.173717 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15629.840547 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13916.030534 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 34156.951863 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 17175.242815 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 21082.676715 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43292.975324 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43292.975324 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16624.510045 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16624.510045 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14959.086955 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14959.086955 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34777.783182 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34777.783182 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15629.840547 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13916.030534 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34156.951863 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22862.447311 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24734.100203 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15629.840547 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13916.030534 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34156.951863 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22862.447311 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43292.975324 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28848.626951 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.170350 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16417.840376 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13934.410646 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 34861.491418 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 16713.285878 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20911.654953 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38554.249774 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38554.249774 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16629.455757 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16629.455757 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14988.192760 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14988.192760 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 672500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 672500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32516.320161 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32516.320161 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16417.840376 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13934.410646 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34861.491418 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21818.401111 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24002.958087 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16417.840376 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13934.410646 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34861.491418 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21818.401111 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38554.249774 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27197.704539 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78850 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161993.712996 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161509.164287 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161174.081166 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161174.081166 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78850 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 161619.370955 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161356.611048 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1243272 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 949021 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 4907 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 4907 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 137784 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 47376 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadReq 1277963 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 964810 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 14341 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 138868 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 45574 # Transaction distribution system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 75841 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43101 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 89718 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 96830 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 79934 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1336034 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 901614 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17159 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 43403 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2298210 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 42747664 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29480945 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30676 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 79768 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 72339053 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 592219 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1674781 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 3.301785 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.459032 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36263 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 76215 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43067 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 89621 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 96319 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 79290 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1344847 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 942237 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 16928 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 42916 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2346928 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 43030144 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29597157 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29980 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 78136 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 72735417 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 628857 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1745350 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.328609 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.469708 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 1169358 69.82% 69.82% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 505423 30.18% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 1171812 67.14% 67.14% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 573538 32.86% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1674781 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 730243456 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1745350 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 748369465 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 87400998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 88425999 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1002964345 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1009581341 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 454923751 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 468876167 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 9604282 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 9538553 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 23499938 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 23419937 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 31011 # Transaction distribution system.iobus.trans_dist::ReadResp 31011 # Transaction distribution @@ -2851,23 +2874,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198996708 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198987475 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84715000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36791507 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36777012 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36458 # number of replacements -system.iocache.tags.tagsinuse 14.446927 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.446991 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 254830116000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.446927 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.902933 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.902933 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 254817991000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.446991 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.902937 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.902937 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2881,14 +2904,14 @@ system.iocache.demand_misses::realview.ide 252 # system.iocache.demand_misses::total 252 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 252 # number of overall misses system.iocache.overall_misses::total 252 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32290377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32290377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6656632824 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6656632824 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32290377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32290377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32290377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32290377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32304877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32304877 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6652654586 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6652654586 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32304877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32304877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32304877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32304877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -2905,19 +2928,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 128136.416667 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 128136.416667 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183763.052783 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183763.052783 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 128136.416667 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 128136.416667 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 128136.416667 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 128136.416667 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 23055 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128193.956349 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128193.956349 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183653.229516 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183653.229516 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128193.956349 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128193.956349 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128193.956349 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128193.956349 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22817 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3532 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3477 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.527463 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.562266 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -2931,14 +2954,14 @@ system.iocache.demand_mshr_misses::realview.ide 252 system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19155377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19155377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4772970838 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4772970838 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 19155377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 19155377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 19155377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 19155377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19198877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19198877 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4768982610 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4768982610 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19198877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19198877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19198877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19198877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2947,584 +2970,597 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76013.400794 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76013.400794 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131762.666685 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131762.666685 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76013.400794 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76013.400794 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76013.400794 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76013.400794 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76186.019841 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76186.019841 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131652.567635 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131652.567635 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76186.019841 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76186.019841 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76186.019841 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76186.019841 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 136223 # number of replacements -system.l2c.tags.tagsinuse 64041.513044 # Cycle average of tags in use -system.l2c.tags.total_refs 356136 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 200557 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.775735 # Average number of references to valid blocks. +system.l2c.tags.replacements 130801 # number of replacements +system.l2c.tags.tagsinuse 64048.619051 # Cycle average of tags in use +system.l2c.tags.total_refs 351623 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 195125 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.802040 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12781.567033 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.527645 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.082100 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5930.123644 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1752.659752 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33401.860992 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.992291 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.903251 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3387.143441 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1822.858320 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4939.794575 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.195031 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000237 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000017 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.090487 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.026743 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.509672 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000122 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 12682.907006 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.525676 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 2.048604 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5727.667382 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1961.871644 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34750.097208 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.787095 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.903255 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3571.469043 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1470.884658 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3857.457480 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.193526 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000222 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000031 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.087397 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.029936 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.530244 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000134 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.051684 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.027815 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.075375 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.977196 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 31391 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 32916 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 116 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6119 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 25156 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 474 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4913 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 27508 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.478989 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.502258 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5099427 # Number of tag accesses -system.l2c.tags.data_accesses 5099427 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 187 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 89 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 32294 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 45191 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 42802 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 34 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 17148 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11819 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 7598 # number of ReadReq hits -system.l2c.ReadReq_hits::total 157222 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 232253 # number of Writeback hits -system.l2c.Writeback_hits::total 232253 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2477 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 788 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3265 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 249 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 61 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 310 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3656 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1776 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5432 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 187 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 89 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 32294 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 48847 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 42802 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 60 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 34 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 17148 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 13595 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 7598 # number of demand (read+write) hits -system.l2c.demand_hits::total 162654 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 187 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 89 # number of overall hits -system.l2c.overall_hits::cpu0.inst 32294 # number of overall hits -system.l2c.overall_hits::cpu0.data 48847 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 42802 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 60 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 34 # number of overall hits -system.l2c.overall_hits::cpu1.inst 17148 # number of overall hits -system.l2c.overall_hits::cpu1.data 13595 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 7598 # number of overall hits -system.l2c.overall_hits::total 162654 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 28 # number of ReadReq misses +system.l2c.tags.occ_percent::cpu1.inst 0.054496 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.022444 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.058860 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.977304 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 31466 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 31 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 32827 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 119 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 6139 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 25208 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 30 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4937 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 27395 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.480133 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000473 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.500900 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5006121 # Number of tag accesses +system.l2c.tags.data_accesses 5006121 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 169 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 68 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 31569 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 45303 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 43197 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 68 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 33 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 16772 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 11005 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 7251 # number of ReadReq hits +system.l2c.ReadReq_hits::total 155435 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 227479 # number of Writeback hits +system.l2c.Writeback_hits::total 227479 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2575 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 820 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3395 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 255 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 98 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 353 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 3872 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 2196 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 6068 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 169 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 68 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 31569 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 49175 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 43197 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 68 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 33 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 16772 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 13201 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 7251 # number of demand (read+write) hits +system.l2c.demand_hits::total 161503 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 169 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 68 # number of overall hits +system.l2c.overall_hits::cpu0.inst 31569 # number of overall hits +system.l2c.overall_hits::cpu0.data 49175 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 43197 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 68 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 33 # number of overall hits +system.l2c.overall_hits::cpu1.inst 16772 # number of overall hits +system.l2c.overall_hits::cpu1.data 13201 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 7251 # number of overall hits +system.l2c.overall_hits::total 161503 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 27 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 17722 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 8264 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 130446 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 17327 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 8118 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 128828 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5101 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 2487 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 10677 # number of ReadReq misses -system.l2c.ReadReq_misses::total 174741 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 8406 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3815 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12221 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 945 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1142 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2087 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11293 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9270 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 20563 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 28 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu1.inst 5250 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 2138 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 9461 # number of ReadReq misses +system.l2c.ReadReq_misses::total 171166 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 8455 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3870 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 12325 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 920 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1168 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2088 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 10724 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8176 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 18900 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 17722 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 19557 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 130446 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 17327 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 18842 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 128828 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5101 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 11757 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 10677 # number of demand (read+write) misses -system.l2c.demand_misses::total 195304 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 28 # number of overall misses +system.l2c.demand_misses::cpu1.inst 5250 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10314 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 9461 # number of demand (read+write) misses +system.l2c.demand_misses::total 190066 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 27 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu0.inst 17722 # number of overall misses -system.l2c.overall_misses::cpu0.data 19557 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 130446 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses +system.l2c.overall_misses::cpu0.inst 17327 # number of overall misses +system.l2c.overall_misses::cpu0.data 18842 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 128828 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 5101 # number of overall misses -system.l2c.overall_misses::cpu1.data 11757 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 10677 # number of overall misses -system.l2c.overall_misses::total 195304 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2541750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 428750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 1457831781 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 749814704 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 14466749329 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 937500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 83000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 434889757 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 222071664 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 1466736489 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18802084724 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 7178272 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 2845410 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 10023682 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1135970 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 748476 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1884446 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 1078166540 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 778316723 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1856483263 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 2541750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 428750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1457831781 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1827981244 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14466749329 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 937500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 83000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 434889757 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1000388387 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1466736489 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 20658567987 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 2541750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 428750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1457831781 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1827981244 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14466749329 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 937500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 83000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 434889757 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1000388387 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1466736489 # number of overall miss cycles -system.l2c.overall_miss_latency::total 20658567987 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 215 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 94 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 50016 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 53455 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 173248 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 70 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 35 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 22249 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 14306 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 18275 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 331963 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 232253 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 232253 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 10883 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4603 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 15486 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1194 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1203 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2397 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 14949 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 11046 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 25995 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 215 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 94 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 50016 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 68404 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 173248 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 70 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 22249 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 25352 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 18275 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 357958 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 215 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 94 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 50016 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 68404 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 173248 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 70 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 22249 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 25352 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 18275 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 357958 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.130233 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.053191 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.354327 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.154597 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.752944 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.142857 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.028571 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.229269 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.173843 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.584241 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.526387 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.772397 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.828807 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.789164 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.791457 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.949293 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.870672 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.755435 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.839218 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.791037 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.130233 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.053191 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.354327 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.285904 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.752944 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.142857 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.028571 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.229269 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.463750 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.584241 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.545606 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.130233 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.053191 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.354327 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.285904 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.752944 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.142857 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.028571 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.229269 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.463750 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.584241 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.545606 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 90776.785714 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 85750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 82261.131983 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 90732.660213 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 110902.207266 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 93750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 83000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85255.784552 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 89292.989144 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 137373.465299 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 107599.731740 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 853.946229 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 745.847969 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 820.201457 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1202.084656 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 655.408056 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 902.944897 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 95472.110157 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83960.811543 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 90282.705004 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90776.785714 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 85750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 82261.131983 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 93469.409623 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 110902.207266 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 93750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 85255.784552 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 85088.746024 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 137373.465299 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 105776.471485 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90776.785714 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 85750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 82261.131983 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 93469.409623 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 110902.207266 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 93750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 85255.784552 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 85088.746024 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 137373.465299 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 105776.471485 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 1085 # number of cycles access was blocked +system.l2c.overall_misses::cpu1.inst 5250 # number of overall misses +system.l2c.overall_misses::cpu1.data 10314 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 9461 # number of overall misses +system.l2c.overall_misses::total 190066 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2599500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 443500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 1426835542 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 735252946 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 14338160773 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1206000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 97250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 448103000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 186224591 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 1256067564 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 18394990666 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 7116778 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 2985907 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 10102685 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1350463 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1030967 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2381430 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 1037256751 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 678589231 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1715845982 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 2599500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 443500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1426835542 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1772509697 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14338160773 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1206000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 97250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 448103000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 864813822 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1256067564 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 20110836648 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 2599500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 443500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1426835542 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1772509697 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14338160773 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1206000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 97250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 448103000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 864813822 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1256067564 # number of overall miss cycles +system.l2c.overall_miss_latency::total 20110836648 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 196 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 73 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 48896 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 53421 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 172025 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 79 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 34 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 22022 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 13143 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 16712 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 326601 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 227479 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 227479 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 11030 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4690 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 15720 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 1175 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1266 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2441 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 14596 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 10372 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 24968 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 196 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 73 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 48896 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 68017 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 172025 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 79 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 34 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 22022 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 23515 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 16712 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 351569 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 196 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 73 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 48896 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 68017 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 172025 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 79 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 34 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 22022 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 23515 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 16712 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 351569 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.137755 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.068493 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.354364 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.151963 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.748891 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.139241 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.029412 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.238398 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.162672 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.566120 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.524083 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.766546 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.825160 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.784033 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.782979 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.922591 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.855387 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.734722 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.788276 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.756969 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.137755 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.068493 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.354364 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.277019 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.748891 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.139241 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.029412 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.238398 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.438614 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.566120 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.540622 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.137755 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.068493 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.354364 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.277019 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.748891 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.139241 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.029412 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.238398 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.438614 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.566120 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.540622 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 96277.777778 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 88700 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 82347.523634 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 90570.700419 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 111296.929029 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 109636.363636 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 97250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85352.952381 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 87102.240879 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 132762.663989 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 107468.718472 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 841.724187 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 771.552196 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 819.690467 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1467.894565 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 882.677226 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1140.531609 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 96722.934633 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82997.704379 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 90785.501693 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 96277.777778 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88700 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 82347.523634 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 94072.269239 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 111296.929029 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 109636.363636 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 97250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 85352.952381 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 83848.538104 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132762.663989 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 105809.753707 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 96277.777778 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88700 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 82347.523634 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 94072.269239 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 111296.929029 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 109636.363636 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 97250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 85352.952381 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 83848.538104 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132762.663989 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 105809.753707 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 234 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 10 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 108.500000 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 117 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 103197 # number of writebacks -system.l2c.writebacks::total 103197 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 16 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 12 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 16 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 28 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 28 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 98707 # number of writebacks +system.l2c.writebacks::total 98707 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 27 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 5 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 17706 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 8264 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 130446 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 17319 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 8118 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 128828 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 5089 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 2487 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 10677 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 174713 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 8406 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3815 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 12221 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 945 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1142 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2087 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 11293 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 9270 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 20563 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 28 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 5241 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 2138 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 9461 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 171149 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8455 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3870 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 12325 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 920 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1168 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2088 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 10724 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 8176 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 18900 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 27 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 5 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 17706 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 19557 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 130446 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 17319 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 18842 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 128828 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 5089 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 11757 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 10677 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 195276 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 28 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 5241 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 10314 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 9461 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 190049 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 27 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 5 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 17706 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 19557 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 130446 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 17319 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 18842 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 128828 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 5089 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 11757 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 10677 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 195276 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2189250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 365750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1235097219 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 646670292 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12862638093 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 812500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 70500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 370572993 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 190918836 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1336066301 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 16645401734 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 149850873 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 67813301 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 217664174 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16896440 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20270643 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 37167083 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 939052460 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 662623777 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1601676237 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2189250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 365750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1235097219 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 1585722752 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12862638093 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 812500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 70500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 370572993 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 853542613 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1336066301 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 18247077971 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2189250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 365750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1235097219 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 1585722752 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12862638093 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 812500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 70500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 370572993 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 853542613 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1336066301 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 18247077971 # number of overall MSHR miss cycles +system.l2c.overall_mshr_misses::cpu1.inst 5241 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 10314 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 9461 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 190049 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3002 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 17965 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 100 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17055 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 38122 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16714 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 31055 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3002 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34679 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 100 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 31396 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 69177 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2258000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 380000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1209530708 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 633945550 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12753851063 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1069000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 84250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 381902000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 159442409 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1140236224 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 16282699204 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 150732427 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 68800353 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 219532780 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16443920 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20736167 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 37180087 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 905183749 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 576557769 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1481741518 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2258000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 380000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1209530708 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1539129299 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12753851063 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1069000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 84250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 381902000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 736000178 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1140236224 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 17764440722 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2258000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 380000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1209530708 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1539129299 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12753851063 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1069000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 84250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 381902000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 736000178 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1140236224 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 17764440722 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 181479250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4804405000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5954500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 824214500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5816053250 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3576332065 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 720875502 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4297207567 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3198370250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5885000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2430251250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5815985750 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2250411545 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2045879002 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4296290547 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 181479250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8380737065 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5954500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1545090002 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10113260817 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.130233 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.053191 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.354007 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.154597 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.752944 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.228729 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.173843 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.584241 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.526303 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.772397 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.828807 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.789164 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.791457 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.949293 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.870672 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.755435 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.839218 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.791037 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.130233 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.053191 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.354007 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.285904 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.752944 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.228729 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.463750 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.584241 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.545528 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.130233 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.053191 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.354007 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.285904 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.752944 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.228729 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.463750 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.584241 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.545528 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 78187.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 73150 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69755.857845 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 78251.487415 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98605.078676 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 81250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72818.430536 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76766.721351 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125134.991196 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 95272.828776 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17826.656317 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17775.439318 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17810.668030 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17879.830688 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17750.125219 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17808.856253 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83153.498627 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71480.450593 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 77891.175266 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78187.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73150 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69755.857845 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 81082.106254 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98605.078676 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72818.430536 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72598.674237 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125134.991196 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 93442.501746 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78187.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73150 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69755.857845 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 81082.106254 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98605.078676 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72818.430536 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72598.674237 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125134.991196 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 93442.501746 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5448781795 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5885000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4476130252 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10112276297 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.137755 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.068493 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.354201 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.151963 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748891 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.139241 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.029412 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.237989 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.162672 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.566120 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.524031 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.766546 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.825160 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.784033 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.782979 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.922591 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.855387 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.734722 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.788276 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.756969 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.137755 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.068493 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.354201 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.277019 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748891 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.139241 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.029412 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.237989 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.438614 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.566120 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.540574 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.137755 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.068493 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.354201 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.277019 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748891 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.139241 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.029412 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.237989 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.438614 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.566120 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.540574 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 83629.629630 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 76000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69838.368728 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 78091.346391 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98999.061252 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 97181.818182 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 84250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72868.154932 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74575.495323 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120519.630483 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 95137.565536 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17827.608161 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17777.868992 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17811.990264 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17873.826087 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17753.567637 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17806.555077 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 84407.287300 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70518.318126 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 78399.022116 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83629.629630 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 76000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69838.368728 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 81686.089534 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98999.061252 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 97181.818182 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 84250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72868.154932 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71359.334691 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120519.630483 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 93472.950250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83629.629630 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 76000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69838.368728 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 81686.089534 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98999.061252 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 97181.818182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 84250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72868.154932 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71359.334691 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120519.630483 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 93472.950250 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60452.781479 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 178033.412190 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58850 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142494.942832 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 152562.450816 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 134642.308544 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 142659.438114 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138344.567606 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60452.781479 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 157120.499294 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58850 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 142570.080647 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 146179.746115 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 213069 # Transaction distribution -system.membus.trans_dist::ReadResp 213068 # Transaction distribution -system.membus.trans_dist::WriteReq 31079 # Transaction distribution -system.membus.trans_dist::WriteResp 31079 # Transaction distribution -system.membus.trans_dist::Writeback 139403 # Transaction distribution +system.membus.trans_dist::ReadReq 209523 # Transaction distribution +system.membus.trans_dist::ReadResp 209522 # Transaction distribution +system.membus.trans_dist::WriteReq 31055 # Transaction distribution +system.membus.trans_dist::WriteResp 31055 # Transaction distribution +system.membus.trans_dist::Writeback 134913 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 77234 # Transaction distribution +system.membus.trans_dist::UpgradeReq 78034 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 41651 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14409 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution -system.membus.trans_dist::ReadExReq 40484 # Transaction distribution -system.membus.trans_dist::ReadExResp 20462 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14508 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution +system.membus.trans_dist::ReadExReq 38508 # Transaction distribution +system.membus.trans_dist::ReadExResp 18805 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14202 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 662750 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 784904 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14300 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 648289 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 770541 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108921 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 893825 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 879462 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162793 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28404 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19143964 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19335481 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18522228 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18713941 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23971961 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 125081 # Total snoops (count) -system.membus.snoop_fanout::samples 510035 # Request fanout histogram +system.membus.pkt_size::total 23350421 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 125464 # Total snoops (count) +system.membus.snoop_fanout::samples 569969 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 510035 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 569969 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 510035 # Request fanout histogram -system.membus.reqLayer0.occupancy 81680000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 569969 # Request fanout histogram +system.membus.reqLayer0.occupancy 81685500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 28500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11944988 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12047488 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1164089698 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1135057072 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1154561869 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1127535962 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37506493 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 37496988 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -3557,48 +3593,48 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 494432 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 494416 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31079 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31079 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 232253 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 80398 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41961 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 122359 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50963 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50963 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1036150 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 339974 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1376124 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31294456 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6755201 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 38049657 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 290334 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 898197 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.040648 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.197474 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 490298 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 490282 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31055 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 227479 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36263 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 81334 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 42004 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 123338 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 34 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50269 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50269 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 990291 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 371073 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1361364 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 30980096 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6355093 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 37335189 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 292587 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 958737 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.038087 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.191405 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 861687 95.94% 95.94% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36510 4.06% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 922222 96.19% 96.19% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36515 3.81% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 898197 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 772973190 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 958737 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 763418418 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 355500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 636594669 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 618495385 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 265283017 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 276060555 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 2070 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2748 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2756 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 5de8c3a92..674e14430 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.827616 # Nu sim_ticks 2827616186000 # Number of ticks simulated final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94820 # Simulator instruction rate (inst/s) -host_op_rate 115016 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2369528287 # Simulator tick rate (ticks/s) -host_mem_usage 555256 # Number of bytes of host memory used -host_seconds 1193.32 # Real time elapsed on the host +host_inst_rate 97479 # Simulator instruction rate (inst/s) +host_op_rate 118241 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2435971946 # Simulator tick rate (ticks/s) +host_mem_usage 621864 # Number of bytes of host memory used +host_seconds 1160.78 # Real time elapsed on the host sim_insts 113151083 # Number of instructions simulated sim_ops 137250963 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -16,9 +16,9 @@ system.clk_domain.clock 1000 # Cl system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1325344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9769956 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9769960 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11098052 # Number of bytes read from this memory +system.physmem.bytes_read::total 11098056 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1325344 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1325344 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 8387584 # Number of bytes written to this memory @@ -27,18 +27,18 @@ system.physmem.bytes_written::total 8405108 # Nu system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 22954 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 153175 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 153176 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 176172 # Number of read requests responded to by this memory +system.physmem.num_reads::total 176173 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 131056 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::total 135437 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 468714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3455192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3455193 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3924879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3924881 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 468714 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 468714 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 2966309 # Write bandwidth from this memory (bytes/s) @@ -48,19 +48,19 @@ system.physmem.bw_total::writebacks 2966309 # To system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 468714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3461389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3461391 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6897386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 176173 # Number of read requests accepted +system.physmem.bw_total::total 6897387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 176174 # Number of read requests accepted system.physmem.writeReqs 171661 # Number of write requests accepted -system.physmem.readBursts 176173 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 176174 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 171661 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 11266304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue +system.physmem.bytesReadWrQ 8832 # Total number of bytes read from write queue system.physmem.bytesWritten 9457344 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11098116 # Total read bytes from the system interface side +system.physmem.bytesReadSys 11098120 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 10723444 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 138 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 23861 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4579 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 11334 # Per bank write bursts @@ -100,7 +100,7 @@ system.physmem.numWrRetry 58 # Nu system.physmem.totGap 2827615975000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 541 # Read request sizes (log2) +system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 2994 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) @@ -265,12 +265,12 @@ system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Wr system.physmem.wrPerTurnAround::752-767 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 6252 # Writes before turning the bus around for reads -system.physmem.totQLat 2104910750 # Total ticks spent queuing -system.physmem.totMemAccLat 5405585750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2104913750 # Total ticks spent queuing +system.physmem.totMemAccLat 5405588750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 880180000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11957.27 # Average queueing delay per DRAM burst +system.physmem.avgQLat 11957.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30707.27 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30707.29 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.34 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s @@ -285,35 +285,35 @@ system.physmem.readRowHits 145058 # Nu system.physmem.writeRowHits 112529 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes -system.physmem.avgGap 8129210.99 # Average gap between requests +system.physmem.avgGap 8129187.62 # Average gap between requests system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 260517600 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 142147500 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 718356600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 486693360 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 81488168145 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625088669750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1892870659755 # Total energy per rank (pJ) +system.physmem_0.actBackEnergy 81488169855 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625088668250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1892870659965 # Total energy per rank (pJ) system.physmem_0.averagePower 669.422846 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2703351125494 # Time in different power states +system.physmem_0.memoryStateTime::IDLE 2703351122494 # Time in different power states system.physmem_0.memoryStateTime::REF 94420300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 29844453256 # Time in different power states +system.physmem_0.memoryStateTime::ACT 29844456256 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 240098040 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 131005875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 654716400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 470862720 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 80123989140 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1626285318000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1892592096975 # Total energy per rank (pJ) +system.physmem_1.actBackEnergy 80123990850 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626285316500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1892592097185 # Total energy per rank (pJ) system.physmem_1.averagePower 669.324331 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2705354979994 # Time in different power states +system.physmem_1.memoryStateTime::IDLE 2705354976994 # Time in different power states system.physmem_1.memoryStateTime::REF 94420300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27840892506 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27840895506 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory @@ -431,7 +431,7 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7962 system.cpu.dtb.walker.walkRequestOrigin::total 80333 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25461870 # DTB read hits +system.cpu.dtb.read_hits 25461869 # DTB read hits system.cpu.dtb.read_misses 62291 # DTB read misses system.cpu.dtb.write_hits 19915387 # DTB write hits system.cpu.dtb.write_misses 10080 # DTB write misses @@ -444,12 +444,12 @@ system.cpu.dtb.align_faults 348 # Nu system.cpu.dtb.prefetch_faults 2290 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 1335 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25524161 # DTB read accesses +system.cpu.dtb.read_accesses 25524160 # DTB read accesses system.cpu.dtb.write_accesses 19925467 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45377257 # DTB hits +system.cpu.dtb.hits 45377256 # DTB hits system.cpu.dtb.misses 72371 # DTB misses -system.cpu.dtb.accesses 45449628 # DTB accesses +system.cpu.dtb.accesses 45449627 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -591,15 +591,15 @@ system.cpu.decode.SquashedInsts 3690202 # Nu system.cpu.rename.SquashCycles 2601803 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 83861883 # Number of cycles rename is idle system.cpu.rename.BlockCycles 10277178 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 74822970 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 74822964 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 62634848 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 22677863 # Number of cycles rename is unblocking +system.cpu.rename.UnblockCycles 22677869 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 146804130 # Number of instructions processed by rename system.cpu.rename.SquashedInsts 949467 # Number of squashed instructions processed by rename system.cpu.rename.ROBFullEvents 441862 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 64017 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 17858 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 19908146 # Number of times rename has blocked due to SQ full +system.cpu.rename.SQFullEvents 19908152 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 150492299 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 678751292 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 164435882 # Number of integer rename lookups @@ -615,7 +615,7 @@ system.cpu.memDep0.conflictingLoads 1687720 # Nu system.cpu.memDep0.conflictingStores 2166938 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 143540852 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143328299 # Number of instructions issued +system.cpu.iq.iqInstsIssued 143328298 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 8409052 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph @@ -624,8 +624,8 @@ system.cpu.iq.issued_per_cycle::samples 256876545 # Nu system.cpu.iq.issued_per_cycle::mean 0.557966 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 0.879925 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 168573863 65.62% 65.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45206233 17.60% 83.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 168573864 65.62% 65.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45206232 17.60% 83.22% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 31980064 12.45% 95.67% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 10303635 4.01% 99.68% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 812717 0.32% 100.00% # Number of insts issued each cycle @@ -701,21 +701,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 8586 0.01% 67.07% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26193107 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26193106 18.27% 85.34% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 21007096 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143328299 # Type of FU issued +system.cpu.iq.FU_type_0::total 143328298 # Type of FU issued system.cpu.iq.rate 0.544758 # Inst issue rate system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 566346239 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 566346237 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 154074171 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 13216 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165879209 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 165879208 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 323617 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -725,7 +725,7 @@ system.cpu.iew.lsq.thread0.memOrderViolation 18357 system.cpu.iew.lsq.thread0.squashedStores 705133 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 87835 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 87833 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 6849 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 2601803 # Number of cycles IEW is squashing @@ -742,16 +742,16 @@ system.cpu.iew.memOrderViolationEvents 18357 # Nu system.cpu.iew.predictedTakenIncorrect 317506 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 471434 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 788940 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142382518 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25789726 # Number of load instructions executed +system.cpu.iew.iewExecutedInsts 142382517 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25789725 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 873528 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 201053 # number of nop insts executed -system.cpu.iew.exec_refs 46667575 # number of memory reference insts executed +system.cpu.iew.exec_refs 46667574 # number of memory reference insts executed system.cpu.iew.exec_branches 26530134 # Number of branches executed system.cpu.iew.exec_stores 20877849 # Number of stores executed system.cpu.iew.exec_rate 0.541163 # Inst execution rate -system.cpu.iew.wb_sent 141996043 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent 141996041 # cumulative count of insts sent to commit system.cpu.iew.wb_count 140222490 # cumulative count of insts written-back system.cpu.iew.wb_producers 63271750 # num instructions producing a value system.cpu.iew.wb_consumers 95823649 # num instructions consuming a value @@ -836,13 +836,13 @@ system.cpu.cpi 2.325250 # CP system.cpu.cpi_total 2.325250 # CPI: Total CPI of All Threads system.cpu.ipc 0.430061 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.430061 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155826637 # number of integer regfile reads +system.cpu.int_regfile_reads 155826636 # number of integer regfile reads system.cpu.int_regfile_writes 88633021 # number of integer regfile writes system.cpu.fp_regfile_reads 9606 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502981881 # number of cc regfile reads +system.cpu.cc_regfile_reads 502981878 # number of cc regfile reads system.cpu.cc_regfile_writes 53178096 # number of cc regfile writes -system.cpu.misc_regfile_reads 446088161 # number of misc regfile reads +system.cpu.misc_regfile_reads 446088160 # number of misc regfile reads system.cpu.misc_regfile_writes 1519760 # number of misc regfile writes system.cpu.dcache.tags.replacements 839617 # number of replacements system.cpu.dcache.tags.tagsinuse 511.954240 # Cycle average of tags in use @@ -890,16 +890,16 @@ system.cpu.dcache.overall_misses::cpu.data 4478306 # system.cpu.dcache.overall_misses::total 4478306 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 10273111663 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 10273111663 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502760344 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 149502760344 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502808344 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 149502808344 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365521996 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 365521996 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 209000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 209000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 159775872007 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 159775872007 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 159775872007 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 159775872007 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 159775920007 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 159775920007 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 159775920007 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 159775920007 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 24021805 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 24021805 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19156176 # number of WriteReq accesses(hits+misses) @@ -930,16 +930,16 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.102475 system.cpu.dcache.overall_miss_rate::total 0.102475 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14556.964202 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 14556.964202 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.568194 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.568194 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.581546 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.581546 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13607.400640 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13607.400640 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.680485 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37149.680485 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.747793 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35677.747793 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.691645 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37149.691645 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.758511 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35677.758511 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 582483 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 7397 # number of cycles access was blocked @@ -974,26 +974,32 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 714916 system.cpu.dcache.demand_mshr_misses::total 714916 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 834525 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 834525 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5660697158 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 5660697158 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235278165 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235278165 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235281165 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235281165 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562991253 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562991253 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 123125251 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 123125251 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895975323 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18895975323 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458966576 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20458966576 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831900750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831900750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895978323 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18895978323 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458969576 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20458969576 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831942750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831942750 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4511868951 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4511868951 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343769701 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343769701 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343811701 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343811701 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017261 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017261 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015675 # mshr miss rate for WriteReq accesses @@ -1010,24 +1016,24 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019096 system.cpu.dcache.overall_mshr_miss_rate::total 0.019096 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13652.043956 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13652.043956 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.189793 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.189793 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.199784 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.199784 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13067.505397 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13067.505397 # average SoftPFReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14692.750716 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14692.750716 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40300 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40300 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.042700 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.042700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.702437 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.702437 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.046896 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.046896 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.706032 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.706032 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187359.615446 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187359.615446 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163568.334941 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163568.334941 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176181.834767 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176181.834767 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1892540 # number of replacements system.cpu.icache.tags.tagsinuse 511.345997 # Cycle average of tags in use @@ -1102,6 +1108,10 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1893071 system.cpu.icache.demand_mshr_misses::total 1893071 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1893071 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1893071 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable +system.cpu.icache.ReadReq_mshr_uncacheable::total 3002 # number of ReadReq MSHR uncacheable +system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 3002 # number of overall MSHR uncacheable misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23219754000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 23219754000 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23219754000 # number of demand (read+write) MSHR miss cycles @@ -1124,10 +1134,10 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12265.654062 system.cpu.icache.demand_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75071.952032 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75071.952032 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 103160 # number of replacements system.cpu.l2cache.tags.tagsinuse 65071.102218 # Cycle average of tags in use @@ -1211,18 +1221,18 @@ system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 966469 system.cpu.l2cache.UpgradeReq_miss_latency::total 966469 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 165000 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 165000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197750141 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11197750141 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197753141 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 11197753141 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1759750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 789750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 1637862750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12425243891 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14065656141 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12425246891 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14065659141 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1759750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 789750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 1637862750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12425243891 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14065656141 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12425246891 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14065659141 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 56051 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12594 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 1893036 # number of ReadReq accesses(hits+misses) @@ -1276,18 +1286,18 @@ system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 355.319485 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 355.319485 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82500 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82500 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.605529 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.605529 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.626875 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.626875 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80430.790095 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80430.807250 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80430.790095 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80430.807250 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1328,6 +1338,14 @@ system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 system.cpu.l2cache.overall_mshr_misses::cpu.inst 19963 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 154754 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 174745 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34129 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61713 # number of overall MSHR uncacheable misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1495250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 701750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1386544250 # number of ReadReq MSHR miss cycles @@ -1337,26 +1355,26 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48397220 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48397220 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440466859 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440466859 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440469859 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440469859 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1495250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 701750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1386544250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482081359 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11870822609 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482084359 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11870825609 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1495250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 701750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1386544250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482081359 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11870822609 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482084359 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11870825609 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 181832000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395641750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577473750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395669750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577501750 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151610000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151610000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 181832000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547251750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729083750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547279750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729111750 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for ReadReq accesses @@ -1387,29 +1405,29 @@ system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17793.095588 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17793.095588 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.811008 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.811008 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.832354 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.832354 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173343.712854 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163424.118785 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150507.903132 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150507.903132 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162614.837935 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157650.928492 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2564423 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2564403 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2564424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2564404 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 696320 # Transaction distribution @@ -1420,36 +1438,34 @@ system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # system.cpu.toL2Bus.trans_dist::ReadExReq 297641 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 297641 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3792109 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499775 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499777 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 131034 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6455012 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6455014 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121202208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530841 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530845 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50376 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224204 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 220007629 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 220007633 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 62589 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3563285 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.010244 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.100691 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 3624998 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.036134 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.186622 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3526784 98.98% 98.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 36501 1.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3494014 96.39% 96.39% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 130984 3.61% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3563285 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2504368234 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3624998 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2504368734 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 2847443747 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1338895897 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1338896897 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 19507738 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) @@ -1655,8 +1671,8 @@ system.iocache.demand_avg_mshr_miss_latency::total 70600.330472 system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 68566 # Transaction distribution -system.membus.trans_dist::ReadResp 68565 # Transaction distribution +system.membus.trans_dist::ReadReq 68567 # Transaction distribution +system.membus.trans_dist::ReadResp 68566 # Transaction distribution system.membus.trans_dist::WriteReq 27584 # Transaction distribution system.membus.trans_dist::WriteResp 27584 # Transaction distribution system.membus.trans_dist::Writeback 131056 # Transaction distribution @@ -1670,40 +1686,40 @@ system.membus.trans_dist::ReadExResp 138681 # Tr system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465380 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572944 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465382 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572946 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108886 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108886 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 681830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 681832 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349433 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186044 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349437 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21984889 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21984893 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 497 # Total snoops (count) -system.membus.snoop_fanout::samples 345038 # Request fanout histogram +system.membus.snoop_fanout::samples 406751 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 345038 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 406751 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 345038 # Request fanout histogram +system.membus.snoop_fanout::total 406751 # Request fanout histogram system.membus.reqLayer0.occupancy 83856500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 1725500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1057991143 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1057992643 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1020411671 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1020413671 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 37506490 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 4a1673e29..81d261f28 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.817778 # Nu sim_ticks 2817777605000 # Number of ticks simulated final_tick 2817777605000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 278686 # Simulator instruction rate (inst/s) -host_op_rate 338399 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6220604315 # Simulator tick rate (ticks/s) -host_mem_usage 555292 # Number of bytes of host memory used -host_seconds 452.98 # Real time elapsed on the host +host_inst_rate 294801 # Simulator instruction rate (inst/s) +host_op_rate 357967 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6580315461 # Simulator tick rate (ticks/s) +host_mem_usage 623656 # Number of bytes of host memory used +host_seconds 428.21 # Real time elapsed on the host sim_insts 126237777 # Number of instructions simulated sim_ops 153286368 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -775,6 +775,15 @@ system.cpu0.dcache.demand_mshr_misses::total 372246 system.cpu0.dcache.overall_mshr_misses::cpu1.data 114514 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu2.data 322025 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 436539 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 5880 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 8599 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14479 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 4601 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 6739 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 11340 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 10481 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 15338 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 25819 # number of overall MSHR uncacheable misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 823130250 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2155055358 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2978185608 # number of ReadReq MSHR miss cycles @@ -844,15 +853,15 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26892.807885 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21649.046667 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26000.062865 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24858.693436 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177408.078231 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 196862.425863 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188961.910353 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174550.967181 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 194575.011129 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186450.617284 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 176153.849823 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 195857.412961 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 187858.921724 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1799096 # number of replacements system.cpu0.icache.tags.tagsinuse 511.534039 # Cycle average of tags in use @@ -2270,6 +2279,15 @@ system.l2c.overall_mshr_misses::cpu2.dtb.walker 92 system.l2c.overall_mshr_misses::cpu2.inst 8124 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.data 64429 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 91595 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5880 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2.data 8599 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 14479 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4601 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2.data 6739 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 11340 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10481 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2.data 15338 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 25819 # number of overall MSHR uncacheable misses system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 70000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 132598250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.data 173127242 # number of ReadReq MSHR miss cycles @@ -2366,15 +2384,15 @@ system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 73211.956522 system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 71458.148695 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69541.309084 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 69076.292636 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163404.166667 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 182859.169671 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 174958.388010 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161549.228429 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 181573.304645 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 173448.897707 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 162589.876920 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 182294.203938 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 174295.402610 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 74250 # Transaction distribution system.membus.trans_dist::ReadResp 74249 # Transaction distribution @@ -2405,17 +2423,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4642624 system.membus.pkt_size_system.iocache.mem_side::total 4642624 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 21734523 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 283 # Total snoops (count) -system.membus.snoop_fanout::samples 341064 # Request fanout histogram +system.membus.snoop_fanout::samples 408724 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 341064 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 408724 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 341064 # Request fanout histogram +system.membus.snoop_fanout::total 408724 # Request fanout histogram system.membus.reqLayer0.occupancy 45631500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 463000 # Layer occupancy (ticks) @@ -2479,19 +2497,17 @@ system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 4 system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 154828 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 213072335 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 51752 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3427725 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.010649 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.102642 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 3495385 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.029269 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.168561 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3391224 98.94% 98.94% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 36501 1.06% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3393077 97.07% 97.07% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 102308 2.93% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3427725 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3495385 # Request fanout histogram system.toL2Bus.reqLayer0.occupancy 1275217471 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 177000 # Layer occupancy (ticks) diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 220af110d..db0feca69 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.804323 # Nu sim_ticks 2804323403500 # Number of ticks simulated final_tick 2804323403500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105186 # Simulator instruction rate (inst/s) -host_op_rate 127668 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2521360773 # Simulator tick rate (ticks/s) -host_mem_usage 559780 # Number of bytes of host memory used -host_seconds 1112.23 # Real time elapsed on the host +host_inst_rate 111575 # Simulator instruction rate (inst/s) +host_op_rate 135423 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2674508102 # Simulator tick rate (ticks/s) +host_mem_usage 626368 # Number of bytes of host memory used +host_seconds 1048.54 # Real time elapsed on the host sim_insts 116990114 # Number of instructions simulated sim_ops 141995948 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -19,9 +19,9 @@ system.physmem.bytes_read::cpu0.inst 690752 # Nu system.physmem.bytes_read::cpu0.data 4989088 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 4032 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 687552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4838852 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4838856 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11215652 # Number of bytes read from this memory +system.physmem.bytes_read::total 11215656 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 690752 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 687552 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1378304 # Number of instructions bytes read from this memory @@ -35,9 +35,9 @@ system.physmem.num_reads::cpu0.inst 10793 # Nu system.physmem.num_reads::cpu0.data 78473 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 63 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 10743 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75608 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75609 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 175764 # Number of read requests responded to by this memory +system.physmem.num_reads::total 175765 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 131657 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory @@ -48,9 +48,9 @@ system.physmem.bw_read::cpu0.inst 246317 # To system.physmem.bw_read::cpu0.data 1779070 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 1438 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 245176 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1725497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1725499 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3999415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3999416 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 246317 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 245176 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 491493 # Instruction read bandwidth from this memory (bytes/s) @@ -65,19 +65,19 @@ system.physmem.bw_total::cpu0.inst 246317 # To system.physmem.bw_total::cpu0.data 1785316 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 1438 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 245176 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1725500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1725501 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 342 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7010327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 175765 # Number of read requests accepted +system.physmem.bw_total::total 7010328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 175766 # Number of read requests accepted system.physmem.writeReqs 172232 # Number of write requests accepted -system.physmem.readBursts 175765 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 175766 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 172232 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 11239872 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue +system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue system.physmem.bytesWritten 9513088 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11215716 # Total read bytes from the system interface side +system.physmem.bytesReadSys 11215720 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 10759988 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 23563 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4633 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 11568 # Per bank write bursts @@ -117,7 +117,7 @@ system.physmem.numWrRetry 53 # Nu system.physmem.totGap 2804323239500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 541 # Read request sizes (log2) +system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) @@ -279,12 +279,12 @@ system.physmem.wrPerTurnAround::528-543 1 0.02% 99.89% # Wr system.physmem.wrPerTurnAround::544-559 6 0.10% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::608-623 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 6306 # Writes before turning the bus around for reads -system.physmem.totQLat 2686689750 # Total ticks spent queuing -system.physmem.totMemAccLat 5979621000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2686692750 # Total ticks spent queuing +system.physmem.totMemAccLat 5979624000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 878115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15298.05 # Average queueing delay per DRAM burst +system.physmem.avgQLat 15298.07 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34048.05 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 34048.07 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.01 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.39 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.00 # Average system read bandwidth in MiByte/s @@ -299,7 +299,7 @@ system.physmem.readRowHits 145297 # Nu system.physmem.writeRowHits 112992 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.73 # Row buffer hit rate for reads system.physmem.writeRowHitRate 76.00 # Row buffer hit rate for writes -system.physmem.avgGap 8058469.58 # Average gap between requests +system.physmem.avgGap 8058446.43 # Average gap between requests system.physmem.pageHitRate 79.65 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 264138840 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 144123375 # Energy for precharge commands per rank (pJ) @@ -1054,6 +1054,15 @@ system.cpu0.dcache.demand_mshr_misses::total 724963 system.cpu0.dcache.overall_mshr_misses::cpu0.data 427411 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu1.data 420424 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 847835 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16558 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 14569 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16166 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 11418 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32724 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 25987 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2911652660 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2946522646 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5858175306 # number of ReadReq MSHR miss cycles @@ -1076,14 +1085,14 @@ system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10800326180 system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10511181656 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 21311507836 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3107181500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2733312000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5840493500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2733353000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5840534500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2374455377 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2136736500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4511191877 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5481636877 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4870048500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10351685377 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4870089500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10351726377 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016596 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015934 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016259 # mshr miss rate for ReadReq accesses @@ -1126,15 +1135,15 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27090.051611 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25269.181607 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25001.383499 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25136.386014 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 187654.396666 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187614.318073 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187635.637871 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 146879.585364 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 187137.545980 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163543.789044 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 167511.211252 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 187404.837034 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176316.642145 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1944350 # number of replacements system.cpu0.icache.tags.tagsinuse 511.567211 # Cycle average of tags in use @@ -1174,14 +1183,14 @@ system.cpu0.icache.overall_misses::cpu0.inst 1041065 system.cpu0.icache.overall_misses::cpu1.inst 1047869 # number of overall misses system.cpu0.icache.overall_misses::total 2088934 # number of overall misses system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14016266373 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14162864905 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 28179131278 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14162867905 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 28179134278 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency::cpu0.inst 14016266373 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 14162864905 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 28179131278 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 14162867905 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 28179134278 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency::cpu0.inst 14016266373 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 14162864905 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 28179131278 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 14162867905 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 28179134278 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 20232960 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::cpu1.inst 20978073 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 41211033 # number of ReadReq accesses(hits+misses) @@ -1201,14 +1210,14 @@ system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051454 system.cpu0.icache.overall_miss_rate::cpu1.inst 0.049951 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.050689 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13463.392173 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13515.873554 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13489.718334 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13515.876417 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13489.719770 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13463.392173 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13515.873554 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13489.718334 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13515.876417 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13489.719770 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13463.392173 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13515.873554 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13489.718334 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13515.876417 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13489.719770 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 10636 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 597 # number of cycles access was blocked @@ -1235,15 +1244,19 @@ system.cpu0.icache.demand_mshr_misses::total 1944951 system.cpu0.icache.overall_mshr_misses::cpu0.inst 969720 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::cpu1.inst 975231 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 1944951 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 666 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 666 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 666 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 666 # number of overall MSHR uncacheable misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11896534814 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 12012710558 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 23909245372 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 12012713558 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 23909248372 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11896534814 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 12012710558 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 23909245372 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 12012713558 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 23909248372 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11896534814 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 12012710558 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 23909245372 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 12012713558 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 23909248372 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 52863250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 52863250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 52863250 # number of overall MSHR uncacheable cycles @@ -1258,18 +1271,18 @@ system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047928 system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046488 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.047195 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12268.010162 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12317.810404 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12292.980837 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12317.813480 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12292.982380 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12268.010162 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12317.810404 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12292.980837 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12317.813480 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12292.982380 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12268.010162 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12317.810404 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12292.980837 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12317.813480 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12292.982380 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 79374.249249 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 79374.249249 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 79374.249249 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 79374.249249 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.branchPred.lookups 27831531 # Number of BP lookups system.cpu1.branchPred.condPredicted 14488346 # Number of conditional branches predicted @@ -1372,7 +1385,7 @@ system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5226 system.cpu1.dtb.walker.walkRequestOrigin::total 63374 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 14522718 # DTB read hits +system.cpu1.dtb.read_hits 14522717 # DTB read hits system.cpu1.dtb.read_misses 49745 # DTB read misses system.cpu1.dtb.write_hits 10695995 # DTB write hits system.cpu1.dtb.write_misses 8403 # DTB write misses @@ -1385,12 +1398,12 @@ system.cpu1.dtb.align_faults 922 # Nu system.cpu1.dtb.prefetch_faults 1213 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 578 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 14572463 # DTB read accesses +system.cpu1.dtb.read_accesses 14572462 # DTB read accesses system.cpu1.dtb.write_accesses 10704398 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 25218713 # DTB hits +system.cpu1.dtb.hits 25218712 # DTB hits system.cpu1.dtb.misses 58148 # DTB misses -system.cpu1.dtb.accesses 25276861 # DTB accesses +system.cpu1.dtb.accesses 25276860 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1502,7 +1515,7 @@ system.cpu1.fetch.icacheStallCycles 40802320 # Nu system.cpu1.fetch.Insts 108613899 # Number of instructions fetch has processed system.cpu1.fetch.Branches 27831531 # Number of branches that fetch encountered system.cpu1.fetch.predictedBranches 19968612 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 63156516 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.Cycles 63156510 # Number of cycles fetch has run and was not squashing or blocked system.cpu1.fetch.SquashCycles 3276855 # Number of cycles fetch has spent squashing system.cpu1.fetch.TlbCycles 120748 # Number of cycles fetch has spent waiting for tlb system.cpu1.fetch.MiscStallCycles 7463 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs @@ -1513,11 +1526,11 @@ system.cpu1.fetch.IcacheWaitRetryStallCycles 290 system.cpu1.fetch.CacheLines 20978077 # Number of cache lines fetched system.cpu1.fetch.IcacheSquashes 379105 # Number of outstanding Icache misses that were squashed system.cpu1.fetch.ItlbSquashes 3473 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 106194794 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::samples 106194788 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::mean 1.229505 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::stdev 2.326126 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 76382369 71.93% 71.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 76382363 71.93% 71.93% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::1 3967856 3.74% 75.66% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::2 2509209 2.36% 78.03% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::3 8248224 7.77% 85.79% # Number of instructions fetched each cycle (Total) @@ -1529,11 +1542,11 @@ system.cpu1.fetch.rateDist::8 4785005 4.51% 100.00% # Nu system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 106194794 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::total 106194788 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.branchRate 0.255909 # Number of branch fetches per cycle system.cpu1.fetch.rate 0.998697 # Number of inst fetches per cycle system.cpu1.decode.IdleCycles 27865394 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 59086639 # Number of cycles decode is blocked +system.cpu1.decode.BlockedCycles 59086633 # Number of cycles decode is blocked system.cpu1.decode.RunCycles 16014101 # Number of cycles decode is running system.cpu1.decode.UnblockCycles 1741536 # Number of cycles decode is unblocking system.cpu1.decode.SquashCycles 1486862 # Number of cycles decode is squashing @@ -1544,7 +1557,7 @@ system.cpu1.decode.SquashedInsts 499096 # Nu system.cpu1.rename.SquashCycles 1486862 # Number of cycles rename is squashing system.cpu1.rename.IdleCycles 28829421 # Number of cycles rename is idle system.cpu1.rename.BlockCycles 4993628 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 46364709 # count of cycles rename stalled for serializing inst +system.cpu1.rename.serializeStallCycles 46364703 # count of cycles rename stalled for serializing inst system.cpu1.rename.RunCycles 16784538 # Number of cycles rename is running system.cpu1.rename.UnblockCycles 7735362 # Number of cycles rename is unblocking system.cpu1.rename.RenamedInsts 86665296 # Number of instructions processed by rename @@ -1567,17 +1580,17 @@ system.cpu1.memDep0.conflictingLoads 2188376 # Nu system.cpu1.memDep0.conflictingStores 2888870 # Number of conflicting stores. system.cpu1.iq.iqInstsAdded 83375619 # Number of instructions added to the IQ (excludes non-spec) system.cpu1.iq.iqNonSpecInstsAdded 1158159 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 79910900 # Number of instructions issued +system.cpu1.iq.iqInstsIssued 79910899 # Number of instructions issued system.cpu1.iq.iqSquashedInstsIssued 92494 # Number of squashed instructions issued system.cpu1.iq.iqSquashedInstsExamined 11441232 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu1.iq.iqSquashedOperandsExamined 25615832 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.iq.iqSquashedNonSpecRemoved 107265 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 106194794 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::samples 106194788 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::mean 0.752494 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::stdev 1.434563 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 74167078 69.84% 69.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10703730 10.08% 79.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 74167073 69.84% 69.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10703729 10.08% 79.92% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::2 8178605 7.70% 87.62% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::3 6800959 6.40% 94.03% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::4 2513016 2.37% 96.39% # Number of insts issued each cycle @@ -1588,7 +1601,7 @@ system.cpu1.iq.issued_per_cycle::8 243435 0.23% 100.00% # Nu system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 106194794 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 106194788 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IntAlu 110018 9.66% 9.66% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 6 0.00% 9.66% # attempts to use FU when none available @@ -1653,21 +1666,21 @@ system.cpu1.iq.FU_type_0::SimdFloatMisc 4262 0.01% 67.14% # Ty system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.14% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 67.14% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 14931901 18.69% 85.82% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 14931900 18.69% 85.82% # Type of FU issued system.cpu1.iq.FU_type_0::MemWrite 11328871 14.18% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 79910900 # Type of FU issued +system.cpu1.iq.FU_type_0::total 79910899 # Type of FU issued system.cpu1.iq.rate 0.734775 # Inst issue rate system.cpu1.iq.fu_busy_cnt 1139082 # FU busy when requested system.cpu1.iq.fu_busy_rate 0.014254 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 267236211 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_reads 267236203 # Number of integer instruction queue reads system.cpu1.iq.int_inst_queue_writes 96019084 # Number of integer instruction queue writes system.cpu1.iq.int_inst_queue_wakeup_accesses 77543645 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 11959 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 6290 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 5191 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 81043378 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 81043377 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 6453 # Number of floating point alu accesses system.cpu1.iew.lsq.thread0.forwLoads 351971 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -1677,7 +1690,7 @@ system.cpu1.iew.lsq.thread0.memOrderViolation 51509 system.cpu1.iew.lsq.thread0.squashedStores 1138977 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 192559 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.rescheduledLoads 192557 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 108870 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu1.iew.iewSquashCycles 1486862 # Number of cycles IEW is squashing @@ -1691,19 +1704,19 @@ system.cpu1.iew.iewDispNonSpecInsts 585252 # Nu system.cpu1.iew.iewIQFullEvents 42277 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 608480 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.memOrderViolationEvents 51509 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 260306 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 260301 # Number of branches that were predicted taken incorrectly system.cpu1.iew.predictedNotTakenIncorrect 223242 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 483548 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 79294807 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 14687603 # Number of load instructions executed +system.cpu1.iew.branchMispredicts 483543 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 79294806 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 14687602 # Number of load instructions executed system.cpu1.iew.iewExecSquashedInsts 558095 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed system.cpu1.iew.exec_nop 123637 # number of nop insts executed -system.cpu1.iew.exec_refs 25906138 # number of memory reference insts executed +system.cpu1.iew.exec_refs 25906137 # number of memory reference insts executed system.cpu1.iew.exec_branches 14775343 # Number of branches executed system.cpu1.iew.exec_stores 11218535 # Number of stores executed system.cpu1.iew.exec_rate 0.729110 # Inst execution rate -system.cpu1.iew.wb_sent 78721985 # cumulative count of insts sent to commit +system.cpu1.iew.wb_sent 78721983 # cumulative count of insts sent to commit system.cpu1.iew.wb_count 77548836 # cumulative count of insts written-back system.cpu1.iew.wb_producers 40818570 # num instructions producing a value system.cpu1.iew.wb_consumers 71550295 # num instructions consuming a value @@ -1714,11 +1727,11 @@ system.cpu1.iew.wb_penalized_rate 0 # fr system.cpu1.commit.commitSquashedInsts 11482053 # The number of squashed insts skipped by commit system.cpu1.commit.commitNonSpecStalls 1050894 # The number of times commit has been forced to stall to communicate backwards system.cpu1.commit.branchMispredicts 406174 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 103612513 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::samples 103612507 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::mean 0.706116 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::stdev 1.593552 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 75208985 72.59% 72.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 75208979 72.59% 72.59% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::1 12628786 12.19% 84.78% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::2 6551089 6.32% 91.10% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::3 2721278 2.63% 93.72% # Number of insts commited each cycle @@ -1730,7 +1743,7 @@ system.cpu1.commit.committed_per_cycle::8 1807529 1.74% 100.00% # N system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 103612513 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::total 103612507 # Number of insts commited each cycle system.cpu1.commit.committedInsts 60426665 # Number of instructions committed system.cpu1.commit.committedOps 73162446 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed @@ -1777,10 +1790,10 @@ system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::total 73162446 # Class of committed instruction system.cpu1.commit.bw_lim_events 1807529 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 173729023 # The number of ROB reads +system.cpu1.rob.rob_reads 173729017 # The number of ROB reads system.cpu1.rob.rob_writes 171875858 # The number of ROB writes system.cpu1.timesIdled 390006 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2560821 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.idleCycles 2560827 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu1.quiesceCycles 2437360736 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu1.committedInsts 60356761 # Number of Instructions Simulated system.cpu1.committedOps 73092542 # Number of Ops (including micro ops) Simulated @@ -1788,13 +1801,13 @@ system.cpu1.cpi 1.801880 # CP system.cpu1.cpi_total 1.801880 # CPI: Total CPI of All Threads system.cpu1.ipc 0.554976 # IPC: Instructions Per Cycle system.cpu1.ipc_total 0.554976 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 86251315 # number of integer regfile reads +system.cpu1.int_regfile_reads 86251314 # number of integer regfile reads system.cpu1.int_regfile_writes 49415173 # number of integer regfile writes system.cpu1.fp_regfile_reads 15994 # number of floating regfile reads system.cpu1.fp_regfile_writes 13022 # number of floating regfile writes -system.cpu1.cc_regfile_reads 279979129 # number of cc regfile reads +system.cpu1.cc_regfile_reads 279979126 # number of cc regfile reads system.cpu1.cc_regfile_writes 29562027 # number of cc regfile writes -system.cpu1.misc_regfile_reads 195055078 # number of misc regfile reads +system.cpu1.misc_regfile_reads 195055071 # number of misc regfile reads system.cpu1.misc_regfile_writes 795609 # number of misc regfile writes system.iobus.trans_dist::ReadReq 30198 # Transaction distribution system.iobus.trans_dist::ReadResp 30198 # Transaction distribution @@ -2109,9 +2122,9 @@ system.l2c.ReadReq_miss_latency::cpu0.itb.walker 68750 system.l2c.ReadReq_miss_latency::cpu0.inst 835233999 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.data 610760750 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 5497500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 894308500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 894311500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.data 720028000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 3071819249 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 3071822249 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu0.data 436986 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 406987 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 843973 # number of UpgradeReq miss cycles @@ -2126,17 +2139,17 @@ system.l2c.demand_miss_latency::cpu0.itb.walker 68750 system.l2c.demand_miss_latency::cpu0.inst 835233999 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 6637230290 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 5497500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 894308500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 894311500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 6424786320 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 14803047109 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 14803050109 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 5921750 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 68750 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.inst 835233999 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 6637230290 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 5497500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 894308500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 894311500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 6424786320 # number of overall miss cycles -system.l2c.overall_miss_latency::total 14803047109 # number of overall miss cycles +system.l2c.overall_miss_latency::total 14803050109 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 36451 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 8251 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.inst 969612 # number of ReadReq accesses(hits+misses) @@ -2213,9 +2226,9 @@ system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 68750 system.l2c.ReadReq_avg_miss_latency::cpu0.inst 82345.854185 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 86473.276228 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87261.904762 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83191.488372 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83191.767442 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 88520.776985 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 84805.346171 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 84805.428993 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 300.747419 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 317.710383 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 308.695318 # average UpgradeReq miss latency @@ -2230,17 +2243,17 @@ system.l2c.demand_avg_miss_latency::cpu0.itb.walker 68750 system.l2c.demand_avg_miss_latency::cpu0.inst 82345.854185 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 83925.273946 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87261.904762 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 83191.488372 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 83191.767442 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 83707.298998 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 83697.817571 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 83697.834533 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87084.558824 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 68750 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 82345.854185 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 83925.273946 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87261.904762 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 83191.488372 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 83191.767442 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 83707.298998 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 83697.817571 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 83697.834533 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2299,14 +2312,25 @@ system.l2c.overall_mshr_misses::cpu1.dtb.walker 63 system.l2c.overall_mshr_misses::cpu1.inst 10744 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 76692 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 176717 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 666 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16558 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14569 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 31793 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16166 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11418 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 666 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 32724 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 25987 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 59377 # number of overall MSHR uncacheable misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5068250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 56250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 708062999 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.data 518326750 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4705500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 759667250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 759670250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.data 614985750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 2610872749 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2610875749 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25946451 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 22749281 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 48695732 # number of UpgradeReq MSHR miss cycles @@ -2321,28 +2345,28 @@ system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 56250 system.l2c.demand_mshr_miss_latency::cpu0.inst 708062999 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.data 5648283210 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 4705500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 759667250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 759670250 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 5469024930 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 12594868389 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 12594871389 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 5068250 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 56250 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 708062999 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.data 5648283210 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 4705500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 759667250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 759670250 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 5469024930 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 12594868389 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 12594871389 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 41164749 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2875017500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2529278000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5445460249 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2529305000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5445487249 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2162093500 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1988256000 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::total 4150349500 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 41164749 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5037111000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4517534000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 9595809749 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4517561000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 9595836749 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001866 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000121 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.010457 # mshr miss rate for ReadReq accesses @@ -2381,9 +2405,9 @@ system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 56250 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69835.585265 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74173.833715 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70706.184847 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70706.464073 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76178.093645 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 72371.458837 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 72371.541995 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17857.158293 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17759.001561 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17811.167520 # average UpgradeReq mshr miss latency @@ -2398,31 +2422,31 @@ system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 56250 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69835.585265 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 71488.206683 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70706.184847 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70706.464073 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71311.543968 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 71271.402236 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 71271.419213 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 74533.088235 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 56250 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69835.585265 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 71488.206683 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70706.184847 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70706.464073 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71311.543968 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 71271.402236 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_miss_latency::total 71271.419213 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 61808.932432 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173633.138060 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173608.689684 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171279.440411 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 133743.257454 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174133.473463 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 150462.206352 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 61808.932432 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 153927.117712 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 173839.265787 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 161608.648955 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 68117 # Transaction distribution -system.membus.trans_dist::ReadResp 68116 # Transaction distribution +system.membus.trans_dist::ReadReq 68118 # Transaction distribution +system.membus.trans_dist::ReadResp 68117 # Transaction distribution system.membus.trans_dist::WriteReq 27584 # Transaction distribution system.membus.trans_dist::WriteResp 27584 # Transaction distribution system.membus.trans_dist::Writeback 131657 # Transaction distribution @@ -2436,40 +2460,40 @@ system.membus.trans_dist::ReadExResp 138750 # Tr system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 20 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 465311 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 572879 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 465313 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 572881 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108814 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 681693 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 681695 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 640 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17344024 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17507929 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17344028 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17507933 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4631616 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4631616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22139545 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22139549 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 523 # Total snoops (count) -system.membus.snoop_fanout::samples 347614 # Request fanout histogram +system.membus.snoop_fanout::samples 406994 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 347614 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 406994 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 347614 # Request fanout histogram +system.membus.snoop_fanout::total 406994 # Request fanout histogram system.membus.reqLayer0.occupancy 95655500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 16812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 1658000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1067095796 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1067096296 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1022748121 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1022750121 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 37540981 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) @@ -2504,8 +2528,8 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2657013 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2656927 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2657014 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2656928 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution system.toL2Bus.trans_dist::Writeback 704443 # Transaction distribution @@ -2516,36 +2540,34 @@ system.toL2Bus.trans_dist::UpgradeResp 2876 # Tr system.toL2Bus.trans_dist::ReadExReq 296803 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 296803 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3891000 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2536659 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2536661 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42360 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169075 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6639094 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6639096 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124504512 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99962073 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99962077 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 64700 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 291504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 224822789 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 224822793 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 70210 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3665576 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.009952 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.099262 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 3724954 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.042649 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.202064 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3629096 99.00% 99.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 36480 1.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3566090 95.74% 95.74% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 158864 4.26% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3665576 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2562503934 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3724954 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2562504434 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 246000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 2923288858 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1353662761 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1353663761 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 26203715 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 63a2010ed..5aa558433 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.443139 # Number of seconds simulated -sim_ticks 47443139283500 # Number of ticks simulated -final_tick 47443139283500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.365947 # Number of seconds simulated +sim_ticks 47365946685500 # Number of ticks simulated +final_tick 47365946685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 174986 # Simulator instruction rate (inst/s) -host_op_rate 205797 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9320406551 # Simulator tick rate (ticks/s) -host_mem_usage 765676 # Number of bytes of host memory used -host_seconds 5090.24 # Real time elapsed on the host -sim_insts 890723033 # Number of instructions simulated -sim_ops 1047557701 # Number of ops (including micro ops) simulated +host_inst_rate 174192 # Simulator instruction rate (inst/s) +host_op_rate 204861 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9672451523 # Simulator tick rate (ticks/s) +host_mem_usage 763596 # Number of bytes of host memory used +host_seconds 4897.00 # Real time elapsed on the host +sim_insts 853019792 # Number of instructions simulated +sim_ops 1003201701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 111744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 91648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7668224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 13156952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 13340800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 149248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 146240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3865344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 11856672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 13765376 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 430976 # Number of bytes read from this memory -system.physmem.bytes_read::total 64583224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 7668224 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3865344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11533568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 75782720 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 65472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 7833792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 12003144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 10766848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 71104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 69248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2839488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 7678416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 7994432 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 439552 # Number of bytes read from this memory +system.physmem.bytes_read::total 49825880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 7833792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2839488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10673280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 62800512 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 75803536 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1746 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1432 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 119816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 205599 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 208450 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2332 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2285 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 60396 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 185275 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 215084 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6734 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1009149 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1184105 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 62821096 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1023 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1006 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 122403 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 187562 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 168232 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1111 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1082 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 44367 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 119988 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 124913 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6868 # Number of read requests responded to by this memory +system.physmem.num_reads::total 778555 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 981258 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1186708 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2355 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 161630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 277320 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 281196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 81473 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 249913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 290145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1361276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 161630 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 81473 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 243103 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1597338 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 983832 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 165389 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 253413 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 227312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 162108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 168780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9280 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1051935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 165389 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 225337 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1325858 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1597777 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1597338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 161630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 277759 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 281196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3082 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 81473 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 249913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 290145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2959053 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1009149 # Number of read requests accepted -system.physmem.writeReqs 1850399 # Number of write requests accepted -system.physmem.readBursts 1009149 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1850399 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 64564224 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21312 # Total number of bytes read from write queue -system.physmem.bytesWritten 115242304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 64583224 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 118279760 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 333 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 49721 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 115106 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 57845 # Per bank write bursts -system.physmem.perBankRdBursts::1 61929 # Per bank write bursts -system.physmem.perBankRdBursts::2 56818 # Per bank write bursts -system.physmem.perBankRdBursts::3 63723 # Per bank write bursts -system.physmem.perBankRdBursts::4 61880 # Per bank write bursts -system.physmem.perBankRdBursts::5 68171 # Per bank write bursts -system.physmem.perBankRdBursts::6 59739 # Per bank write bursts -system.physmem.perBankRdBursts::7 60869 # Per bank write bursts -system.physmem.perBankRdBursts::8 54876 # Per bank write bursts -system.physmem.perBankRdBursts::9 108415 # Per bank write bursts -system.physmem.perBankRdBursts::10 50407 # Per bank write bursts -system.physmem.perBankRdBursts::11 61358 # Per bank write bursts -system.physmem.perBankRdBursts::12 58228 # Per bank write bursts -system.physmem.perBankRdBursts::13 64090 # Per bank write bursts -system.physmem.perBankRdBursts::14 57873 # Per bank write bursts -system.physmem.perBankRdBursts::15 62595 # Per bank write bursts -system.physmem.perBankWrBursts::0 107469 # Per bank write bursts -system.physmem.perBankWrBursts::1 113594 # Per bank write bursts -system.physmem.perBankWrBursts::2 115011 # Per bank write bursts -system.physmem.perBankWrBursts::3 118413 # Per bank write bursts -system.physmem.perBankWrBursts::4 118243 # Per bank write bursts -system.physmem.perBankWrBursts::5 118449 # Per bank write bursts -system.physmem.perBankWrBursts::6 111339 # Per bank write bursts -system.physmem.perBankWrBursts::7 115322 # Per bank write bursts -system.physmem.perBankWrBursts::8 110047 # Per bank write bursts -system.physmem.perBankWrBursts::9 111027 # Per bank write bursts -system.physmem.perBankWrBursts::10 102767 # Per bank write bursts -system.physmem.perBankWrBursts::11 112058 # Per bank write bursts -system.physmem.perBankWrBursts::12 108184 # Per bank write bursts -system.physmem.perBankWrBursts::13 112341 # Per bank write bursts -system.physmem.perBankWrBursts::14 110504 # Per bank write bursts -system.physmem.perBankWrBursts::15 115893 # Per bank write bursts +system.physmem.bw_write::total 1326292 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1325858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1382 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 165389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 253847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 227312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 162108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 168780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2378227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 778555 # Number of read requests accepted +system.physmem.writeReqs 1622091 # Number of write requests accepted +system.physmem.readBursts 778555 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1622091 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 49803520 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 24000 # Total number of bytes read from write queue +system.physmem.bytesWritten 100652928 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 49825880 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 103669672 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 375 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 49366 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 111816 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 42060 # Per bank write bursts +system.physmem.perBankRdBursts::1 53156 # Per bank write bursts +system.physmem.perBankRdBursts::2 42442 # Per bank write bursts +system.physmem.perBankRdBursts::3 47567 # Per bank write bursts +system.physmem.perBankRdBursts::4 45723 # Per bank write bursts +system.physmem.perBankRdBursts::5 54413 # Per bank write bursts +system.physmem.perBankRdBursts::6 50594 # Per bank write bursts +system.physmem.perBankRdBursts::7 44772 # Per bank write bursts +system.physmem.perBankRdBursts::8 41306 # Per bank write bursts +system.physmem.perBankRdBursts::9 93457 # Per bank write bursts +system.physmem.perBankRdBursts::10 34541 # Per bank write bursts +system.physmem.perBankRdBursts::11 47870 # Per bank write bursts +system.physmem.perBankRdBursts::12 47765 # Per bank write bursts +system.physmem.perBankRdBursts::13 46143 # Per bank write bursts +system.physmem.perBankRdBursts::14 39677 # Per bank write bursts +system.physmem.perBankRdBursts::15 46694 # Per bank write bursts +system.physmem.perBankWrBursts::0 94318 # Per bank write bursts +system.physmem.perBankWrBursts::1 104450 # Per bank write bursts +system.physmem.perBankWrBursts::2 99318 # Per bank write bursts +system.physmem.perBankWrBursts::3 101345 # Per bank write bursts +system.physmem.perBankWrBursts::4 99792 # Per bank write bursts +system.physmem.perBankWrBursts::5 104837 # Per bank write bursts +system.physmem.perBankWrBursts::6 100210 # Per bank write bursts +system.physmem.perBankWrBursts::7 98464 # Per bank write bursts +system.physmem.perBankWrBursts::8 93421 # Per bank write bursts +system.physmem.perBankWrBursts::9 95649 # Per bank write bursts +system.physmem.perBankWrBursts::10 88541 # Per bank write bursts +system.physmem.perBankWrBursts::11 99820 # Per bank write bursts +system.physmem.perBankWrBursts::12 96824 # Per bank write bursts +system.physmem.perBankWrBursts::13 96750 # Per bank write bursts +system.physmem.perBankWrBursts::14 94484 # Per bank write bursts +system.physmem.perBankWrBursts::15 104479 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 251 # Number of times write queue was full causing retry -system.physmem.totGap 47443137361000 # Total gap between requests +system.physmem.numWrRetry 276 # Number of times write queue was full causing retry +system.physmem.totGap 47365944763000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 37 # Read request sizes (log2) +system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1009107 # Read request sizes (log2) +system.physmem.readPktSize::6 778525 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) -system.physmem.writePktSize::3 2601 # Write request sizes (log2) +system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1847796 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 676531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 118770 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 34633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 29357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 26883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 24732 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 22204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18862 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 5388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1619517 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 550292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 82276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 20492 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 18686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 17057 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 15108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 12648 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 556 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 158 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 141 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -188,169 +188,167 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 43843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 64070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 91575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 102673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 109951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 108175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 103872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 98771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 95896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 92750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 92610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 110859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 98695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 94070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 109570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 97266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 90790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 87057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 7476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 6313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 8079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 7980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 6184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 7891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 6061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 4360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 3055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 832 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1017757 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 176.667963 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 107.708761 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 246.723752 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 648817 63.75% 63.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 197916 19.45% 83.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 48918 4.81% 88.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23519 2.31% 90.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 17229 1.69% 92.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11413 1.12% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8164 0.80% 93.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7432 0.73% 94.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 54349 5.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1017757 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 78960 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 12.776165 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 140.389446 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 78957 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 40446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 59954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 84735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 94224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 98939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 95817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 91113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 85467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 82456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 78613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 78193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 94725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 83224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 77979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 91163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 80486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 75147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 72304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 7065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 6188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 8039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 6691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 3304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1783 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 873 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 836953 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 179.765373 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 108.063876 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 253.948875 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 534704 63.89% 63.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 162086 19.37% 83.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 38261 4.57% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 18116 2.16% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12763 1.52% 91.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8799 1.05% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6603 0.79% 93.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6067 0.72% 94.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 49554 5.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 836953 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 65558 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 11.869901 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 153.975731 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 65556 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 78960 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 78960 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.804724 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.151306 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.211366 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 71201 90.17% 90.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 3689 4.67% 94.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 1610 2.04% 96.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 798 1.01% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 435 0.55% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 299 0.38% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 436 0.55% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 198 0.25% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 63 0.08% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 19 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 61 0.08% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 31 0.04% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 15 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 6 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 4 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 5 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 7 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 4 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 9 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 8 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 9 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 14 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 4 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 4 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 65558 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 65558 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.989475 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.876910 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.036255 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 57911 88.34% 88.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 3625 5.53% 93.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 1537 2.34% 96.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 756 1.15% 97.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 457 0.70% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 339 0.52% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 446 0.68% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 180 0.27% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 59 0.09% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 25 0.04% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 57 0.09% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 41 0.06% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 16 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 6 0.01% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.00% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 7 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 6 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 4 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 12 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 9 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 13 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 20 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::576-591 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::736-751 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::848-863 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 78960 # Writes before turning the bus around for reads -system.physmem.totQLat 36416381887 # Total ticks spent queuing -system.physmem.totMemAccLat 55331681887 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5044080000 # Total ticks spent in databus transfers -system.physmem.avgQLat 36098.14 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 65558 # Writes before turning the bus around for reads +system.physmem.totQLat 24526926504 # Total ticks spent queuing +system.physmem.totMemAccLat 39117801504 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3890900000 # Total ticks spent in databus transfers +system.physmem.avgQLat 31518.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 54848.14 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.36 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.43 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.36 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.49 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 50268.32 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.05 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.13 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.05 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.19 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing -system.physmem.readRowHits 756126 # Number of row buffer hits during reads -system.physmem.writeRowHits 1035585 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.95 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.51 # Row buffer hit rate for writes -system.physmem.avgGap 16591131.66 # Average gap between requests -system.physmem.pageHitRate 63.77 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3944550960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2152284750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3829511400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5947512480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3098754740640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1192681206900 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27419667632250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31726977439380 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.736993 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45614623336779 # Time in different power states -system.physmem_0.memoryStateTime::REF 1584230440000 # Time in different power states +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.72 # Average write queue length when enqueuing +system.physmem.readRowHits 582169 # Number of row buffer hits during reads +system.physmem.writeRowHits 931750 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.24 # Row buffer hit rate for writes +system.physmem.avgGap 19730499.53 # Average gap between requests +system.physmem.pageHitRate 64.40 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3287730600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1793900625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2969101200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5201632080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3093712876800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1175633111385 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27388306372500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31670904725190 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.643023 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45562569995604 # Time in different power states +system.physmem_0.memoryStateTime::REF 1581652800000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 244280410221 # Time in different power states +system.physmem_0.memoryStateTime::ACT 221716854896 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3749639040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2045934000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4039144200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5720654160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3098754740640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1188668792790 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27423187293750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31726166198580 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.719894 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45620445429017 # Time in different power states -system.physmem_1.memoryStateTime::REF 1584230440000 # Time in different power states +system.physmem_1.actEnergy 3039558480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1658489250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3100125600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4989373200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3093712876800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1167524389710 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27395419294500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31669444107540 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.612186 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45574402608448 # Time in different power states +system.physmem_1.memoryStateTime::REF 1581652800000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 238458431983 # Time in different power states +system.physmem_1.memoryStateTime::ACT 209885438552 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -384,15 +382,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1674 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 130059643 # Number of BP lookups -system.cpu0.branchPred.condPredicted 92054393 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5970282 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 98035548 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 70777475 # Number of BTB hits +system.cpu0.branchPred.lookups 133649210 # Number of BP lookups +system.cpu0.branchPred.condPredicted 93568356 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6412350 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 100434532 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 71867706 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.195725 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15296635 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1065115 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 71.556769 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 16148203 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1115497 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -423,61 +421,67 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 268213 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 268213 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8180 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 73055 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 268213 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 268213 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 268213 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 81235 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 18802.895870 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 17058.372218 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 13418.609606 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 80487 99.08% 99.08% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 639 0.79% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 31 0.04% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 33 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 28 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 81235 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 281840 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 281840 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8577 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76588 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 281840 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 281840 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 281840 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 85165 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 18850.134868 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 17191.967454 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 12262.040349 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 80924 95.02% 95.02% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3552 4.17% 99.19% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 385 0.45% 99.64% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 201 0.24% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 20 0.02% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 10 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 25 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 15 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 9 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 16 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 85165 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 788586204 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 788586204 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 788586204 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 73055 89.93% 89.93% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 8180 10.07% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 81235 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 268213 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 76588 89.93% 89.93% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 8577 10.07% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 85165 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 281840 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 268213 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 81235 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 281840 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85165 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 81235 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 349448 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85165 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 367005 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 82876233 # DTB read hits -system.cpu0.dtb.read_misses 221834 # DTB read misses -system.cpu0.dtb.write_hits 73950839 # DTB write hits -system.cpu0.dtb.write_misses 46379 # DTB write misses +system.cpu0.dtb.read_hits 86621651 # DTB read hits +system.cpu0.dtb.read_misses 235326 # DTB read misses +system.cpu0.dtb.write_hits 77269391 # DTB write hits +system.cpu0.dtb.write_misses 46514 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41692 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 33850 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2174 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9634 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 36825 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2231 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9213 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10897 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 83098067 # DTB read accesses -system.cpu0.dtb.write_accesses 73997218 # DTB write accesses +system.cpu0.dtb.perms_faults 11443 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 86856977 # DTB read accesses +system.cpu0.dtb.write_accesses 77315905 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 156827072 # DTB hits -system.cpu0.dtb.misses 268213 # DTB misses -system.cpu0.dtb.accesses 157095285 # DTB accesses +system.cpu0.dtb.hits 163891042 # DTB hits +system.cpu0.dtb.misses 281840 # DTB misses +system.cpu0.dtb.accesses 164172882 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -507,191 +511,191 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 59559 # Table walker walks requested -system.cpu0.itb.walker.walksLong 59559 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 562 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52025 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 59559 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 59559 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 59559 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 52587 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 21528.762508 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 19318.036298 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 15879.557576 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 47969 91.22% 91.22% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 3703 7.04% 98.26% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 280 0.53% 98.79% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 523 0.99% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 24 0.05% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 24 0.05% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 27 0.05% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 16 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 8 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 66347 # Table walker walks requested +system.cpu0.itb.walker.walksLong 66347 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 679 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58898 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 66347 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 66347 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 66347 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 59577 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 21233.631049 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 19420.255520 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 13392.583355 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 54894 92.14% 92.14% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 3878 6.51% 98.65% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 278 0.47% 99.12% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 464 0.78% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 13 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 10 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 21 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 10 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 52587 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 59577 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 787865704 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 787865704 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 787865704 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 52025 98.93% 98.93% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 562 1.07% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 52587 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 58898 98.86% 98.86% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 679 1.14% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 59577 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 59559 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 59559 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66347 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66347 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52587 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52587 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 112146 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 232580630 # ITB inst hits -system.cpu0.itb.inst_misses 59559 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59577 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59577 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 125924 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 239632917 # ITB inst hits +system.cpu0.itb.inst_misses 66347 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41692 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 23871 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26379 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 192056 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 196328 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 232640189 # ITB inst accesses -system.cpu0.itb.hits 232580630 # DTB hits -system.cpu0.itb.misses 59559 # DTB misses -system.cpu0.itb.accesses 232640189 # DTB accesses -system.cpu0.numCycles 928928804 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 239699264 # ITB inst accesses +system.cpu0.itb.hits 239632917 # DTB hits +system.cpu0.itb.misses 66347 # DTB misses +system.cpu0.itb.accesses 239699264 # DTB accesses +system.cpu0.numCycles 955623985 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 429144762 # Number of instructions committed -system.cpu0.committedOps 504441860 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 43734034 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 3788 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93957994041 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.164605 # CPI: cycles per instruction -system.cpu0.ipc 0.461978 # IPC: instructions per cycle +system.cpu0.committedInsts 445844997 # Number of instructions committed +system.cpu0.committedOps 524389125 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 43457031 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4220 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93776986984 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.143400 # CPI: cycles per instruction +system.cpu0.ipc 0.466549 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 12678 # number of quiesce instructions executed -system.cpu0.tickCycles 694752800 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 234176004 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5394073 # number of replacements -system.cpu0.dcache.tags.tagsinuse 480.331401 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 148625740 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5394584 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.550918 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 5096417500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.331401 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938147 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.938147 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 13187 # number of quiesce instructions executed +system.cpu0.tickCycles 717454138 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 238169847 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5506052 # number of replacements +system.cpu0.dcache.tags.tagsinuse 502.001203 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 155497940 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5506563 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.238656 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 5093256500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.001203 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980471 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.980471 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 316412315 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 316412315 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75879605 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75879605 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 68405292 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 68405292 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 266627 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 266627 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 249000 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 249000 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1685353 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1685353 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1648257 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1648257 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 144284897 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 144284897 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 144551524 # number of overall hits -system.cpu0.dcache.overall_hits::total 144551524 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3254530 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3254530 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2315784 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2315784 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 640707 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 640707 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 788472 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 788472 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 144645 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 144645 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 180684 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 180684 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5570314 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5570314 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6211021 # number of overall misses -system.cpu0.dcache.overall_misses::total 6211021 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 49481056746 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 49481056746 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 45032988844 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 45032988844 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 32697185728 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 32697185728 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2134918217 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2134918217 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3848217698 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3848217698 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3587000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3587000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 94514045590 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 94514045590 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 94514045590 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 94514045590 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 79134135 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 79134135 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 70721076 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 70721076 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 907334 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 907334 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1037472 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1037472 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1829998 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1829998 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1828941 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1828941 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 149855211 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 149855211 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 150762545 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 150762545 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041127 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.041127 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032745 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.032745 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.706142 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.706142 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.759994 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.759994 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079041 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079041 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098792 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098792 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037171 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.037171 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041197 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.041197 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15203.748850 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15203.748850 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19446.109328 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19446.109328 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41469.051188 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41469.051188 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14759.709751 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14759.709751 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21298.054604 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21298.054604 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 330491760 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 330491760 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 79543100 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 79543100 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 71719508 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 71719508 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 278613 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 278613 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 256505 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 256505 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1617523 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1617523 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1589938 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1589938 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 151262608 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 151262608 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 151541221 # number of overall hits +system.cpu0.dcache.overall_hits::total 151541221 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3339841 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3339841 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2311852 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2311852 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 620748 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 620748 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 822680 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 822680 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 157499 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 157499 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 183638 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 183638 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5651693 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5651693 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 6272441 # number of overall misses +system.cpu0.dcache.overall_misses::total 6272441 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 49670372012 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 49670372012 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 43497452544 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 43497452544 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 32835554230 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 32835554230 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2312206455 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2312206455 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3898320876 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3898320876 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3663000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3663000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 93167824556 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 93167824556 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 93167824556 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 93167824556 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 82882941 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 82882941 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74031360 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 74031360 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 899361 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 899361 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1079185 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1079185 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1775022 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1775022 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1773576 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1773576 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 156914301 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 156914301 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 157813662 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 157813662 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040296 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.040296 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031228 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.031228 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.690210 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.690210 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.762316 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.762316 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088731 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088731 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.103541 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.103541 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036018 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.036018 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039746 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.039746 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14872.076848 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14872.076848 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18814.981471 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18814.981471 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 39912.911740 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 39912.911740 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14680.769116 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14680.769116 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21228.290855 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21228.290855 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16967.453826 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16967.453826 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15217.151188 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15217.151188 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16484.940806 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16484.940806 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14853.519476 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14853.519476 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -700,155 +704,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3714069 # number of writebacks -system.cpu0.dcache.writebacks::total 3714069 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 414551 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 414551 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 973091 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 973091 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 89 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 89 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 40213 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 40213 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 42 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 42 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1387642 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1387642 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1387642 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1387642 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2839979 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2839979 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1342693 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1342693 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 635024 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 635024 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 788383 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 788383 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104432 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 104432 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 180642 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 180642 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4182672 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4182672 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 4817696 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4817696 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37224821633 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37224821633 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 24320285408 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 24320285408 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14430000107 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14430000107 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 31505168022 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 31505168022 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1352929391 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1352929391 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3566593771 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3566593771 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3248500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3248500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61545107041 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 61545107041 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 75975107148 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 75975107148 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5918601247 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5918601247 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5692373000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5692373000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11610974247 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11610974247 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035888 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035888 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018986 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018986 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.699879 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.699879 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.759908 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.759908 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057067 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057067 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098769 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098769 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027911 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027911 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031956 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031956 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13107.428482 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13107.428482 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18113.064869 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18113.064869 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22723.550774 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22723.550774 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39961.754657 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39961.754657 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12955.122865 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12955.122865 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19743.989609 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19743.989609 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3760610 # number of writebacks +system.cpu0.dcache.writebacks::total 3760610 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 413115 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 413115 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 966709 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 966709 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 96 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 96 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 42490 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 42490 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 52 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 52 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1379824 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1379824 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1379824 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1379824 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2926726 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2926726 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1345143 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1345143 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 614981 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 614981 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 822584 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 822584 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 115009 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 115009 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 183586 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 183586 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4271869 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4271869 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4886850 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4886850 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 33259 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33259 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 33163 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33163 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 66422 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 66422 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37662767131 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37662767131 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 23537156289 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 23537156289 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13208319439 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13208319439 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 31592370271 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 31592370271 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1454810141 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1454810141 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3611856094 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3611856094 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3160000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3160000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61199923420 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 61199923420 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 74408242859 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 74408242859 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5916157251 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5916157251 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5692664250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5692664250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11608821501 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11608821501 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035312 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035312 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018170 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018170 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.683798 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.683798 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.762227 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.762227 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064793 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064793 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.103512 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.103512 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027224 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027224 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030966 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030966 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12868.566149 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12868.566149 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17497.884083 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17497.884083 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21477.605713 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21477.605713 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 38406.254280 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 38406.254280 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12649.533002 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12649.533002 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19673.919003 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19673.919003 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14714.303928 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14714.303928 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15770.008558 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15770.008558 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14326.264083 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14326.264083 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15226.217882 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15226.217882 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177881.393036 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 177881.393036 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171657.095257 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171657.095257 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 174773.742149 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174773.742149 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 9298569 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.930207 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 223083541 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 9299081 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 23.989848 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 24039613250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930207 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999864 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 9994306 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.930109 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 229434949 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 9994818 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 22.955390 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 24035147250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930109 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999863 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 423 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 254 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 474064354 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 474064354 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 223083541 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 223083541 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 223083541 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 223083541 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 223083541 # number of overall hits -system.cpu0.icache.overall_hits::total 223083541 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9299091 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9299091 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9299091 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9299091 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9299091 # number of overall misses -system.cpu0.icache.overall_misses::total 9299091 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 92099739258 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 92099739258 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 92099739258 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 92099739258 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 92099739258 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 92099739258 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 232382632 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 232382632 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 232382632 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 232382632 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 232382632 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 232382632 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.040016 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.040016 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.040016 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.040016 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.040016 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.040016 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9904.165822 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9904.165822 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9904.165822 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9904.165822 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9904.165822 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9904.165822 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 488854379 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 488854379 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 229434949 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 229434949 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 229434949 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 229434949 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 229434949 # number of overall hits +system.cpu0.icache.overall_hits::total 229434949 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9994827 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9994827 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9994827 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9994827 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9994827 # number of overall misses +system.cpu0.icache.overall_misses::total 9994827 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 98560798487 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 98560798487 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 98560798487 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 98560798487 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 98560798487 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 98560798487 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 239429776 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 239429776 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 239429776 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 239429776 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 239429776 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 239429776 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.041744 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.041744 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.041744 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.041744 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.041744 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.041744 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9861.181038 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9861.181038 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9861.181038 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9861.181038 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9861.181038 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9861.181038 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -857,464 +867,467 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9299091 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 9299091 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 9299091 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 9299091 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 9299091 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 9299091 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 82773169690 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 82773169690 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 82773169690 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 82773169690 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 82773169690 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 82773169690 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9994827 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 9994827 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 9994827 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 9994827 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 9994827 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 9994827 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52307 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 52307 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52307 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 52307 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 88537189453 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 88537189453 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 88537189453 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 88537189453 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 88537189453 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 88537189453 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4833897250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 4833897250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.040016 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.040016 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.040016 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.040016 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.040016 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.040016 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8901.210848 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8901.210848 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8901.210848 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8901.210848 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8901.210848 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8901.210848 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.041744 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.041744 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.041744 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.041744 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.041744 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.041744 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8858.301345 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8858.301345 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8858.301345 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8858.301345 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8858.301345 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8858.301345 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92413.964670 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92413.964670 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92413.964670 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92413.964670 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7190203 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7193896 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 3174 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7230073 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7233896 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 3309 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 922256 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2625541 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15991.413435 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 14807300 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2641343 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.605974 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 5822698500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4879.764539 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 24.400359 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 12.549912 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 6476.155414 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3443.547426 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1154.995785 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.297837 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001489 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000766 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.395273 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.210177 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.070495 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.976038 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 899 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 100 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14803 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 131 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 286 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 212 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 261 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 49 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 584 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3987 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7940 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2205 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.054871 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006104 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.903503 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 317363753 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 317363753 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 462963 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 140724 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 8558678 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2632719 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 11795084 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 3714063 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 3714063 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 203687 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 203687 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 102333 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 102333 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 31948 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 31948 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 859061 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 859061 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 462963 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 140724 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 8558678 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3491780 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 12654145 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 462963 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 140724 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 8558678 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3491780 # number of overall hits -system.cpu0.l2cache.overall_hits::total 12654145 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10993 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8048 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 740412 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 946440 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1705893 # number of ReadReq misses -system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses -system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 583142 # number of WriteInvalidateReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::total 583142 # number of WriteInvalidateReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 124112 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 124112 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 148691 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 148691 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 269272 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 269272 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10993 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8048 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 740412 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1215712 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1975165 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10993 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8048 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 740412 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1215712 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1975165 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 390640720 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 300789761 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 22448225702 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 32185912694 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 55325568877 # number of ReadReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 214128828 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 214128828 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2731788344 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 2731788344 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3090531448 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3090531448 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3176498 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3176498 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13196588662 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 13196588662 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 390640720 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 300789761 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22448225702 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 45382501356 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 68522157539 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 390640720 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 300789761 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22448225702 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 45382501356 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 68522157539 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 473956 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 148772 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 9299090 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3579159 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 13500977 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 3714064 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 3714064 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 786829 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::total 786829 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 226445 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 226445 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 180639 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 180639 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1128333 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1128333 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 473956 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 148772 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 9299090 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 4707492 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 14629310 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 473956 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 148772 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 9299090 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 4707492 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 14629310 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.023194 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.054096 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.079622 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.264431 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.126353 # miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.741129 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.741129 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.548089 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.548089 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.823139 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.823139 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.prefetcher.pfSpanPage 950560 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2661651 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16101.576152 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 15630806 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2677359 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.838143 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 5822133500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 5793.980406 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 73.792044 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 73.619480 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5777.684117 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3504.905506 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 877.594600 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.353636 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004504 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004493 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.352642 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.213922 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.053564 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.982762 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1351 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14265 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 52 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 263 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 985 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 51 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 56 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 31 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 705 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5210 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7781 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 446 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.082458 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.870667 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 331999507 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 331999507 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 494334 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 160804 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 9208783 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 2710357 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 12574278 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 3760607 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 3760607 # number of Writeback hits +system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 232072 # number of WriteInvalidateReq hits +system.cpu0.l2cache.WriteInvalidateReq_hits::total 232072 # number of WriteInvalidateReq hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 101378 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 101378 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 33994 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 33994 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 863447 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 863447 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 494334 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 160804 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 9208783 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3573804 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 13437725 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 494334 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 160804 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 9208783 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3573804 # number of overall hits +system.cpu0.l2cache.overall_hits::total 13437725 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10659 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7834 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 786043 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 946030 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 1750566 # number of ReadReq misses +system.cpu0.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses +system.cpu0.l2cache.Writeback_misses::total 2 # number of Writeback misses +system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 588987 # number of WriteInvalidateReq misses +system.cpu0.l2cache.WriteInvalidateReq_misses::total 588987 # number of WriteInvalidateReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 124560 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 124560 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 149586 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 149586 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 267892 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 267892 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10659 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7834 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 786043 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1213922 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2018458 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10659 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7834 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 786043 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1213922 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2018458 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 318928487 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 253391761 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 23635812248 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 30920172081 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 55128304577 # number of ReadReq miss cycles +system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 210558524 # number of WriteInvalidateReq miss cycles +system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 210558524 # number of WriteInvalidateReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2759900095 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 2759900095 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3121911280 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3121911280 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3089998 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3089998 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12386704821 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 12386704821 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 318928487 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 253391761 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 23635812248 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 43306876902 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 67515009398 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 318928487 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 253391761 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 23635812248 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 43306876902 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 67515009398 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 504993 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 168638 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 9994826 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3656387 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 14324844 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 3760609 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 3760609 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 821059 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::total 821059 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 225938 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 225938 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 183580 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 183580 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1131339 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1131339 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 504993 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 168638 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 9994826 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 4787726 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 15456183 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 504993 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 168638 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 9994826 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 4787726 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 15456183 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021107 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.046455 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.078645 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.258734 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.122205 # miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000001 # miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_miss_rate::total 0.000001 # miss rate for Writeback accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.717350 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.717350 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.551302 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.551302 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.814827 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.814827 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.238646 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.238646 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.023194 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.054096 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.079622 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.258250 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.135014 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.023194 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.054096 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.079622 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.258250 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.135014 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35535.406168 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 37374.473285 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30318.560075 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 34007.346154 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32432.027611 # average ReadReq miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 367.198432 # average WriteInvalidateReq miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 367.198432 # average WriteInvalidateReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22010.670556 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22010.670556 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20784.926109 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20784.926109 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 1058832.666667 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1058832.666667 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49008.395459 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49008.395459 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35535.406168 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 37374.473285 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30318.560075 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37329.977294 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 34691.865003 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35535.406168 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 37374.473285 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30318.560075 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37329.977294 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 34691.865003 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.236792 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.236792 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021107 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.046455 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.078645 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.253549 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.130592 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021107 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.046455 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.078645 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.253549 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.130592 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 29921.051412 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 32345.131606 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30069.362933 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 32684.134838 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31491.703013 # average ReadReq miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 357.492651 # average WriteInvalidateReq miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 357.492651 # average WriteInvalidateReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22157.194083 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22157.194083 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20870.344016 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20870.344016 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 514999.666667 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 514999.666667 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 46237.680935 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 46237.680935 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 29921.051412 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 32345.131606 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30069.362933 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35675.172624 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 33448.805671 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 29921.051412 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 32345.131606 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30069.362933 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35675.172624 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 33448.805671 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 99 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1355884 # number of writebacks -system.cpu0.l2cache.writebacks::total 1355884 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits +system.cpu0.l2cache.writebacks::writebacks 1339072 # number of writebacks +system.cpu0.l2cache.writebacks::total 1339072 # number of writebacks system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 6 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 800 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 808 # number of ReadReq MSHR hits -system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 23 # number of WriteInvalidateReq MSHR hits -system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 23 # number of WriteInvalidateReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 7927 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 7927 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 981 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 987 # number of ReadReq MSHR hits +system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 31 # number of WriteInvalidateReq MSHR hits +system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 31 # number of WriteInvalidateReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6237 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 6237 # number of ReadExReq MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 8727 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 8735 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 7218 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 7224 # number of demand (read+write) MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 8727 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 8735 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10992 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8047 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 740406 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 945640 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 1705085 # number of ReadReq MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 695861 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 695861 # number of HardPFReq MSHR misses -system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 583119 # number of WriteInvalidateReq MSHR misses -system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 583119 # number of WriteInvalidateReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 124112 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 124112 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 148691 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 148691 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 261345 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 261345 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10992 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8047 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 740406 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1206985 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 1966430 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10992 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8047 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 740406 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1206985 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 695861 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 2662291 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 318665266 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 248030007 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 17610392548 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 25914267732 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 44091355553 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 32596842182 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 32596842182 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 25478427229 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 25478427229 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2526518712 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2526518712 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2211223584 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2211223584 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2721498 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2721498 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10434978340 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10434978340 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 318665266 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 248030007 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 17610392548 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 36349246072 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 54526333893 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 318665266 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 248030007 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 17610392548 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 36349246072 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 32596842182 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 87123176075 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 7218 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 7224 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10659 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7834 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 786037 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 945049 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 1749579 # number of ReadReq MSHR misses +system.cpu0.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses +system.cpu0.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 685342 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 685342 # number of HardPFReq MSHR misses +system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 588956 # number of WriteInvalidateReq MSHR misses +system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 588956 # number of WriteInvalidateReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 124560 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 124560 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 149586 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 149586 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 261655 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 261655 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10659 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7834 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 786037 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1206704 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 2011234 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10659 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7834 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 786037 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1206704 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 685342 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 2696576 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52307 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 33259 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 85566 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 33163 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 33163 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52307 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 66422 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 118729 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 249336497 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 202183759 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 18500486252 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 24637742155 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 43589748663 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 26923200622 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 26923200622 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 25292544478 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 25292544478 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2524783016 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2524783016 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2234342769 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2234342769 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2647998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2647998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 9878225571 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9878225571 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 249336497 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 202183759 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 18500486252 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 34515967726 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 53467974234 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 249336497 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 202183759 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 18500486252 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 34515967726 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 26923200622 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 80391174856 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5652021253 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10043092003 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5443565000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5443565000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5650020250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10041091000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5443925500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5443925500 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11095586253 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15486657003 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.023192 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.054089 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.079621 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.264207 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.126293 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11093945750 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15485016500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021107 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.046455 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.078644 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.258465 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.122136 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000001 # mshr miss rate for Writeback accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.741100 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.741100 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.548089 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.548089 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.823139 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.823139 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.717313 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.717313 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.551302 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.551302 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.814827 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.814827 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.231620 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231620 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.023192 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.054089 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.079621 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256397 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.134417 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.023192 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.054089 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079621 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256397 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.231279 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231279 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021107 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046455 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.078644 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.252041 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.130125 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021107 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046455 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078644 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.252041 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.181983 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28990.653748 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 30822.667702 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23784.778281 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27403.946250 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25858.743437 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46843.898684 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46843.898684 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43693.358009 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43693.358009 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20356.764149 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20356.764149 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14871.267151 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14871.267151 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 907166 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 907166 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39927.981557 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39927.981557 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28990.653748 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 30822.667702 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23784.778281 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30115.739692 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27728.591352 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28990.653748 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 30822.667702 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23784.778281 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30115.739692 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46843.898684 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 32724.888480 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.174466 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 23392.109673 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 25808.496171 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23536.406368 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26070.333025 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24914.421505 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39284.329024 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 39284.329024 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 42944.709754 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 42944.709754 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20269.613166 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20269.613166 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14936.844150 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14936.844150 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 441333 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 441333 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 37752.863775 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 37752.863775 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23392.109673 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 25808.496171 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23536.406368 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28603.508173 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26584.661076 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23392.109673 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 25808.496171 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23536.406368 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28603.508173 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39284.329024 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 29812.315639 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169879.438648 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117349.075567 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164156.605253 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164156.605253 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 167022.157568 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 130423.203261 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 16236238 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 13810704 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 33172 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 33172 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3714064 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1025800 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1145042 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 786829 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 475552 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 336189 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 478151 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 52 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 119 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1267323 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1138296 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18702794 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15835764 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 326673 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1038123 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 35903354 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 598489344 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 596885449 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1190176 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3791640 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1200356609 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 4763261 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 24114639 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 3.184867 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.388190 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 16764997 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 14635279 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 38250 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 33163 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3760609 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 997781 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1159753 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 821059 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 475624 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 336764 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 482191 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1257493 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1141567 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20094267 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16118866 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366766 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1099589 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 37679488 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 643016512 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 607271415 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1349104 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4039944 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1255676975 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4414025 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 24791334 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.197604 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.398192 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 19656632 81.51% 81.51% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 4458007 18.49% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 19892474 80.24% 80.24% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4898860 19.76% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 24114639 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 14405309409 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 24791334 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 14940946397 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 207723992 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 210442490 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 14053020534 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 15097277267 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7776245419 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7911607131 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 178137962 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 198319454 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 564500428 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 594828175 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 140284857 # Number of BP lookups -system.cpu1.branchPred.condPredicted 99939687 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6358953 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 105820632 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 77032296 # Number of BTB hits +system.cpu1.branchPred.lookups 123549187 # Number of BP lookups +system.cpu1.branchPred.condPredicted 87841692 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5708078 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 93157119 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 67436708 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 72.795158 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16359380 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 1035022 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.390289 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 14460012 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 934859 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1344,61 +1357,65 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 298079 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 298079 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11270 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 91179 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 298079 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 298079 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 298079 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 102449 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 19055.295776 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17104.036055 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15328.339502 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 101103 98.69% 98.69% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1144 1.12% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 36 0.04% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 71 0.07% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 73 0.07% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 15 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 102449 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1267166444 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1267166444 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1267166444 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 91179 89.00% 89.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 11270 11.00% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 102449 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 298079 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 259362 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 259362 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8416 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76621 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 259362 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 259362 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 259362 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 85037 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 18225.042946 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 16628.571422 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 11774.469557 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 81545 95.89% 95.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2790 3.28% 99.17% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 403 0.47% 99.65% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 201 0.24% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 25 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 11 0.01% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 23 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 9 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 14 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 11 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 85037 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1261494444 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1261494444 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1261494444 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 76621 90.10% 90.10% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 8416 9.90% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 85037 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 259362 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 298079 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 102449 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 259362 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 85037 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 102449 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 400528 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 85037 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 344399 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 91176680 # DTB read hits -system.cpu1.dtb.read_misses 248433 # DTB read misses -system.cpu1.dtb.write_hits 79002879 # DTB write hits -system.cpu1.dtb.write_misses 49646 # DTB write misses +system.cpu1.dtb.read_hits 80542266 # DTB read hits +system.cpu1.dtb.read_misses 214982 # DTB read misses +system.cpu1.dtb.write_hits 69249357 # DTB write hits +system.cpu1.dtb.write_misses 44380 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41692 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 41482 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 884 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 7879 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 35601 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 736 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6438 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11586 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 91425113 # DTB read accesses -system.cpu1.dtb.write_accesses 79052525 # DTB write accesses +system.cpu1.dtb.perms_faults 9960 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 80757248 # DTB read accesses +system.cpu1.dtb.write_accesses 69293737 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 170179559 # DTB hits -system.cpu1.dtb.misses 298079 # DTB misses -system.cpu1.dtb.accesses 170477638 # DTB accesses +system.cpu1.dtb.hits 149791623 # DTB hits +system.cpu1.dtb.misses 259362 # DTB misses +system.cpu1.dtb.accesses 150050985 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1428,194 +1445,191 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 68407 # Table walker walks requested -system.cpu1.itb.walker.walksLong 68407 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 609 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 58709 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 68407 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 68407 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 68407 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 59318 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 21639.401767 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 18915.934077 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18524.659910 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 54668 92.16% 92.16% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 3100 5.23% 97.39% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 594 1.00% 98.39% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 801 1.35% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 32 0.05% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 14 0.02% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 58 0.10% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 21 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 5 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 60478 # Table walker walks requested +system.cpu1.itb.walker.walksLong 60478 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 478 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 50972 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 60478 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 60478 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 60478 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 51450 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 20568.513975 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 18499.951285 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 14805.800668 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 47723 92.76% 92.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 2940 5.71% 98.47% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 278 0.54% 99.01% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 425 0.83% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 16 0.03% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 10 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 27 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 13 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 59318 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1266435944 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1266435944 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1266435944 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 58709 98.97% 98.97% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 609 1.03% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 59318 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 51450 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1260837944 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1260837944 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1260837944 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 50972 99.07% 99.07% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 478 0.93% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 51450 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 68407 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 68407 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60478 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60478 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 59318 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 59318 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 127725 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 251160195 # ITB inst hits -system.cpu1.itb.inst_misses 68407 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 51450 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 51450 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 111928 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 220701471 # ITB inst hits +system.cpu1.itb.inst_misses 60478 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41692 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 30244 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25765 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 224879 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 203408 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 251228602 # ITB inst accesses -system.cpu1.itb.hits 251160195 # DTB hits -system.cpu1.itb.misses 68407 # DTB misses -system.cpu1.itb.accesses 251228602 # DTB accesses -system.cpu1.numCycles 937856787 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 220761949 # ITB inst accesses +system.cpu1.itb.hits 220701471 # DTB hits +system.cpu1.itb.misses 60478 # DTB misses +system.cpu1.itb.accesses 220761949 # DTB accesses +system.cpu1.numCycles 819495419 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 461578271 # Number of instructions committed -system.cpu1.committedOps 543115841 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 48137471 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 5811 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93949323576 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.031848 # CPI: cycles per instruction -system.cpu1.ipc 0.492163 # IPC: instructions per cycle +system.cpu1.committedInsts 407174795 # Number of instructions committed +system.cpu1.committedOps 478812576 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 42038613 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5231 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93913157476 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.012638 # CPI: cycles per instruction +system.cpu1.ipc 0.496860 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5892 # number of quiesce instructions executed -system.cpu1.tickCycles 744774671 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 193082116 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 5501509 # number of replacements -system.cpu1.dcache.tags.tagsinuse 462.401458 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 161882040 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5502021 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.422287 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8380046591500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 462.401458 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.903128 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.903128 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 5271 # number of quiesce instructions executed +system.cpu1.tickCycles 656184177 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 163311242 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 4776829 # number of replacements +system.cpu1.dcache.tags.tagsinuse 427.655512 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 142582647 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4777341 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.845608 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8380053198500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 427.655512 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.835265 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.835265 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 343173973 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 343173973 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 83605080 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 83605080 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 73820570 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 73820570 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 234480 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 234480 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 75463 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 75463 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1844270 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1844270 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1832447 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1832447 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 157425650 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 157425650 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 157660130 # number of overall hits -system.cpu1.dcache.overall_hits::total 157660130 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3592418 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3592418 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2291328 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2291328 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 658469 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 658469 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 456956 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 456956 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 185722 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 185722 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 196000 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 196000 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5883746 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5883746 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6542215 # number of overall misses -system.cpu1.dcache.overall_misses::total 6542215 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 54049590884 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 54049590884 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 39638005604 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 39638005604 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 12577649145 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 12577649145 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2799761413 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2799761413 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4076020251 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4076020251 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2567000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2567000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 93687596488 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 93687596488 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 93687596488 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 93687596488 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 87197498 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 87197498 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 76111898 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 76111898 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 892949 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 892949 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 532419 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 532419 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2029992 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2029992 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2028447 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2028447 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 163309396 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 163309396 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 164202345 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 164202345 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041199 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.041199 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030105 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030105 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.737409 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.737409 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.858264 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.858264 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091489 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091489 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.096626 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.096626 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036028 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.036028 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039842 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.039842 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15045.462662 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15045.462662 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17299.140762 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17299.140762 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27524.858291 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27524.858291 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15075.012185 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15075.012185 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20796.021689 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20796.021689 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 302037341 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 302037341 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 73896099 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 73896099 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 64629380 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 64629380 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 204586 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 204586 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 67650 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 67650 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1684264 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1684264 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1653940 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1653940 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 138525479 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 138525479 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 138730065 # number of overall hits +system.cpu1.dcache.overall_hits::total 138730065 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3123049 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3123049 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2001792 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2001792 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 560125 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 560125 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 418714 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 418714 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158898 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 158898 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187849 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 187849 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5124841 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5124841 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5684966 # number of overall misses +system.cpu1.dcache.overall_misses::total 5684966 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43997999443 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 43997999443 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 34323796172 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 34323796172 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11321642584 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11321642584 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2327905715 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2327905715 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3931505754 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3931505754 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3098000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3098000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 78321795615 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 78321795615 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 78321795615 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 78321795615 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 77019148 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 77019148 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 66631172 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 66631172 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 764711 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 764711 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 486364 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 486364 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1843162 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1843162 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1841789 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1841789 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 143650320 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 143650320 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 144415031 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 144415031 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040549 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.040549 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030043 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030043 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.732466 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.732466 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.860907 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.860907 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086209 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086209 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101993 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101993 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035676 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.035676 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039365 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.039365 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14088.155339 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14088.155339 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17146.534791 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17146.534791 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27039.082964 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27039.082964 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14650.314762 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14650.314762 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20929.074704 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20929.074704 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15923.120490 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15923.120490 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14320.470435 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14320.470435 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15282.775722 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15282.775722 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13777.003348 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13777.003348 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1624,155 +1638,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3514313 # number of writebacks -system.cpu1.dcache.writebacks::total 3514313 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 402319 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 402319 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 938195 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 938195 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 62 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 62 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44601 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44601 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 41 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 41 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1340514 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1340514 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1340514 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1340514 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3190099 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3190099 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1353133 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1353133 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 658162 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 658162 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 456894 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 456894 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 141121 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 141121 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195959 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 195959 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4543232 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4543232 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5201394 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5201394 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41952700254 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41952700254 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21819340170 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21819340170 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13178817169 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13178817169 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11885329605 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11885329605 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1778237950 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1778237950 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3771476218 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3771476218 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2255500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2255500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 63772040424 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 63772040424 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 76950857593 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 76950857593 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 517375000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 517375000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 587265498 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 587265498 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1104640498 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1104640498 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036585 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036585 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017778 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017778 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.737066 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.737066 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.858147 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.858147 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069518 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069518 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096605 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096605 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027820 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027820 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031677 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031677 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13150.908562 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13150.908562 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16125.052135 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16125.052135 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20023.667682 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20023.667682 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26013.319512 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26013.319512 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12600.803211 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12600.803211 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19246.251604 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19246.251604 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3038485 # number of writebacks +system.cpu1.dcache.writebacks::total 3038485 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 341138 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 341138 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 817934 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 817934 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 47 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 47 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39869 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39869 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 63 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 63 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1159072 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1159072 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1159072 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1159072 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2781911 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2781911 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1183858 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1183858 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 559909 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 559909 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 418667 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 418667 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 119029 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 119029 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187786 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 187786 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 3965769 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 3965769 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4525678 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4525678 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5083 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5083 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5087 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5087 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10170 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10170 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 34163110205 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 34163110205 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 18897365962 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 18897365962 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10922522145 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 10922522145 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 10687856416 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 10687856416 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1507570159 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1507570159 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3640144702 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3640144702 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2571500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2571500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 53060476167 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 53060476167 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 63982998312 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 63982998312 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 518115500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 518115500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 583373999 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 583373999 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1101489499 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1101489499 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036120 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036120 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017767 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017767 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.732184 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.732184 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.860810 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.860810 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064579 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064579 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101958 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101958 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027607 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027607 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031338 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031338 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12280.446860 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12280.446860 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15962.527568 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15962.527568 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19507.673827 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19507.673827 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25528.299140 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25528.299140 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12665.570231 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12665.570231 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19384.537197 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19384.537197 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14036.712284 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14036.712284 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14794.275841 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14794.275841 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13379.618472 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13379.618472 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14137.770807 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14137.770807 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 101931.044659 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 101931.044659 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 114679.378612 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 114679.378612 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 108307.718682 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 108307.718682 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 9531492 # number of replacements -system.cpu1.icache.tags.tagsinuse 507.211334 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 241397065 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 9532004 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 25.324902 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8370013399000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.211334 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990647 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990647 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 8549825 # number of replacements +system.cpu1.icache.tags.tagsinuse 507.203595 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 211942190 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 8550337 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 24.787583 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8370006207500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.203595 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990632 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990632 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 76 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 511390144 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 511390144 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 241397065 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 241397065 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 241397065 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 241397065 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 241397065 # number of overall hits -system.cpu1.icache.overall_hits::total 241397065 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 9532005 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 9532005 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 9532005 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 9532005 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 9532005 # number of overall misses -system.cpu1.icache.overall_misses::total 9532005 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 94727843232 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 94727843232 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 94727843232 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 94727843232 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 94727843232 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 94727843232 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 250929070 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 250929070 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 250929070 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 250929070 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 250929070 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 250929070 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037987 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.037987 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037987 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.037987 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037987 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.037987 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9937.871752 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9937.871752 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9937.871752 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9937.871752 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9937.871752 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9937.871752 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 449535393 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 449535393 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 211942190 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 211942190 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 211942190 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 211942190 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 211942190 # number of overall hits +system.cpu1.icache.overall_hits::total 211942190 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 8550338 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 8550338 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 8550338 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 8550338 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 8550338 # number of overall misses +system.cpu1.icache.overall_misses::total 8550338 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 84064963562 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 84064963562 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 84064963562 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 84064963562 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 84064963562 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 84064963562 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 220492528 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 220492528 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 220492528 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 220492528 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 220492528 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 220492528 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038778 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.038778 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038778 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.038778 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038778 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.038778 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9831.770810 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9831.770810 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9831.770810 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9831.770810 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9831.770810 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9831.770810 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1781,236 +1801,241 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9532005 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 9532005 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 9532005 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 9532005 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 9532005 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 9532005 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 85170319722 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 85170319722 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 85170319722 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 85170319722 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 85170319722 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 85170319722 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8117000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8117000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8117000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8117000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037987 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037987 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037987 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.037987 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037987 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.037987 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8935.194612 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8935.194612 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8935.194612 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8935.194612 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8935.194612 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8935.194612 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8550338 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 8550338 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 8550338 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 8550338 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 8550338 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 8550338 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 90 # number of ReadReq MSHR uncacheable +system.cpu1.icache.ReadReq_mshr_uncacheable::total 90 # number of ReadReq MSHR uncacheable +system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 90 # number of overall MSHR uncacheable misses +system.cpu1.icache.overall_mshr_uncacheable_misses::total 90 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 75495426368 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 75495426368 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 75495426368 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 75495426368 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 75495426368 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 75495426368 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8549000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8549000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8549000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8549000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038778 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038778 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038778 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.038778 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038778 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.038778 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8829.525379 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8829.525379 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8829.525379 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8829.525379 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8829.525379 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8829.525379 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94988.888889 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94988.888889 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94988.888889 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94988.888889 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7632700 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7634373 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 1426 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6602862 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6604361 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 1239 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 974619 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2493350 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13598.009718 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 15504995 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2509448 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 6.178648 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9806309185500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5002.427380 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 85.119837 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 87.520686 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4382.194744 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3239.455000 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 801.292071 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.305324 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.005195 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005342 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.267468 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.197721 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048907 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.829957 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1340 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14690 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 24 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 317 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 958 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 41 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 38 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 27 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1230 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4980 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7916 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 444 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.081787 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.896606 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 320697996 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 320697996 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 533308 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 157578 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 8712936 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2963890 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 12367712 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3514312 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3514312 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 195589 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 195589 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 70594 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 70594 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 40360 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 40360 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 897925 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 897925 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 533308 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 157578 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 8712936 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3861815 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 13265637 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 533308 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 157578 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 8712936 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3861815 # number of overall hits -system.cpu1.l2cache.overall_hits::total 13265637 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12573 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8955 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 819069 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 1025149 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1865746 # number of ReadReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 260149 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 260149 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 141488 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 141488 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 155591 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 155591 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 8 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 244809 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 244809 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12573 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8955 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 819069 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1269958 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 2110555 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12573 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8955 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 819069 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1269958 # number of overall misses -system.cpu1.l2cache.overall_misses::total 2110555 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 462714995 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 376910753 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 23725938333 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 33521266479 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 58086830560 # number of ReadReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 226799088 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 226799088 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3089566814 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 3089566814 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3237262107 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3237262107 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2205498 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2205498 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10480888835 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 10480888835 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 462714995 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 376910753 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 23725938333 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 44002155314 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 68567719395 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 462714995 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 376910753 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 23725938333 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 44002155314 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 68567719395 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 545881 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 166533 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 9532005 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3989039 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 14233458 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3514312 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3514312 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 455738 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::total 455738 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 212082 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 212082 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195951 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 195951 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1142734 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1142734 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 545881 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 166533 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 9532005 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 5131773 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 15376192 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 545881 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 166533 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 9532005 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 5131773 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 15376192 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023032 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.053773 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.085928 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.256991 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.131082 # miss rate for ReadReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.570830 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.570830 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.667138 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.667138 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.794030 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.794030 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.prefetcher.pfSpanPage 840391 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2149670 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13538.161783 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 13667574 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2165890 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 6.310373 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9806309103500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5443.099185 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 82.941597 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 88.885416 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3832.023077 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3147.321084 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 943.891423 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.332220 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.005062 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005425 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.233888 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.192097 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.057611 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.826304 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1444 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 51 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14725 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 21 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 436 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 846 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 141 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 24 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 24 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1094 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5482 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7066 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 978 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.088135 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.898743 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 283341479 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 283341479 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 455761 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 138301 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 7823529 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 2545685 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 10963276 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 3038484 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 3038484 # number of Writeback hits +system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 176317 # number of WriteInvalidateReq hits +system.cpu1.l2cache.WriteInvalidateReq_hits::total 176317 # number of WriteInvalidateReq hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 59890 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 59890 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 34545 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 34545 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 755491 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 755491 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 455761 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 138301 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 7823529 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3301176 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 11718767 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 455761 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 138301 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 7823529 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3301176 # number of overall hits +system.cpu1.l2cache.overall_hits::total 11718767 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11008 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7757 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 726809 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 914890 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 1660464 # number of ReadReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 241215 # number of WriteInvalidateReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::total 241215 # number of WriteInvalidateReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 139061 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 139061 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 153238 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 153238 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 230973 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 230973 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11008 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7757 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 726809 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1145863 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1891437 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11008 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7757 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 726809 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1145863 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1891437 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 327528752 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 257164513 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 20327901458 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 26467087148 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 47379681871 # number of ReadReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 239660388 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 239660388 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3007716761 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 3007716761 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3151750139 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3151750139 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2513499 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2513499 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 8819162910 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 8819162910 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 327528752 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 257164513 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 20327901458 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 35286250058 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 56198844781 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 327528752 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 257164513 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 20327901458 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 35286250058 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 56198844781 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 466769 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 146058 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 8550338 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3460575 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 12623740 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 3038484 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 3038484 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 417532 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::total 417532 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 198951 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 198951 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 187783 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 187783 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 986464 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 986464 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 466769 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 146058 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 8550338 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 4447039 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 13610204 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 466769 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 146058 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 8550338 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 4447039 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 13610204 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023583 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.053109 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.085004 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.264375 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.131535 # miss rate for ReadReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.577716 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.577716 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.698971 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.698971 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.816038 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.816038 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.214231 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.214231 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023032 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.053773 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.085928 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.247470 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.137261 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023032 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.053773 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.085928 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.247470 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.137261 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 36802.274318 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 42089.419654 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 28966.959234 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32698.921307 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31133.300331 # average ReadReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 871.804574 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 871.804574 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21836.246282 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21836.246282 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20806.229840 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20806.229840 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 275687.250000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 275687.250000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42812.514389 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42812.514389 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 36802.274318 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 42089.419654 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28966.959234 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34648.512245 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 32488.004053 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 36802.274318 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 42089.419654 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28966.959234 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34648.512245 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 32488.004053 # average overall miss latency +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.234142 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.234142 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023583 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.053109 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.085004 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.257669 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.138972 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023583 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.053109 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.085004 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.257669 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.138972 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 29753.702035 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 33152.573546 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 27968.698046 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 28929.256138 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 28534.001262 # average ReadReq miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 993.555077 # average WriteInvalidateReq miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 993.555077 # average WriteInvalidateReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21628.758322 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21628.758322 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20567.679942 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20567.679942 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 837833 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 837833 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38182.657324 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38182.657324 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 29753.702035 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 33152.573546 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 27968.698046 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30794.475481 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 29712.247768 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 29753.702035 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 33152.573546 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 27968.698046 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30794.475481 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 29712.247768 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2019,213 +2044,216 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 1040490 # number of writebacks -system.cpu1.l2cache.writebacks::total 1040490 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits +system.cpu1.l2cache.writebacks::writebacks 875308 # number of writebacks +system.cpu1.l2cache.writebacks::total 875308 # number of writebacks system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 845 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 849 # number of ReadReq MSHR hits -system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 8 # number of WriteInvalidateReq MSHR hits -system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 8 # number of WriteInvalidateReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 7280 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 7280 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 523 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 527 # number of ReadReq MSHR hits +system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 9 # number of WriteInvalidateReq MSHR hits +system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 9 # number of WriteInvalidateReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 3864 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 3864 # number of ReadExReq MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 8125 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 8129 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4387 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 4391 # number of demand (read+write) MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 8125 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 8129 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12572 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8954 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 819067 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 1024304 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 1864897 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 717839 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 717839 # number of HardPFReq MSHR misses -system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 260141 # number of WriteInvalidateReq MSHR misses -system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 260141 # number of WriteInvalidateReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 141488 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 141488 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 155591 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 155591 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 8 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 237529 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 237529 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12572 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8954 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 819067 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1261833 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 2102426 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12572 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8954 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 819067 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1261833 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 717839 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 2820265 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 380310007 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 318025257 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 18380027667 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 26750668121 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 45829031052 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 32395588345 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 32395588345 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 8350999174 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 8350999174 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2765649497 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2765649497 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2300876668 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2300876668 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1886998 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1886998 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7923837459 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7923837459 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 380310007 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 318025257 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 18380027667 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 34674505580 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 53752868511 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 380310007 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 318025257 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 18380027667 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 34674505580 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 32395588345 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 86148456856 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7360000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 476808000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 484168000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 548574002 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 548574002 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7360000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1025382002 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1032742002 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023031 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.053767 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.085928 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.256780 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.131022 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4387 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 4391 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11008 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7756 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 726806 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 914367 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 1659937 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 617005 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 617005 # number of HardPFReq MSHR misses +system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 241206 # number of WriteInvalidateReq MSHR misses +system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 241206 # number of WriteInvalidateReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 139061 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 139061 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 153238 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 153238 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 227109 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 227109 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11008 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7756 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 726806 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1141476 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 1887046 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11008 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7756 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 726806 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1141476 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 617005 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 2504051 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 90 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5083 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5173 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5087 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5087 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 90 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10170 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10260 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 255658756 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 206438003 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 15587531792 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 20464504451 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 36514133002 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 19899573281 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 19899573281 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 7445733077 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 7445733077 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2687293206 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2687293206 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2230899638 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2230899638 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2142999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2142999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 6831385140 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 6831385140 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 255658756 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 206438003 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 15587531792 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 27295889591 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 43345518142 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 255658756 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 206438003 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 15587531792 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 27295889591 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 19899573281 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 63245091423 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7792000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 477441500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 485233500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 545217001 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 545217001 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7792000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1022658501 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1030450501 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023583 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.053102 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.085003 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.264224 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.131493 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.570813 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.570813 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.667138 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.667138 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.794030 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.794030 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.577695 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.577695 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.698971 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.698971 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.816038 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.816038 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.207860 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.207860 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023031 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053767 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.085928 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245886 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.136733 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023031 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053767 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.085928 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245886 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.230225 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.230225 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023583 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053102 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.085003 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.256682 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.138649 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023583 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053102 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.085003 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.256682 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183418 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30250.557350 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35517.674447 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22440.200456 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26115.946165 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24574.564200 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45129.323351 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45129.323351 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32101.818529 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32101.818529 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19546.883813 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19546.883813 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14787.980462 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14787.980462 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 235874.750000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 235874.750000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33359.452778 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33359.452778 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30250.557350 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35517.674447 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22440.200456 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27479.472783 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25567.068002 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30250.557350 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35517.674447 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22440.200456 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27479.472783 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45129.323351 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30546.227697 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183983 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 23224.814317 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 26616.555312 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21446.619582 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 22381.061927 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 21997.300501 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 32251.883341 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 32251.883341 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30868.772240 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 30868.772240 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19324.564083 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19324.564083 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14558.396990 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14558.396990 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 714333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 714333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30079.764078 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30079.764078 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 23224.814317 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26616.555312 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21446.619582 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23912.802013 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22970.037902 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 23224.814317 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26616.555312 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21446.619582 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23912.802013 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 32251.883341 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25257.109948 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86577.777778 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 93929.077317 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 93801.179200 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 107178.494397 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 107178.494397 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86577.777778 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 100556.391445 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 100433.772027 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 16743915 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 14472665 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 5158 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5158 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3514312 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 1035959 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1137929 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 455738 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 448749 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 344575 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 466415 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 78 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 119 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1299611 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1147815 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 19064189 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15671741 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 370835 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1205745 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 36312510 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 610054016 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 588145619 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1332264 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4367048 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1203898947 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4911557 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 24519969 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 3.188170 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.390848 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 15242466 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 12851003 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 38250 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5087 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3038484 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 900400 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1105427 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 417532 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 439071 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337307 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 446846 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 71 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1140783 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 991898 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17100855 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13710565 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 326713 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1037575 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 32175708 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 547227328 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 511521449 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1168464 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3734152 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1063651393 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4928167 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 22242259 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.242416 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.428544 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 19906035 81.18% 81.18% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 4613934 18.82% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 16850390 75.76% 75.76% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 5391869 24.24% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 24519969 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 13930930666 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 22242259 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 12259577677 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 160378480 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 163507981 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 14310919255 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 12835259097 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8198844119 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7129308669 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 204674963 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 180853196 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 660298903 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 571040175 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40379 # Transaction distribution -system.iobus.trans_dist::ReadResp 40379 # Transaction distribution -system.iobus.trans_dist::WriteReq 136954 # Transaction distribution -system.iobus.trans_dist::WriteResp 29970 # Transaction distribution +system.iobus.trans_dist::ReadReq 40383 # Transaction distribution +system.iobus.trans_dist::ReadResp 40383 # Transaction distribution +system.iobus.trans_dist::WriteReq 136956 # Transaction distribution +system.iobus.trans_dist::WriteResp 29972 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106984 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47768 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2240,13 +2268,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122846 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122858 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231740 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 231740 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354666 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47776 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354678 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47788 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2261,13 +2289,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155896 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355312 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 7355312 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7513282 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36279000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7513294 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36287000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2295,29 +2323,29 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 609062244 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 608916622 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92879000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92889000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148791282 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148804483 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 171000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115866 # number of replacements -system.iocache.tags.tagsinuse 11.306200 # Cycle average of tags in use +system.iocache.tags.replacements 115850 # number of replacements +system.iocache.tags.tagsinuse 11.297267 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115882 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115866 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9129676346000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.405197 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.901004 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.462825 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.243813 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706638 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9129662020000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.840346 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.456922 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240022 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466058 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706079 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1043187 # Number of tag accesses system.iocache.tags.data_accesses 1043187 # Number of data accesses @@ -2334,19 +2362,19 @@ system.iocache.demand_misses::total 8926 # nu system.iocache.overall_misses::realview.ethernet 40 # number of overall misses system.iocache.overall_misses::realview.ide 8886 # number of overall misses system.iocache.overall_misses::total 8926 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5190000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1626687073 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1631877073 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ethernet 5219500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1645546182 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1650765682 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19941362889 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19941362889 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5559000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1626687073 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1632246073 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5559000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1626687073 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1632246073 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19952013957 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19952013957 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5588500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1645546182 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1651134682 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5588500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1645546182 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1651134682 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::realview.ide 8886 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 8923 # number of ReadReq accesses(hits+misses) @@ -2373,29 +2401,29 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140270.270270 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 183061.790795 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 182884.352012 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141067.567568 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 185184.130317 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 185001.197131 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186395.749729 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 186395.749729 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 138975 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 183061.790795 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 182864.225073 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 138975 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 183061.790795 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 182864.225073 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 111964 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186495.307308 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 186495.307308 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139712.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 185184.130317 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 184980.358727 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139712.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 185184.130317 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 184980.358727 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 111929 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16416 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16372 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.820419 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.836611 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106950 # number of writebacks -system.iocache.writebacks::total 106950 # number of writebacks +system.iocache.writebacks::writebacks 106949 # number of writebacks +system.iocache.writebacks::total 106949 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::realview.ide 8886 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 8923 # number of ReadReq MSHR misses @@ -2409,19 +2437,19 @@ system.iocache.demand_mshr_misses::total 8926 # nu system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses system.iocache.overall_mshr_misses::realview.ide 8886 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 8926 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3264000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1163415573 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1166679573 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3294500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1182279102 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1185573602 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14378130953 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14378130953 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3477000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1163415573 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1166892573 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3477000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1163415573 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1166892573 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14388800003 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14388800003 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3507500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1182279102 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1185786602 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3507500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1182279102 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1185786602 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2435,628 +2463,643 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88216.216216 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130926.803174 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 130749.699989 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 89040.540541 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133049.640108 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 132867.152527 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134395.152107 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134395.152107 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 86925 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 130926.803174 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 130729.618306 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 86925 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 130926.803174 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 130729.618306 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134494.877767 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134494.877767 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87687.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 133049.640108 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 132846.359175 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87687.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 133049.640108 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 132846.359175 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1418934 # number of replacements -system.l2c.tags.tagsinuse 64475.403646 # Cycle average of tags in use -system.l2c.tags.total_refs 4887849 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1480275 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.301987 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8811587000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 16720.464314 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 9.676845 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 2.082484 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3893.344537 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5310.090712 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3772.998059 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 379.879752 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 518.261056 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4648.220337 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11740.962883 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17479.422666 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.255134 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000148 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000032 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.059408 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.081026 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.057571 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005797 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.007908 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.070926 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.179153 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.266715 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.983817 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 9966 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 213 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 51162 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 69 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 272 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 1682 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 7941 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 195 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1978 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 11118 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 37794 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.152069 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003250 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.780670 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 63367915 # Number of tag accesses -system.l2c.tags.data_accesses 63367915 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6326 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4773 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 672724 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 551559 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 298336 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6350 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4103 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 758519 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 584378 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 311165 # number of ReadReq hits -system.l2c.ReadReq_hits::total 3198233 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2396374 # number of Writeback hits -system.l2c.Writeback_hits::total 2396374 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 132089 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 134441 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 266530 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 29493 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 27736 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 57229 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 5838 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6131 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 11969 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 53859 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 51185 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 105044 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6326 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4773 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 672724 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 605418 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 298336 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6350 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4103 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 758519 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 635563 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 311165 # number of demand (read+write) hits -system.l2c.demand_hits::total 3303277 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6326 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4773 # number of overall hits -system.l2c.overall_hits::cpu0.inst 672724 # number of overall hits -system.l2c.overall_hits::cpu0.data 605418 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 298336 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6350 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4103 # number of overall hits -system.l2c.overall_hits::cpu1.inst 758519 # number of overall hits -system.l2c.overall_hits::cpu1.data 635563 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 311165 # number of overall hits -system.l2c.overall_hits::total 3303277 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1746 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1432 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 67682 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 130428 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 208623 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2332 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2285 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 60547 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 132466 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 215131 # number of ReadReq misses -system.l2c.ReadReq_misses::total 822672 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 442954 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 116624 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 559578 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 45697 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 44658 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 90355 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 8940 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 8873 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 17813 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 77535 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 55004 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 132539 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1746 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1432 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 67682 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 207963 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 208623 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2332 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2285 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 60547 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 187470 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 215131 # number of demand (read+write) misses -system.l2c.demand_misses::total 955211 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1746 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1432 # number of overall misses -system.l2c.overall_misses::cpu0.inst 67682 # number of overall misses -system.l2c.overall_misses::cpu0.data 207963 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 208623 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2332 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2285 # number of overall misses -system.l2c.overall_misses::cpu1.inst 60547 # number of overall misses -system.l2c.overall_misses::cpu1.data 187470 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 215131 # number of overall misses -system.l2c.overall_misses::total 955211 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 161430014 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 133523499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 5728187863 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 12139315223 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 27793617273 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 206166757 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 199956257 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 5085068912 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 11808697846 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 27463393997 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 90719357641 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 48375493 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 41411697 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 89787190 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 259807838 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 288996819 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 548804657 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 49028949 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 59371116 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 108400065 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6929592651 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4617668591 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 11547261242 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 161430014 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 133523499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 5728187863 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 19068907874 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 27793617273 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 206166757 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 199956257 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 5085068912 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 16426366437 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 27463393997 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 102266618883 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 161430014 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 133523499 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 5728187863 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 19068907874 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 27793617273 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 206166757 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 199956257 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 5085068912 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 16426366437 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 27463393997 # number of overall miss cycles -system.l2c.overall_miss_latency::total 102266618883 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 8072 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 6205 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 740406 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 681987 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 506959 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 8682 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6388 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 819066 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 716844 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 526296 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 4020905 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 2396374 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2396374 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 575043 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 251065 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 826108 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 75190 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 72394 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 147584 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 14778 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 15004 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 29782 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 131394 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 106189 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 237583 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8072 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6205 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 740406 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 813381 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 506959 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 8682 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6388 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 819066 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 823033 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 526296 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 4258488 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8072 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6205 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 740406 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 813381 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 506959 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 8682 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6388 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 819066 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 823033 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 526296 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4258488 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.216303 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.230782 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.091412 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.191247 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.411518 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.268602 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.357702 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.073922 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.184791 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.408764 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.204599 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.770297 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.464517 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.677367 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.607754 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.616874 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.612228 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.604953 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.591376 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.598113 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.590095 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.517982 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.557864 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.216303 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.230782 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.091412 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.255677 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.411518 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.268602 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.357702 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.073922 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.227779 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.408764 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.224308 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.216303 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.230782 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.091412 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.255677 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.411518 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.268602 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.357702 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.073922 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.227779 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.408764 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.224308 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 92457.052692 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 93242.666899 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84633.844493 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 93072.923168 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 133224.128083 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88407.700257 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 87508.208753 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83985.480899 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 89145.122869 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 127658.933380 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 110274.031012 # average ReadReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 109.211099 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 355.087263 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::total 160.455182 # average WriteInvalidateReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5685.446266 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6471.333669 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 6073.871474 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5484.222483 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6691.211090 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 6085.446865 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89373.736390 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83951.505181 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 87123.497552 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 92457.052692 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 93242.666899 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 84633.844493 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 91693.752610 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 133224.128083 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88407.700257 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87508.208753 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 83985.480899 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 87621.307073 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 127658.933380 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 107061.810305 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 92457.052692 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 93242.666899 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 84633.844493 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 91693.752610 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 133224.128083 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88407.700257 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 87508.208753 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 83985.480899 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 87621.307073 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 127658.933380 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 107061.810305 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 855 # number of cycles access was blocked +system.l2c.tags.replacements 1147719 # number of replacements +system.l2c.tags.tagsinuse 64326.028489 # Cycle average of tags in use +system.l2c.tags.total_refs 4694874 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1208975 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.883351 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8775850000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 21201.345204 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 99.174306 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 102.969089 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 6287.304380 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9789.287555 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7119.681672 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 173.781032 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 211.002205 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4753.478760 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6062.523137 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8525.481150 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.323507 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001513 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.001571 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.095937 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.149373 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.108638 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002652 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003220 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.072532 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.092507 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.130089 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.981537 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 9955 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 220 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 51081 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 63 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 299 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 192 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 1433 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 7968 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 215 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2117 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 11769 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 36932 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.151901 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.779434 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 59123537 # Number of tag accesses +system.l2c.tags.data_accesses 59123537 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6743 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4986 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 715760 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 559628 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 328609 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 6048 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 4129 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 682361 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 522413 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 303271 # number of ReadReq hits +system.l2c.ReadReq_hits::total 3133948 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 2214381 # number of Writeback hits +system.l2c.Writeback_hits::total 2214381 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 145887 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 132101 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 277988 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 29325 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 26221 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 55546 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 6410 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 5303 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 11713 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 57124 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 48409 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 105533 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6743 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4986 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 715760 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 616752 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 328609 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6048 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4129 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 682361 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 570822 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 303271 # number of demand (read+write) hits +system.l2c.demand_hits::total 3239481 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6743 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4986 # number of overall hits +system.l2c.overall_hits::cpu0.inst 715760 # number of overall hits +system.l2c.overall_hits::cpu0.data 616752 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 328609 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6048 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4129 # number of overall hits +system.l2c.overall_hits::cpu1.inst 682361 # number of overall hits +system.l2c.overall_hits::cpu1.data 570822 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 303271 # number of overall hits +system.l2c.overall_hits::total 3239481 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 1023 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1006 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 70277 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 119509 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 168399 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 1111 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1082 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 44445 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 78155 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 124967 # number of ReadReq misses +system.l2c.ReadReq_misses::total 609974 # number of ReadReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.data 434854 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.data 99438 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::total 534292 # number of WriteInvalidateReq misses +system.l2c.UpgradeReq_misses::cpu0.data 45074 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 42732 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 87806 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 9265 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 7405 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 16670 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 70615 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 44107 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 114722 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 1023 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1006 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 70277 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 190124 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 168399 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1111 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1082 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 44445 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 122262 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 124967 # number of demand (read+write) misses +system.l2c.demand_misses::total 724696 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 1023 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1006 # number of overall misses +system.l2c.overall_misses::cpu0.inst 70277 # number of overall misses +system.l2c.overall_misses::cpu0.data 190124 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 168399 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 1111 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1082 # number of overall misses +system.l2c.overall_misses::cpu1.inst 44445 # number of overall misses +system.l2c.overall_misses::cpu1.data 122262 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 124967 # number of overall misses +system.l2c.overall_misses::total 724696 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 90170503 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 86831257 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 5869737346 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 10761538889 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 21763176095 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 95166250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 96017000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 3692339104 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 6847833445 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 15053704575 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 64356514464 # number of ReadReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 50866916 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 43440127 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::total 94307043 # number of WriteInvalidateReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 280117177 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 285028454 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 565145631 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 53423811 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 47784487 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 101208298 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6307677426 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3604652546 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9912329972 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 90170503 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 86831257 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 5869737346 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 17069216315 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 21763176095 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 95166250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 96017000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 3692339104 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 10452485991 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 15053704575 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 74268844436 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 90170503 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 86831257 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 5869737346 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 17069216315 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 21763176095 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 95166250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 96017000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 3692339104 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 10452485991 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 15053704575 # number of overall miss cycles +system.l2c.overall_miss_latency::total 74268844436 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 7766 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 5992 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 786037 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 679137 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 497008 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 7159 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 5211 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 726806 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 600568 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 428238 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 3743922 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 2214381 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 2214381 # number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.data 580741 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.data 231539 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 812280 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 74399 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 68953 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 143352 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 15675 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 12708 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 28383 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 127739 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 92516 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 220255 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 7766 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 5992 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 786037 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 806876 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 497008 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 7159 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5211 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 726806 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 693084 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 428238 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3964177 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 7766 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 5992 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 786037 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 806876 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 497008 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 7159 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5211 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 726806 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 693084 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 428238 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3964177 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.131728 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.167891 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.089407 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.175972 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.338826 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.155189 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.207638 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.061151 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.130135 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.291817 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.162924 # miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.748792 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.429465 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::total 0.657768 # miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.605841 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.619726 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.612520 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.591069 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.582704 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.587323 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.552807 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.476750 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.520860 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.131728 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.167891 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.089407 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.235630 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.338826 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.155189 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.207638 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.061151 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.176403 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.291817 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.182811 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.131728 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.167891 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.089407 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.235630 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.338826 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.155189 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.207638 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.061151 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.176403 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.291817 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.182811 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 88143.209189 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 86313.376740 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83522.878694 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 90047.936883 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 129235.779874 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 85658.190819 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 88740.295749 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83076.591383 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 87618.622545 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 120461.438420 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 105506.979747 # average ReadReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 116.974700 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 436.856403 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::total 176.508432 # average WriteInvalidateReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6214.606580 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6670.140738 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 6436.298556 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5766.196546 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6453.002971 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 6071.283623 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89324.894512 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81725.180720 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 86403.043636 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88143.209189 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 86313.376740 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 83522.878694 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 89779.387742 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 129235.779874 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85658.190819 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88740.295749 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 83076.591383 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 85492.515998 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120461.438420 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 102482.757509 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88143.209189 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 86313.376740 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 83522.878694 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 89779.387742 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 129235.779874 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85658.190819 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88740.295749 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 83076.591383 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 85492.515998 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120461.438420 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 102482.757509 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 106.875000 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1077155 # number of writebacks -system.l2c.writebacks::total 1077155 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 162 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 20 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 217 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 18 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 417 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 162 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 20 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 217 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 18 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 417 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 162 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 20 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 217 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 18 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 417 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1746 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1432 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 67520 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 130408 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 208623 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2332 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2285 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 60330 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 132448 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 215131 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 822255 # number of ReadReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 442954 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 116624 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::total 559578 # number of WriteInvalidateReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 45697 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 44658 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 90355 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 8940 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 8873 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 17813 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 77535 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 55004 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 132539 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 1746 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 1432 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 67520 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 207943 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 208623 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 2332 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 2285 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 60330 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 187452 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 215131 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 954794 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 1746 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 1432 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 67520 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 207943 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 208623 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 2332 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 2285 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 60330 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 187452 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 215131 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 954794 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 139394486 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 115450499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 4870282387 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10505515777 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 25233483205 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 176791243 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 171176743 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 4312003588 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 10147787904 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 24818336697 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 80490222529 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 14873961513 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 3737572303 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::total 18611533816 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 814223914 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 794539944 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 1608763858 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 159553413 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 157960839 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 317514252 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5960412849 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3929978409 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 9890391258 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 139394486 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 115450499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 4870282387 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 16465928626 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 25233483205 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 176791243 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 171176743 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 4312003588 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 14077766313 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 24818336697 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 90380613787 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 139394486 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 115450499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 4870282387 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 16465928626 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 25233483205 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 176791243 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 171176743 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 4312003588 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 14077766313 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 24818336697 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 90380613787 # number of overall MSHR miss cycles +system.l2c.writebacks::writebacks 874309 # number of writebacks +system.l2c.writebacks::total 874309 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 170 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 24 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 144 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 21 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 360 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 170 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 24 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 144 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 21 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 360 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 170 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 24 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 144 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 21 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 360 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1023 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1006 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 70107 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 119485 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 168399 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1111 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1082 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 44301 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 78134 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 124966 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 609614 # number of ReadReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 434854 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 99438 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::total 534292 # number of WriteInvalidateReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 45074 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 42732 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 87806 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9265 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 7405 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 16670 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 70615 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 44107 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 114722 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 1023 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 1006 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 70107 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 190100 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 168399 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 1111 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1082 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 44301 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 122241 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 124966 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 724336 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 1023 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 1006 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 70107 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 190100 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 168399 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 1111 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1082 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 44301 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 122241 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 124966 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 724336 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52307 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 33259 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 90 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5081 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 90737 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 33163 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5087 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 38250 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52307 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 66422 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 90 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10168 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 128987 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 77296003 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 74149743 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 4978677404 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 9263784361 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 19697035299 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 81192250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 82396000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3126135146 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 5867580805 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 13516096621 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 56764343632 # number of ReadReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 14608180584 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 3180916875 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::total 17789097459 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 802841847 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 760303552 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1563145399 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 165105237 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 131856877 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 296962114 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5424714574 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3052436454 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8477151028 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 77296003 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 74149743 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 4978677404 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 14688498935 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 19697035299 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 81192250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 82396000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3126135146 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 8920017259 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 13516096621 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 65241494660 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 77296003 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 74149743 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 4978677404 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 14688498935 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 19697035299 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 81192250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 82396000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 3126135146 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 8920017259 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 13516096621 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 65241494660 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3188012750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5001418750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5293500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 377070000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 8571795000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4829205000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 452800000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5282005000 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5000535750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5725000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 377455500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 8571729000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4829727000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 450782500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5280509500 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3188012750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9830623750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5293500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 829870000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 13853800000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.216303 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.230782 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.091193 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.191218 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.411518 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.268602 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.357702 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.073657 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.184765 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.408764 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.204495 # mshr miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.770297 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.464517 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.677367 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.607754 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.616874 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.612228 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.604953 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.591376 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.598113 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.590095 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.517982 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.557864 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.216303 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.230782 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.091193 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.255653 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.411518 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.268602 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.357702 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.073657 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.227758 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.408764 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.224210 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.216303 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.230782 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.091193 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.255653 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.411518 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.268602 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.357702 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.073657 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.227758 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.408764 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.224210 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79836.475372 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 80621.856844 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72130.959523 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80558.829037 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120952.546963 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75810.996141 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 74913.235449 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71473.621548 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76617.147137 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115363.832721 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 97889.611530 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33579.020650 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32048.054457 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33259.945559 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17817.885507 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17791.659815 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17804.923446 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17847.137919 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17802.416206 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17824.861169 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76873.835674 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71448.956603 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 74622.497967 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79836.475372 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80621.856844 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72130.959523 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79184.818080 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120952.546963 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75810.996141 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 74913.235449 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71473.621548 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75100.646101 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115363.832721 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 94659.804929 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79836.475372 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80621.856844 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72130.959523 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79184.818080 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120952.546963 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75810.996141 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 74913.235449 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71473.621548 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75100.646101 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115363.832721 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 94659.804929 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9830262750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5725000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 828238000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 13852238500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.131728 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.167891 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.089190 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.175937 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.338826 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.155189 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.207638 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.060953 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.130100 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.291814 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.162828 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.748792 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.429465 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.657768 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.605841 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.619726 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.612520 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.591069 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.582704 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.587323 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.552807 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.476750 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.520860 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.131728 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.167891 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.089190 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.235600 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.338826 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.155189 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.207638 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.060953 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.176373 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.291814 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.182720 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.131728 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.167891 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.089190 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.235600 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.338826 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.155189 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.207638 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.060953 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.176373 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.291814 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.182720 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 75558.165200 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 73707.498012 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71015.410786 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 77530.939959 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116966.462384 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73080.333033 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76151.571165 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70565.791878 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75096.383201 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108158.191996 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 93115.223128 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33593.299323 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31988.946630 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33294.710494 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17811.639681 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17792.369934 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17802.261793 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17820.316999 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17806.465496 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17814.164007 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76820.995171 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69205.261160 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 73892.985025 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75558.165200 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73707.498012 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71015.410786 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77267.222173 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116966.462384 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73080.333033 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76151.571165 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70565.791878 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72970.748431 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108158.191996 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 90070.760890 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75558.165200 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73707.498012 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71015.410786 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77267.222173 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116966.462384 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73080.333033 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76151.571165 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70565.791878 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72970.748431 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108158.191996 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 90070.760890 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60948.109240 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 150351.356024 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63611.111111 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 74287.640228 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 94467.846634 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 145636.010011 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 88614.605858 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138052.535948 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60948.109240 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 147997.090572 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63611.111111 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81455.350118 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 107392.516300 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 921958 # Transaction distribution -system.membus.trans_dist::ReadResp 921958 # Transaction distribution -system.membus.trans_dist::WriteReq 38330 # Transaction distribution -system.membus.trans_dist::WriteResp 38330 # Transaction distribution -system.membus.trans_dist::Writeback 1184105 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 663691 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 663691 # Transaction distribution -system.membus.trans_dist::UpgradeReq 435500 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 292205 # Transaction distribution -system.membus.trans_dist::UpgradeResp 115129 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution -system.membus.trans_dist::ReadExReq 144960 # Transaction distribution -system.membus.trans_dist::ReadExResp 128452 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122846 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 709274 # Transaction distribution +system.membus.trans_dist::ReadResp 709274 # Transaction distribution +system.membus.trans_dist::WriteReq 38250 # Transaction distribution +system.membus.trans_dist::WriteResp 38250 # Transaction distribution +system.membus.trans_dist::Writeback 981258 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 638260 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 638259 # Transaction distribution +system.membus.trans_dist::UpgradeReq 441618 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 290995 # Transaction distribution +system.membus.trans_dist::UpgradeResp 111840 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 38 # Transaction distribution +system.membus.trans_dist::ReadExReq 127489 # Transaction distribution +system.membus.trans_dist::ReadExResp 110378 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122858 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25278 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5060662 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5208838 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336578 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 336578 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5545416 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155884 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4347669 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4495681 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336711 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 336711 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4832392 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155896 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 168740232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 168947996 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14122752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14122752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 183070748 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 632037 # Total snoops (count) -system.membus.snoop_fanout::samples 3551920 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50204 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 139364352 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 139571776 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14131264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14131264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 153703040 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 640714 # Total snoops (count) +system.membus.snoop_fanout::samples 3227461 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3551920 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3227461 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3551920 # Request fanout histogram -system.membus.reqLayer0.occupancy 109974000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3227461 # Request fanout histogram +system.membus.reqLayer0.occupancy 110051499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33484 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21181500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20984500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 10917620106 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9462597488 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6186347625 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4943193797 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 152234718 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 152223017 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3100,45 +3143,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 4966231 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4959010 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38330 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38330 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2396374 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 933256 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 826108 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 485771 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 304174 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 789945 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 119 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 119 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295867 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295867 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7796872 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6899953 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 14696825 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 260005833 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 222466259 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 482472092 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1634381 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9291173 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012493 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.111071 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 4701983 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4694752 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38250 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38250 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2214381 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 919435 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 812281 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 489803 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 302708 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 792511 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 125 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 280473 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 280473 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7857713 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6052239 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 13909952 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 261128039 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 189974361 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 451102400 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1657293 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8947338 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012974 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.113161 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 9175099 98.75% 98.75% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 116074 1.25% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 8831258 98.70% 98.70% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 116080 1.30% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9291173 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8184497542 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8947338 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 7728831785 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2554500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2539500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4445775595 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4493592227 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4394903352 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3891101888 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index f1c6e64c5..828dae038 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.609999 # Nu sim_ticks 51609998980000 # Number of ticks simulated final_tick 51609998980000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125549 # Simulator instruction rate (inst/s) -host_op_rate 147521 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6837484784 # Simulator tick rate (ticks/s) -host_mem_usage 653616 # Number of bytes of host memory used -host_seconds 7548.10 # Real time elapsed on the host +host_inst_rate 182485 # Simulator instruction rate (inst/s) +host_op_rate 214421 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9938249935 # Simulator tick rate (ticks/s) +host_mem_usage 720032 # Number of bytes of host memory used +host_seconds 5193.07 # Real time elapsed on the host sim_insts 947659008 # Number of instructions simulated sim_ops 1113505098 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -683,6 +683,12 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 8185275 system.cpu.dcache.demand_mshr_misses::total 8185275 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9651575 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9651575 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33696 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33705 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33705 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67401 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67401 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84566997800 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 84566997800 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78901247228 # number of WriteReq MSHR miss cycles @@ -737,12 +743,12 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19971.014416 system.cpu.dcache.demand_avg_mshr_miss_latency::total 19971.014416 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19292.065367 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 19292.065367 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170695.156458 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170695.156458 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166484.683281 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166484.683281 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168589.638759 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168589.638759 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 24538707 # number of replacements system.cpu.icache.tags.tagsinuse 511.926996 # Cycle average of tags in use @@ -810,6 +816,10 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 24539229 system.cpu.icache.demand_mshr_misses::total 24539229 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 24539229 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 24539229 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52294 # number of ReadReq MSHR uncacheable +system.cpu.icache.ReadReq_mshr_uncacheable::total 52294 # number of ReadReq MSHR uncacheable +system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52294 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 52294 # number of overall MSHR uncacheable misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 290116862082 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 290116862082 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 290116862082 # number of demand (read+write) MSHR miss cycles @@ -832,10 +842,10 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11822.574462 system.cpu.icache.demand_avg_mshr_miss_latency::total 11822.574462 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11822.574462 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 11822.574462 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76950.806976 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76950.806976 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76950.806976 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76950.806976 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1594461 # number of replacements system.cpu.l2cache.tags.tagsinuse 65370.145273 # Cycle average of tags in use @@ -1048,6 +1058,14 @@ system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5190 system.cpu.l2cache.overall_mshr_misses::cpu.inst 107545 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1025546 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1144509 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52294 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 85990 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33705 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33705 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52294 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67401 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 119695 # number of overall MSHR uncacheable misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 460278992 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 386982750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7477222552 # number of ReadReq MSHR miss cycles @@ -1125,14 +1143,14 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74563.150289 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69526.454526 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70673.372070 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70600.823870 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59450.797415 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156677.253977 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 97549.909873 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153464.085447 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153464.085447 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59450.797415 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155070.455186 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 113294.822257 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 33827953 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 33819864 # Transaction distribution @@ -1157,19 +1175,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_si system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7738512 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 2838692178 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 565529 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 46009467 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.002514 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.050072 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 46129162 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.039419 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.194589 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 45893822 99.75% 99.75% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 115645 0.25% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 44310813 96.06% 96.06% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1818349 3.94% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 46009467 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 46129162 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 32777837483 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 1164000 # Layer occupancy (ticks) @@ -1440,17 +1456,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14069952 system.membus.pkt_size_system.iocache.mem_side::total 14069952 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 212687818 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 2980 # Total snoops (count) -system.membus.snoop_fanout::samples 3310460 # Request fanout histogram +system.membus.snoop_fanout::samples 3430156 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3310460 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3430156 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3310460 # Request fanout histogram +system.membus.snoop_fanout::total 3430156 # Request fanout histogram system.membus.reqLayer0.occupancy 99903000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt index ace9880b6..1e8b1ca15 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.320469 # Nu sim_ticks 51320468905000 # Number of ticks simulated final_tick 51320468905000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88986 # Simulator instruction rate (inst/s) -host_op_rate 104557 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5338089020 # Simulator tick rate (ticks/s) -host_mem_usage 657992 # Number of bytes of host memory used -host_seconds 9614.02 # Real time elapsed on the host +host_inst_rate 81731 # Simulator instruction rate (inst/s) +host_op_rate 96032 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4902851121 # Simulator tick rate (ticks/s) +host_mem_usage 723872 # Number of bytes of host memory used +host_seconds 10467.47 # Real time elapsed on the host sim_insts 855512158 # Number of instructions simulated sim_ops 1005211605 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1140,6 +1140,12 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 7197092 system.cpu.dcache.demand_mshr_misses::total 7197092 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 8381734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 8381734 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33661 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33661 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33682 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33682 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67343 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67343 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 73626554579 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 73626554579 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 56871439750 # number of WriteReq MSHR miss cycles @@ -1194,12 +1200,12 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18132.044766 system.cpu.dcache.demand_avg_mshr_miss_latency::total 18132.044766 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17902.025238 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 17902.025238 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170713.451769 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170713.451769 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 167130.276349 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 167130.276349 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168921.305377 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168921.305377 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 15070815 # number of replacements system.cpu.icache.tags.tagsinuse 511.953323 # Cycle average of tags in use @@ -1273,6 +1279,10 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15071548 system.cpu.icache.demand_mshr_misses::total 15071548 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15071548 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15071548 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable +system.cpu.icache.ReadReq_mshr_uncacheable::total 21295 # number of ReadReq MSHR uncacheable +system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 21295 # number of overall MSHR uncacheable misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179787086612 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 179787086612 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179787086612 # number of demand (read+write) MSHR miss cycles @@ -1295,10 +1305,10 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11928.906481 system.cpu.icache.demand_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74431.051890 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74431.051890 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74431.051890 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74431.051890 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1159288 # number of replacements system.cpu.l2cache.tags.tagsinuse 65272.997993 # Cycle average of tags in use @@ -1510,6 +1520,14 @@ system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3020 system.cpu.l2cache.overall_mshr_misses::cpu.inst 84629 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 667358 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 758173 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33661 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54956 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33682 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33682 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67343 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88638 # number of overall MSHR uncacheable misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 237171251 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 225518000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6085544162 # number of ReadReq MSHR miss cycles @@ -1587,14 +1605,14 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59931.028410 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156696.577642 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 119200.719667 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153989.267264 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153989.267264 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59931.028410 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155342.500334 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 132420.195063 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 23293786 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 23285542 # Transaction distribution @@ -1619,21 +1637,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_si system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6472392 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 2085922949 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 583028 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 34186904 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.003382 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.058057 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 34275542 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.049559 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.217032 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 34071281 99.66% 99.66% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115623 0.34% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 32576878 95.04% 95.04% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1698664 4.96% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 34186904 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 34275542 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 25901169608 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 909000 # Layer occupancy (ticks) @@ -1904,17 +1918,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14066304 system.membus.pkt_size_system.iocache.mem_side::total 14066304 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 157288413 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 3023 # Total snoops (count) -system.membus.snoop_fanout::samples 2488136 # Request fanout histogram +system.membus.snoop_fanout::samples 2576774 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2488136 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2576774 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2488136 # Request fanout histogram +system.membus.snoop_fanout::total 2576774 # Request fanout histogram system.membus.reqLayer0.occupancy 104078000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks) diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 417d3b817..49f083338 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,167 +1,167 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.305566 # Number of seconds simulated -sim_ticks 47305566199500 # Number of ticks simulated -final_tick 47305566199500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.385466 # Number of seconds simulated +sim_ticks 47385466309500 # Number of ticks simulated +final_tick 47385466309500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108918 # Simulator instruction rate (inst/s) -host_op_rate 128082 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5794473291 # Simulator tick rate (ticks/s) -host_mem_usage 707548 # Number of bytes of host memory used -host_seconds 8163.91 # Real time elapsed on the host -sim_insts 889196991 # Number of instructions simulated -sim_ops 1045647845 # Number of ops (including micro ops) simulated +host_inst_rate 109383 # Simulator instruction rate (inst/s) +host_op_rate 128637 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5566054279 # Simulator tick rate (ticks/s) +host_mem_usage 771804 # Number of bytes of host memory used +host_seconds 8513.30 # Real time elapsed on the host +sim_insts 931207580 # Number of instructions simulated +sim_ops 1095127739 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 75776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 60928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4503136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 12909720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 13016640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 167424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 164416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2523040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 10482528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 14576384 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 439104 # Number of bytes read from this memory -system.physmem.bytes_read::total 58919096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4503136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2523040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7026176 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 75116864 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 167872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 148672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4509472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 15471624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 18877376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 171456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 164224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3092064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 12069648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 17196544 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 427520 # Number of bytes read from this memory +system.physmem.bytes_read::total 72296472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4509472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3092064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7601536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 87689472 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 75137680 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1184 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 952 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 86314 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 201736 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 203385 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2569 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 39466 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 163804 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 227756 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6861 # Number of read requests responded to by this memory -system.physmem.num_reads::total 936643 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1173701 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 87710056 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2623 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2323 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 86413 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 241757 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 294959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2679 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2566 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 48357 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 188601 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 268696 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6680 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1145654 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1370148 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1176304 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 95193 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 272901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 275161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3539 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3476 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 221592 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 308133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9282 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1245500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 95193 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 148527 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1587908 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 440 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1372722 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 95166 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 326506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 398379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 65253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 254712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 362908 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1525710 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 95166 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 65253 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 160419 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1850556 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1588348 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1587908 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1602 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 95193 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 273341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 275161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3539 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 221592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 308133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9282 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2833848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 936643 # Number of read requests accepted -system.physmem.writeReqs 1837953 # Number of write requests accepted -system.physmem.readBursts 936643 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1837953 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 59924608 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20544 # Total number of bytes read from write queue -system.physmem.bytesWritten 114470976 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 58919096 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 117483216 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 321 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 49325 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 117374 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 55305 # Per bank write bursts -system.physmem.perBankRdBursts::1 59995 # Per bank write bursts -system.physmem.perBankRdBursts::2 52034 # Per bank write bursts -system.physmem.perBankRdBursts::3 56018 # Per bank write bursts -system.physmem.perBankRdBursts::4 58058 # Per bank write bursts -system.physmem.perBankRdBursts::5 68871 # Per bank write bursts -system.physmem.perBankRdBursts::6 59545 # Per bank write bursts -system.physmem.perBankRdBursts::7 57406 # Per bank write bursts -system.physmem.perBankRdBursts::8 51483 # Per bank write bursts -system.physmem.perBankRdBursts::9 77850 # Per bank write bursts -system.physmem.perBankRdBursts::10 53930 # Per bank write bursts -system.physmem.perBankRdBursts::11 57982 # Per bank write bursts -system.physmem.perBankRdBursts::12 54532 # Per bank write bursts -system.physmem.perBankRdBursts::13 56851 # Per bank write bursts -system.physmem.perBankRdBursts::14 60976 # Per bank write bursts -system.physmem.perBankRdBursts::15 55486 # Per bank write bursts -system.physmem.perBankWrBursts::0 110085 # Per bank write bursts -system.physmem.perBankWrBursts::1 112883 # Per bank write bursts -system.physmem.perBankWrBursts::2 108062 # Per bank write bursts -system.physmem.perBankWrBursts::3 109070 # Per bank write bursts -system.physmem.perBankWrBursts::4 113169 # Per bank write bursts -system.physmem.perBankWrBursts::5 118310 # Per bank write bursts -system.physmem.perBankWrBursts::6 115499 # Per bank write bursts -system.physmem.perBankWrBursts::7 111959 # Per bank write bursts -system.physmem.perBankWrBursts::8 107874 # Per bank write bursts -system.physmem.perBankWrBursts::9 113071 # Per bank write bursts -system.physmem.perBankWrBursts::10 109141 # Per bank write bursts -system.physmem.perBankWrBursts::11 113654 # Per bank write bursts -system.physmem.perBankWrBursts::12 105244 # Per bank write bursts -system.physmem.perBankWrBursts::13 111328 # Per bank write bursts -system.physmem.perBankWrBursts::14 115976 # Per bank write bursts -system.physmem.perBankWrBursts::15 113284 # Per bank write bursts +system.physmem.bw_write::total 1850991 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1850556 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 95166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 326940 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 398379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3618 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 65253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 254712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 362908 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3376701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1145654 # Number of read requests accepted +system.physmem.writeReqs 2060182 # Number of write requests accepted +system.physmem.readBursts 1145654 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2060182 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 73301632 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20224 # Total number of bytes read from write queue +system.physmem.bytesWritten 128743424 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 72296472 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 131707496 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 316 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 48535 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 120456 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 65572 # Per bank write bursts +system.physmem.perBankRdBursts::1 75328 # Per bank write bursts +system.physmem.perBankRdBursts::2 66668 # Per bank write bursts +system.physmem.perBankRdBursts::3 73797 # Per bank write bursts +system.physmem.perBankRdBursts::4 73498 # Per bank write bursts +system.physmem.perBankRdBursts::5 82651 # Per bank write bursts +system.physmem.perBankRdBursts::6 70750 # Per bank write bursts +system.physmem.perBankRdBursts::7 70075 # Per bank write bursts +system.physmem.perBankRdBursts::8 62480 # Per bank write bursts +system.physmem.perBankRdBursts::9 88491 # Per bank write bursts +system.physmem.perBankRdBursts::10 66146 # Per bank write bursts +system.physmem.perBankRdBursts::11 72268 # Per bank write bursts +system.physmem.perBankRdBursts::12 67491 # Per bank write bursts +system.physmem.perBankRdBursts::13 74959 # Per bank write bursts +system.physmem.perBankRdBursts::14 69333 # Per bank write bursts +system.physmem.perBankRdBursts::15 65831 # Per bank write bursts +system.physmem.perBankWrBursts::0 122352 # Per bank write bursts +system.physmem.perBankWrBursts::1 129436 # Per bank write bursts +system.physmem.perBankWrBursts::2 124260 # Per bank write bursts +system.physmem.perBankWrBursts::3 131298 # Per bank write bursts +system.physmem.perBankWrBursts::4 127700 # Per bank write bursts +system.physmem.perBankWrBursts::5 133890 # Per bank write bursts +system.physmem.perBankWrBursts::6 125807 # Per bank write bursts +system.physmem.perBankWrBursts::7 124647 # Per bank write bursts +system.physmem.perBankWrBursts::8 116114 # Per bank write bursts +system.physmem.perBankWrBursts::9 124444 # Per bank write bursts +system.physmem.perBankWrBursts::10 122980 # Per bank write bursts +system.physmem.perBankWrBursts::11 126137 # Per bank write bursts +system.physmem.perBankWrBursts::12 123363 # Per bank write bursts +system.physmem.perBankWrBursts::13 128612 # Per bank write bursts +system.physmem.perBankWrBursts::14 126014 # Per bank write bursts +system.physmem.perBankWrBursts::15 124562 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 81608 # Number of times write queue was full causing retry -system.physmem.totGap 47305564753000 # Total gap between requests +system.physmem.numWrRetry 81198 # Number of times write queue was full causing retry +system.physmem.totGap 47385464863500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 37 # Read request sizes (log2) +system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 915273 # Read request sizes (log2) +system.physmem.readPktSize::6 1124296 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) -system.physmem.writePktSize::3 2601 # Write request sizes (log2) +system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1835350 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 429452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 211261 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 82392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 54481 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 35792 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 29912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 27031 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 22393 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 8038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 3479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1011 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 510 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2057608 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 487455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 272298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 106854 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 72030 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 47157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 39210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 35683 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 33198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 29456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 723 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 559 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -188,136 +188,136 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 31294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 42762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 50992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 57625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 67617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 67331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 70370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 78632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 77296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 79817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 88544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 82050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 81883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 102987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 87472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 82523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 74776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 11408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 9295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 8921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 10393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 8966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 9255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 8034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 7640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 7450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 7439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 6226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 5791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 5896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 5137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 4222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 3205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 3127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 2893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 3002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 2825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 2650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 2954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 7063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 7984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 354953 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 953575 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 182.885667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 110.719338 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 252.430373 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 592274 62.11% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 190618 19.99% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 51298 5.38% 87.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22604 2.37% 89.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 16941 1.78% 91.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10334 1.08% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7600 0.80% 93.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7080 0.74% 94.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 54826 5.75% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 953575 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60764 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.409042 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 72.355469 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 60757 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 29112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 48128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 57284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 64958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 76298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 77584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 81647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 91142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 91147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 94824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 104842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 97550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 99736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 122228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 105767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 99735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 90681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 12739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 9828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 10412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 8556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 10053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 7840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 7194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 7547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 6708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 6021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 6115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 5369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 4788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 3634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 3586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 3218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 2942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 2764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 2992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 7153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 8045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 352485 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1120451 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 180.324302 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 110.099448 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 247.440504 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 698811 62.37% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 221320 19.75% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 61667 5.50% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27543 2.46% 90.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 21267 1.90% 91.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12605 1.12% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9064 0.81% 93.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8274 0.74% 94.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 59900 5.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1120451 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 73379 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.608158 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 65.872388 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 73373 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60764 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60764 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 29.435340 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.473917 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 995.068690 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-4095 60761 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 73379 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 73379 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.414056 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.095862 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 903.451601 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-4095 73376 100.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::98304-102399 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::102400-106495 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::192512-196607 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60764 # Writes before turning the bus around for reads -system.physmem.totQLat 43948740923 # Total ticks spent queuing -system.physmem.totMemAccLat 61504778423 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4681610000 # Total ticks spent in databus transfers -system.physmem.avgQLat 46937.64 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 73379 # Writes before turning the bus around for reads +system.physmem.totQLat 58866128789 # Total ticks spent queuing +system.physmem.totMemAccLat 80341216289 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5726690000 # Total ticks spent in databus transfers +system.physmem.avgQLat 51396.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 65687.64 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.27 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.42 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.25 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.48 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 70146.29 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.72 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.53 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.78 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.58 # Average write queue length when enqueuing -system.physmem.readRowHits 706637 # Number of row buffer hits during reads -system.physmem.writeRowHits 1064717 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.53 # Row buffer hit rate for writes -system.physmem.avgGap 17049532.53 # Average gap between requests -system.physmem.pageHitRate 65.01 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3636465840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1984182750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3644362800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5825759760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3089769502560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1155369631905 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27369856613250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31630086518865 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.633528 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45532077679143 # Time in different power states -system.physmem_0.memoryStateTime::REF 1579636760000 # Time in different power states +system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.33 # Average write queue length when enqueuing +system.physmem.readRowHits 867894 # Number of row buffer hits during reads +system.physmem.writeRowHits 1168605 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.78 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.09 # Row buffer hit rate for writes +system.physmem.avgGap 14781000.92 # Average gap between requests +system.physmem.pageHitRate 64.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4336385760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2366083500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4510974000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6605647200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3094987836720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1170067048560 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27404900969250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31687774944990 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.723600 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45590272941113 # Time in different power states +system.physmem_0.memoryStateTime::REF 1582304620000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 193851315857 # Time in different power states +system.physmem_0.memoryStateTime::ACT 212884395887 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3572561160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1949314125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3658902000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5764426560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3089769502560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1152447208560 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27372420142500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31629582057465 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.622864 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45536350688414 # Time in different power states -system.physmem_1.memoryStateTime::REF 1579636760000 # Time in different power states +system.physmem_1.actEnergy 4134208680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2255768625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4422568800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 6429624480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3094987836720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1167604821270 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27407060817750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31686895646325 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.705044 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45593855726560 # Time in different power states +system.physmem_1.memoryStateTime::REF 1582304620000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 189577142836 # Time in different power states +system.physmem_1.memoryStateTime::ACT 209300747940 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -351,15 +351,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 136259129 # Number of BP lookups -system.cpu0.branchPred.condPredicted 90543195 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6799058 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 95853282 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 62504832 # Number of BTB hits +system.cpu0.branchPred.lookups 143219505 # Number of BP lookups +system.cpu0.branchPred.condPredicted 95215917 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6874228 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 100849572 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 65904871 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.208860 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 18504887 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 186011 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 65.349678 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 19505246 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 190029 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -390,85 +390,88 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 520196 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 520196 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10690 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 81668 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 225929 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 294267 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 1575.669375 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 10064.565371 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 292845 99.52% 99.52% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1067 0.36% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 263 0.09% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 47 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 36 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 294267 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 252771 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 15945.045037 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 13637.155107 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 11018.196964 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 241135 95.40% 95.40% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 10520 4.16% 99.56% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 548 0.22% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 339 0.13% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 68 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 47 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 65 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 16 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 9 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 12 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 252771 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 499007353192 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.597965 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.527283 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 498187132192 99.84% 99.84% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 450171500 0.09% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 169118500 0.03% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 80846500 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 62229500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 34680000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 10096500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 12800000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 278500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 499007353192 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 81668 88.43% 88.43% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10690 11.57% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 92358 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 520196 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 557114 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 557114 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11925 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88835 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 245678 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 311436 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 1783.814331 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 11278.873416 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 309571 99.40% 99.40% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1396 0.45% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 332 0.11% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 57 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 59 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 14 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 311436 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 275434 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 16916.133019 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 14128.427647 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 15086.481481 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 261399 94.90% 94.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 11343 4.12% 99.02% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 1146 0.42% 99.44% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 802 0.29% 99.73% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 102 0.04% 99.77% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 163 0.06% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 287 0.10% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 70 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 43 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 36 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 22 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 9 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-425983 9 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::425984-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 275434 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 527372589640 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.581951 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.533395 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 526425698140 99.82% 99.82% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 513345500 0.10% 99.92% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 204440500 0.04% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 94120000 0.02% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 67519500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 37561500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 13535000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 16113500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 245000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 11000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 527372589640 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 88835 88.16% 88.16% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11925 11.84% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 100760 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 557114 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 520196 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 92358 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 557114 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 100760 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 92358 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 612554 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 100760 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 657874 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 98496070 # DTB read hits -system.cpu0.dtb.read_misses 369414 # DTB read misses -system.cpu0.dtb.write_hits 81551465 # DTB write hits -system.cpu0.dtb.write_misses 150782 # DTB write misses +system.cpu0.dtb.read_hits 103903304 # DTB read hits +system.cpu0.dtb.read_misses 386941 # DTB read misses +system.cpu0.dtb.write_hits 87265042 # DTB write hits +system.cpu0.dtb.write_misses 170173 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 36102 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 400 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 5365 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 44809 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1073 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 37535 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 216 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 6819 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 40284 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 98865484 # DTB read accesses -system.cpu0.dtb.write_accesses 81702247 # DTB write accesses +system.cpu0.dtb.perms_faults 40407 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 104290245 # DTB read accesses +system.cpu0.dtb.write_accesses 87435215 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 180047535 # DTB hits -system.cpu0.dtb.misses 520196 # DTB misses -system.cpu0.dtb.accesses 180567731 # DTB accesses +system.cpu0.dtb.hits 191168346 # DTB hits +system.cpu0.dtb.misses 557114 # DTB misses +system.cpu0.dtb.accesses 191725460 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -498,1116 +501,1134 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 81590 # Table walker walks requested -system.cpu0.itb.walker.walksLong 81590 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 901 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59909 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 9188 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 72402 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 845.170023 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 6470.995618 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 72024 99.48% 99.48% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 242 0.33% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 56 0.08% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 61 0.08% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 85759 # Table walker walks requested +system.cpu0.itb.walker.walksLong 85759 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 908 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 62470 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 9907 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 75852 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1136.575173 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 8938.964276 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 75266 99.23% 99.23% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 257 0.34% 99.57% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 133 0.18% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 159 0.21% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 9 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 8 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 72402 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 69998 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 20035.793294 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 17827.568317 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 13688.582598 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 69301 99.00% 99.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 578 0.83% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 67 0.10% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 29 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 14 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 7 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 75852 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 73285 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 21415.899529 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 18467.660437 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 19009.032462 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 71796 97.97% 97.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1220 1.66% 99.63% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 122 0.17% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 69 0.09% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 44 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 12 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 69998 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 370135740312 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.825869 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.379347 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 64468447528 17.42% 17.42% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 305652352784 82.58% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 13699000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 1205500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 35500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 370135740312 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 59909 98.52% 98.52% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 901 1.48% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 60810 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 73285 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 394225556964 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.858766 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.348387 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 55694159292 14.13% 14.13% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 338516533172 85.87% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 13791500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 1055500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 17500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 394225556964 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 62470 98.57% 98.57% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 908 1.43% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 63378 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 81590 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 81590 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85759 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85759 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60810 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60810 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 142400 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 213929001 # ITB inst hits -system.cpu0.itb.inst_misses 81590 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 63378 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 63378 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 149137 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 225166936 # ITB inst hits +system.cpu0.itb.inst_misses 85759 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25953 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 44809 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1073 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26709 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 203878 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 217420 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 214010591 # ITB inst accesses -system.cpu0.itb.hits 213929001 # DTB hits -system.cpu0.itb.misses 81590 # DTB misses -system.cpu0.itb.accesses 214010591 # DTB accesses -system.cpu0.numCycles 728554790 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 225252695 # ITB inst accesses +system.cpu0.itb.hits 225166936 # DTB hits +system.cpu0.itb.misses 85759 # DTB misses +system.cpu0.itb.accesses 225252695 # DTB accesses +system.cpu0.numCycles 777590959 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 88185009 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 601844339 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 136259129 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 81009719 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 601618645 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 14617520 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1590376 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 274448 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 5655980 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 730298 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 721373 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 213725526 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1720356 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 27419 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 706084889 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.998504 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.224315 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 90148881 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 632830647 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 143219505 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 85410117 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 647310508 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 14846236 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 1771940 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 282653 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6199385 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 737729 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 721364 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 224948990 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1718929 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 28705 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 754595578 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.984480 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.221164 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 368651970 52.21% 52.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 130906496 18.54% 70.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 45457211 6.44% 77.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 161069212 22.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 398817072 52.85% 52.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 138444624 18.35% 71.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 47562041 6.30% 77.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 169771841 22.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 706084889 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.187027 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.826080 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 103877352 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 333585554 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 228251571 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 35190646 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5179766 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19720762 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2170804 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 623516514 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 23718954 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5179766 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 138234059 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 46790455 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 227164838 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 228535971 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 60179800 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 606373965 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6065859 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 8641063 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 231610 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 454065 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 27284745 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 11061 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 577786095 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 931076470 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 716156173 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 752358 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 519674265 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 58111818 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 14452887 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 12546195 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 71496186 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 99205558 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 84922074 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 8773729 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 7651066 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 585335843 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 14506928 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 587846614 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2739409 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 54557687 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 35502721 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 263475 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 706084889 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.832544 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.074450 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 754595578 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.184184 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.813835 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 107688832 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 365256192 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 237731032 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 38638584 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5280938 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 20683549 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2184734 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 657953246 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 23988018 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5280938 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 144086550 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 51798126 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 247348242 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 239349699 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 66732023 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 640403541 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6134927 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 9593053 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 279391 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 288384 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 30790790 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 11378 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 609803525 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 987601051 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 757009838 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 819226 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 550929032 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 58874487 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 16040201 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 14019715 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 78263207 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 104115554 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 90761559 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 9526213 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8179417 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 617656959 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 16134834 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 622248752 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2762846 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 55648828 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 35830856 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 282296 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 754595578 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.824612 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.071196 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 387752647 54.92% 54.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 129908491 18.40% 73.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 115071565 16.30% 89.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 65618038 9.29% 98.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 7729861 1.09% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 4287 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 416444489 55.19% 55.19% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 139981431 18.55% 73.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 120577545 15.98% 89.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 69261363 9.18% 98.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 8325608 1.10% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 5142 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 706084889 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 754595578 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 62081849 46.00% 46.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 53806 0.04% 46.04% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 26012 0.02% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 10 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 46.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 34882864 25.85% 71.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 37902238 28.09% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 64632492 45.32% 45.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 49764 0.03% 45.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 24321 0.02% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 8 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 36912792 25.88% 71.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 41006253 28.75% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 401971331 68.38% 68.38% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1424969 0.24% 68.62% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 76351 0.01% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 44028 0.01% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 101506921 17.27% 85.91% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 82822965 14.09% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 425093937 68.32% 68.32% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1435088 0.23% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 72707 0.01% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 80017 0.01% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 106973715 17.19% 85.76% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 88593239 14.24% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 587846614 # Type of FU issued -system.cpu0.iq.rate 0.806867 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 134946779 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.229561 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2018256641 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 654059965 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 571438682 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1207660 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 478909 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 443638 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 722040340 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 753051 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2688850 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 622248752 # Type of FU issued +system.cpu0.iq.rate 0.800226 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 142625630 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.229210 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2143120412 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 689044772 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 604966692 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1361144 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 552290 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 506244 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 764032585 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 841796 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2890526 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 12347690 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 15246 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 139538 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 5796061 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 12594321 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 16775 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 157768 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 6060902 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2638151 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4049170 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2889033 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4437246 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5179766 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 6081153 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 2925805 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 599957845 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5280938 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 6404578 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 3121375 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 633914393 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 99205558 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 84922074 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 12284210 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 51884 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2819346 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 139538 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2067264 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2909526 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 4976790 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 580052597 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 98485742 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7283117 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 104115554 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 90761559 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13746258 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 66239 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2987519 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 157768 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2095186 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2941806 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5036992 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 614307958 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 103896068 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7396426 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 115074 # number of nop insts executed -system.cpu0.iew.exec_refs 180036231 # number of memory reference insts executed -system.cpu0.iew.exec_branches 109604684 # Number of branches executed -system.cpu0.iew.exec_stores 81550489 # Number of stores executed -system.cpu0.iew.exec_rate 0.796169 # Inst execution rate -system.cpu0.iew.wb_sent 572646335 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 571882320 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 278067639 # num instructions producing a value -system.cpu0.iew.wb_consumers 456095391 # num instructions consuming a value +system.cpu0.iew.exec_nop 122600 # number of nop insts executed +system.cpu0.iew.exec_refs 191163401 # number of memory reference insts executed +system.cpu0.iew.exec_branches 115873704 # Number of branches executed +system.cpu0.iew.exec_stores 87267333 # Number of stores executed +system.cpu0.iew.exec_rate 0.790014 # Inst execution rate +system.cpu0.iew.wb_sent 606266119 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 605472936 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 293481694 # num instructions producing a value +system.cpu0.iew.wb_consumers 481488998 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.784954 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609670 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.778652 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609529 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 47584416 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 14243453 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4670064 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 697066716 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.782257 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.580851 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 48614829 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15852538 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4732048 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 745378077 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.775637 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.576449 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 460295975 66.03% 66.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 120461861 17.28% 83.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 53495228 7.67% 90.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 18161397 2.61% 93.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 13064824 1.87% 95.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 8746806 1.25% 96.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 5864289 0.84% 97.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3641188 0.52% 98.09% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 13335148 1.91% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 493396348 66.19% 66.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 129662648 17.40% 83.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 56044004 7.52% 91.11% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 18992920 2.55% 93.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 13761945 1.85% 95.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 9179296 1.23% 96.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6220016 0.83% 97.57% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3818014 0.51% 98.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14302886 1.92% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 697066716 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 464477894 # Number of instructions committed -system.cpu0.commit.committedOps 545285068 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 745378077 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 491403423 # Number of instructions committed +system.cpu0.commit.committedOps 578142958 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 165983876 # Number of memory references committed -system.cpu0.commit.loads 86857868 # Number of loads committed -system.cpu0.commit.membars 3594521 # Number of memory barriers committed -system.cpu0.commit.branches 103961213 # Number of branches committed -system.cpu0.commit.fp_insts 434735 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 500421802 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13758946 # Number of function calls committed. +system.cpu0.commit.refs 176221889 # Number of memory references committed +system.cpu0.commit.loads 91521232 # Number of loads committed +system.cpu0.commit.membars 3904419 # Number of memory barriers committed +system.cpu0.commit.branches 110044339 # Number of branches committed +system.cpu0.commit.fp_insts 493876 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 530522943 # Number of committed integer instructions. +system.cpu0.commit.function_calls 14584303 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 378032624 69.33% 69.33% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1169798 0.21% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 60419 0.01% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 38309 0.01% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 86857868 15.93% 85.49% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 79126008 14.51% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 400598379 69.29% 69.29% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1193753 0.21% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 57671 0.01% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 71224 0.01% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 91521232 15.83% 85.35% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 84700657 14.65% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 545285068 # Class of committed instruction -system.cpu0.commit.bw_lim_events 13335148 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1272468420 # The number of ROB reads -system.cpu0.rob.rob_writes 1194722923 # The number of ROB writes -system.cpu0.timesIdled 998377 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 22469901 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93882577668 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 464477894 # Number of Instructions Simulated -system.cpu0.committedOps 545285068 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.568546 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.568546 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.637533 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.637533 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 684802624 # number of integer regfile reads -system.cpu0.int_regfile_writes 407591789 # number of integer regfile writes -system.cpu0.fp_regfile_reads 737398 # number of floating regfile reads -system.cpu0.fp_regfile_writes 323628 # number of floating regfile writes -system.cpu0.cc_regfile_reads 126081114 # number of cc regfile reads -system.cpu0.cc_regfile_writes 126833812 # number of cc regfile writes -system.cpu0.misc_regfile_reads 2842254449 # number of misc regfile reads -system.cpu0.misc_regfile_writes 14406777 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 5807270 # number of replacements -system.cpu0.dcache.tags.tagsinuse 503.185727 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 154700200 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5807781 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 26.636714 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1931738500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.185727 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.982785 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.982785 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 578142958 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14302886 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1353470869 # The number of ROB reads +system.cpu0.rob.rob_writes 1262695982 # The number of ROB writes +system.cpu0.timesIdled 1015060 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 22995381 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93993341722 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 491403423 # Number of Instructions Simulated +system.cpu0.committedOps 578142958 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.582388 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.582388 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.631956 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.631956 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 725839901 # number of integer regfile reads +system.cpu0.int_regfile_writes 430463320 # number of integer regfile writes +system.cpu0.fp_regfile_reads 805500 # number of floating regfile reads +system.cpu0.fp_regfile_writes 450680 # number of floating regfile writes +system.cpu0.cc_regfile_reads 133543353 # number of cc regfile reads +system.cpu0.cc_regfile_writes 134332816 # number of cc regfile writes +system.cpu0.misc_regfile_reads 3015329804 # number of misc regfile reads +system.cpu0.misc_regfile_writes 16059632 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 6141043 # number of replacements +system.cpu0.dcache.tags.tagsinuse 503.422627 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 163818652 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6141554 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 26.673811 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1929842500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.422627 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983247 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.983247 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 291 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 366 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 344453115 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 344453115 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 80805507 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 80805507 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 69071717 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 69071717 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209524 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 209524 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 255543 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 255543 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1772811 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1772811 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1798532 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1798532 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 149877224 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 149877224 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 150086748 # number of overall hits -system.cpu0.dcache.overall_hits::total 150086748 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6456855 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 6456855 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 6956516 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 6956516 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 664764 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 664764 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 829133 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 829133 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 256042 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 256042 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194087 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 194087 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 13413371 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 13413371 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 14078135 # number of overall misses -system.cpu0.dcache.overall_misses::total 14078135 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 92345367100 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 92345367100 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 122121346040 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 122121346040 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 37689944158 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 37689944158 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3513328512 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3513328512 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4123602814 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4123602814 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5259500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5259500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 214466713140 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 214466713140 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 214466713140 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 214466713140 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 87262362 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 87262362 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 76028233 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 76028233 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 874288 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 874288 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1084676 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1084676 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2028853 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2028853 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1992619 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1992619 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 163290595 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 163290595 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 164164883 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 164164883 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.073994 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.073994 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.091499 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.091499 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760349 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760349 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.764406 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.764406 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.126200 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.126200 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097403 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097403 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.082144 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.082144 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085756 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.085756 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14301.911240 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14301.911240 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17554.957976 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17554.957976 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 45457.054728 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 45457.054728 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13721.688286 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13721.688286 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21246.156693 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21246.156693 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 365108655 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 365108655 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 84789793 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 84789793 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73815215 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73815215 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 223529 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 223529 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 254722 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 254722 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1935633 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1935633 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1977053 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1977053 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 158605008 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 158605008 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 158828537 # number of overall hits +system.cpu0.dcache.overall_hits::total 158828537 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 6791004 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 6791004 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 7631461 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 7631461 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 739012 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 739012 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 806083 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 806083 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 273207 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 273207 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195599 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 195599 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 14422465 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 14422465 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 15161477 # number of overall misses +system.cpu0.dcache.overall_misses::total 15161477 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 101570086088 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 101570086088 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 139050346077 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 139050346077 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 37625975422 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 37625975422 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3995007021 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 3995007021 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4127543324 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4127543324 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2928500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2928500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 240620432165 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 240620432165 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 240620432165 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 240620432165 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 91580797 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 91580797 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81446676 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81446676 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 962541 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 962541 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1060805 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1060805 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2208840 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2208840 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2172652 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2172652 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 173027473 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 173027473 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 173990014 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 173990014 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.074153 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.074153 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.093699 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.093699 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.767772 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.767772 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.759879 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.759879 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.123688 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.123688 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.090028 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.090028 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.083354 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.083354 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.087140 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.087140 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14956.564020 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14956.564020 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18220.671779 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18220.671779 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 46677.544896 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 46677.544896 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14622.637857 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14622.637857 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21102.067618 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21102.067618 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15989.024171 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15989.024171 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15234.028736 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15234.028736 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 10974284 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 17020056 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 751732 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 670987 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.598665 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 25.365702 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16683.724465 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16683.724465 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15870.513946 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15870.513946 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 10994171 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 20243365 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 733732 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 746062 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.983906 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 27.133623 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3967066 # number of writebacks -system.cpu0.dcache.writebacks::total 3967066 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3312893 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3312893 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5560546 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 5560546 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 4546 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4546 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 132684 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 132684 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 8873439 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 8873439 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 8873439 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 8873439 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3143962 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3143962 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1395970 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1395970 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 657971 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 657971 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 824587 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 824587 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 123358 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 123358 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194072 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 194072 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4539932 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4539932 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5197903 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5197903 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41375173894 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41375173894 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 26017592924 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 26017592924 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14556234769 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14556234769 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 36285250520 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 36285250520 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1556312588 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1556312588 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3823478686 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3823478686 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5096000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5096000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 67392766818 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 67392766818 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 81949001587 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 81949001587 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5745168998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5745168998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5504162016 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5504162016 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11249331014 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11249331014 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036029 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036029 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018361 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018361 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.752579 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.752579 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.760215 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.760215 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060802 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060802 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097395 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097395 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027803 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027803 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031663 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031663 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13160.201648 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13160.201648 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18637.644737 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18637.644737 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22122.912361 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22122.912361 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 44004.150587 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 44004.150587 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12616.227468 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12616.227468 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19701.341183 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19701.341183 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 4196368 # number of writebacks +system.cpu0.dcache.writebacks::total 4196368 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3475469 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3475469 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6119501 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6119501 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 4173 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4173 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 141236 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 141236 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9594970 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 9594970 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9594970 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 9594970 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3315535 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3315535 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1511960 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1511960 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 732291 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 732291 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 801910 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 801910 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 131971 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 131971 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195594 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 195594 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4827495 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4827495 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5559786 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5559786 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31767 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31767 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31179 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31179 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62946 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62946 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45402822425 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45402822425 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 28839272084 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 28839272084 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16627256811 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16627256811 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 36253693272 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 36253693272 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1734403771 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1734403771 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3825076676 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3825076676 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2835500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2835500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 74242094509 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 74242094509 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 90869351320 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 90869351320 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5616435750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5616435750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5304462017 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5304462017 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10920897767 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10920897767 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036203 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036203 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018564 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018564 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.760789 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.760789 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.755945 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.755945 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059747 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059747 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.090025 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.090025 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027900 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027900 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031955 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031955 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13693.965657 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13693.965657 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19074.097254 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19074.097254 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22705.805221 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22705.805221 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 45209.179674 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 45209.179674 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13142.309833 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13142.309833 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19556.206612 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19556.206612 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14844.444106 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14844.444106 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15765.781237 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15765.781237 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15379.010130 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15379.010130 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16344.037580 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16344.037580 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176800.949098 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176800.949098 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170129.318355 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170129.318355 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 173496.294713 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 173496.294713 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 6071622 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.960367 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 207290998 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6072134 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.138080 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 14063099250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960367 # Average occupied blocks per requestor +system.cpu0.icache.tags.replacements 6182706 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.960451 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 218406038 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6183218 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 35.322390 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 14060425250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960451 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999923 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999923 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 329 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 92 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 433467798 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 433467798 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 207290998 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 207290998 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 207290998 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 207290998 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 207290998 # number of overall hits -system.cpu0.icache.overall_hits::total 207290998 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6406823 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6406823 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6406823 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6406823 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6406823 # number of overall misses -system.cpu0.icache.overall_misses::total 6406823 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 67980327142 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 67980327142 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 67980327142 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 67980327142 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 67980327142 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 67980327142 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 213697821 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 213697821 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 213697821 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 213697821 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 213697821 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 213697821 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029981 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029981 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029981 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029981 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029981 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029981 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10610.614206 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10610.614206 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10610.614206 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10610.614206 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10610.614206 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10610.614206 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 9344678 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 782 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 720412 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.971297 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 78.200000 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 456025787 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 456025787 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 218406038 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 218406038 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 218406038 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 218406038 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 218406038 # number of overall hits +system.cpu0.icache.overall_hits::total 218406038 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6515233 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6515233 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6515233 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6515233 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6515233 # number of overall misses +system.cpu0.icache.overall_misses::total 6515233 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 69121769887 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 69121769887 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 69121769887 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 69121769887 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 69121769887 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 69121769887 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 224921271 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 224921271 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 224921271 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 224921271 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 224921271 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 224921271 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028967 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.028967 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028967 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.028967 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028967 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.028967 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10609.255246 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10609.255246 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10609.255246 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10609.255246 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10609.255246 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10609.255246 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 9343070 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 429 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 716553 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.038910 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 47.666667 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 334667 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 334667 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 334667 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 334667 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 334667 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 334667 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6072156 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 6072156 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6072156 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 6072156 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6072156 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 6072156 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 58462486516 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 58462486516 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 58462486516 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 58462486516 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 58462486516 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 58462486516 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 331988 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 331988 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 331988 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 331988 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 331988 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 331988 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6183245 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6183245 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6183245 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6183245 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6183245 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6183245 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 59487086557 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 59487086557 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 59487086557 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 59487086557 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 59487086557 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 59487086557 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1881164498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1881164498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1881164498 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1881164498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028415 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028415 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028415 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028415 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028415 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028415 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9627.961883 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9627.961883 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9627.961883 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9627.961883 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9627.961883 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9627.961883 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027491 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027491 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027491 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.027491 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027491 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.027491 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9620.690520 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9620.690520 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9620.690520 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9620.690520 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9620.690520 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9620.690520 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88342.467268 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88342.467268 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88342.467268 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88342.467268 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7322641 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7635134 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 270741 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7927934 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8230587 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 262068 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 993362 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2579397 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16158.447303 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 12271567 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2594941 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 4.729035 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2266482500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 5660.592746 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 40.404376 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 30.912164 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5710.050306 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3705.001610 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1011.486101 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.345495 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002466 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001887 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.348514 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.226135 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.061736 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.986233 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1380 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 93 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14071 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 72 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 271 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 414 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 620 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 63 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 688 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5473 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2257 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5451 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.084229 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005676 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.858826 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 277998240 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 277998240 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 501930 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 167379 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 5436143 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2922103 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 9027555 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 3967054 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 3967054 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 228126 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 228126 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 108640 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 108640 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 33975 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 33975 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 890755 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 890755 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 501930 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 167379 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 5436143 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3812858 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 9918310 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 501930 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 167379 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 5436143 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3812858 # number of overall hits -system.cpu0.l2cache.overall_hits::total 9918310 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10652 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8152 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 635995 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 1000489 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1655288 # number of ReadReq misses +system.cpu0.l2cache.prefetcher.pfSpanPage 1052933 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2785828 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16244.844688 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 12810731 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2801890 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 4.572175 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 2265530500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 7084.641278 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 80.581753 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 91.908936 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4232.509595 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3861.356831 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 893.846295 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.432412 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004918 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005610 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.258332 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.235679 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.054556 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.991507 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1296 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 85 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14681 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 27 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 251 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 612 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 406 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 47 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1442 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5343 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4502 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3254 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.079102 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.896057 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 290229122 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 290229122 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 541748 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 180817 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 5534153 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 3094433 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 9351151 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 4196351 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 4196351 # number of Writeback hits +system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 207942 # number of WriteInvalidateReq hits +system.cpu0.l2cache.WriteInvalidateReq_hits::total 207942 # number of WriteInvalidateReq hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 120308 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 120308 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 36466 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 36466 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 968728 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 968728 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 541748 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 180817 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 5534153 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 4063161 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 10319879 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 541748 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 180817 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 5534153 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 4063161 # number of overall hits +system.cpu0.l2cache.overall_hits::total 10319879 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12343 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9059 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 649075 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 1080475 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 1750952 # number of ReadReq misses system.cpu0.l2cache.Writeback_misses::writebacks 10 # number of Writeback misses system.cpu0.l2cache.Writeback_misses::total 10 # number of Writeback misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 594866 # number of WriteInvalidateReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::total 594866 # number of WriteInvalidateReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 133117 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 133117 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 160078 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 160078 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 19 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 19 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 274591 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 274591 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10652 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8152 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 635995 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1275080 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1929879 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10652 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8152 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 635995 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1275080 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1929879 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 338313980 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 267505335 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 19973277607 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 34240699717 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 54819796639 # number of ReadReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 238254135 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 238254135 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2940744545 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 2940744545 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3318665043 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3318665043 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4985998 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4985998 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 14040093164 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 14040093164 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 338313980 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 267505335 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 19973277607 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 48280792881 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 68859889803 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 338313980 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 267505335 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 19973277607 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 48280792881 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 68859889803 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 512582 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 175531 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 6072138 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3922592 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 10682843 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 3967064 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 3967064 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 822992 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::total 822992 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 241757 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 241757 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 194053 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 194053 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 19 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 19 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1165346 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1165346 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 512582 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 175531 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 6072138 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5087938 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 11848189 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 512582 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 175531 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 6072138 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5087938 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 11848189 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020781 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.046442 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.104740 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.255058 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.154948 # miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000003 # miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_miss_rate::total 0.000003 # miss rate for Writeback accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.722809 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.722809 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.550623 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.550623 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.824919 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.824919 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 592445 # number of WriteInvalidateReq misses +system.cpu0.l2cache.WriteInvalidateReq_misses::total 592445 # number of WriteInvalidateReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 136302 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 136302 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 159123 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 159123 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 299943 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 299943 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12343 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9059 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 649075 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1380418 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2050895 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12343 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9059 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 649075 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1380418 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2050895 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 496433453 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 403677084 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 20306210078 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 39087285353 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 60293605968 # number of ReadReq miss cycles +system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 252817543 # number of WriteInvalidateReq miss cycles +system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 252817543 # number of WriteInvalidateReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2986484321 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 2986484321 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3304695138 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3304695138 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2772999 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2772999 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16034165055 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 16034165055 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 496433453 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 403677084 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 20306210078 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 55121450408 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 76327771023 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 496433453 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 403677084 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 20306210078 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 55121450408 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 76327771023 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 554091 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 189876 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 6183228 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4174908 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 11102103 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 4196361 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 4196361 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 800387 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::total 800387 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 256610 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 256610 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 195589 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 195589 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1268671 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1268671 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 554091 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 189876 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 6183228 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5443579 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 12370774 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 554091 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 189876 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 6183228 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5443579 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 12370774 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.022276 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.047710 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.104973 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.258802 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.157714 # miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.740198 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.740198 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.531164 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.531164 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.813558 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.813558 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.235630 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.235630 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020781 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.046442 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.104740 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.250608 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.162884 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020781 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.046442 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.104740 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.250608 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.162884 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 31760.606459 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 32814.687807 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 31404.771432 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 34223.964199 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33117.981064 # average ReadReq miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 400.517318 # average WriteInvalidateReq miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 400.517318 # average WriteInvalidateReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22091.427429 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22091.427429 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20731.549888 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20731.549888 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 262420.947368 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 262420.947368 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 51130.929870 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 51130.929870 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 31760.606459 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 32814.687807 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31404.771432 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37864.912696 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 35680.936371 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 31760.606459 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 32814.687807 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31404.771432 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37864.912696 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 35680.936371 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.236423 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.236423 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022276 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.047710 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.104973 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.253586 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.165786 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022276 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.047710 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.104973 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.253586 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.165786 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 40219.837398 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 44560.887957 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 31284.843936 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 36176.020133 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34434.756617 # average ReadReq miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 426.735888 # average WriteInvalidateReq miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 426.735888 # average WriteInvalidateReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21910.788697 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21910.788697 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20768.180200 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20768.180200 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 554599.800000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 554599.800000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 53457.373751 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 53457.373751 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 40219.837398 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 44560.887957 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31284.843936 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 39930.984968 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 37216.810721 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 40219.837398 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 44560.887957 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31284.843936 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 39930.984968 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 37216.810721 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 70 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 35 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1389796 # number of writebacks -system.cpu0.l2cache.writebacks::total 1389796 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 4 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 142 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 4324 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 4477 # number of ReadReq MSHR hits -system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 6 # number of WriteInvalidateReq MSHR hits -system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 6 # number of WriteInvalidateReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 17304 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 17304 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 4 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 142 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 21628 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 21781 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 4 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 142 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 21628 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 21781 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10648 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8010 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 635988 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 996165 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 1650811 # number of ReadReq MSHR misses +system.cpu0.l2cache.writebacks::writebacks 1537125 # number of writebacks +system.cpu0.l2cache.writebacks::total 1537125 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 3 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 146 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 10 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 4037 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 4196 # number of ReadReq MSHR hits +system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 18 # number of WriteInvalidateReq MSHR hits +system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 18 # number of WriteInvalidateReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 22490 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 22490 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 3 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 146 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 10 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 26527 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 26686 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 3 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 146 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 10 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 26527 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 26686 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12340 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8913 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 649065 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 1076438 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 1746756 # number of ReadReq MSHR misses system.cpu0.l2cache.Writeback_mshr_misses::writebacks 10 # number of Writeback MSHR misses system.cpu0.l2cache.Writeback_mshr_misses::total 10 # number of Writeback MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 695022 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 695022 # number of HardPFReq MSHR misses -system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 594860 # number of WriteInvalidateReq MSHR misses -system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 594860 # number of WriteInvalidateReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 133117 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 133117 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 160078 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 160078 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 19 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 19 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 257287 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 257287 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10648 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8010 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 635988 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1253452 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 1908098 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10648 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8010 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 635988 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1253452 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 695022 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 2603120 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 268701028 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 209265519 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 15816568891 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 27389377929 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 43683913367 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 34637549956 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 34637549956 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 28746452436 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 28746452436 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2662823288 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2662823288 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2368378420 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2368378420 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4277498 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4277498 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10397244749 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10397244749 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 268701028 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 209265519 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 15816568891 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 37786622678 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 54081158116 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 268701028 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 209265519 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 15816568891 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 37786622678 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 34637549956 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 88718708072 # number of overall MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 790245 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 790245 # number of HardPFReq MSHR misses +system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 592427 # number of WriteInvalidateReq MSHR misses +system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 592427 # number of WriteInvalidateReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 136302 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 136302 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 159123 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 159123 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 277453 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 277453 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12340 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8913 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 649065 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1353891 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 2024209 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12340 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8913 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 649065 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1353891 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 790245 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 2814454 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31767 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 53061 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31179 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31179 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 62946 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 84240 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 415403075 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 337276526 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 16064432920 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 31701439881 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 48518552402 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 48655967065 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 48655967065 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 28919407002 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 28919407002 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2740989495 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2740989495 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2358203392 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2358203392 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2369999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2369999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11491009195 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11491009195 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 415403075 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 337276526 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 16064432920 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 43192449076 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 60009561597 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 415403075 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 337276526 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 16064432920 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 43192449076 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 48655967065 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 108665528662 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1711512000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5486110502 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7197622502 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5256416460 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5256416460 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5362208750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7073720750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5065245463 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5065245463 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1711512000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10742526962 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12454038962 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020773 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045633 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.104739 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.253956 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.154529 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000003 # mshr miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000003 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10427454213 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12138966213 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022271 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.046941 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.104972 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.257835 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.157336 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.722802 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.722802 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.550623 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.550623 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.824919 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.824919 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.740176 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.740176 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.531164 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.531164 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.813558 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.813558 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.220782 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.220782 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.020773 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045633 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.104739 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.246358 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.161046 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.020773 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045633 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.104739 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.246358 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.218696 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.218696 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022271 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046941 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.104972 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.248713 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.163628 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022271 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046941 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.104972 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.248713 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.219706 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25234.882419 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26125.532959 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24869.288243 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27494.820566 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26462.092491 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49836.623813 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49836.623813 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 48324.735965 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 48324.735965 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20003.630551 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20003.630551 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14795.152488 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14795.152488 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 225131.473684 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 225131.473684 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40411.076926 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40411.076926 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25234.882419 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26125.532959 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24869.288243 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30146.046820 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28342.966722 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25234.882419 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26125.532959 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24869.288243 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30146.046820 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49836.623813 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34081.682009 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.227508 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 33663.134117 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 37840.965556 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24750.114272 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 29450.316582 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27776.376553 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61570.737006 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 61570.737006 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 48815.140097 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 48815.140097 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20109.679205 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20109.679205 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14820.003343 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14820.003343 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 473999.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 473999.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41416.056756 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41416.056756 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 33663.134117 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 37840.965556 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24750.114272 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31902.456753 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 29645.931619 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 33663.134117 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 37840.965556 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24750.114272 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31902.456753 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61570.737006 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38609.808035 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80375.316991 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168798.084490 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133312.993536 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162456.957022 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162456.957022 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80375.316991 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 165657.138071 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 144099.788853 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 13109671 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 10998966 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 32265 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 32265 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3967064 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 987402 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1170476 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 822992 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 487373 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 355558 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 509064 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 118 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 208 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1297704 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1174184 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12186882 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16978089 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 390292 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1142423 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 30697686 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 388957536 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 639747662 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1404248 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4100656 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1034210102 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 4435865 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 21321710 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 3.191876 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.393776 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 13667246 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11407678 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 38779 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 31179 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 4196361 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1120333 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 10 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1176973 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 800387 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 496358 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 355576 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 523512 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 86 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 143 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1407436 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1277584 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12409061 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17898439 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 414925 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1222034 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 31944459 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 396067296 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 675577736 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1519008 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4432728 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1077596768 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4739028 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 22459193 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.235945 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.424588 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 17230589 80.81% 80.81% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 4091121 19.19% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 17160060 76.41% 76.41% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 5299133 23.59% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 21321710 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 13464993223 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 22459193 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 14039414488 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 208995484 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 204401970 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9149850308 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9316604024 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8376078494 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8912883405 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 215375806 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 225880552 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 630757127 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 669143268 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 124182653 # Number of BP lookups -system.cpu1.branchPred.condPredicted 82299269 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6251064 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 87493813 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 57426824 # Number of BTB hits +system.cpu1.branchPred.lookups 128543512 # Number of BP lookups +system.cpu1.branchPred.condPredicted 85865577 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6421624 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 90850028 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 59627534 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 65.635297 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17076023 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 176220 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 65.632929 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17292026 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 181846 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1637,81 +1658,83 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 534049 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 534049 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11595 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85531 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 242787 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 291262 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2048.229773 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 11850.953616 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 289126 99.27% 99.27% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1672 0.57% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 329 0.11% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 62 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 62 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 10 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 291262 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 270383 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 17183.802917 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 14328.415565 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 16454.576356 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 267229 98.83% 98.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2235 0.83% 99.66% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 352 0.13% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 368 0.14% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 149 0.06% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 35 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 10 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 270383 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 438879688048 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.596096 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.540539 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 437883178548 99.77% 99.77% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 543837500 0.12% 99.90% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 218551000 0.05% 99.95% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 91365500 0.02% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 75836500 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 38561500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 12555000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 15271000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 530000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 438879688048 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 85532 88.06% 88.06% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 11595 11.94% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 97127 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 534049 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 599268 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 599268 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 13824 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 99235 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 280644 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 318624 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 1973.247464 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 12034.928654 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 316338 99.28% 99.28% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1742 0.55% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 377 0.12% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 71 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 83 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 318624 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 319817 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 17305.058052 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 14691.969456 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15678.724582 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 316762 99.04% 99.04% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2191 0.69% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 345 0.11% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 267 0.08% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 157 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 61 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 16 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 319817 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 467242764496 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.609754 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.540089 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 466086530996 99.75% 99.75% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 677505500 0.15% 99.90% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 222526000 0.05% 99.95% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 100711000 0.02% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 81855500 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 40422000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 15395000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 17231500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 579500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 7500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 467242764496 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 99236 87.77% 87.77% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 13824 12.23% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 113060 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 599268 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 534049 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97127 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 599268 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 113060 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97127 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 631176 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 113060 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 712328 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 91849877 # DTB read hits -system.cpu1.dtb.read_misses 382442 # DTB read misses -system.cpu1.dtb.write_hits 75119650 # DTB write hits -system.cpu1.dtb.write_misses 151607 # DTB write misses +system.cpu1.dtb.read_hits 95146273 # DTB read hits +system.cpu1.dtb.read_misses 436726 # DTB read misses +system.cpu1.dtb.write_hits 76756681 # DTB write hits +system.cpu1.dtb.write_misses 162542 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 39274 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 401 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 5573 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 44809 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1073 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 41064 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 604 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6738 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 36948 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 92232319 # DTB read accesses -system.cpu1.dtb.write_accesses 75271257 # DTB write accesses +system.cpu1.dtb.perms_faults 39860 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 95582999 # DTB read accesses +system.cpu1.dtb.write_accesses 76919223 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 166969527 # DTB hits -system.cpu1.dtb.misses 534049 # DTB misses -system.cpu1.dtb.accesses 167503576 # DTB accesses +system.cpu1.dtb.hits 171902954 # DTB hits +system.cpu1.dtb.misses 599268 # DTB misses +system.cpu1.dtb.accesses 172502222 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1741,1114 +1764,1128 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 85651 # Table walker walks requested -system.cpu1.itb.walker.walksLong 85651 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 898 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61483 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 9913 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 75738 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1212.145818 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 8774.873802 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 75006 99.03% 99.03% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 365 0.48% 99.52% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 180 0.24% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 161 0.21% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 83675 # Table walker walks requested +system.cpu1.itb.walker.walksLong 83675 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 922 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 60249 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 9641 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 74034 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1137.571926 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 8570.962609 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 73376 99.11% 99.11% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 334 0.45% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 142 0.19% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 157 0.21% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 7 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::294912-327679 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 75738 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 72294 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 21947.554182 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 18825.235250 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 19960.579515 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 70492 97.51% 97.51% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1482 2.05% 99.56% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 157 0.22% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 99 0.14% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 33 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 72294 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 404519897680 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.847972 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.359205 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 61519279012 15.21% 15.21% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 342981503668 84.79% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 17484500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 1520000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 101500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 9000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 404519897680 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 61483 98.56% 98.56% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 898 1.44% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 62381 # Table walker page sizes translated +system.cpu1.itb.walker.walkWaitTime::total 74034 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 70812 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 21947.603838 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 18689.139556 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 20589.258424 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 68933 97.35% 97.35% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1547 2.18% 99.53% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 153 0.22% 99.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 111 0.16% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 33 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 27 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 70812 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 419972060240 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.852209 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.355033 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 62087724216 14.78% 14.78% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 357865938524 85.21% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 17105000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 1290000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 2500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 419972060240 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 60249 98.49% 98.49% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 922 1.51% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 61171 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 85651 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 85651 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 83675 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 83675 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62381 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62381 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 148032 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 196330607 # ITB inst hits -system.cpu1.itb.inst_misses 85651 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61171 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61171 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 144846 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 203060553 # ITB inst hits +system.cpu1.itb.inst_misses 83675 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 28544 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 44809 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1073 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 29792 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 219679 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 217868 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 196416258 # ITB inst accesses -system.cpu1.itb.hits 196330607 # DTB hits -system.cpu1.itb.misses 85651 # DTB misses -system.cpu1.itb.accesses 196416258 # DTB accesses -system.cpu1.numCycles 659201565 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 203144228 # ITB inst accesses +system.cpu1.itb.hits 203060553 # DTB hits +system.cpu1.itb.misses 83675 # DTB misses +system.cpu1.itb.accesses 203144228 # DTB accesses +system.cpu1.numCycles 689224896 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 81623724 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 551229784 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 124182653 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 74502847 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 545141022 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13475474 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1814701 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 236397 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 6195125 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 729177 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 658891 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 196089515 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1603144 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 28612 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 643136774 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.007577 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.226676 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 83111859 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 570743281 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 128543512 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 76919560 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 571668142 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13828506 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1777982 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 253475 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 6260799 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 781198 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 699050 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 202821648 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1630400 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 27635 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 671466758 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.996773 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.223843 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 333162826 51.80% 51.80% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 120232758 18.69% 70.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 41446819 6.44% 76.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 148294371 23.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 351036099 52.28% 52.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 124470987 18.54% 70.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 43050208 6.41% 77.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 152909464 22.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 643136774 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.188383 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.836208 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 97937463 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 300403958 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 205522733 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 34511986 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 4760634 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 17730932 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 2017504 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 571814983 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 21511068 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 4760634 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 130465176 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 39849524 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 206232237 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 207101717 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 54727486 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 556322152 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5380569 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 8461915 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 304416 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 605845 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 22227660 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 11247 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 528347539 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 856455710 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 657084844 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 755426 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 475426080 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 52921453 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 14732861 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 12829203 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 69624573 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 92331469 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 78236769 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8977003 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7612209 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 535459998 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 14979383 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 539826932 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2475624 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 50076597 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 32301398 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 273094 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 643136774 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.839366 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.069808 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 671466758 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.186504 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.828094 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 100354838 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 318587695 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 211284340 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 36331371 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4908514 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 18177231 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 2045887 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 591006296 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22089664 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4908514 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 134210773 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 44178364 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 216212349 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 213325919 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 58630839 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 574898328 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5600894 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 8989963 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 383271 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 860464 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 24265786 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 10988 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 548407946 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 889065279 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 679031773 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 678204 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 493384651 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 55023295 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15514043 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13585261 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 73076002 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 95606432 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 79961275 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8917606 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7761424 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 553073173 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15730545 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 557717167 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2597694 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 51818937 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 33853803 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 272876 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 671466758 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.830595 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.066249 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 347132433 53.97% 53.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 125915806 19.58% 73.55% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 103467009 16.09% 89.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 59513725 9.25% 98.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7103072 1.10% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 4729 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 364901654 54.34% 54.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 131371089 19.56% 73.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 106572496 15.87% 89.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 61289322 9.13% 98.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7327865 1.09% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 4332 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 643136774 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 671466758 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 53820631 43.79% 43.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 63940 0.05% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 7561 0.01% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 17 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 33515144 27.27% 71.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 35487446 28.88% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 55930906 44.08% 44.08% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 67479 0.05% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 9405 0.01% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 14 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 34760931 27.40% 71.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 36114343 28.46% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 367420702 68.06% 68.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1281309 0.24% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 73255 0.01% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 4 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 2 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 83298 0.02% 68.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.33% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 94677124 17.54% 85.87% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 76291227 14.13% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 41 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 380161908 68.16% 68.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1344725 0.24% 68.41% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 78828 0.01% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 3 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 5 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 45642 0.01% 68.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 98115732 17.59% 86.02% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 77970283 13.98% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 539826932 # Type of FU issued -system.cpu1.iq.rate 0.818910 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 122894739 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.227656 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1846883379 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 600138356 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 524462260 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1277620 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 518844 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 476158 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 661932910 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 788750 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2478321 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 557717167 # Type of FU issued +system.cpu1.iq.rate 0.809195 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 126883078 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.227504 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1915274546 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 620324151 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 541832642 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1107318 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 438573 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 407875 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 683910466 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 689738 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2496582 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 11570290 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 16551 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 142141 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5437069 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 11949439 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 17528 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 140940 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5567236 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2465198 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 3688063 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2504839 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3936319 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 4760634 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6603988 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1453249 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 550562460 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4908514 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 7583348 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1594599 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 568926208 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 92331469 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 78236769 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12610859 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 52882 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1339609 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 142141 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1900150 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2649580 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4549730 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 532747017 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 91844367 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6553150 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 95606432 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 79961275 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 13359998 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 58436 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1466228 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 140940 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1941130 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2763310 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4704440 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 550354066 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 95142052 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6771828 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 123079 # number of nop insts executed -system.cpu1.iew.exec_refs 166962398 # number of memory reference insts executed -system.cpu1.iew.exec_branches 99765376 # Number of branches executed -system.cpu1.iew.exec_stores 75118031 # Number of stores executed -system.cpu1.iew.exec_rate 0.808170 # Inst execution rate -system.cpu1.iew.wb_sent 525632708 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 524938418 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 254712512 # num instructions producing a value -system.cpu1.iew.wb_consumers 416314102 # num instructions consuming a value +system.cpu1.iew.exec_nop 122490 # number of nop insts executed +system.cpu1.iew.exec_refs 171896040 # number of memory reference insts executed +system.cpu1.iew.exec_branches 103292614 # Number of branches executed +system.cpu1.iew.exec_stores 76753988 # Number of stores executed +system.cpu1.iew.exec_rate 0.798512 # Inst execution rate +system.cpu1.iew.wb_sent 542951378 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 542240517 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 263529127 # num instructions producing a value +system.cpu1.iew.wb_consumers 431811268 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.796325 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.611828 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.786740 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.610288 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 43862550 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14706289 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4273961 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 634802902 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.788218 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.581621 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 45371481 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 15457669 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4415885 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 662874998 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.779913 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.574524 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 414870625 65.35% 65.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 114759147 18.08% 83.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 48245889 7.60% 91.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 16373665 2.58% 93.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 11678245 1.84% 95.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 7925650 1.25% 96.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5354812 0.84% 97.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3238197 0.51% 98.05% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 12356672 1.95% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 435019222 65.63% 65.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 119535237 18.03% 83.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 49733246 7.50% 91.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 16752738 2.53% 93.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 12005106 1.81% 95.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 8186664 1.24% 96.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5495672 0.83% 97.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3379842 0.51% 98.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12767271 1.93% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 634802902 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 424719097 # Number of instructions committed -system.cpu1.commit.committedOps 500362777 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 662874998 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 439804157 # Number of instructions committed +system.cpu1.commit.committedOps 516984781 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 153560878 # Number of memory references committed -system.cpu1.commit.loads 80761178 # Number of loads committed -system.cpu1.commit.membars 3652883 # Number of memory barriers committed -system.cpu1.commit.branches 94624372 # Number of branches committed -system.cpu1.commit.fp_insts 463166 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 459868567 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12685398 # Number of function calls committed. +system.cpu1.commit.refs 158051032 # Number of memory references committed +system.cpu1.commit.loads 83656993 # Number of loads committed +system.cpu1.commit.membars 3709079 # Number of memory barriers committed +system.cpu1.commit.branches 98009532 # Number of branches committed +system.cpu1.commit.fp_insts 399401 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 474457036 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12875376 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 345616008 69.07% 69.07% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1054252 0.21% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 58059 0.01% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 73580 0.01% 69.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.31% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 80761178 16.14% 85.45% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 72799700 14.55% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 357731742 69.20% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1099808 0.21% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 62550 0.01% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 39649 0.01% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 83656993 16.18% 85.61% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 74394039 14.39% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 500362777 # Class of committed instruction -system.cpu1.commit.bw_lim_events 12356672 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1162834468 # The number of ROB reads -system.cpu1.rob.rob_writes 1096743807 # The number of ROB writes -system.cpu1.timesIdled 924876 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 16064791 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 93951930875 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 424719097 # Number of Instructions Simulated -system.cpu1.committedOps 500362777 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.552088 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.552088 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.644293 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.644293 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 629086185 # number of integer regfile reads -system.cpu1.int_regfile_writes 373708704 # number of integer regfile writes -system.cpu1.fp_regfile_reads 742781 # number of floating regfile reads -system.cpu1.fp_regfile_writes 462024 # number of floating regfile writes -system.cpu1.cc_regfile_reads 113147370 # number of cc regfile reads -system.cpu1.cc_regfile_writes 113825607 # number of cc regfile writes -system.cpu1.misc_regfile_reads 2613251902 # number of misc regfile reads -system.cpu1.misc_regfile_writes 14637394 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 5151228 # number of replacements -system.cpu1.dcache.tags.tagsinuse 427.693854 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 143143391 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5151740 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.785445 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8478589557500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 427.693854 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.835340 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.835340 # Average percentage of cache occupancy +system.cpu1.commit.op_class_0::total 516984781 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12767271 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1208536006 # The number of ROB reads +system.cpu1.rob.rob_writes 1133266670 # The number of ROB writes +system.cpu1.timesIdled 962801 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 17758138 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94081707774 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 439804157 # Number of Instructions Simulated +system.cpu1.committedOps 516984781 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.567118 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.567118 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.638114 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.638114 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 649922276 # number of integer regfile reads +system.cpu1.int_regfile_writes 385926927 # number of integer regfile writes +system.cpu1.fp_regfile_reads 666608 # number of floating regfile reads +system.cpu1.fp_regfile_writes 325148 # number of floating regfile writes +system.cpu1.cc_regfile_reads 119080359 # number of cc regfile reads +system.cpu1.cc_regfile_writes 119756232 # number of cc regfile writes +system.cpu1.misc_regfile_reads 2706897787 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15455536 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 5466279 # number of replacements +system.cpu1.dcache.tags.tagsinuse 430.006906 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 146874051 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5466791 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 26.866593 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8478589492000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.006906 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.839857 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.839857 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 318663535 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 318663535 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 75155961 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 75155961 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 63737585 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 63737585 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 169811 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 169811 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 58007 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 58007 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1657429 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1657429 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1683439 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1683439 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 138893546 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 138893546 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 139063357 # number of overall hits -system.cpu1.dcache.overall_hits::total 139063357 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6025315 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6025315 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 6706823 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 6706823 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 630176 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 630176 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 421123 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 421123 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 264252 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 264252 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195781 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 195781 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 12732138 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 12732138 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 13362314 # number of overall misses -system.cpu1.dcache.overall_misses::total 13362314 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 87326420147 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 87326420147 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 117804291686 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 117804291686 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 13004978477 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 13004978477 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3882326694 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 3882326694 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4150746008 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4150746008 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4758000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4758000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 205130711833 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 205130711833 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 205130711833 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 205130711833 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 81181276 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 81181276 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 70444408 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 70444408 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 799987 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 799987 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 479130 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 479130 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1921681 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1921681 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1879220 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1879220 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 151625684 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 151625684 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 152425671 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 152425671 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074221 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.074221 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.095207 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.095207 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.787733 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.787733 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.878933 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.878933 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137511 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137511 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104182 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104182 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083971 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.083971 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087664 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.087664 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14493.253904 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14493.253904 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17564.842801 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17564.842801 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 30881.662785 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 30881.662785 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14691.758980 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14691.758980 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21200.964384 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21200.964384 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 328243838 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 328243838 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 77663514 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 77663514 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 64795157 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 64795157 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 170774 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 170774 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 62879 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 62879 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1733317 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1733317 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1753267 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1753267 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 142458671 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 142458671 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 142629445 # number of overall hits +system.cpu1.dcache.overall_hits::total 142629445 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 6440843 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 6440843 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 7141641 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 7141641 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 671959 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 671959 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 448993 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 448993 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 259783 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 259783 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195367 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 195367 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 13582484 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 13582484 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 14254443 # number of overall misses +system.cpu1.dcache.overall_misses::total 14254443 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96129677540 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 96129677540 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 127902484654 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 127902484654 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 14399209171 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 14399209171 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3810993278 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3810993278 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4142660469 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4142660469 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3781500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3781500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 224032162194 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 224032162194 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 224032162194 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 224032162194 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 84104357 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 84104357 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 71936798 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 71936798 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 842733 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 842733 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 511872 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 511872 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1993100 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1993100 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1948634 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1948634 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 156041155 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 156041155 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 156883888 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 156883888 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.076582 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.076582 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.099277 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.099277 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.797357 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.797357 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.877159 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.877159 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.130341 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.130341 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100258 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100258 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.087044 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.087044 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.090860 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.090860 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14925.014868 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14925.014868 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17909.397106 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17909.397106 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 32070.008154 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 32070.008154 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14669.910187 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14669.910187 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21204.504696 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21204.504696 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16111.254200 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16111.254200 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15351.436273 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15351.436273 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 3328310 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 18296285 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 353421 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 675053 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.417409 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 27.103479 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16494.196658 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16494.196658 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15716.654954 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15716.654954 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 3725007 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 19991584 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 377661 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 721598 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.863362 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 27.704600 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3264704 # number of writebacks -system.cpu1.dcache.writebacks::total 3264704 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3035971 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3035971 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5416489 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 5416489 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3258 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3258 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 136728 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 136728 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 8452460 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 8452460 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 8452460 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 8452460 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2989344 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2989344 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1290334 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1290334 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 630111 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 630111 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 417865 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 417865 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 127524 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 127524 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195781 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 195781 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4279678 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4279678 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4909789 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4909789 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39357294362 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39357294362 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22683763866 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22683763866 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12612160940 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12612160940 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12265252837 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 12265252837 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1674709739 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1674709739 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3848237992 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3848237992 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4609500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4609500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62041058228 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 62041058228 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 74653219168 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 74653219168 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 688989750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 688989750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 785556502 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 785556502 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1474546252 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1474546252 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036823 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036823 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018317 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018317 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.787652 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.787652 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.872133 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.872133 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066361 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066361 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104182 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104182 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028225 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028225 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032211 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032211 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13165.863267 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13165.863267 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17579.761415 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17579.761415 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20015.776490 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20015.776490 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 29352.189911 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29352.189911 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13132.506344 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13132.506344 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19655.829687 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19655.829687 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3504875 # number of writebacks +system.cpu1.dcache.writebacks::total 3504875 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3270021 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3270021 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5779466 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5779466 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3415 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3415 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 132178 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 132178 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 9049487 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 9049487 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 9049487 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 9049487 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3170822 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3170822 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1362175 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1362175 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 671771 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 671771 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 445578 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 445578 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 127605 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 127605 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195366 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 195366 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4532997 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4532997 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5204768 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5204768 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7126 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7126 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7600 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7600 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14726 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14726 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42364690330 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42364690330 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24508372089 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24508372089 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14203530799 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14203530799 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 13616215076 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 13616215076 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1679833771 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1679833771 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3840214031 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3840214031 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3660000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3660000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 66873062419 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 66873062419 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 81076593218 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 81076593218 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 831425000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 831425000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 995372500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 995372500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1826797500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1826797500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037701 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037701 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018936 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018936 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.797134 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.797134 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.870487 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.870487 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064023 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064023 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100258 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100258 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029050 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029050 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033176 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033176 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13360.791091 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13360.791091 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17992.087719 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17992.087719 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21143.411667 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21143.411667 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30558.544354 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 30558.544354 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13164.325622 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13164.325622 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19656.511527 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19656.511527 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14496.664989 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14496.664989 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15204.975034 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15204.975034 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14752.505333 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14752.505333 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15577.369293 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15577.369293 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116674.852652 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 116674.852652 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 130970.065789 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 130970.065789 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124052.526144 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124052.526144 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5667991 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.848972 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 190104103 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5668503 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 33.536915 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8518313865250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.848972 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980174 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.980174 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 5740789 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.866118 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 196754052 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5741301 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 34.269942 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8518317120500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.866118 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980207 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.980207 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 347 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 334 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 124 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 397835903 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 397835903 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 190104103 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 190104103 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 190104103 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 190104103 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 190104103 # number of overall hits -system.cpu1.icache.overall_hits::total 190104103 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5979587 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5979587 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5979587 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5979587 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5979587 # number of overall misses -system.cpu1.icache.overall_misses::total 5979587 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 61433525378 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 61433525378 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 61433525378 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 61433525378 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 61433525378 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 61433525378 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 196083690 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 196083690 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 196083690 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 196083690 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 196083690 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 196083690 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030495 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.030495 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030495 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.030495 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030495 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.030495 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10273.874329 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10273.874329 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10273.874329 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10273.874329 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10273.874329 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10273.874329 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 8139519 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 7 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 675212 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.054761 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 411371773 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 411371773 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 196754052 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 196754052 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 196754052 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 196754052 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 196754052 # number of overall hits +system.cpu1.icache.overall_hits::total 196754052 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 6061167 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 6061167 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 6061167 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 6061167 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 6061167 # number of overall misses +system.cpu1.icache.overall_misses::total 6061167 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 63767181305 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 63767181305 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 63767181305 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 63767181305 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 63767181305 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 63767181305 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 202815219 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 202815219 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 202815219 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 202815219 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 202815219 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 202815219 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029885 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.029885 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029885 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.029885 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029885 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.029885 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10520.611180 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10520.611180 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10520.611180 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10520.611180 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10520.611180 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10520.611180 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 8678948 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 76 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 693947 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.506644 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 38 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 311064 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 311064 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 311064 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 311064 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 311064 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 311064 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5668523 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5668523 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5668523 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5668523 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5668523 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5668523 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 52921398555 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 52921398555 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 52921398555 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 52921398555 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 52921398555 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 52921398555 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6131248 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6131248 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6131248 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6131248 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028909 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028909 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028909 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.028909 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028909 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.028909 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9336.011966 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9336.011966 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9336.011966 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9336.011966 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9336.011966 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9336.011966 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 319831 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 319831 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 319831 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 319831 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 319831 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 319831 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5741336 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5741336 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5741336 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5741336 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5741336 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5741336 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable +system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable +system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses +system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 54923658725 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 54923658725 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 54923658725 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 54923658725 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 54923658725 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 54923658725 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6151998 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6151998 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6151998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6151998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028308 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028308 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028308 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.028308 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028308 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.028308 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9566.355065 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9566.355065 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9566.355065 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9566.355065 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9566.355065 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9566.355065 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91820.865672 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 91820.865672 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91820.865672 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 91820.865672 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6924956 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7115948 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 165163 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7332494 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7535643 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 175627 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 889052 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2136964 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13504.433199 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 11477625 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2153158 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 5.330600 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9723406338993 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5663.402040 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 81.532496 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 97.953204 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3050.006780 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3697.963934 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 913.574746 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.345667 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004976 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005979 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.186158 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225706 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055760 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.824245 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1347 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14805 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 237 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 720 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 360 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1369 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5255 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5224 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2823 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.082214 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002563 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903625 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 249290678 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 249290678 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 527309 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 181952 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5073722 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2781354 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 8564337 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3264689 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3264689 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 166971 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 166971 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 66098 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 66098 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 34177 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 34177 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 845253 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 845253 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 527309 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 181952 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 5073722 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3626607 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 9409590 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 527309 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 181952 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 5073722 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3626607 # number of overall hits -system.cpu1.l2cache.overall_hits::total 9409590 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12633 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9907 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 594787 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 963518 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1580845 # number of ReadReq misses -system.cpu1.l2cache.Writeback_misses::writebacks 14 # number of Writeback misses -system.cpu1.l2cache.Writeback_misses::total 14 # number of Writeback misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 249743 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 249743 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 139723 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 139723 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 161589 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 161589 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 15 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 15 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 245189 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 245189 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12633 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9907 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 594787 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1208707 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1826034 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12633 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9907 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 594787 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1208707 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1826034 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 491583485 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 427969129 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 16999057098 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 31500874862 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 49419484574 # number of ReadReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 236089966 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 236089966 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3003661220 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 3003661220 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3342420381 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3342420381 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4508496 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4508496 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11309728111 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 11309728111 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 491583485 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 427969129 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16999057098 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 42810602973 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 60729212685 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 491583485 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 427969129 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16999057098 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 42810602973 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 60729212685 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 539942 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 191859 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5668509 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3744872 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 10145182 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3264703 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3264703 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 416714 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::total 416714 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 205821 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 205821 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195766 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 195766 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 15 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 15 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1090442 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1090442 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 539942 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 191859 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 5668509 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4835314 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 11235624 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 539942 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 191859 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 5668509 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4835314 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 11235624 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023397 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.051637 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.104928 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.257290 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.155822 # miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000004 # miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_miss_rate::total 0.000004 # miss rate for Writeback accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.599315 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.599315 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.678857 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.678857 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.825419 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.825419 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.prefetcher.pfSpanPage 929621 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2299794 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13092.282613 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 11932680 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2315440 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 5.153526 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9714628416493 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5051.662856 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 84.315143 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 91.749127 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3269.093236 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3705.071376 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 890.390874 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.308329 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.005146 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005600 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199530 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.226140 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.054345 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.799090 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1406 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 105 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14135 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 76 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 267 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 643 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 420 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 73 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 703 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4677 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4917 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3606 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.085815 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006409 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.862732 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 260544625 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 260544625 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 585527 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 176354 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5103092 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 2955317 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 8820290 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 3504868 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 3504868 # number of Writeback hits +system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 166502 # number of WriteInvalidateReq hits +system.cpu1.l2cache.WriteInvalidateReq_hits::total 166502 # number of WriteInvalidateReq hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 71993 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 71993 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 35298 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 35298 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 907237 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 907237 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 585527 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 176354 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 5103092 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3862554 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 9727527 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 585527 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 176354 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 5103092 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3862554 # number of overall hits +system.cpu1.l2cache.overall_hits::total 9727527 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 13010 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9568 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 638215 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 1012370 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 1673163 # number of ReadReq misses +system.cpu1.l2cache.Writeback_misses::writebacks 6 # number of Writeback misses +system.cpu1.l2cache.Writeback_misses::total 6 # number of Writeback misses +system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 277800 # number of WriteInvalidateReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::total 277800 # number of WriteInvalidateReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 139883 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 139883 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 160055 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 160055 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 13 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 13 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 249549 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 249549 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 13010 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9568 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 638215 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1261919 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1922712 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 13010 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9568 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 638215 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1261919 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1922712 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 512958208 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 430734867 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 18770053212 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 34728720424 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 54442466711 # number of ReadReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 206094146 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 206094146 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3019471858 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 3019471858 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3326642430 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3326642430 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3578499 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3578499 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12555468370 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 12555468370 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 512958208 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 430734867 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 18770053212 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 47284188794 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 66997935081 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 512958208 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 430734867 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 18770053212 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 47284188794 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 66997935081 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 598537 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 185922 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5741307 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3967687 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 10493453 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 3504874 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 3504874 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 444302 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::total 444302 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 211876 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 211876 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195353 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 195353 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 13 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 13 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1156786 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1156786 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 598537 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 185922 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 5741307 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 5124473 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 11650239 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 598537 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 185922 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 5741307 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 5124473 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 11650239 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021736 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.051462 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.111162 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.255154 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.159448 # miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.625250 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.625250 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.660212 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.660212 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.819312 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.819312 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.224853 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.224853 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023397 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.051637 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.104928 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.249975 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.162522 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023397 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.051637 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.104928 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.249975 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.162522 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 38912.648223 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 43198.660442 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 28580.075049 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32693.602882 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31261.435861 # average ReadReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 945.331665 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 945.331665 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21497.256858 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21497.256858 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20684.702430 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20684.702430 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 300566.400000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 300566.400000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 46126.572199 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 46126.572199 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 38912.648223 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 43198.660442 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28580.075049 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35418.511660 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 33257.438079 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 38912.648223 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 43198.660442 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28580.075049 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35418.511660 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 33257.438079 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 100 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.215726 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.215726 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021736 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.051462 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.111162 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.246253 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.165036 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021736 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.051462 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.111162 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.246253 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.165036 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39427.994466 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 45018.276233 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29410.235128 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 34304.375302 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32538.650873 # average ReadReq miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 741.879575 # average WriteInvalidateReq miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 741.879575 # average WriteInvalidateReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21585.695603 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21585.695603 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20784.370560 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20784.370560 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 275269.153846 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 275269.153846 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50312.637478 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50312.637478 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39427.994466 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 45018.276233 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29410.235128 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37470.066458 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 34845.538532 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39427.994466 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 45018.276233 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29410.235128 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37470.066458 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 34845.538532 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 20 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 25 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 6.666667 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 969171 # number of writebacks -system.cpu1.l2cache.writebacks::total 969171 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 3 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 194 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 3035 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 3232 # number of ReadReq MSHR hits -system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 1 # number of WriteInvalidateReq MSHR hits -system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 1 # number of WriteInvalidateReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 16069 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 16069 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 3 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 194 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 19104 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 19301 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 3 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 194 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 19104 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 19301 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12630 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9713 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 594787 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 960483 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 1577613 # number of ReadReq MSHR misses -system.cpu1.l2cache.Writeback_mshr_misses::writebacks 14 # number of Writeback MSHR misses -system.cpu1.l2cache.Writeback_mshr_misses::total 14 # number of Writeback MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 688186 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 688186 # number of HardPFReq MSHR misses -system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 249742 # number of WriteInvalidateReq MSHR misses -system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 249742 # number of WriteInvalidateReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 139723 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 139723 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 161589 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 161589 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 15 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 15 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 229120 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 229120 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12630 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9713 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 594787 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1189603 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 1806733 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12630 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9713 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 594787 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1189603 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 688186 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 2494919 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 408647025 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 358018255 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 13119737402 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 25025673719 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 38912076401 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 36938967043 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 36938967043 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 8412735671 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 8412735671 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2759951656 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2759951656 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2380296086 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2380296086 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3864996 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3864996 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7878318651 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7878318651 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 408647025 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 358018255 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 13119737402 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 32903992370 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 46790395052 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 408647025 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 358018255 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 13119737402 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 32903992370 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 36938967043 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 83729362095 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5602750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 639050750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 644653500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 738464498 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 738464498 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 5602750 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1377515248 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1383117998 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023391 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050626 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.104928 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.256480 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.155504 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000004 # mshr miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000004 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.writebacks::writebacks 1059677 # number of writebacks +system.cpu1.l2cache.writebacks::total 1059677 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 6 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 183 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 3574 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 3763 # number of ReadReq MSHR hits +system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 5 # number of WriteInvalidateReq MSHR hits +system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 5 # number of WriteInvalidateReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 19034 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 19034 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 6 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 183 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 22608 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 22797 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 6 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 183 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 22608 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 22797 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 13004 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9385 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 638215 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 1008796 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 1669400 # number of ReadReq MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::writebacks 6 # number of Writeback MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::total 6 # number of Writeback MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 738806 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 738806 # number of HardPFReq MSHR misses +system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 277795 # number of WriteInvalidateReq MSHR misses +system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 277795 # number of WriteInvalidateReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 139883 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 139883 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 160055 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 160055 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 13 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 13 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 230515 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 230515 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 13004 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9385 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 638215 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1239311 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 1899915 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 13004 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9385 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 638215 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1239311 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 738806 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 2638721 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 7126 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 7193 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7600 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7600 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 14726 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14793 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 427470062 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 361612807 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 14605198288 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 27880753226 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 43275034383 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 44447581689 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 44447581689 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 9533570164 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 9533570164 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2794262081 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2794262081 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2375248051 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2375248051 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3051999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3051999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8594281659 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8594281659 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 427470062 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 361612807 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14605198288 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 36475034885 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 51869316042 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 427470062 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 361612807 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14605198288 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 36475034885 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 44447581689 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 96316897731 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5626000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 774397000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 780023000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 938365000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 938365000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 5626000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712762000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1718388000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021726 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050478 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.111162 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.254253 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.159090 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.599313 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.599313 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.678857 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.678857 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.825419 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.825419 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.625239 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.625239 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.660212 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.660212 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.819312 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.819312 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.210117 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.210117 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023391 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050626 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.104928 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.246024 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.160804 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023391 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050626 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.104928 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.246024 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.199272 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.199272 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021726 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050478 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.111162 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.241842 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.163079 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021726 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050478 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.111162 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.241842 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.222054 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32355.267221 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 36859.698857 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22057.875175 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26055.301051 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24665.159580 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53675.847871 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 53675.847871 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 33685.706333 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33685.706333 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19753.023167 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19753.023167 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14730.557686 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14730.557686 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 257666.400000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 257666.400000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34385.119811 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34385.119811 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32355.267221 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 36859.698857 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22057.875175 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27659.641385 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25897.791789 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32355.267221 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 36859.698857 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22057.875175 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27659.641385 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53675.847871 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33559.952085 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.226495 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32872.197939 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38530.933085 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22884.448482 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 27637.652435 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25922.507717 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 60161.370764 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 60161.370764 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 34318.724829 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34318.724829 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19975.708850 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19975.708850 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14840.199000 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14840.199000 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 234769.153846 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 234769.153846 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37282.960584 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37282.960584 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32872.197939 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38530.933085 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22884.448482 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29431.704298 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27300.861376 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32872.197939 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38530.933085 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22884.448482 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29431.704298 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 60161.370764 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36501.357184 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83970.149254 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 108672.046029 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 108441.957459 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 123469.078947 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 123469.078947 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83970.149254 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 116308.705691 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 116162.238897 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 12589327 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10390309 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 6277 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 6277 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3264703 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 969369 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1138126 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 416714 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 449544 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 355754 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 472453 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 124 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 208 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1246255 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1097731 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11337166 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14775069 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 416528 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1186159 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 27714922 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 362785648 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 551966772 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1534872 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4319536 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 920606828 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4866324 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 20006897 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 3.227379 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.419140 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 13189135 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10749038 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 38779 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 7600 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3504874 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 1040151 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 17 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1162830 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 444302 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 468816 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 354419 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 478843 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 143 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1323230 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1164313 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11482776 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15667685 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 405853 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1309392 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 28865706 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 367444720 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 587773064 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1487376 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4788296 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 961493456 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5242184 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 21082310 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.277260 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.447646 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 15457744 77.26% 77.26% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 4549153 22.74% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 15237020 72.27% 72.27% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 5845290 27.73% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 20006897 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 11420254845 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 21082310 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 12037419620 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 196151972 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 200301486 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8513145317 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8624197196 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7729223292 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 8185098674 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 225599484 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 220844820 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 647309419 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 711986885 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40298 # Transaction distribution -system.iobus.trans_dist::ReadResp 40298 # Transaction distribution -system.iobus.trans_dist::WriteReq 136633 # Transaction distribution -system.iobus.trans_dist::WriteResp 29905 # Transaction distribution +system.iobus.trans_dist::ReadReq 40346 # Transaction distribution +system.iobus.trans_dist::ReadResp 40346 # Transaction distribution +system.iobus.trans_dist::WriteReq 136632 # Transaction distribution +system.iobus.trans_dist::WriteResp 29904 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47726 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47732 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2863,13 +2900,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122608 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231174 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231174 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122614 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231262 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353862 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47746 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47752 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2884,13 +2921,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155738 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338712 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155744 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339064 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36251000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496894 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36253000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2918,71 +2955,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 607686128 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607574888 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92706000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92713000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148478785 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148591827 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115568 # number of replacements -system.iocache.tags.tagsinuse 11.294495 # Cycle average of tags in use +system.iocache.tags.replacements 115612 # number of replacements +system.iocache.tags.tagsinuse 11.304105 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115584 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115628 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9116942023000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.849176 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.445319 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240573 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.465332 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705906 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9116941730000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.838498 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.465607 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239906 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466600 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706507 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040640 # Number of tag accesses -system.iocache.tags.data_accesses 1040640 # Number of data accesses +system.iocache.tags.tag_accesses 1041036 # Number of tag accesses +system.iocache.tags.data_accesses 1041036 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8859 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8896 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8903 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8940 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8859 # number of demand (read+write) misses -system.iocache.demand_misses::total 8899 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8903 # number of demand (read+write) misses +system.iocache.demand_misses::total 8943 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8859 # number of overall misses -system.iocache.overall_misses::total 8899 # number of overall misses +system.iocache.overall_misses::realview.ide 8903 # number of overall misses +system.iocache.overall_misses::total 8943 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1636729691 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1641925191 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1642618319 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1647813819 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19864825652 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19864825652 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19871992742 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19871992742 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1636729691 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1642294191 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1642618319 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1648182819 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1636729691 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1642294191 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1642618319 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1648182819 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8859 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8896 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8903 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8940 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8859 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8899 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8903 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8943 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8859 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8899 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8903 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8943 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2997,54 +3034,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 184753.323287 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 184568.928844 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 184501.664495 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 184319.219128 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186125.718200 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 186125.718200 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186192.871055 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 186192.871055 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 184753.323287 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 184548.172941 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 184501.664495 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 184298.649111 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 184753.323287 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 184548.172941 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 112586 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 184501.664495 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 184298.649111 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 111619 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16234 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16154 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.935198 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.909682 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8859 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8896 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8903 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8940 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8859 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8899 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8903 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8943 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8859 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8899 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8903 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8943 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1174861151 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1178131651 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1178449871 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1181720371 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14314859762 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14314859762 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14322034844 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14322034844 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1174861151 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1178344651 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1178449871 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1181933371 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1174861151 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1178344651 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1178449871 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1181933371 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3059,632 +3096,639 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132617.806863 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 132433.863647 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132365.480288 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 132183.486689 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134124.688573 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134124.688573 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134191.916311 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134191.916311 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 132617.806863 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 132413.153276 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 132365.480288 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 132162.962205 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 132617.806863 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 132413.153276 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 132365.480288 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 132162.962205 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1377424 # number of replacements -system.l2c.tags.tagsinuse 64428.474571 # Cycle average of tags in use -system.l2c.tags.total_refs 4496154 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1437791 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.127126 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 3245891000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 17415.702003 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 13.555673 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 13.071281 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4037.254225 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5874.753333 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3721.003209 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 357.239386 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 523.990627 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2776.282665 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11847.144423 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17848.477746 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.265743 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000207 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000199 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.061604 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.089642 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.056778 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005451 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.007995 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.042363 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.180773 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.272346 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.983101 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10320 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 289 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49758 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 29 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 178 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 260 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9845 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 285 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2371 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4137 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 42888 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.157471 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.004410 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.759247 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 59850638 # Number of tag accesses -system.l2c.tags.data_accesses 59850638 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6609 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5089 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 570808 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 585040 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 302541 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6014 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4366 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 555272 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 535796 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 269863 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2841398 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2358990 # number of Writeback hits -system.l2c.Writeback_hits::total 2358990 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 147857 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 120344 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 268201 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 33100 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 25345 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 58445 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6120 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5439 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 11559 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 54193 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 49865 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 104058 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6609 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5089 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 570808 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 639233 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 302541 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6014 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4366 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 555272 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 585661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 269863 # number of demand (read+write) hits -system.l2c.demand_hits::total 2945456 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6609 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5089 # number of overall hits -system.l2c.overall_hits::cpu0.inst 570808 # number of overall hits -system.l2c.overall_hits::cpu0.data 639233 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 302541 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6014 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4366 # number of overall hits -system.l2c.overall_hits::cpu1.inst 555272 # number of overall hits -system.l2c.overall_hits::cpu1.data 585661 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 269863 # number of overall hits -system.l2c.overall_hits::total 2945456 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1186 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 952 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 65177 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 129551 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 203502 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2616 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2569 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 39512 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 114014 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 227886 # number of ReadReq misses -system.l2c.ReadReq_misses::total 786965 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 437920 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 120290 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 558210 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 45660 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 46311 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 91971 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 9121 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 8967 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 18088 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 74847 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 51643 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 126490 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1186 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 952 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 65177 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 204398 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 203502 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2616 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2569 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 39512 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 165657 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 227886 # number of demand (read+write) misses -system.l2c.demand_misses::total 913455 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1186 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 952 # number of overall misses -system.l2c.overall_misses::cpu0.inst 65177 # number of overall misses -system.l2c.overall_misses::cpu0.data 204398 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 203502 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2616 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2569 # number of overall misses -system.l2c.overall_misses::cpu1.inst 39512 # number of overall misses -system.l2c.overall_misses::cpu1.data 165657 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 227886 # number of overall misses -system.l2c.overall_misses::total 913455 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 111035273 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 90655016 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 5679579933 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 12742001076 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 29753788309 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 236867766 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 230645249 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 3413499724 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 10938718079 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 32443014097 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 95639804522 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 58893966 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 45248781 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 104142747 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 276167379 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 268661108 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 544828487 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 46772512 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 48520461 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 95292973 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6912544305 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4650422855 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 11562967160 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 111035273 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 90655016 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 5679579933 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 19654545381 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 29753788309 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 236867766 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 230645249 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 3413499724 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 15589140934 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 32443014097 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 107202771682 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 111035273 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 90655016 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 5679579933 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 19654545381 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 29753788309 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 236867766 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 230645249 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 3413499724 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 15589140934 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 32443014097 # number of overall miss cycles -system.l2c.overall_miss_latency::total 107202771682 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 7795 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 6041 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 635985 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 714591 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 506043 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 8630 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6935 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 594784 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 649810 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 497749 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 3628363 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 2358990 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2358990 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 585777 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 240634 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 826411 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 78760 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 71656 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 150416 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 15241 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 14406 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 29647 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 129040 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 101508 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 230548 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 7795 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6041 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 635985 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 843631 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 506043 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 8630 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6935 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 594784 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 751318 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 497749 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3858911 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 7795 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6041 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 635985 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 843631 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 506043 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 8630 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6935 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 594784 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 751318 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 497749 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3858911 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.152149 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.157590 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.102482 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.181294 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.402144 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.303129 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.370440 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.066431 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.175457 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.457833 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.216893 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.747588 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.499888 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.675463 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.579736 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.646296 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.611444 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.598452 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.622449 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.610112 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.580029 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.508758 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.548649 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.152149 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.157590 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.102482 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.242284 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.402144 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.303129 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.370440 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.066431 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.220489 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.457833 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.236713 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.152149 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.157590 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.102482 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.242284 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.402144 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.303129 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.370440 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.066431 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.220489 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.457833 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.236713 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 93621.646712 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 95225.857143 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 87140.861546 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 98355.096263 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 146208.825019 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 90545.782110 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89780.166991 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 86391.469022 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 95941.885023 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 142365.104030 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 121529.934015 # average ReadReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 134.485673 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 376.164112 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::total 186.565534 # average WriteInvalidateReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6048.343824 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5801.237460 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 5923.916093 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5128.002631 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5411.002676 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 5268.297932 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 92355.662952 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 90049.432740 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 91414.081429 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 93621.646712 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 95225.857143 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 87140.861546 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 96158.207913 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 146208.825019 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90545.782110 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89780.166991 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 86391.469022 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 94104.933290 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 142365.104030 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 117359.663784 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 93621.646712 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 95225.857143 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 87140.861546 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 96158.207913 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 146208.825019 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90545.782110 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89780.166991 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 86391.469022 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 94104.933290 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 142365.104030 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 117359.663784 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 11943 # number of cycles access was blocked +system.l2c.tags.replacements 1633733 # number of replacements +system.l2c.tags.tagsinuse 64442.276820 # Cycle average of tags in use +system.l2c.tags.total_refs 4812382 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1694389 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.840187 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 3265660000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 17567.436669 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 345.231271 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 471.940947 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4509.499901 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 13049.127195 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 17952.495565 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 52.864907 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 70.453845 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2659.379343 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 4127.659130 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3636.188048 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.268058 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.005268 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.007201 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.068810 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.199114 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.273933 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000807 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.001075 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.040579 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.062983 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.055484 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.983311 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10750 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 247 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49659 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 1276 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 687 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 8787 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 238 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2518 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4806 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 41987 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.164032 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003769 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.757736 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 65067124 # Number of tag accesses +system.l2c.tags.data_accesses 65067124 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6771 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4585 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 583685 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 633203 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 298139 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 6546 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 4209 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 589652 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 570600 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 281047 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2978437 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 2596817 # number of Writeback hits +system.l2c.Writeback_hits::total 2596817 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 138250 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 130696 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 268946 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 34228 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 26005 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 60233 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 6128 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 6125 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 12253 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 55044 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 49984 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 105028 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6771 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4585 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 583685 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 688247 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 298139 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6546 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4209 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 589652 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 620584 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 281047 # number of demand (read+write) hits +system.l2c.demand_hits::total 3083465 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6771 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4585 # number of overall hits +system.l2c.overall_hits::cpu0.inst 583685 # number of overall hits +system.l2c.overall_hits::cpu0.data 688247 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 298139 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6546 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4209 # number of overall hits +system.l2c.overall_hits::cpu1.inst 589652 # number of overall hits +system.l2c.overall_hits::cpu1.data 620584 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 281047 # number of overall hits +system.l2c.overall_hits::total 3083465 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 2623 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2323 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 65378 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 160715 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 295001 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 2679 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 2566 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 48562 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 132475 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 268900 # number of ReadReq misses +system.l2c.ReadReq_misses::total 981222 # number of ReadReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.data 444602 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.data 139009 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::total 583611 # number of WriteInvalidateReq misses +system.l2c.UpgradeReq_misses::cpu0.data 48239 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 46690 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 94929 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 9164 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 9498 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 18662 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 83588 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 58117 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 141705 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2623 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2323 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 65378 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 244303 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 295001 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 2679 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2566 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 48562 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 190592 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 268900 # number of demand (read+write) misses +system.l2c.demand_misses::total 1122927 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2623 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2323 # number of overall misses +system.l2c.overall_misses::cpu0.inst 65378 # number of overall misses +system.l2c.overall_misses::cpu0.data 244303 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 295001 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 2679 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2566 # number of overall misses +system.l2c.overall_misses::cpu1.inst 48562 # number of overall misses +system.l2c.overall_misses::cpu1.data 190592 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 268900 # number of overall misses +system.l2c.overall_misses::total 1122927 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 244393039 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 217850761 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 5706510559 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 16014013375 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 43733676321 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 249111297 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 239093772 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 4255255686 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 13145453309 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 39841128623 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 123646486742 # number of ReadReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 51997674 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 39165941 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::total 91163615 # number of WriteInvalidateReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 308199351 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 263365265 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 571564616 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 47104504 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 54418277 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 101522781 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 7762052110 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5404141951 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 13166194061 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 244393039 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 217850761 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 5706510559 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 23776065485 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 43733676321 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 249111297 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 239093772 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 4255255686 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 18549595260 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 39841128623 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 136812680803 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 244393039 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 217850761 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 5706510559 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 23776065485 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 43733676321 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 249111297 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 239093772 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 4255255686 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 18549595260 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 39841128623 # number of overall miss cycles +system.l2c.overall_miss_latency::total 136812680803 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 9394 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 6908 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 649063 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 793918 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 593140 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 9225 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6775 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 638214 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 703075 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 549947 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 3959659 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 2596817 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 2596817 # number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.data 582852 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.data 269705 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 852557 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 82467 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 72695 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 155162 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 15292 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 15623 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 30915 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 138632 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 108101 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246733 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 9394 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6908 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 649063 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 932550 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 593140 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 9225 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6775 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 638214 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 811176 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 549947 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 4206392 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 9394 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6908 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 649063 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 932550 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 593140 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 9225 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6775 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 638214 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 811176 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 549947 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 4206392 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.279221 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.336277 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.100727 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.202433 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.497355 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.290407 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.378745 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.076090 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.188422 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.488956 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.247805 # miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.762804 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.515411 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::total 0.684542 # miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.584949 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.642273 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.611806 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.599268 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.607950 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.603655 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.602949 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.537618 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.574325 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.279221 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.336277 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.100727 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.261973 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.497355 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.290407 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.378745 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.076090 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.234958 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.488956 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.266957 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.279221 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.336277 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.100727 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.261973 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.497355 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.290407 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.378745 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.076090 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.234958 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.488956 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.266957 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 93173.099123 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 93779.922944 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 87284.875019 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 99642.307034 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 148249.247701 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 92986.673012 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 93177.619641 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 87625.214901 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 99229.690953 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 148163.364161 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 126012.754241 # average ReadReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 116.953307 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 281.751117 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::total 156.206129 # average WriteInvalidateReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6389.007877 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5640.721032 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 6020.969525 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5140.168485 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5729.445883 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 5440.080431 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 92860.842585 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 92987.283428 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 92912.699347 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 93173.099123 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 93779.922944 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 87284.875019 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 97322.036508 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 148249.247701 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92986.673012 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 93177.619641 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 87625.214901 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 97326.200785 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 148163.364161 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 121835.774545 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 93173.099123 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 93779.922944 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 87284.875019 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 97322.036508 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 148249.247701 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92986.673012 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 93177.619641 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 87625.214901 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 97326.200785 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 148163.364161 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 121835.774545 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 14255 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 84 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 149 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 142.178571 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 95.671141 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1067007 # number of writebacks -system.l2c.writebacks::total 1067007 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.inst 133 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 17 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 90 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 20 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 264 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.dtb.walker 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 133 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 17 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 90 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 20 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 264 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.dtb.walker 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 133 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 17 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 90 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 20 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 264 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1184 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 952 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 65044 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 129534 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 203500 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2616 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2569 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 39422 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 113994 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 227886 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 786701 # number of ReadReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 437920 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 120290 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::total 558210 # number of WriteInvalidateReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 45660 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 46311 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 91971 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9121 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 8967 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 18088 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 74847 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 51643 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 126490 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 1184 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 952 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 65044 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 204381 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 203500 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 2616 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 2569 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 39422 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 165637 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 227886 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 913191 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 1184 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 952 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 65044 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 204381 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 203500 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 2616 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 2569 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 39422 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 165637 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 227886 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 913191 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 95681979 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 78660484 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 4853701817 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 11124617158 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 27259941357 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 203927234 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 198329749 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2912777274 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 9514272921 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 29643980025 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 85885889998 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 17416176424 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 3960645719 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::total 21376822143 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 814816958 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 825298541 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 1640115499 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 162191592 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 159645428 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 321837020 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5979693683 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4008215143 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 9987908826 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 95681979 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 78660484 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 4853701817 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 17104310841 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 27259941357 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 203927234 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 198329749 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 2912777274 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 13522488064 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 29643980025 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 95873798824 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 95681979 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 78660484 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 4853701817 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 17104310841 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 27259941357 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 203927234 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 198329749 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 2912777274 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 13522488064 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 29643980025 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 95873798824 # number of overall MSHR miss cycles +system.l2c.writebacks::writebacks 1263454 # number of writebacks +system.l2c.writebacks::total 1263454 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 235 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 55 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 249 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 31 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 570 # number of ReadReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0.data 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 235 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 56 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 249 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 31 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 571 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 235 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 56 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 249 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 31 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 571 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2623 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2323 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 65143 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 160660 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 295001 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2679 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2566 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 48313 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 132444 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 268900 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 980652 # number of ReadReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 444602 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 139009 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::total 583611 # number of WriteInvalidateReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 48239 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 46690 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 94929 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9164 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 9498 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 18662 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 83587 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 58117 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 141704 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 2623 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2323 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 65143 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 244247 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 295001 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 2679 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 2566 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 48313 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 190561 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 268900 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 1122356 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 2623 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 2323 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 65143 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 244247 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 295001 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 2679 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 2566 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 48313 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 190561 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 268900 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 1122356 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31767 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 7124 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 60252 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 31179 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 7600 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 38779 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 62946 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 14724 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 99031 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 211330935 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 188610731 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 4870726193 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14004672382 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 40114542013 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 215342695 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 206771700 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3630382313 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 11489733691 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 36539403375 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 111471516028 # number of ReadReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 17621248292 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 4582826059 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::total 22204074351 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 860739549 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 832018870 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1692758419 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 163139115 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 169125946 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 332265061 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6720926126 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4681733537 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 11402659663 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 211330935 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 188610731 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 4870726193 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 20725598508 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 40114542013 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 215342695 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 206771700 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3630382313 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 16171467228 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 36539403375 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 122874175691 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 211330935 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 188610731 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 4870726193 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 20725598508 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 40114542013 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 215342695 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 206771700 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 3630382313 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 16171467228 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 36539403375 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 122874175691 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1285623000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4853989000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4264250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 516390251 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6660266501 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4658794041 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 621932502 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5280726543 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4741851751 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4289000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 634532000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6666295751 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4487720539 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 797339000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5285059539 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1285623000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9512783041 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4264250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1138322753 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 11940993044 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.151892 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.157590 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.102273 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.181270 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.402140 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.303129 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.370440 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.066280 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.175427 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.457833 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.216820 # mshr miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.747588 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.499888 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.675463 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.579736 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.646296 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.611444 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.598452 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.622449 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.610112 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.580029 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.508758 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.548649 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.151892 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.157590 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102273 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.242264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.402140 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.303129 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.370440 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.066280 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.220462 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.457833 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.236645 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.151892 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.157590 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102273 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.242264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.402140 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.303129 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.370440 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.066280 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.220462 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.457833 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.236645 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 80812.482264 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 82626.558824 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74621.822413 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 85881.831473 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133955.485784 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77953.835627 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77201.147917 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 73887.100452 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 83462.927180 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130082.497499 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 109172.214092 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39770.223840 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32925.810283 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 38295.304891 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17845.312265 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17820.788603 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17832.963641 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17782.215985 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17803.660979 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17792.847192 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79892.229254 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 77613.909784 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 78962.043055 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80812.482264 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82626.558824 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74621.822413 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83688.360665 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133955.485784 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77953.835627 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77201.147917 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73887.100452 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 81639.295954 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130082.497499 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 104987.673799 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80812.482264 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82626.558824 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74621.822413 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83688.360665 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133955.485784 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77953.835627 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77201.147917 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73887.100452 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 81639.295954 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130082.497499 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 104987.673799 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9229572290 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4289000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1431871000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 11951355290 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.279221 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.336277 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.100365 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.202363 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.497355 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.290407 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.378745 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.075700 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.188378 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.488956 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.247661 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.762804 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.515411 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.684542 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.584949 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.642273 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.611806 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.599268 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.607950 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.603655 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.602942 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.537618 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.574321 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.279221 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.336277 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.100365 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.261913 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.497355 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.290407 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.378745 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.075700 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.234919 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.488956 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.266822 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.279221 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.336277 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.100365 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.261913 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.497355 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.290407 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.378745 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.075700 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.234919 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.488956 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.266822 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 80568.408311 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 81192.738269 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74769.755661 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 87169.627673 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135981.037396 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 80381.745054 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 80581.332814 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75142.970070 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 86751.636095 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135884.728059 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 113670.819035 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39633.758490 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32967.837039 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 38046.017555 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17843.229524 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17820.065753 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17831.836625 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17802.173178 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17806.479891 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17804.365073 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80406.356563 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 80557.040745 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 80468.156601 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80568.408311 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 81192.738269 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74769.755661 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84855.079113 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135981.037396 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80381.745054 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 80581.332814 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75142.970070 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 84862.417955 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135884.728059 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 109478.788986 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80568.408311 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 81192.738269 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74769.755661 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84855.079113 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135981.037396 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80381.745054 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 80581.332814 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75142.970070 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 84862.417955 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135884.728059 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 109478.788986 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60374.894336 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 149269.737495 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64014.925373 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 89069.623807 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 110640.240175 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 143934.075467 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 104913.026316 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 136286.638103 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60374.894336 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 146626.827598 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64014.925373 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 97247.419180 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 120682.970888 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 855568 # Transaction distribution -system.membus.trans_dist::ReadResp 855568 # Transaction distribution -system.membus.trans_dist::WriteReq 38542 # Transaction distribution -system.membus.trans_dist::WriteResp 38542 # Transaction distribution -system.membus.trans_dist::Writeback 1173701 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 661649 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 661649 # Transaction distribution -system.membus.trans_dist::UpgradeReq 438223 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 309934 # Transaction distribution -system.membus.trans_dist::UpgradeResp 117397 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution -system.membus.trans_dist::ReadExReq 139893 # Transaction distribution -system.membus.trans_dist::ReadExResp 122444 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122608 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1049844 # Transaction distribution +system.membus.trans_dist::ReadResp 1049844 # Transaction distribution +system.membus.trans_dist::WriteReq 38779 # Transaction distribution +system.membus.trans_dist::WriteResp 38779 # Transaction distribution +system.membus.trans_dist::Writeback 1370148 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 687460 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 687460 # Transaction distribution +system.membus.trans_dist::UpgradeReq 443336 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 306800 # Transaction distribution +system.membus.trans_dist::UpgradeResp 120479 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution +system.membus.trans_dist::ReadExReq 155568 # Transaction distribution +system.membus.trans_dist::ReadExResp 137698 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122614 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4925384 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5074464 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5410374 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155738 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27506 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5597252 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5747450 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335773 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335773 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6083223 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155744 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52788 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 162304200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 162513298 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14098112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14098112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 176611410 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 651055 # Total snoops (count) -system.membus.snoop_fanout::samples 3600660 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55012 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 189917440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 190128768 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14086528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14086528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 204215296 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 650589 # Total snoops (count) +system.membus.snoop_fanout::samples 4133180 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3600660 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4133180 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3600660 # Request fanout histogram -system.membus.reqLayer0.occupancy 98274497 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4133180 # Request fanout histogram +system.membus.reqLayer0.occupancy 98178497 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22081484 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22861986 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 10699049257 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 12090027529 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5725496770 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6852398799 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 151866715 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 152088673 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3728,49 +3772,49 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 4566673 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4559437 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38542 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38542 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2358990 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 933261 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 826411 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 489333 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 321493 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 810826 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 208 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 208 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 288168 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 288168 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7677415 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6169065 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 13846480 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255017262 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 196496484 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 451513746 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1675443 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8934179 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012956 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.113084 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 4896771 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4889534 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38779 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38779 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2596817 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 959438 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 852557 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 496684 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 319053 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 815737 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 143 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 143 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 305200 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 305200 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8223954 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6618870 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 14842824 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 276507544 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 214143912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 490651456 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1673717 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9649223 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012003 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.108901 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 8818430 98.70% 98.70% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115749 1.30% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 9533399 98.80% 98.80% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115824 1.20% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8934179 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 7984163233 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 9649223 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8593373447 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2491500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2556000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4301185209 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4622045284 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3898685571 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4138277748 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13668 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 13964 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5222 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 5482 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index b4cf0acf8..066bd26f3 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.320469 # Nu sim_ticks 51320468905000 # Number of ticks simulated final_tick 51320468905000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112338 # Simulator instruction rate (inst/s) -host_op_rate 131995 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6738935517 # Simulator tick rate (ticks/s) -host_mem_usage 657468 # Number of bytes of host memory used -host_seconds 7615.52 # Real time elapsed on the host +host_inst_rate 115752 # Simulator instruction rate (inst/s) +host_op_rate 136007 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6943747154 # Simulator tick rate (ticks/s) +host_mem_usage 724128 # Number of bytes of host memory used +host_seconds 7390.89 # Real time elapsed on the host sim_insts 855512158 # Number of instructions simulated sim_ops 1005211605 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1001,6 +1001,12 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 7197092 system.cpu.dcache.demand_mshr_misses::total 7197092 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 8381734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 8381734 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33661 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33661 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33682 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33682 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67343 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67343 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 73626554579 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 73626554579 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 56871439750 # number of WriteReq MSHR miss cycles @@ -1055,12 +1061,12 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18132.044766 system.cpu.dcache.demand_avg_mshr_miss_latency::total 18132.044766 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17902.025238 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 17902.025238 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170713.451769 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170713.451769 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 167130.276349 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 167130.276349 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168921.305377 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168921.305377 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 15070815 # number of replacements system.cpu.icache.tags.tagsinuse 511.953323 # Cycle average of tags in use @@ -1134,6 +1140,10 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15071548 system.cpu.icache.demand_mshr_misses::total 15071548 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15071548 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15071548 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable +system.cpu.icache.ReadReq_mshr_uncacheable::total 21295 # number of ReadReq MSHR uncacheable +system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 21295 # number of overall MSHR uncacheable misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179787086612 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 179787086612 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179787086612 # number of demand (read+write) MSHR miss cycles @@ -1156,10 +1166,10 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11928.906481 system.cpu.icache.demand_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74431.051890 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74431.051890 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74431.051890 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74431.051890 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1159288 # number of replacements system.cpu.l2cache.tags.tagsinuse 65272.997993 # Cycle average of tags in use @@ -1371,6 +1381,14 @@ system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3020 system.cpu.l2cache.overall_mshr_misses::cpu.inst 84629 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 667358 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 758173 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33661 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54956 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33682 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33682 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67343 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88638 # number of overall MSHR uncacheable misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 237171251 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 225518000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6085544162 # number of ReadReq MSHR miss cycles @@ -1448,14 +1466,14 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59931.028410 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156696.577642 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 119200.719667 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153989.267264 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153989.267264 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59931.028410 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155342.500334 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 132420.195063 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 23293786 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 23285542 # Transaction distribution @@ -1480,19 +1498,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_si system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6472392 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 2085922949 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 583028 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 34186904 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.003382 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.058057 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 34275542 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.049559 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.217032 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 34071281 99.66% 99.66% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 115623 0.34% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 32576878 95.04% 95.04% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1698664 4.96% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 34186904 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 34275542 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 25901169608 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 909000 # Layer occupancy (ticks) @@ -1763,17 +1779,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14066304 system.membus.pkt_size_system.iocache.mem_side::total 14066304 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 157288413 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 3023 # Total snoops (count) -system.membus.snoop_fanout::samples 2488136 # Request fanout histogram +system.membus.snoop_fanout::samples 2576774 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2488136 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2576774 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2488136 # Request fanout histogram +system.membus.snoop_fanout::total 2576774 # Request fanout histogram system.membus.reqLayer0.occupancy 104078000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks) diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt index f7646988d..347570290 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111153 # Nu sim_ticks 51111152682000 # Number of ticks simulated final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 929959 # Simulator instruction rate (inst/s) -host_op_rate 1092854 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48276126697 # Simulator tick rate (ticks/s) -host_mem_usage 712572 # Number of bytes of host memory used -host_seconds 1058.73 # Real time elapsed on the host +host_inst_rate 1198732 # Simulator instruction rate (inst/s) +host_op_rate 1408707 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62228718243 # Simulator tick rate (ticks/s) +host_mem_usage 717580 # Number of bytes of host memory used +host_seconds 821.34 # Real time elapsed on the host sim_insts 984570519 # Number of instructions simulated sim_ops 1157031967 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -569,19 +569,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_si system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 2238699610 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 116338 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 36147883 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.003196 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.056441 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 36258168 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.034933 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.183610 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 36032362 99.68% 99.68% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 34991563 96.51% 96.51% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1266605 3.49% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 36147883 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 36258168 # Request fanout histogram system.iobus.trans_dist::ReadReq 40246 # Transaction distribution system.iobus.trans_dist::ReadResp 40246 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution @@ -724,17 +722,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 227117498 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3583537 # Request fanout histogram +system.membus.snoop_fanout::samples 3693822 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3583537 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3693822 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3583537 # Request fanout histogram +system.membus.snoop_fanout::total 3693822 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index b412f009d..6328b25f9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -4,74 +4,74 @@ sim_seconds 47.216814 # Nu sim_ticks 47216814145000 # Number of ticks simulated final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1225013 # Simulator instruction rate (inst/s) -host_op_rate 1441119 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59296512316 # Simulator tick rate (ticks/s) -host_mem_usage 723320 # Number of bytes of host memory used -host_seconds 796.28 # Real time elapsed on the host +host_inst_rate 1152960 # Simulator instruction rate (inst/s) +host_op_rate 1356355 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55808802200 # Simulator tick rate (ticks/s) +host_mem_usage 723640 # Number of bytes of host memory used +host_seconds 846.05 # Real time elapsed on the host sim_insts 975457230 # Number of instructions simulated sim_ops 1147538415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 154048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 152320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3911220 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 35234584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 222912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 221184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2638152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 38475968 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 412928 # Number of bytes read from this memory -system.physmem.bytes_read::total 81399700 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3911220 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2638152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6549372 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 100563072 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 3903156 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 35201416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 222016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 221568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2639368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 38466864 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 412736 # Number of bytes read from this memory +system.physmem.bytes_read::total 81348148 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3903156 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2639368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6542524 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 100538752 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 100583888 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2407 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 100559336 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2380 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2011 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 101520 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 550562 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3483 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 3456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 41328 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 601205 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6452 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1312424 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1571298 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 101394 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 550035 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3469 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3462 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 41347 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 601061 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6449 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1311608 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1570918 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1573901 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3263 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1573492 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3226 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 2726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 82835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 746230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4721 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 4684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 55873 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 814879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8745 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1723956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 82835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 55873 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 138708 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2129815 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 441 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 82665 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 745527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4702 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 4693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 55899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 814686 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8741 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1722864 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 82665 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 55899 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 138563 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2129300 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2130256 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2129815 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2129736 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2129300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3226 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 2726 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 82835 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 746670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 4684 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 55873 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 814879 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8745 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3854211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 82665 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 745963 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4702 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 4693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 55899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 814686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8741 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3852600 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -303,12 +303,12 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu0.op_class::total 585300003 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 6272759 # number of replacements +system.cpu0.dcache.tags.replacements 6272773 # number of replacements system.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 172015744 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6273271 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.420423 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 35630500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.total_refs 172015769 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6273285 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.420366 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.885315 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978292 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.978292 # Average percentage of cache occupancy @@ -317,44 +317,44 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 363162158 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 363162158 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 86214905 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 86214905 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 80919887 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 80919887 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 215655 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 215655 # number of SoftPFReq hits +system.cpu0.dcache.tags.tag_accesses 363162250 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 363162250 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 86214909 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 86214909 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 80919814 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 80919814 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 215654 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 215654 # number of SoftPFReq hits system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 262024 # number of WriteInvalidateReq hits system.cpu0.dcache.WriteInvalidateReq_hits::total 262024 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076466 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 2076466 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036774 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 2036774 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 167134792 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 167134792 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 167350447 # number of overall hits -system.cpu0.dcache.overall_hits::total 167350447 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3309378 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3309378 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1475526 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1475526 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 772138 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 772138 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076465 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 2076465 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036713 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2036713 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 167134723 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 167134723 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 167350377 # number of overall hits +system.cpu0.dcache.overall_hits::total 167350377 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3309384 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3309384 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1475628 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1475628 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 772139 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 772139 # number of SoftPFReq misses system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 831696 # number of WriteInvalidateReq misses system.cpu0.dcache.WriteInvalidateReq_misses::total 831696 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119816 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 119816 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158369 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 158369 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4784904 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4784904 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5557042 # number of overall misses -system.cpu0.dcache.overall_misses::total 5557042 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 89524283 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 89524283 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 82395413 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 82395413 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119817 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 119817 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158430 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 158430 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4785012 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4785012 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5557151 # number of overall misses +system.cpu0.dcache.overall_misses::total 5557151 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 89524293 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 89524293 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 82395442 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 82395442 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 987793 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 987793 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1093720 # number of WriteInvalidateReq accesses(hits+misses) @@ -363,24 +363,24 @@ system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2196282 system.cpu0.dcache.LoadLockedReq_accesses::total 2196282 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2195143 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 2195143 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 171919696 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 171919696 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 172907489 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 172907489 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 171919735 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 171919735 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 172907528 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 172907528 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036966 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017908 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017908 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781680 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781680 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017909 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017909 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781681 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781681 # miss rate for SoftPFReq accesses system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.760429 # miss rate for WriteInvalidateReq accesses system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.760429 # miss rate for WriteInvalidateReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072145 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072145 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027832 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027832 # miss rate for demand accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072173 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072173 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027833 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027833 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032139 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.032139 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -391,14 +391,14 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 4469723 # number of writebacks -system.cpu0.dcache.writebacks::total 4469723 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 4471084 # number of writebacks +system.cpu0.dcache.writebacks::total 4471084 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 5539081 # number of replacements +system.cpu0.icache.tags.replacements 5539078 # number of replacements system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 492212891 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5539593 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 88.853620 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 492212894 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5539590 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 88.853669 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy @@ -409,20 +409,20 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 256 system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 1001044576 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 1001044576 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 492212891 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 492212891 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 492212891 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 492212891 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 492212891 # number of overall hits -system.cpu0.icache.overall_hits::total 492212891 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5539598 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5539598 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5539598 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5539598 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5539598 # number of overall misses -system.cpu0.icache.overall_misses::total 5539598 # number of overall misses +system.cpu0.icache.tags.tag_accesses 1001044573 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 1001044573 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 492212894 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 492212894 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 492212894 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 492212894 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 492212894 # number of overall hits +system.cpu0.icache.overall_hits::total 492212894 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5539595 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5539595 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5539595 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5539595 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5539595 # number of overall misses +system.cpu0.icache.overall_misses::total 5539595 # number of overall misses system.cpu0.icache.ReadReq_accesses::cpu0.inst 497752489 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 497752489 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 497752489 # number of demand (read+write) accesses @@ -450,132 +450,131 @@ system.cpu0.l2cache.prefetcher.pfBufferHit 0 # system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2710840 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16208.843540 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 11548798 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2726836 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 4.235237 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 2709460 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16213.748169 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 11555205 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2725459 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 4.239728 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 5735.641953 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 53.550576 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 55.046098 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4528.763909 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 5835.841004 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.350076 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003268 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003360 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.276414 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.356191 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.989309 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15944 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1162 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4591 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5299 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4659 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973145 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 278654950 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 278654950 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 269350 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 141753 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4971397 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2944075 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 8326575 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 4469723 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 4469723 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 222737 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 222737 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3521 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 3521 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 634814 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 634814 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 269350 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 141753 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4971397 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3578889 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 8961389 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 269350 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 141753 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4971397 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3578889 # number of overall hits -system.cpu0.l2cache.overall_hits::total 8961389 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11316 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8593 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 568201 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 1257257 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1845367 # number of ReadReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 608598 # number of WriteInvalidateReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::total 608598 # number of WriteInvalidateReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 128143 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 128143 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158369 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 158369 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 709409 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 709409 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11316 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8593 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 568201 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1966666 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2554776 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11316 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8593 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 568201 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1966666 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2554776 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 280666 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 150346 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5539598 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4201332 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 10171942 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 4469723 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 4469723 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 831335 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::total 831335 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 131664 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 131664 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158369 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 158369 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344223 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1344223 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 280666 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 150346 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 5539598 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5545555 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 11516165 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 280666 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 150346 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 5539598 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5545555 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 11516165 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.057155 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.102571 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.299252 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.181417 # miss rate for ReadReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.732073 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.732073 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.973258 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.973258 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.tags.occ_blocks::writebacks 5709.903296 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 52.786445 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 57.022731 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4531.359232 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 5862.676466 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.348505 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003222 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003480 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.276572 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.357829 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.989609 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 48 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15951 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 33 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 234 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1167 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4590 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5333 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4627 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002930 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973572 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 278732920 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 278732920 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 271204 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 143552 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4971662 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 2944246 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 8330664 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 4471084 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 4471084 # number of Writeback hits +system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 223142 # number of WriteInvalidateReq hits +system.cpu0.l2cache.WriteInvalidateReq_hits::total 223142 # number of WriteInvalidateReq hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3523 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 3523 # number of UpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 635192 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 635192 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 271204 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 143552 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 4971662 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3579438 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 8965856 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 271204 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 143552 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 4971662 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3579438 # number of overall hits +system.cpu0.l2cache.overall_hits::total 8965856 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11221 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8442 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 567933 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 1257094 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 1844690 # number of ReadReq misses +system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 608192 # number of WriteInvalidateReq misses +system.cpu0.l2cache.WriteInvalidateReq_misses::total 608192 # number of WriteInvalidateReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 128237 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 128237 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158430 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 158430 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 709038 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 709038 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11221 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8442 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 567933 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1966132 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2553728 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11221 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8442 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 567933 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1966132 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2553728 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 282425 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 151994 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5539595 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4201340 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 10175354 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 4471084 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 4471084 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 831334 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::total 831334 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 131760 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 131760 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158430 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 158430 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344230 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1344230 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 282425 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 151994 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 5539595 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5545570 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 11519584 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 282425 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 151994 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 5539595 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5545570 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 11519584 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.039731 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.055542 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.102522 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.299213 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.181290 # miss rate for ReadReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.731586 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.731586 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.973262 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.973262 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.527747 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.527747 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.057155 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102571 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.354638 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.221843 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.057155 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102571 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.354638 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.221843 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.527468 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.527468 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039731 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.055542 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102522 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.354541 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.221686 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039731 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.055542 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102522 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.354541 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.221686 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -584,45 +583,43 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1573452 # number of writebacks -system.cpu0.l2cache.writebacks::total 1573452 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 1573136 # number of writebacks +system.cpu0.l2cache.writebacks::total 1573136 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 10363949 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 10363949 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 32448 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 32448 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 4469723 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 831335 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 831335 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 131664 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158369 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 290033 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1344223 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1344223 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 11165446 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17933523 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.trans_dist::ReadReq 10363944 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 10363944 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 32419 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 32419 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 4471084 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 831334 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 831334 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 131760 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158430 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 290190 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1344230 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1344230 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 11165440 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17935148 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 30193699 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706772 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 694376897 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 30195318 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706580 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 694464585 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1053462589 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 3346385 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 20385280 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 3.155096 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.361996 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 1053550085 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 3357578 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 20506010 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.181419 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.385365 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 17223609 84.49% 84.49% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 3161671 15.51% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 16785836 81.86% 81.86% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 3720174 18.14% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 20385280 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 20506010 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -839,36 +836,36 @@ system.cpu1.dcache.tags.tag_accesses 348813711 # Nu system.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 76990336 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 76990336 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 76990302 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 76990302 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 63447 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 63447 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 63438 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 63438 # number of WriteInvalidateReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048907 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 2048907 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 160687900 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 160687900 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 160875754 # number of overall hits -system.cpu1.dcache.overall_hits::total 160875754 # number of overall hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048921 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 2048921 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 160687866 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 160687866 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 160875720 # number of overall hits +system.cpu1.dcache.overall_hits::total 160875720 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1453140 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1453140 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1453174 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1453174 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 427052 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 427052 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 427061 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 427061 # number of WriteInvalidateReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158842 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 158842 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4811362 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4811362 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5603713 # number of overall misses -system.cpu1.dcache.overall_misses::total 5603713 # number of overall misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158828 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 158828 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4811396 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4811396 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5603747 # number of overall misses +system.cpu1.dcache.overall_misses::total 5603747 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses) @@ -891,12 +888,12 @@ system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018525 system.cpu1.dcache.WriteReq_miss_rate::total 0.018525 # miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.870648 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.870648 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.870666 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.870666 # miss rate for WriteInvalidateReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071947 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071947 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071941 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071941 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029072 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.029072 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033660 # miss rate for overall accesses @@ -909,8 +906,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 4030826 # number of writebacks -system.cpu1.dcache.writebacks::total 4030826 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 4032690 # number of writebacks +system.cpu1.dcache.writebacks::total 4032690 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 4741297 # number of replacements system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use @@ -967,132 +964,133 @@ system.cpu1.l2cache.prefetcher.pfBufferHit 0 # system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2278914 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13451.937852 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 10861278 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2294953 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 4.732680 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9726491516500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5180.760257 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 68.434503 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 91.707533 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2828.453932 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5282.581627 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.316209 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004177 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005597 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.172635 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.322423 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.821041 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 105 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15934 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 64 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1583 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5963 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4534 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3771 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006409 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.972534 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 254019378 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 254019378 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 325118 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141158 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4217165 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 3057891 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 7741332 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 4030826 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 4030826 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 161366 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 161366 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3865 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 3865 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614191 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 614191 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 325118 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 141158 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4217165 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3672082 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8355523 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 325118 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 141158 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4217165 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3672082 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8355523 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12489 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9780 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 524644 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 1239502 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1786415 # number of ReadReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 265480 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 265480 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133591 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 133591 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158842 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 158842 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 701699 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 701699 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12489 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9780 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 524644 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1941201 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 2488114 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12489 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9780 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 524644 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1941201 # number of overall misses -system.cpu1.l2cache.overall_misses::total 2488114 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 337607 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 150938 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.tags.replacements 2276750 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13455.535871 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 10863007 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2292767 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 4.737946 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9713557209000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5167.508425 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.262953 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 86.675159 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2849.798557 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5285.290777 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.315400 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004044 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005290 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.173938 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.322589 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.821261 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 96 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15921 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 49 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1571 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5986 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4452 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3831 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005859 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.971741 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 254014080 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 254014080 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 324472 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 140015 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4218186 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 3058286 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 7740959 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 4032690 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 4032690 # number of Writeback hits +system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 161150 # number of WriteInvalidateReq hits +system.cpu1.l2cache.WriteInvalidateReq_hits::total 161150 # number of WriteInvalidateReq hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3831 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 3831 # number of UpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614491 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 614491 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 324472 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 140015 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 4218186 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3672777 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 8355450 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 324472 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 140015 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 4218186 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3672777 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8355450 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12267 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9705 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 523623 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 1239107 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 1784702 # number of ReadReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 265696 # number of WriteInvalidateReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::total 265696 # number of WriteInvalidateReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133668 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 133668 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158828 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 158828 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 701399 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 701399 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12267 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9705 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 523623 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1940506 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 2486101 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12267 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9705 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 523623 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1940506 # number of overall misses +system.cpu1.l2cache.overall_misses::total 2486101 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 336739 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 149720 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4741809 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.data 4297393 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 9527747 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 4030826 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 4030826 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 9525661 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 4032690 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 4032690 # number of Writeback accesses(hits+misses) system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 426846 # number of WriteInvalidateReq accesses(hits+misses) system.cpu1.l2cache.WriteInvalidateReq_accesses::total 426846 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137456 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 137456 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158842 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 158842 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137499 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 137499 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158828 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 158828 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 337607 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 150938 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 336739 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 149720 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10843637 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 337607 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 150938 # number of overall (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 10841551 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 336739 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 149720 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10843637 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.064795 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.110642 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.288431 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.187496 # miss rate for ReadReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.621957 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.621957 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.971882 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.971882 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.overall_accesses::total 10841551 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036429 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.064821 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.110427 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.288339 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.187357 # miss rate for ReadReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.622463 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.622463 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.972138 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.972138 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533250 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.533250 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.064795 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110642 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345823 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.229454 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.064795 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110642 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345823 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.229454 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533023 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.533023 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036429 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.064821 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110427 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345699 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.229312 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036429 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.064821 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110427 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345699 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.229312 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1101,45 +1099,43 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 1183487 # number of writebacks -system.cpu1.l2cache.writebacks::total 1183487 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 1183004 # number of writebacks +system.cpu1.l2cache.writebacks::total 1183004 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.toL2Bus.trans_dist::ReadReq 9645413 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 4030826 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 4032690 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 426846 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 426846 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 137456 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158842 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 296298 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 137499 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158828 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 296327 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9483878 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16729164 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16731086 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 27412486 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 27414408 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 303476296 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 644579516 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 644698812 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 952853588 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 3730448 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 19274314 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 3.184989 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.388288 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 952972884 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 3837128 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 19395843 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.220254 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.414418 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 15708784 81.50% 81.50% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 3565530 18.50% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 15123827 77.97% 77.97% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 4272016 22.03% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 19274314 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 19395843 # Request fanout histogram system.iobus.trans_dist::ReadReq 40295 # Transaction distribution system.iobus.trans_dist::ReadResp 40295 # Transaction distribution system.iobus.trans_dist::WriteReq 136634 # Transaction distribution @@ -1253,205 +1249,205 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1759966 # number of replacements -system.l2c.tags.tagsinuse 62842.185631 # Cycle average of tags in use -system.l2c.tags.total_refs 3707512 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1818705 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.038545 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 482634500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 35219.340736 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 46.907098 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 57.886687 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3338.956610 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6965.181537 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 309.496433 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 430.211698 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2959.236338 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 13514.968494 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.537404 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000716 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000883 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.050948 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.106280 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004723 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006565 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.045154 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.206222 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.958896 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 231 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 58508 # Occupied blocks per task id +system.l2c.tags.replacements 1759191 # number of replacements +system.l2c.tags.tagsinuse 62867.167491 # Cycle average of tags in use +system.l2c.tags.total_refs 3704436 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1817948 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.037702 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 483416500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 35264.935108 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 45.422401 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 57.110376 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3318.609191 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6952.273283 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 314.594733 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 425.085194 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2976.403767 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 13512.733438 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.538100 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000693 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000871 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.050638 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.106083 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004800 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.006486 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.045416 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.206188 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.959277 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 227 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 58530 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 229 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 549 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3406 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5650 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 48840 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003525 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.892761 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 66406004 # Number of tag accesses -system.l2c.tags.data_accesses 66406004 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6334 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4677 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 509782 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 744386 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5569 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3610 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 483417 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 692017 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2449792 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2756939 # number of Writeback hits -system.l2c.Writeback_hits::total 2756939 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 121538 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 97977 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 219515 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 13827 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 10932 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 24759 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 1566 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1304 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2870 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 202688 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 171255 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 373943 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6334 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4677 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 509782 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 947074 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5569 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3610 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 483417 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 863272 # number of demand (read+write) hits -system.l2c.demand_hits::total 2823735 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6334 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4677 # number of overall hits -system.l2c.overall_hits::cpu0.inst 509782 # number of overall hits -system.l2c.overall_hits::cpu0.data 947074 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5569 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3610 # number of overall hits -system.l2c.overall_hits::cpu1.inst 483417 # number of overall hits -system.l2c.overall_hits::cpu1.data 863272 # number of overall hits -system.l2c.overall_hits::total 2823735 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2407 # number of ReadReq misses +system.l2c.tags.age_task_id_blocks_1023::4 225 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 564 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3441 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5617 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 48852 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.003464 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.893097 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 66366738 # Number of tag accesses +system.l2c.tags.data_accesses 66366738 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6239 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4535 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 509640 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 744526 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5366 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3579 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 482377 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 691195 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2447457 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 2756140 # number of Writeback hits +system.l2c.Writeback_hits::total 2756140 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 121071 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 98425 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 219496 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 13420 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 10778 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 24198 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 1497 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 1278 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2775 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 202220 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 170877 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 373097 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6239 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4535 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 509640 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 946746 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5366 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3579 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 482377 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 862072 # number of demand (read+write) hits +system.l2c.demand_hits::total 2820554 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6239 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4535 # number of overall hits +system.l2c.overall_hits::cpu0.inst 509640 # number of overall hits +system.l2c.overall_hits::cpu0.data 946746 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5366 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3579 # number of overall hits +system.l2c.overall_hits::cpu1.inst 482377 # number of overall hits +system.l2c.overall_hits::cpu1.data 862072 # number of overall hits +system.l2c.overall_hits::total 2820554 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 2380 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2011 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 58419 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 184134 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3483 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 3456 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 41227 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 189746 # number of ReadReq misses -system.l2c.ReadReq_misses::total 484883 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 479213 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 160846 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 640059 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 58018 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 53853 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 111871 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 7722 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 7423 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 15145 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 377543 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 418309 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 795852 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2407 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 58293 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 183599 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 3469 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 3462 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 41246 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 189649 # number of ReadReq misses +system.l2c.ReadReq_misses::total 484109 # number of ReadReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.data 479323 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.data 160634 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::total 639957 # number of WriteInvalidateReq misses +system.l2c.UpgradeReq_misses::cpu0.data 58449 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 54093 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 112542 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 7788 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 7462 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 15250 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 377640 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 418302 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 795942 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2380 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2011 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 58419 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 561677 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3483 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 3456 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 41227 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 608055 # number of demand (read+write) misses -system.l2c.demand_misses::total 1280735 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2407 # number of overall misses +system.l2c.demand_misses::cpu0.inst 58293 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 561239 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3469 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 3462 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 41246 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 607951 # number of demand (read+write) misses +system.l2c.demand_misses::total 1280051 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2380 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2011 # number of overall misses -system.l2c.overall_misses::cpu0.inst 58419 # number of overall misses -system.l2c.overall_misses::cpu0.data 561677 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3483 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 3456 # number of overall misses -system.l2c.overall_misses::cpu1.inst 41227 # number of overall misses -system.l2c.overall_misses::cpu1.data 608055 # number of overall misses -system.l2c.overall_misses::total 1280735 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 8741 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 6688 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 568201 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 928520 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 9052 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 7066 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 524644 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 881763 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2934675 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 2756939 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2756939 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 600751 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 258823 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 859574 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 71845 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 64785 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 136630 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 9288 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 8727 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 18015 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 580231 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 589564 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 1169795 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8741 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6688 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 568201 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1508751 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 9052 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7066 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 524644 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 1471327 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 4104470 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8741 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6688 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 568201 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1508751 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 9052 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7066 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 524644 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 1471327 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4104470 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.275369 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.300688 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.102814 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.198309 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.384777 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.489103 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.078581 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.215189 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.165225 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.797690 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.621452 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.744623 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.807544 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.831257 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.818788 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.831395 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.850579 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.840688 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.650677 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.709523 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.680335 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.275369 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.300688 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.102814 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.372279 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.384777 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.489103 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.078581 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.413270 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.312034 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.275369 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.300688 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.102814 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.372279 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.384777 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.489103 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.078581 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.413270 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.312034 # miss rate for overall accesses +system.l2c.overall_misses::cpu0.inst 58293 # number of overall misses +system.l2c.overall_misses::cpu0.data 561239 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3469 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 3462 # number of overall misses +system.l2c.overall_misses::cpu1.inst 41246 # number of overall misses +system.l2c.overall_misses::cpu1.data 607951 # number of overall misses +system.l2c.overall_misses::total 1280051 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 8619 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 6546 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 567933 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 928125 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 8835 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 7041 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 523623 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 880844 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2931566 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 2756140 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 2756140 # number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.data 600394 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.data 259059 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 859453 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 71869 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 64871 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 136740 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 9285 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 8740 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 18025 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 579860 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 589179 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 1169039 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8619 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6546 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 567933 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1507985 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 8835 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7041 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 523623 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 1470023 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 4100605 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8619 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6546 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 567933 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1507985 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 8835 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7041 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 523623 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 1470023 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 4100605 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.276134 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.307211 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.102641 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.197817 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.392643 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.491692 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.078770 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.215304 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.165137 # miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.798347 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.620067 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::total 0.744610 # miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.813271 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.833855 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.823036 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.838772 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.853776 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.846047 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.651261 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.709974 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.680852 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.276134 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.307211 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.102641 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.372178 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.392643 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.491692 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.078770 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.413566 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.312161 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.276134 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.307211 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.102641 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.372178 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.392643 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.491692 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.078770 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.413566 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.312161 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1460,49 +1456,49 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1464604 # number of writebacks -system.l2c.writebacks::total 1464604 # number of writebacks +system.l2c.writebacks::writebacks 1464224 # number of writebacks +system.l2c.writebacks::total 1464224 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 575939 # Transaction distribution -system.membus.trans_dist::ReadResp 575939 # Transaction distribution -system.membus.trans_dist::WriteReq 38831 # Transaction distribution -system.membus.trans_dist::WriteResp 38831 # Transaction distribution -system.membus.trans_dist::Writeback 1571298 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 742240 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 742240 # Transaction distribution -system.membus.trans_dist::UpgradeReq 327418 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 314341 # Transaction distribution -system.membus.trans_dist::UpgradeResp 148936 # Transaction distribution -system.membus.trans_dist::ReadExReq 965776 # Transaction distribution -system.membus.trans_dist::ReadExResp 778482 # Transaction distribution +system.membus.trans_dist::ReadReq 575153 # Transaction distribution +system.membus.trans_dist::ReadResp 575153 # Transaction distribution +system.membus.trans_dist::WriteReq 38802 # Transaction distribution +system.membus.trans_dist::WriteResp 38802 # Transaction distribution +system.membus.trans_dist::Writeback 1570918 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 742110 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 742110 # Transaction distribution +system.membus.trans_dist::UpgradeReq 328170 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 314483 # Transaction distribution +system.membus.trans_dist::UpgradeResp 149857 # Transaction distribution +system.membus.trans_dist::ReadExReq 965890 # Transaction distribution +system.membus.trans_dist::ReadExResp 778455 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6332069 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6482289 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6331701 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6481921 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337982 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 337982 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6820271 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6819903 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 215456868 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 215667865 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 215372636 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 215583633 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14229440 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 14229440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 229897305 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 229813073 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4414869 # Request fanout histogram +system.membus.snoop_fanout::samples 4535526 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4414869 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4535526 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4414869 # Request fanout histogram +system.membus.snoop_fanout::total 4535526 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1545,35 +1541,35 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 3713925 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3713925 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38831 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38831 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2756939 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 859574 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 859574 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 330257 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 317211 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 647468 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1357089 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1357089 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8689428 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7301285 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15990713 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301218837 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249930820 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 551149657 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 117306 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9368496 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012344 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.110415 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 3711525 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3711525 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38802 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38802 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2756140 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 859453 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 859453 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 330303 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 317258 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 647561 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1356474 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1356474 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8686436 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7297334 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15983770 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301115229 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249782916 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 550898145 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 117325 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9485599 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012192 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.109740 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 9252852 98.77% 98.77% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115644 1.23% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 9369955 98.78% 98.78% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115644 1.22% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9368496 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 9485599 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index b381100ef..a28434f3e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111153 # Nu sim_ticks 51111152682000 # Number of ticks simulated final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1276359 # Simulator instruction rate (inst/s) -host_op_rate 1499931 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66258489115 # Simulator tick rate (ticks/s) -host_mem_usage 712024 # Number of bytes of host memory used -host_seconds 771.39 # Real time elapsed on the host +host_inst_rate 1196191 # Simulator instruction rate (inst/s) +host_op_rate 1405721 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62096813616 # Simulator tick rate (ticks/s) +host_mem_usage 713636 # Number of bytes of host memory used +host_seconds 823.09 # Real time elapsed on the host sim_insts 984570519 # Number of instructions simulated sim_ops 1157031967 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -569,19 +569,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_si system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 2238699610 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 116338 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 36147883 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.003196 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.056441 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 36258168 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.034933 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.183610 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 36032362 99.68% 99.68% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 34991563 96.51% 96.51% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1266605 3.49% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 36147883 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 36258168 # Request fanout histogram system.iobus.trans_dist::ReadReq 40246 # Transaction distribution system.iobus.trans_dist::ReadResp 40246 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution @@ -724,17 +722,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 227117498 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3583537 # Request fanout histogram +system.membus.snoop_fanout::samples 3693822 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3583537 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3693822 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3583537 # Request fanout histogram +system.membus.snoop_fanout::total 3693822 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index fb0fbc4a7..5570b9a7c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.367818 # Number of seconds simulated -sim_ticks 47367817574000 # Number of ticks simulated -final_tick 47367817574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.526955 # Number of seconds simulated +sim_ticks 47526954967000 # Number of ticks simulated +final_tick 47526954967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 678056 # Simulator instruction rate (inst/s) -host_op_rate 798173 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38043399524 # Simulator tick rate (ticks/s) -host_mem_usage 751768 # Number of bytes of host memory used -host_seconds 1245.10 # Real time elapsed on the host -sim_insts 844246943 # Number of instructions simulated -sim_ops 993804803 # Number of ops (including micro ops) simulated +host_inst_rate 679404 # Simulator instruction rate (inst/s) +host_op_rate 799114 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36258651928 # Simulator tick rate (ticks/s) +host_mem_usage 756696 # Number of bytes of host memory used +host_seconds 1310.78 # Real time elapsed on the host +sim_insts 890546366 # Number of instructions simulated +sim_ops 1047459319 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 36928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 40576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2794548 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9993048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 9568064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 72256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 86016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2509048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 8105888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 7582272 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 437184 # Number of bytes read from this memory -system.physmem.bytes_read::total 41225828 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2794548 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2509048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5303596 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 61292480 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 120896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 123520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3402100 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 13323656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 13846976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 139776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 143808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3041464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 11124432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 15361728 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 416704 # Number of bytes read from this memory +system.physmem.bytes_read::total 61045060 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3402100 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3041464 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6443564 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 78583104 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 61313296 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 577 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 634 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 84072 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 156163 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 149501 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1129 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1344 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 39292 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 126669 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 118473 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6831 # Number of read requests responded to by this memory -system.physmem.num_reads::total 684685 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 957695 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 78603688 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1889 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1930 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 93565 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 208195 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 216359 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2184 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2247 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 47611 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 173832 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 240027 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6511 # Number of read requests responded to by this memory +system.physmem.num_reads::total 994350 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1227861 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 960298 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 857 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 58997 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 210967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 201995 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1816 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52969 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 171126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 160072 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 870334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 58997 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52969 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 111966 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1293969 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1230435 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2544 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 71583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 280339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 291350 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 63995 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 234066 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 323221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1284430 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 71583 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 63995 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 135577 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1653443 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1294408 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1293969 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 857 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 58997 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 211406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 201995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1816 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52969 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 171127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 160072 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9230 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2164742 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 684685 # Number of read requests accepted -system.physmem.writeReqs 1596629 # Number of write requests accepted -system.physmem.readBursts 684685 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1596629 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 43802304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 17536 # Total number of bytes read from write queue -system.physmem.bytesWritten 99044160 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 41225828 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 102038480 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 274 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 49035 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 111704 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 42136 # Per bank write bursts -system.physmem.perBankRdBursts::1 44080 # Per bank write bursts -system.physmem.perBankRdBursts::2 34958 # Per bank write bursts -system.physmem.perBankRdBursts::3 41288 # Per bank write bursts -system.physmem.perBankRdBursts::4 39326 # Per bank write bursts -system.physmem.perBankRdBursts::5 49165 # Per bank write bursts -system.physmem.perBankRdBursts::6 40428 # Per bank write bursts -system.physmem.perBankRdBursts::7 47118 # Per bank write bursts -system.physmem.perBankRdBursts::8 36254 # Per bank write bursts -system.physmem.perBankRdBursts::9 81044 # Per bank write bursts -system.physmem.perBankRdBursts::10 36070 # Per bank write bursts -system.physmem.perBankRdBursts::11 40557 # Per bank write bursts -system.physmem.perBankRdBursts::12 34453 # Per bank write bursts -system.physmem.perBankRdBursts::13 38158 # Per bank write bursts -system.physmem.perBankRdBursts::14 37145 # Per bank write bursts -system.physmem.perBankRdBursts::15 42231 # Per bank write bursts -system.physmem.perBankWrBursts::0 97165 # Per bank write bursts -system.physmem.perBankWrBursts::1 99476 # Per bank write bursts -system.physmem.perBankWrBursts::2 95543 # Per bank write bursts -system.physmem.perBankWrBursts::3 98326 # Per bank write bursts -system.physmem.perBankWrBursts::4 92692 # Per bank write bursts -system.physmem.perBankWrBursts::5 102230 # Per bank write bursts -system.physmem.perBankWrBursts::6 96747 # Per bank write bursts -system.physmem.perBankWrBursts::7 98806 # Per bank write bursts -system.physmem.perBankWrBursts::8 93672 # Per bank write bursts -system.physmem.perBankWrBursts::9 100275 # Per bank write bursts -system.physmem.perBankWrBursts::10 92352 # Per bank write bursts -system.physmem.perBankWrBursts::11 96579 # Per bank write bursts -system.physmem.perBankWrBursts::12 94667 # Per bank write bursts -system.physmem.perBankWrBursts::13 97213 # Per bank write bursts -system.physmem.perBankWrBursts::14 92658 # Per bank write bursts -system.physmem.perBankWrBursts::15 99164 # Per bank write bursts +system.physmem.bw_write::total 1653876 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1653443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2544 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 71583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 280772 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 291350 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 63995 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 234066 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 323221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2938306 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 994350 # Number of read requests accepted +system.physmem.writeReqs 1902822 # Number of write requests accepted +system.physmem.readBursts 994350 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1902822 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 63617152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21248 # Total number of bytes read from write queue +system.physmem.bytesWritten 118663680 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 61045060 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 121636456 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 332 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 48679 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 115330 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 57482 # Per bank write bursts +system.physmem.perBankRdBursts::1 61474 # Per bank write bursts +system.physmem.perBankRdBursts::2 58055 # Per bank write bursts +system.physmem.perBankRdBursts::3 62815 # Per bank write bursts +system.physmem.perBankRdBursts::4 61744 # Per bank write bursts +system.physmem.perBankRdBursts::5 72443 # Per bank write bursts +system.physmem.perBankRdBursts::6 62137 # Per bank write bursts +system.physmem.perBankRdBursts::7 62898 # Per bank write bursts +system.physmem.perBankRdBursts::8 53757 # Per bank write bursts +system.physmem.perBankRdBursts::9 98485 # Per bank write bursts +system.physmem.perBankRdBursts::10 53699 # Per bank write bursts +system.physmem.perBankRdBursts::11 61424 # Per bank write bursts +system.physmem.perBankRdBursts::12 50178 # Per bank write bursts +system.physmem.perBankRdBursts::13 60766 # Per bank write bursts +system.physmem.perBankRdBursts::14 57507 # Per bank write bursts +system.physmem.perBankRdBursts::15 59154 # Per bank write bursts +system.physmem.perBankWrBursts::0 114707 # Per bank write bursts +system.physmem.perBankWrBursts::1 119877 # Per bank write bursts +system.physmem.perBankWrBursts::2 118693 # Per bank write bursts +system.physmem.perBankWrBursts::3 118700 # Per bank write bursts +system.physmem.perBankWrBursts::4 118108 # Per bank write bursts +system.physmem.perBankWrBursts::5 125436 # Per bank write bursts +system.physmem.perBankWrBursts::6 113884 # Per bank write bursts +system.physmem.perBankWrBursts::7 116296 # Per bank write bursts +system.physmem.perBankWrBursts::8 112515 # Per bank write bursts +system.physmem.perBankWrBursts::9 116242 # Per bank write bursts +system.physmem.perBankWrBursts::10 112992 # Per bank write bursts +system.physmem.perBankWrBursts::11 118745 # Per bank write bursts +system.physmem.perBankWrBursts::12 107808 # Per bank write bursts +system.physmem.perBankWrBursts::13 111387 # Per bank write bursts +system.physmem.perBankWrBursts::14 114155 # Per bank write bursts +system.physmem.perBankWrBursts::15 114575 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 352 # Number of times write queue was full causing retry -system.physmem.totGap 47367814519500 # Total gap between requests +system.physmem.numWrRetry 406 # Number of times write queue was full causing retry +system.physmem.totGap 47526951912500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) -system.physmem.readPktSize::3 37 # Read request sizes (log2) +system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 641448 # Read request sizes (log2) +system.physmem.readPktSize::6 951125 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) -system.physmem.writePktSize::3 2601 # Write request sizes (log2) +system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1594026 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 510577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 50448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 25290 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 21897 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 18597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 16379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 14128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 12156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 9819 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2868 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 632 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1900248 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 698116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 83658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42191 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 36638 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 31495 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 28119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 24839 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 21358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 17624 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1385 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1018 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 839 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 464 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 93 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -188,170 +188,169 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 50983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 63815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 77905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 83850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 85536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 82535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 80562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 80737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 81986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 81840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 82529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 87953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 83182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 82789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 95240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 86941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 82400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 79288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 6110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 5077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 5187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 6766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 5946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 6638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 5635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 4863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 4938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 3930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1324 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 813055 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 175.690629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 106.318755 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 249.924527 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 526198 64.72% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 156067 19.20% 83.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 35208 4.33% 88.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 17256 2.12% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12096 1.49% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8107 1.00% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6222 0.77% 93.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5625 0.69% 94.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 46276 5.69% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 813055 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 73772 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 9.277314 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 118.735455 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 73768 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 55966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 69244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 86453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 95710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 99723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 98450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 98652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 98653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 101180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 101256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 102685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 108850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 104999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 104785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 118151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 108223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 102687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 99179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 6890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 5566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 6838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 6775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 6158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 4899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 4456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1611 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1054851 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 172.802142 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 106.115345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 242.100455 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 681651 64.62% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 201380 19.09% 83.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 48895 4.64% 88.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24340 2.31% 90.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 17755 1.68% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11649 1.10% 93.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8558 0.81% 94.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7940 0.75% 95.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 52683 4.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1054851 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 92018 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 10.802300 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 106.341779 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 92015 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 73772 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 73772 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.977674 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.369218 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 19.656514 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 71961 97.55% 97.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 712 0.97% 98.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 29 0.04% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 36 0.05% 98.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 132 0.18% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 174 0.24% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 342 0.46% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 135 0.18% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 19 0.03% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 12 0.02% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 64 0.09% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 33 0.04% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 12 0.02% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 4 0.01% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 4 0.01% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 7 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 6 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 10 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 9 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 6 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 10 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 15 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 3 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 6 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 7 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::592-607 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 73772 # Writes before turning the bus around for reads -system.physmem.totQLat 20326500723 # Total ticks spent queuing -system.physmem.totMemAccLat 33159206973 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3422055000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29699.26 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 92018 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 92018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.149536 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.827281 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.009129 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 90131 97.95% 97.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 760 0.83% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 32 0.03% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 41 0.04% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 142 0.15% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 182 0.20% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 347 0.38% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 116 0.13% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 35 0.04% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 12 0.01% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 63 0.07% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 31 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 15 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 6 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 4 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 5 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 6 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 11 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 16 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 8 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 24 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 4 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-751 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::848-863 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 92018 # Writes before turning the bus around for reads +system.physmem.totQLat 36585898476 # Total ticks spent queuing +system.physmem.totMemAccLat 55223735976 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4970090000 # Total ticks spent in databus transfers +system.physmem.avgQLat 36806.07 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 48449.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.92 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.09 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.87 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.15 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 55556.07 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.34 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.50 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.28 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.56 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.81 # Average write queue length when enqueuing -system.physmem.readRowHits 509481 # Number of row buffer hits during reads -system.physmem.writeRowHits 909439 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.76 # Row buffer hit rate for writes -system.physmem.avgGap 20763390.98 # Average gap between requests -system.physmem.pageHitRate 63.57 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3169991160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1729657875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2640253200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5060782800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1178038765890 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27387322041000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31671796931685 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.635370 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45560807372172 # Time in different power states -system.physmem_0.memoryStateTime::REF 1581715460000 # Time in different power states +system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.94 # Average write queue length when enqueuing +system.physmem.readRowHits 744165 # Number of row buffer hits during reads +system.physmem.writeRowHits 1049121 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.86 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 56.58 # Row buffer hit rate for writes +system.physmem.avgGap 16404601.42 # Average gap between requests +system.physmem.pageHitRate 62.96 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4105851120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2240295750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3892535400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6128142480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3104229389040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1214897373855 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27450471155250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31785964742895 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.798736 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45665609957576 # Time in different power states +system.physmem_0.memoryStateTime::REF 1587029340000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 225294290828 # Time in different power states +system.physmem_0.memoryStateTime::ACT 274315218424 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2976704640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1624194000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2698113600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4967438400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1169320459140 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27394969678500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31670392028040 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.605711 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45573545582628 # Time in different power states -system.physmem_1.memoryStateTime::REF 1581715460000 # Time in different power states +system.physmem_1.actEnergy 3868822440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2110964625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3860766000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5886555120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3104229389040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1202076105075 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27461717882250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31783750484550 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.752146 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45684364167822 # Time in different power states +system.physmem_1.memoryStateTime::REF 1587029340000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 212554603622 # Time in different power states +system.physmem_1.memoryStateTime::ACT 255557515928 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -415,67 +414,69 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 95467 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 95467 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8616 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 72889 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 95458 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.225230 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 69.587670 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 95457 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::20480-22527 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 95458 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 81514 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 17324.683490 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 15769.335506 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 10694.107977 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 81100 99.49% 99.49% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 359 0.44% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 15 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 17 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 14 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 101631 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 101631 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9048 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76119 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 11 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 101620 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.113167 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 36.075158 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-1023 101619 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::11264-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 101620 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 85178 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 19101.889572 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 17045.635811 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 15664.933997 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 84047 98.67% 98.67% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 953 1.12% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 46 0.05% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 63 0.07% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 53 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 81514 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 1873275212 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.115454 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -216276296 -11.55% -11.55% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 2089551508 111.55% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1873275212 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 72890 89.43% 89.43% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 8616 10.57% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 81506 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 95467 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 85178 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 6479942056 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.123756 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -801929896 -12.38% -12.38% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 7281871952 112.38% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 6479942056 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 76120 89.38% 89.38% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 9048 10.62% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 85168 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 101631 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 95467 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 81506 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 101631 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85168 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 81506 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 176973 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85168 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 186799 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 81219280 # DTB read hits -system.cpu0.dtb.read_misses 71070 # DTB read misses -system.cpu0.dtb.write_hits 73504932 # DTB write hits -system.cpu0.dtb.write_misses 24397 # DTB write misses +system.cpu0.dtb.read_hits 83767358 # DTB read hits +system.cpu0.dtb.read_misses 74871 # DTB read misses +system.cpu0.dtb.write_hits 75914688 # DTB write hits +system.cpu0.dtb.write_misses 26760 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 38298 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 32159 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4007 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 3900 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10240 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 81290350 # DTB read accesses -system.cpu0.dtb.write_accesses 73529329 # DTB write accesses +system.cpu0.dtb.perms_faults 8424 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 83842229 # DTB read accesses +system.cpu0.dtb.write_accesses 75941448 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 154724212 # DTB hits -system.cpu0.dtb.misses 95467 # DTB misses -system.cpu0.dtb.accesses 154819679 # DTB accesses +system.cpu0.dtb.hits 159682046 # DTB hits +system.cpu0.dtb.misses 101631 # DTB misses +system.cpu0.dtb.accesses 159783677 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -505,239 +506,235 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 56383 # Table walker walks requested -system.cpu0.itb.walker.walksLong 56383 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 751 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 50468 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 56383 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 56383 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 56383 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 51219 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 19351.129327 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 17618.924664 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 12629.312385 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 47792 93.31% 93.31% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 2988 5.83% 99.14% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 157 0.31% 99.45% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 221 0.43% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 13 0.03% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 4 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 16 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 51219 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 55722 # Table walker walks requested +system.cpu0.itb.walker.walksLong 55722 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 543 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49598 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 55722 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 55722 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 55722 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 50141 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 22337.612912 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 19289.783493 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 21041.520478 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 48785 97.30% 97.30% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1144 2.28% 99.58% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 57 0.11% 99.69% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 79 0.16% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 56 0.11% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 50141 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples -241360296 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 -241360296 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total -241360296 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 50468 98.53% 98.53% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 751 1.47% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 51219 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 49598 98.92% 98.92% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 543 1.08% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 50141 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 56383 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 56383 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 55722 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 55722 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 51219 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 51219 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 107602 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 434853798 # ITB inst hits -system.cpu0.itb.inst_misses 56383 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50141 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50141 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 105863 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 444122432 # ITB inst hits +system.cpu0.itb.inst_misses 55722 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26912 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 22526 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 434910181 # ITB inst accesses -system.cpu0.itb.hits 434853798 # DTB hits -system.cpu0.itb.misses 56383 # DTB misses -system.cpu0.itb.accesses 434910181 # DTB accesses -system.cpu0.numCycles 94735635148 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 444178154 # ITB inst accesses +system.cpu0.itb.hits 444122432 # DTB hits +system.cpu0.itb.misses 55722 # DTB misses +system.cpu0.itb.accesses 444178154 # DTB accesses +system.cpu0.numCycles 95053909934 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 434594659 # Number of instructions committed -system.cpu0.committedOps 509819268 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 468245604 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 368958 # Number of float alu accesses -system.cpu0.num_func_calls 25685063 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 65742912 # number of instructions that are conditional controls -system.cpu0.num_int_insts 468245604 # number of integer instructions -system.cpu0.num_fp_insts 368958 # number of float instructions -system.cpu0.num_int_register_reads 681605000 # number of times the integer registers were read -system.cpu0.num_int_register_writes 371986080 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 629019 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 237888 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 113785122 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 113402508 # number of times the CC registers were written -system.cpu0.num_mem_refs 154715442 # number of memory refs -system.cpu0.num_load_insts 81215665 # Number of load instructions -system.cpu0.num_store_insts 73499777 # Number of store instructions -system.cpu0.num_idle_cycles 93677942540.842026 # Number of idle cycles -system.cpu0.num_busy_cycles 1057692607.157978 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011165 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988835 # Percentage of idle cycles -system.cpu0.Branches 96525602 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 354149041 69.42% 69.42% # Class of executed instruction -system.cpu0.op_class::IntMult 1173113 0.23% 69.65% # Class of executed instruction -system.cpu0.op_class::IntDiv 59997 0.01% 69.67% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 23937 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::MemRead 81215665 15.92% 85.59% # Class of executed instruction -system.cpu0.op_class::MemWrite 73499777 14.41% 100.00% # Class of executed instruction +system.cpu0.committedInsts 443872382 # Number of instructions committed +system.cpu0.committedOps 521690846 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 479475231 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 421225 # Number of float alu accesses +system.cpu0.num_func_calls 26535732 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 67239811 # number of instructions that are conditional controls +system.cpu0.num_int_insts 479475231 # number of integer instructions +system.cpu0.num_fp_insts 421225 # number of float instructions +system.cpu0.num_int_register_reads 693782505 # number of times the integer registers were read +system.cpu0.num_int_register_writes 380162379 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 701849 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 304628 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 115037577 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 114748059 # number of times the CC registers were written +system.cpu0.num_mem_refs 159672530 # number of memory refs +system.cpu0.num_load_insts 83761106 # Number of load instructions +system.cpu0.num_store_insts 75911424 # Number of store instructions +system.cpu0.num_idle_cycles 93959856753.206024 # Number of idle cycles +system.cpu0.num_busy_cycles 1094053180.793977 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011510 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988490 # Percentage of idle cycles +system.cpu0.Branches 99058393 # Number of branches fetched +system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 361081858 69.17% 69.17% # Class of executed instruction +system.cpu0.op_class::IntMult 1125018 0.22% 69.39% # Class of executed instruction +system.cpu0.op_class::IntDiv 61306 0.01% 69.40% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 43308 0.01% 69.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction +system.cpu0.op_class::MemRead 83761106 16.05% 85.46% # Class of executed instruction +system.cpu0.op_class::MemWrite 75911424 14.54% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 510121531 # Class of executed instruction +system.cpu0.op_class::total 521984020 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13974 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 5284481 # number of replacements -system.cpu0.dcache.tags.tagsinuse 474.292500 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 149186915 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5284993 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.228404 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 4077089500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 474.292500 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.926353 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.926353 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 314708854 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 314708854 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75740068 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75740068 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 69444390 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 69444390 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177454 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 177454 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 143100 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 143100 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1662300 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1662300 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1634095 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1634095 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 145184458 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 145184458 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 145361912 # number of overall hits -system.cpu0.dcache.overall_hits::total 145361912 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2820396 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 2820396 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1320543 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1320543 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 635767 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 635767 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 746024 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 746024 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 156072 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 156072 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 182947 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 182947 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4140939 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4140939 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4776706 # number of overall misses -system.cpu0.dcache.overall_misses::total 4776706 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39561901741 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 39561901741 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24338572363 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 24338572363 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 30943018074 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 30943018074 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2147538753 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2147538753 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3961701456 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3961701456 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1248500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1248500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 63900474104 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 63900474104 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 63900474104 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 63900474104 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 78560464 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 78560464 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 70764933 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 70764933 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 813221 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 813221 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 889124 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 889124 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1818372 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1818372 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1817042 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1817042 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 149325397 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 149325397 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 150138618 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 150138618 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.035901 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.035901 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018661 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018661 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781789 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781789 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839055 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.839055 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085831 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085831 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100684 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100684 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027731 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027731 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031815 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.031815 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14027.073411 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14027.073411 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18430.730664 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 18430.730664 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41477.242118 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41477.242118 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13759.923324 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13759.923324 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21654.913478 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21654.913478 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 5106 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 5414405 # number of replacements +system.cpu0.dcache.tags.tagsinuse 480.206026 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 154030593 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5414914 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.445621 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 4071814500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.206026 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937902 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.937902 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 344 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 324790756 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 324790756 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 77996551 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 77996551 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 71694037 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 71694037 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 187802 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 187802 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 131287 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 131287 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1831493 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1831493 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1787873 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1787873 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 149690588 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 149690588 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 149878390 # number of overall hits +system.cpu0.dcache.overall_hits::total 149878390 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2964325 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 2964325 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1343066 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1343066 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 617580 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 617580 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 739156 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 739156 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 153043 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 153043 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195288 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 195288 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4307391 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4307391 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 4924971 # number of overall misses +system.cpu0.dcache.overall_misses::total 4924971 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 44154787210 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 44154787210 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26046845450 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 26046845450 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 30884044772 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 30884044772 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2257944026 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2257944026 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4202199390 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4202199390 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2186500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2186500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 70201632660 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 70201632660 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 70201632660 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 70201632660 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 80960876 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 80960876 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 73037103 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 73037103 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 805382 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 805382 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 870443 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 870443 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1984536 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1984536 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1983161 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1983161 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 153997979 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 153997979 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 154803361 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 154803361 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036614 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036614 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018389 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018389 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.766816 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766816 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.849172 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.849172 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077118 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.077118 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098473 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098473 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027970 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027970 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031814 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.031814 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14895.393457 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14895.393457 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19393.570718 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19393.570718 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41782.850673 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41782.850673 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14753.657639 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14753.657639 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21517.960090 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21517.960090 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15431.397107 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15431.397107 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13377.518755 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13377.518755 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16297.947565 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16297.947565 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14254.222545 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14254.222545 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -746,151 +743,157 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3634622 # number of writebacks -system.cpu0.dcache.writebacks::total 3634622 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28612 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 28612 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21357 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21357 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 38145 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 38145 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 49969 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 49969 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 49969 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 49969 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2791784 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2791784 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1299186 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1299186 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 630147 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 630147 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 746024 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 746024 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 117927 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 117927 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 182947 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 182947 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4090970 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4090970 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 4721117 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4721117 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 34314944268 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 34314944268 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 21777665637 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 21777665637 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 12432309289 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 12432309289 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 29820271426 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 29820271426 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1422971246 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1422971246 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3676791544 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3676791544 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1208000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1208000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 56092609905 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 56092609905 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 68524919194 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 68524919194 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4525228998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4525228998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4129291250 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4129291250 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 8654520248 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 8654520248 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035537 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035537 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018359 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018359 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.774878 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.774878 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.839055 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.839055 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064853 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064853 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.100684 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.100684 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027396 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027396 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031445 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031445 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12291.403729 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12291.403729 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16762.546423 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16762.546423 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19729.220783 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19729.220783 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39972.268219 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39972.268219 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12066.543251 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12066.543251 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20097.577681 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20097.577681 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3655915 # number of writebacks +system.cpu0.dcache.writebacks::total 3655915 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 33290 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 33290 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21376 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21376 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 42886 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 42886 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 54666 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 54666 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 54666 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 54666 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2931035 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2931035 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1321690 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1321690 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 611921 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 611921 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 739156 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 739156 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 110157 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 110157 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195288 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 195288 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4252725 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4252725 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4864646 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4864646 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16584 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16584 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18033 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18033 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34617 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34617 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 38329059920 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 38329059920 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 23455096050 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 23455096050 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13388812156 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13388812156 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 29772038228 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 29772038228 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1440580476 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1440580476 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3899742610 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3899742610 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2117500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2117500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61784155970 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 61784155970 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 75172968126 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 75172968126 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2701006250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2701006250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2792188500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2792188500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5493194750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5493194750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036203 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036203 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018096 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018096 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759790 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759790 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.849172 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.849172 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055508 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055508 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098473 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098473 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027615 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027615 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031425 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031425 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13076.971077 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13076.971077 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17746.291528 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17746.291528 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21879.968421 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21879.968421 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 40278.423267 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 40278.423267 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13077.520956 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13077.520956 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19969.187098 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19969.187098 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13711.322719 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13711.322719 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14514.556448 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14514.556448 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14528.133366 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14528.133366 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15452.916435 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15452.916435 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162868.201278 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162868.201278 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 154837.714191 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154837.714191 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 158684.887483 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 158684.887483 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 4499955 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.899412 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 430353331 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 4500467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 95.624150 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 33435593250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.899412 # Average occupied blocks per requestor +system.cpu0.icache.tags.replacements 5032307 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.899757 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 439089613 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5032819 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 87.245262 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 33435686250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.899757 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999804 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 122 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 874208063 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 874208063 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 430353331 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 430353331 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 430353331 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 430353331 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 430353331 # number of overall hits -system.cpu0.icache.overall_hits::total 430353331 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 4500467 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 4500467 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 4500467 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 4500467 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 4500467 # number of overall misses -system.cpu0.icache.overall_misses::total 4500467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 47768563979 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 47768563979 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 47768563979 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 47768563979 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 47768563979 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 47768563979 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 434853798 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 434853798 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 434853798 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 434853798 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 434853798 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 434853798 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010349 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.010349 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010349 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.010349 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010349 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.010349 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10614.134928 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10614.134928 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10614.134928 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10614.134928 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10614.134928 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10614.134928 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 893277683 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 893277683 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 439089613 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 439089613 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 439089613 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 439089613 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 439089613 # number of overall hits +system.cpu0.icache.overall_hits::total 439089613 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5032819 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5032819 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5032819 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5032819 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5032819 # number of overall misses +system.cpu0.icache.overall_misses::total 5032819 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 52854361147 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 52854361147 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 52854361147 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 52854361147 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 52854361147 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 52854361147 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 444122432 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 444122432 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 444122432 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 444122432 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 444122432 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 444122432 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011332 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011332 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011332 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011332 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011332 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011332 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10501.939598 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10501.939598 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10501.939598 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10501.939598 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10501.939598 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10501.939598 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -899,240 +902,239 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4500467 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 4500467 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 4500467 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 4500467 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 4500467 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 4500467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 43254050535 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 43254050535 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 43254050535 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 43254050535 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 43254050535 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 43254050535 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5032819 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 5032819 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 5032819 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 5032819 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 5032819 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 5032819 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 47804251855 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 47804251855 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 47804251855 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 47804251855 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 47804251855 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 47804251855 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3811870500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3811870500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3811870500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 3811870500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010349 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010349 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010349 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010349 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010349 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010349 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9611.013820 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9611.013820 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9611.013820 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9611.013820 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9611.013820 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9611.013820 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011332 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011332 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011332 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011332 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011332 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011332 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9498.504090 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9498.504090 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9498.504090 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9498.504090 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9498.504090 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9498.504090 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88391.200000 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88391.200000 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88391.200000 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88391.200000 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7625512 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7625539 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7211191 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7211221 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 975949 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2276475 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16164.000425 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 9930056 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2292579 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 4.331391 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 5342662500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7643.384526 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.376858 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 75.669060 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3718.900652 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3598.062438 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1070.606892 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.466515 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003502 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004618 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.226984 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.219608 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.065345 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.986572 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1394 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14660 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 18 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 269 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 592 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 515 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 17 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 811 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4617 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5283 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3880 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.085083 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.894775 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 232158629 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 232158629 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 184213 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 122134 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 3989528 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2659243 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 6955118 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 3634621 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 3634621 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 174040 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 174040 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 97614 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 97614 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 30602 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 30602 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 869323 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 869323 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 184213 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 122134 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 3989528 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3528566 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 7824441 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 184213 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 122134 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 3989528 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3528566 # number of overall hits -system.cpu0.l2cache.overall_hits::total 7824441 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 8450 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 6821 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 510939 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 880615 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1406825 # number of ReadReq misses -system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses -system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 570673 # number of WriteInvalidateReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::total 570673 # number of WriteInvalidateReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 121192 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 121192 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 152342 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 152342 # number of SCUpgradeReq misses +system.cpu0.l2cache.prefetcher.pfSpanPage 945331 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2374120 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16169.428044 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 10531211 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2389368 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 4.407530 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 5341335500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 8264.618229 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 69.150581 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 77.449352 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3311.410043 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3382.587139 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1064.212699 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.504432 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004221 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004727 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.202112 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.206457 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.064954 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.986904 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1373 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 85 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13790 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 173 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 780 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 417 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 54 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3709 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6679 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3275 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.083801 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.841675 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 244043620 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 244043620 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 211402 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 128647 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4517111 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 2702351 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 7559511 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 3655914 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 3655914 # number of Writeback hits +system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 175642 # number of WriteInvalidateReq hits +system.cpu0.l2cache.WriteInvalidateReq_hits::total 175642 # number of WriteInvalidateReq hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 102383 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 102383 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 30801 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 30801 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 876779 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 876779 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 211402 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 128647 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 4517111 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3579130 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 8436290 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 211402 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 128647 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 4517111 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3579130 # number of overall hits +system.cpu0.l2cache.overall_hits::total 8436290 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10881 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8892 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 515708 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 950762 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 1486243 # number of ReadReq misses +system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 562136 # number of WriteInvalidateReq misses +system.cpu0.l2cache.WriteInvalidateReq_misses::total 562136 # number of WriteInvalidateReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 120119 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 120119 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 164484 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 164484 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 228613 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 228613 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 8450 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 6821 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 510939 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1109228 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1635438 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 8450 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 6821 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 510939 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1109228 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1635438 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 233396250 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 201613986 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 15055870276 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 27344253636 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 42835134148 # number of ReadReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 214216390 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 214216390 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2669808389 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 2669808389 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3193098671 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3193098671 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1181000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1181000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 10520875436 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 10520875436 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 233396250 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 201613986 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 15055870276 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 37865129072 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 53356009584 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 233396250 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 201613986 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 15055870276 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 37865129072 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 53356009584 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 192663 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 128955 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 4500467 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3539858 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 8361943 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 3634622 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 3634622 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 744713 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::total 744713 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 218806 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 218806 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 182944 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 182944 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 240029 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 240029 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10881 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8892 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 515708 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1190791 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 1726272 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10881 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8892 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 515708 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1190791 # number of overall misses +system.cpu0.l2cache.overall_misses::total 1726272 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 393469249 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 355451999 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 15907969852 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 31938942740 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 48595833840 # number of ReadReq miss cycles +system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 181717619 # number of WriteInvalidateReq miss cycles +system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 181717619 # number of WriteInvalidateReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2563026586 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 2563026586 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3399427212 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3399427212 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2070498 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2070498 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12166293140 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 12166293140 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 393469249 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 355451999 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 15907969852 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 44105235880 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 60762126980 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 393469249 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 355451999 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 15907969852 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 44105235880 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 60762126980 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 222283 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 137539 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5032819 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3653113 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 9045754 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 3655914 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 3655914 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 737778 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::total 737778 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 222502 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 222502 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 195285 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 195285 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1097936 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1097936 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 192663 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 128955 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 4500467 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 4637794 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 9459879 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 192663 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 128955 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 4500467 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 4637794 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 9459879 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.043859 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052894 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.113530 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.248771 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.168241 # miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.766299 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.766299 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.553879 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.553879 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.832725 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.832725 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1116808 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1116808 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 222283 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 137539 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 5032819 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 4769921 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 10162562 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 222283 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 137539 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 5032819 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 4769921 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 10162562 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.048951 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.064651 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.102469 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.260261 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.164303 # miss rate for ReadReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.761931 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.761931 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.539856 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.539856 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.842277 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.842277 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.208221 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.208221 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.043859 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052894 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.113530 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.239171 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.172881 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.043859 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052894 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.113530 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.239171 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.172881 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27620.857988 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 29557.834042 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 29467.060209 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 31051.314861 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30448.089953 # average ReadReq miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 375.375022 # average WriteInvalidateReq miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 375.375022 # average WriteInvalidateReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22029.576119 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22029.576119 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20960.067946 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20960.067946 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 393666.666667 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 393666.666667 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 46020.460061 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 46020.460061 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27620.857988 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 29557.834042 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29467.060209 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34136.470655 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 32624.905123 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27620.857988 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 29557.834042 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29467.060209 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34136.470655 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 32624.905123 # average overall miss latency +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.214924 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.214924 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.048951 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.064651 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102469 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.249646 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.169866 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.048951 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.064651 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102469 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.249646 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.169866 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36161.129400 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 39974.358862 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30846.854910 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 33592.994609 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32697.098550 # average ReadReq miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 323.262732 # average WriteInvalidateReq miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 323.262732 # average WriteInvalidateReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21337.395300 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21337.395300 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20667.221201 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20667.221201 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 690166 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 690166 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50686.763433 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50686.763433 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36161.129400 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 39974.358862 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30846.854910 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37038.603651 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 35198.466395 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36161.129400 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 39974.358862 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30846.854910 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37038.603651 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 35198.466395 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1141,199 +1143,201 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1283433 # number of writebacks -system.cpu0.l2cache.writebacks::total 1283433 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 443 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 443 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3351 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 3351 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3794 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 3794 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3794 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 3794 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 8450 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 6821 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 510939 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 880172 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 1406382 # number of ReadReq MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 635942 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 635942 # number of HardPFReq MSHR misses -system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 570673 # number of WriteInvalidateReq MSHR misses -system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 570673 # number of WriteInvalidateReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 121192 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 121192 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 152342 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 152342 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.writebacks::writebacks 1321734 # number of writebacks +system.cpu0.l2cache.writebacks::total 1321734 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 498 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 498 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6011 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 6011 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6509 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 6509 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6509 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 6509 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10881 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8892 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 515708 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 950264 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 1485745 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 659076 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 659076 # number of HardPFReq MSHR misses +system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 562136 # number of WriteInvalidateReq MSHR misses +system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 562136 # number of WriteInvalidateReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 120119 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 120119 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 164484 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 164484 # number of SCUpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 225262 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 225262 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 8450 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 6821 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 510939 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1105434 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 1631644 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 8450 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 6821 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 510939 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1105434 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 635942 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 2267586 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 178310250 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 157112514 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 11720586224 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 21558629277 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 33614638265 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 23030840367 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 23030840367 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 24220184845 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 24220184845 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2529730528 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2529730528 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2304861456 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2304861456 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1005500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1005500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 8691962659 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 8691962659 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 178310250 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 157112514 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 11720586224 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 30250591936 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 42306600924 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 178310250 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 157112514 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 11720586224 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 30250591936 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 23030840367 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 65337441291 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 234018 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 234018 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10881 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8892 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 515708 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1184282 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 1719763 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10881 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8892 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 515708 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1184282 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 659076 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 2378839 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 16584 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 59709 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 18033 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 18033 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34617 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 77742 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 322190251 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 297082001 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 12538366148 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 25676104173 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 38833742573 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 32139076466 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 32139076466 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 24223804784 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 24223804784 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2466827080 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2466827080 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2435399890 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2435399890 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1771498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1771498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 9980703954 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9980703954 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 322190251 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 297082001 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 12538366148 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 35656808127 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 48814446527 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 322190251 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 297082001 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 12538366148 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 35656808127 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 32139076466 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 80953522993 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3468251000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4307274002 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7775525002 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3933705500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3933705500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2568327500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6036578500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2656940000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2656940000 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3468251000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 8240979502 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11709230502 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.248646 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.168188 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5225267500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8693518500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.048951 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.064651 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.102469 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.260124 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.164248 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.766299 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.766299 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.553879 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.553879 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.832725 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.832725 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.761931 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.761931 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.539856 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.539856 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.842277 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.842277 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.205169 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.205169 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.238353 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.172480 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.238353 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.209542 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.209542 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.048951 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.064651 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.102469 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.248281 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.169225 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.048951 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.064651 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.102469 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.248281 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.239706 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 24493.654964 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23901.499212 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 36215.315810 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 36215.315810 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 42441.441675 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 42441.441675 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20873.741897 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20873.741897 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15129.520789 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15129.520789 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 335166.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 335166.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38586.013882 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38586.013882 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27365.353278 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25928.818372 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27365.353278 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 36215.315810 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28813.655266 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.234079 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29610.353001 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24312.917674 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27019.969370 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26137.555619 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48763.839779 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48763.839779 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43092.427427 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43092.427427 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20536.526944 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20536.526944 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14806.302680 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14806.302680 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 590499.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 590499.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42649.300285 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42649.300285 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29610.353001 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24312.917674 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30108.376322 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28384.403274 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29610.353001 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24312.917674 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30108.376322 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48763.839779 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34030.685975 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80423.211594 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154867.794260 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 101099.976553 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147337.658737 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 147337.658737 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80423.211594 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 150945.128116 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 111825.248900 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 10272423 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 8656546 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 26078 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26078 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3634622 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 896357 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1072966 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 744713 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 432357 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 330872 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 471310 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1218200 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1108311 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 9087184 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15490281 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 297199 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 469779 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 25344443 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 288202388 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 584369767 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1031640 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1541304 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 875145099 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 3727007 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 17787477 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 3.192426 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.394206 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 11389901 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9301467 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 38146 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 18033 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3655914 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 950949 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1103178 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 737778 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 440847 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 362789 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 484218 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1248974 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1125262 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 10151888 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15745151 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 304033 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 517558 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 26718630 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 322272916 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 593126965 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1100312 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1778264 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 918278457 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4307980 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 19190741 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.234424 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.423639 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 14364709 80.76% 80.76% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 3422768 19.24% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 14691964 76.56% 76.56% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4498777 23.44% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 17787477 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 11622970748 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 19190741 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 11979643994 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 201159488 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 187059488 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 6810939722 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7611089646 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7629819592 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7824710310 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 168326514 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 166780001 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 277196500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 295551751 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1364,67 +1368,68 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 92509 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 92509 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6608 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 71644 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 92500 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.081081 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 24.659848 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-511 92499 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 115983 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 115983 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11170 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 89969 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 19 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 115964 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.064675 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 22.024176 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-511 115963 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::7168-7679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 92500 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 78261 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 18926.409693 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17150.140934 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 13619.258696 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 77412 98.92% 98.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 724 0.93% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 33 0.04% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 50 0.06% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 28 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 12 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 78261 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 2425306712 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.143168 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.350244 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 2078081352 85.68% 85.68% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 347225360 14.32% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 2425306712 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 71644 91.56% 91.56% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 6608 8.44% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 78252 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 92509 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::total 115964 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 101158 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 19050.238172 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17171.563979 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14858.973019 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 99918 98.77% 98.77% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1061 1.05% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 33 0.03% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 72 0.07% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 53 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 101158 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 3223072220 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.344065 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.475063 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 2114124352 65.59% 65.59% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 1108947868 34.41% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 3223072220 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 89969 88.96% 88.96% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 11170 11.04% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 101139 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 115983 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 92509 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 78252 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 115983 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 101139 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 78252 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 170761 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 101139 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 217122 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 78277454 # DTB read hits -system.cpu1.dtb.read_misses 68245 # DTB read misses -system.cpu1.dtb.write_hits 71517077 # DTB write hits -system.cpu1.dtb.write_misses 24264 # DTB write misses +system.cpu1.dtb.read_hits 83993689 # DTB read hits +system.cpu1.dtb.read_misses 86321 # DTB read misses +system.cpu1.dtb.write_hits 76478778 # DTB write hits +system.cpu1.dtb.write_misses 29662 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 32777 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 42752 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 3876 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4958 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 8314 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 78345699 # DTB read accesses -system.cpu1.dtb.write_accesses 71541341 # DTB write accesses +system.cpu1.dtb.perms_faults 11385 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 84080010 # DTB read accesses +system.cpu1.dtb.write_accesses 76508440 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 149794531 # DTB hits -system.cpu1.dtb.misses 92509 # DTB misses -system.cpu1.dtb.accesses 149887040 # DTB accesses +system.cpu1.dtb.hits 160472467 # DTB hits +system.cpu1.dtb.misses 115983 # DTB misses +system.cpu1.dtb.accesses 160588450 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1454,242 +1459,236 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 60524 # Table walker walks requested -system.cpu1.itb.walker.walksLong 60524 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 415 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54985 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 60524 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 60524 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 60524 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 55400 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 21598.519856 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 19393.747052 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 17485.706336 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 51757 93.42% 93.42% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 2619 4.73% 98.15% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 338 0.61% 98.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 537 0.97% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 24 0.04% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 37 0.07% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 14 0.03% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 28 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 16 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 55400 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 2054805852 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 2054805852 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 2054805852 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 54985 99.25% 99.25% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 415 0.75% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 55400 # Table walker page sizes translated +system.cpu1.itb.walker.walks 60651 # Table walker walks requested +system.cpu1.itb.walker.walksLong 60651 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 616 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54731 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 60651 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 60651 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 60651 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 55347 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 21982.528123 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 19135.216139 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 20466.687075 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 53969 97.51% 97.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1178 2.13% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 42 0.08% 99.71% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 68 0.12% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 60 0.11% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 20 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 55347 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 2053569352 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 2053569352 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 2053569352 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 54731 98.89% 98.89% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 616 1.11% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 55347 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60524 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60524 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60651 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60651 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55400 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55400 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 115924 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 409921957 # ITB inst hits -system.cpu1.itb.inst_misses 60524 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55347 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55347 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 115998 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 446979774 # ITB inst hits +system.cpu1.itb.inst_misses 60651 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 23091 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 29800 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 409982481 # ITB inst accesses -system.cpu1.itb.hits 409921957 # DTB hits -system.cpu1.itb.misses 60524 # DTB misses -system.cpu1.itb.accesses 409982481 # DTB accesses -system.cpu1.numCycles 94735635148 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 447040425 # ITB inst accesses +system.cpu1.itb.hits 446979774 # DTB hits +system.cpu1.itb.misses 60651 # DTB misses +system.cpu1.itb.accesses 447040425 # DTB accesses +system.cpu1.numCycles 95053909934 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 409652284 # Number of instructions committed -system.cpu1.committedOps 483985535 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 446181756 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 565626 # Number of float alu accesses -system.cpu1.num_func_calls 25682090 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 61510479 # number of instructions that are conditional controls -system.cpu1.num_int_insts 446181756 # number of integer instructions -system.cpu1.num_fp_insts 565626 # number of float instructions -system.cpu1.num_int_register_reads 638057436 # number of times the integer registers were read -system.cpu1.num_int_register_writes 352717621 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 886208 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 535956 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 102771786 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 102542500 # number of times the CC registers were written -system.cpu1.num_mem_refs 149782083 # number of memory refs -system.cpu1.num_load_insts 78271508 # Number of load instructions -system.cpu1.num_store_insts 71510575 # Number of store instructions -system.cpu1.num_idle_cycles 93767065494.048019 # Number of idle cycles -system.cpu1.num_busy_cycles 968569653.951980 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010224 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989776 # Percentage of idle cycles -system.cpu1.Branches 91673037 # Number of branches fetched -system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 333338821 68.84% 68.84% # Class of executed instruction -system.cpu1.op_class::IntMult 986884 0.20% 69.04% # Class of executed instruction -system.cpu1.op_class::IntDiv 58271 0.01% 69.05% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.05% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 89216 0.02% 69.07% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.07% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.07% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.07% # Class of executed instruction -system.cpu1.op_class::MemRead 78271508 16.16% 85.23% # Class of executed instruction -system.cpu1.op_class::MemWrite 71510575 14.77% 100.00% # Class of executed instruction +system.cpu1.committedInsts 446673984 # Number of instructions committed +system.cpu1.committedOps 525768473 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 482657433 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 472663 # Number of float alu accesses +system.cpu1.num_func_calls 26533376 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 68272280 # number of instructions that are conditional controls +system.cpu1.num_int_insts 482657433 # number of integer instructions +system.cpu1.num_fp_insts 472663 # number of float instructions +system.cpu1.num_int_register_reads 706740468 # number of times the integer registers were read +system.cpu1.num_int_register_writes 383340050 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 750974 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 430296 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 118015071 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 117677935 # number of times the CC registers were written +system.cpu1.num_mem_refs 160465117 # number of memory refs +system.cpu1.num_load_insts 83993061 # Number of load instructions +system.cpu1.num_store_insts 76472056 # Number of store instructions +system.cpu1.num_idle_cycles 93999959015.450027 # Number of idle cycles +system.cpu1.num_busy_cycles 1053950918.549978 # Number of busy cycles +system.cpu1.not_idle_fraction 0.011088 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.988912 # Percentage of idle cycles +system.cpu1.Branches 99666047 # Number of branches fetched +system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 364374913 69.26% 69.26% # Class of executed instruction +system.cpu1.op_class::IntMult 1108574 0.21% 69.47% # Class of executed instruction +system.cpu1.op_class::IntDiv 57501 0.01% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 68224 0.01% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::MemRead 83993061 15.97% 85.46% # Class of executed instruction +system.cpu1.op_class::MemWrite 76472056 14.54% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 484255317 # Class of executed instruction +system.cpu1.op_class::total 526074372 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5204 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 4752540 # number of replacements -system.cpu1.dcache.tags.tagsinuse 455.880794 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 144856637 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4753051 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 30.476559 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8382286333500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.880794 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890392 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.890392 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 304369060 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 304369060 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 73044937 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 73044937 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 67886662 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 67886662 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 184038 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 184038 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 188938 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 188938 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1611925 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1611925 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1592857 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1592857 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 140931599 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 140931599 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 141115637 # number of overall hits -system.cpu1.dcache.overall_hits::total 141115637 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2767627 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2767627 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1154762 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1154762 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 498783 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 498783 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 496292 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 496292 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158321 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 158321 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 176268 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 176268 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 3922389 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 3922389 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 4421172 # number of overall misses -system.cpu1.dcache.overall_misses::total 4421172 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 37645623046 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 37645623046 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 19534966036 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 19534966036 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11881656902 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11881656902 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2306877268 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2306877268 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3770896575 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3770896575 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1887000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1887000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 57180589082 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 57180589082 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 57180589082 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 57180589082 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 75812564 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 75812564 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 69041424 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 69041424 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 682821 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 682821 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 685230 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 685230 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1770246 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1770246 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1769125 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1769125 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 144853988 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 144853988 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 145536809 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 145536809 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036506 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036506 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.016726 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.016726 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.730474 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.730474 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.724271 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.724271 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089434 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089434 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099636 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099636 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027078 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.027078 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030378 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.030378 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13602.130289 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13602.130289 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16916.876409 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16916.876409 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 23940.859216 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 23940.859216 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14570.886162 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14570.886162 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21392.973058 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21392.973058 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 14059 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 5413042 # number of replacements +system.cpu1.dcache.tags.tagsinuse 455.092206 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 154856630 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5413554 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.605354 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8382280704500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.092206 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.888852 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.888852 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 419 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 326337345 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 326337345 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 78172197 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 78172197 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 72471418 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 72471418 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 183858 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 183858 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 197039 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 197039 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1730902 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1730902 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1704111 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1704111 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 150643615 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 150643615 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 150827473 # number of overall hits +system.cpu1.dcache.overall_hits::total 150827473 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3026410 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3026410 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1374450 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1374450 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 681215 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 681215 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 497314 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 497314 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 177400 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 177400 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 202765 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 202765 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4400860 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4400860 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5082075 # number of overall misses +system.cpu1.dcache.overall_misses::total 5082075 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 44105582717 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 44105582717 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 23281173553 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 23281173553 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 13579881027 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 13579881027 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2688373759 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2688373759 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4348203540 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4348203540 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1867000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1867000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 67386756270 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 67386756270 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 67386756270 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 67386756270 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 81198607 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 81198607 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 73845868 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 73845868 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 865073 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 865073 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 694353 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 694353 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1908302 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1908302 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1906876 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1906876 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 155044475 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 155044475 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 155909548 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 155909548 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037272 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.037272 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018612 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018612 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.787465 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.787465 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.716226 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.716226 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092962 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092962 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106334 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106334 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028385 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.028385 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032596 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.032596 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14573.564956 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14573.564956 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16938.537999 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16938.537999 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27306.452316 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27306.452316 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15154.305293 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15154.305293 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21444.546840 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21444.546840 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14578.000571 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14578.000571 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12933.355473 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 12933.355473 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15312.179045 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15312.179045 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13259.693387 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13259.693387 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1698,152 +1697,158 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3063492 # number of writebacks -system.cpu1.dcache.writebacks::total 3063492 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 11545 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 11545 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 352 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 352 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 46682 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46682 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 11897 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 11897 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 11897 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 11897 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2756082 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2756082 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1154410 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1154410 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 498783 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 498783 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 496292 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 496292 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 111639 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 111639 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 176268 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 176268 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 3910492 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 3910492 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4409275 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4409275 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 32859790378 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 32859790378 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 17743172214 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 17743172214 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 9770846491 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 9770846491 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11134079098 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11134079098 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1396307998 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1396307998 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3498646925 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3498646925 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1819500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1819500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 50602962592 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 50602962592 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 60373809083 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 60373809083 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1936116751 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1936116751 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2164016499 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2164016499 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4100133250 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4100133250 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036354 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036354 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016721 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.016721 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.730474 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.730474 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.724271 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.724271 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063064 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063064 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099636 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099636 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026996 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026996 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030297 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030297 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11922.646125 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11922.646125 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15369.905158 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15369.905158 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19589.373517 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19589.373517 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 22434.532690 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22434.532690 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12507.349564 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12507.349564 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19848.451931 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19848.451931 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3550271 # number of writebacks +system.cpu1.dcache.writebacks::total 3550271 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18006 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 18006 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 425 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 425 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44886 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44886 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 18431 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 18431 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 18431 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 18431 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3008404 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3008404 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1374025 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1374025 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 681215 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 681215 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 497314 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 497314 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 132514 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 132514 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202765 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 202765 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4382429 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4382429 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5063644 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5063644 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 21725 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 21725 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 20113 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 20113 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 41838 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 41838 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38446720676 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38446720676 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21137642197 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21137642197 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13605784836 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13605784836 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12830642973 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 12830642973 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1690394742 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1690394742 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4033173960 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4033173960 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1807000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1807000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 59584362873 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 59584362873 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 73190147709 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 73190147709 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3727466501 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3727466501 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3465674500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3465674500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7193141001 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7193141001 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037050 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037050 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018607 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018607 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.787465 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.787465 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.716226 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.716226 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069441 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069441 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106334 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106334 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028266 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028266 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032478 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032478 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12779.773154 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12779.773154 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15383.739158 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15383.739158 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19972.820381 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19972.820381 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25799.882917 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25799.882917 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12756.348325 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12756.348325 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19890.878406 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19890.878406 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12940.305873 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12940.305873 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13692.457169 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13692.457169 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13596.195825 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13596.195825 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14454.046870 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14454.046870 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171574.982785 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171574.982785 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 172310.172525 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172310.172525 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171928.414384 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 171928.414384 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5523110 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.341944 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 404398330 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5523622 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 73.212528 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8382258847250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.341944 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969418 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969418 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 4892397 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.394395 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 442086860 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4892909 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 90.352561 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8382252985250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.394395 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969520 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969520 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 825367541 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 825367541 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 404398330 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 404398330 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 404398330 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 404398330 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 404398330 # number of overall hits -system.cpu1.icache.overall_hits::total 404398330 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5523627 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5523627 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5523627 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5523627 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5523627 # number of overall misses -system.cpu1.icache.overall_misses::total 5523627 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54612807078 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 54612807078 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 54612807078 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 54612807078 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 54612807078 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 54612807078 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 409921957 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 409921957 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 409921957 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 409921957 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 409921957 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 409921957 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013475 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.013475 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013475 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.013475 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013475 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.013475 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9887.127983 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9887.127983 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9887.127983 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9887.127983 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9887.127983 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9887.127983 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 898852462 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 898852462 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 442086860 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 442086860 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 442086860 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 442086860 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 442086860 # number of overall hits +system.cpu1.icache.overall_hits::total 442086860 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4892914 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 4892914 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 4892914 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 4892914 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 4892914 # number of overall misses +system.cpu1.icache.overall_misses::total 4892914 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 51771462698 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 51771462698 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 51771462698 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 51771462698 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 51771462698 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 51771462698 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 446979774 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 446979774 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 446979774 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 446979774 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 446979774 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 446979774 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.010947 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.010947 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.010947 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.010947 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.010947 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.010947 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10580.905918 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10580.905918 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10580.905918 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10580.905918 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10580.905918 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10580.905918 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1852,236 +1857,243 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5523627 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5523627 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5523627 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5523627 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5523627 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5523627 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 49075741422 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 49075741422 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 49075741422 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 49075741422 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 49075741422 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 49075741422 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9805750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9805750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9805750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 9805750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013475 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.013475 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.013475 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8884.695042 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8884.695042 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8884.695042 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4892914 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 4892914 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 4892914 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 4892914 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 4892914 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 4892914 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable +system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable +system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses +system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 46862593334 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 46862593334 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 46862593334 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 46862593334 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 46862593334 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 46862593334 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10105750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10105750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10105750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10105750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.010947 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.010947 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.010947 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.010947 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.010947 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.010947 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9577.645005 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9577.645005 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9577.645005 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9577.645005 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9577.645005 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9577.645005 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91870.454545 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 91870.454545 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91870.454545 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 91870.454545 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 5870481 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 5870524 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 29 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7631682 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7631760 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 35 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 773012 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 1638473 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13410.207774 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 10772955 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 1654198 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 6.512494 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10040948806000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5186.730932 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 70.626422 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 88.861590 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3789.090493 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3453.027216 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 821.871120 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.316573 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004311 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005424 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.231268 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.210756 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.050163 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.818494 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1616 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14027 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 271 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 744 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 601 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 43 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2440 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6290 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5121 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.098633 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005005 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.856140 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 229858181 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 229858181 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 196843 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 146711 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5082589 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2590406 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 8016549 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3063492 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3063492 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 265137 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 265137 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 50742 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 50742 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 28295 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 28295 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 777406 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 777406 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 196843 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 146711 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 5082589 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3367812 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8793955 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 196843 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 146711 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 5082589 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3367812 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8793955 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9130 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7601 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 441038 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 776098 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1233867 # number of ReadReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 229595 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 229595 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 120541 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 120541 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 147968 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 147968 # number of SCUpgradeReq misses +system.cpu1.l2cache.prefetcher.pfSpanPage 935080 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2142260 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13497.078408 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 10799538 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2158371 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 5.003560 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9893608612000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5297.531895 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 78.016993 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 87.104378 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3470.735386 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3768.987855 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 794.701900 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.323336 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004762 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005316 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.211837 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.230041 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048505 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.823796 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1633 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 75 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14403 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 31 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 128 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 713 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 761 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 32 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 43 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1571 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5509 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 6302 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.099670 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004578 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.879089 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 240281832 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 240281832 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 248777 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141659 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4360207 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 2869888 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 7620531 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 3550270 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 3550270 # number of Writeback hits +system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 228063 # number of WriteInvalidateReq hits +system.cpu1.l2cache.WriteInvalidateReq_hits::total 228063 # number of WriteInvalidateReq hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 73786 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 73786 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 35221 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 35221 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 953536 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 953536 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 248777 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 141659 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 4360207 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3823424 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 8574067 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 248777 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 141659 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 4360207 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3823424 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8574067 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9961 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7958 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 532707 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 952245 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 1502871 # number of ReadReq misses +system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses +system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses +system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 267701 # number of WriteInvalidateReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::total 267701 # number of WriteInvalidateReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 120750 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 120750 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 167539 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 167539 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 207551 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 207551 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9130 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7601 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 441038 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 983649 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1441418 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9130 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7601 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 441038 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 983649 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1441418 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 287537248 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 274641499 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 13255864672 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 23821498253 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 37639541672 # number of ReadReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 209637116 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 209637116 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2569493734 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2569493734 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3076594441 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3076594441 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1773498 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1773498 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 8057830380 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 8057830380 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 287537248 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 274641499 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 13255864672 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 31879328633 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 45697372052 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 287537248 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 274641499 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 13255864672 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 31879328633 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 45697372052 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 205973 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 154312 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5523627 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3366504 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 9250416 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3063492 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3063492 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 494732 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::total 494732 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 171283 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 171283 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 176263 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 176263 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 227703 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 227703 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9961 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7958 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 532707 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1179948 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1730574 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9961 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7958 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 532707 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1179948 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1730574 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 394640977 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 358915726 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 16056528318 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 31264991014 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 48075076035 # number of ReadReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 240883663 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 240883663 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2642176746 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 2642176746 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3519293594 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3519293594 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1767000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1767000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9869071556 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 9869071556 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 394640977 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 358915726 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16056528318 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 41134062570 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 57944147591 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 394640977 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 358915726 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16056528318 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 41134062570 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 57944147591 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 258738 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 149617 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4892914 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3822133 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 9123402 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 3550271 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 3550271 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 495764 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::total 495764 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 194536 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 194536 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 202760 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 202760 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 984957 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 984957 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 205973 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 154312 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 5523627 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4351461 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10235373 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 205973 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 154312 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 5523627 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4351461 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10235373 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.044326 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.049257 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.079846 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.230535 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.133385 # miss rate for ReadReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.464080 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.464080 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.703753 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.703753 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.839473 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.839473 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1181239 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1181239 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 258738 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 149617 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 4892914 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 5003372 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 10304641 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 258738 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 149617 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 4892914 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 5003372 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 10304641 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.038498 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.053189 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.108873 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.249140 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.164727 # miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.539977 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.539977 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.620708 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.620708 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.826292 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.826292 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.210721 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.210721 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.044326 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.049257 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.079846 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.226050 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.140827 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.044326 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.049257 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.079846 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.226050 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.140827 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 31493.674480 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36132.285094 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30056.060185 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 30693.930732 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 30505.347555 # average ReadReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 913.073525 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 913.073525 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21316.346587 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21316.346587 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20792.295909 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20792.295909 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 354699.600000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 354699.600000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38823.375363 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38823.375363 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 31493.674480 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36132.285094 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30056.060185 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32409.252318 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 31703.067432 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 31493.674480 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36132.285094 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30056.060185 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32409.252318 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 31703.067432 # average overall miss latency +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.192766 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.192766 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.038498 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.053189 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.108873 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.235831 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.167941 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.038498 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.053189 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.108873 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.235831 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.167941 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39618.610280 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 45101.247298 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30141.387889 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32832.927465 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31988.824081 # average ReadReq miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 899.823546 # average WriteInvalidateReq miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 899.823546 # average WriteInvalidateReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21881.380919 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21881.380919 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21005.817117 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21005.817117 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 353400 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 353400 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43341.860037 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43341.860037 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39618.610280 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 45101.247298 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30141.387889 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34860.911303 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 33482.617670 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39618.610280 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 45101.247298 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30141.387889 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34860.911303 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 33482.617670 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2090,202 +2102,214 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 764216 # number of writebacks -system.cpu1.l2cache.writebacks::total 764216 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 323 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 323 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 2534 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 2534 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 2857 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 2857 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 2857 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 2857 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9130 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7601 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 441038 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 775775 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 1233544 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 524912 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 524912 # number of HardPFReq MSHR misses -system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 229595 # number of WriteInvalidateReq MSHR misses -system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 229595 # number of WriteInvalidateReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 120541 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 120541 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 147968 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 147968 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.writebacks::writebacks 1053113 # number of writebacks +system.cpu1.l2cache.writebacks::total 1053113 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 432 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 432 # number of ReadReq MSHR hits +system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 1 # number of WriteInvalidateReq MSHR hits +system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 1 # number of WriteInvalidateReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 7197 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 7197 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7629 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 7629 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7629 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 7629 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9961 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7958 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 532707 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 951813 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 1502439 # number of ReadReq MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 707306 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 707306 # number of HardPFReq MSHR misses +system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 267700 # number of WriteInvalidateReq MSHR misses +system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 267700 # number of WriteInvalidateReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 120750 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 120750 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 167539 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 167539 # number of SCUpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 205017 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 205017 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9130 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7601 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 441038 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 980792 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 1438561 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9130 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7601 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 441038 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 980792 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 524912 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 1963473 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 227841252 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 224849501 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 10375497328 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 18713747169 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 29541935250 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 17727784992 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 17727784992 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 7402905507 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 7402905507 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2380480811 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2380480811 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2176947075 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2176947075 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1480998 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1480998 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 6436785468 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 6436785468 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 227841252 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 224849501 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 10375497328 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 25150532637 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 35978720718 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 227841252 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 224849501 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 10375497328 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 25150532637 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 17727784992 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 53706505710 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8938250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1841380999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1850319249 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2067303001 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2067303001 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8938250 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3908684000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3917622250 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.230439 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.133350 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 220506 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 220506 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9961 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7958 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 532707 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1172319 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 1722945 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9961 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7958 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 532707 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1172319 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 707306 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 2430251 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 21725 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 21835 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 20113 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 20113 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 41838 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 41948 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 329233523 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 306561274 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 12577785182 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 24989286886 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 38202866865 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 35407537019 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 35407537019 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 9092223824 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 9092223824 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2448079564 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2448079564 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2512705540 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2512705540 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1507000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1507000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7591763498 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7591763498 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 329233523 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 306561274 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 12577785182 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 32581050384 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 45794630363 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 329233523 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 306561274 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 12577785182 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 32581050384 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 35407537019 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 81202167382 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9241250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3553660750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3562902000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3314826000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3314826000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9241250 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 6868486750 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 6877728000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038498 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.053189 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.108873 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.249027 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.164680 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.464080 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.464080 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.703753 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.703753 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.839473 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.839473 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.539975 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.539975 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.620708 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.620708 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.826292 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.826292 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.208148 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.208148 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.225394 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.140548 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.225394 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.186673 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.186673 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038498 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053189 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.108873 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.234306 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.167201 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038498 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053189 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.108873 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.234306 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191832 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 24122.647893 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 23948.829754 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33772.870485 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32243.321967 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32243.321967 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19748.308136 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19748.308136 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14712.282892 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14712.282892 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 296199.600000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 296199.600000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31396.349903 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31396.349903 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25010.215568 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27352.810917 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.235840 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23611.075473 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26254.408047 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25427.233229 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50059.715341 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50059.715341 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 33964.227957 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33964.227957 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20273.950841 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20273.950841 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14997.735095 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14997.735095 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 301400 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 301400 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34428.829592 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34428.829592 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23611.075473 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27791.966507 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26579.275811 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23611.075473 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27791.966507 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50059.715341 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33413.078477 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84011.363636 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163574.718067 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163173.895123 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 164810.122806 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164810.122806 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84011.363636 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 164168.620632 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 163958.424716 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 11346555 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9442060 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 12895 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 12895 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3063492 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 747367 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1164315 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 494732 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 387368 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 328581 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 412328 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1123330 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 992188 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11047474 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13661084 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 335346 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 476365 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 25520269 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 353512568 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 512414548 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1234496 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1647784 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 868809396 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4168573 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 18149089 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 3.215812 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.411385 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 11407818 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9339972 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 38146 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 20113 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3550271 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 1013669 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1157980 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 495764 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 395206 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 367201 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 457834 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1341582 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1187599 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9786048 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15579584 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 330806 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 594855 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 26291293 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 313146936 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 585201818 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1196936 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2069904 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 901615594 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4634762 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 19271924 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.253755 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.435159 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 14232289 78.42% 78.42% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 3916800 21.58% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 14381570 74.62% 74.62% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 4890354 25.38% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 18149089 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 10693279996 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 19271924 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 11505600998 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 176128990 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 168563993 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8292291078 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7347478432 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7012668647 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 8042476622 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 181227501 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 181503274 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 270567252 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 336447522 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40336 # Transaction distribution -system.iobus.trans_dist::ReadResp 40336 # Transaction distribution -system.iobus.trans_dist::WriteReq 136623 # Transaction distribution -system.iobus.trans_dist::WriteResp 29895 # Transaction distribution +system.iobus.trans_dist::ReadReq 40366 # Transaction distribution +system.iobus.trans_dist::ReadResp 40366 # Transaction distribution +system.iobus.trans_dist::WriteReq 136641 # Transaction distribution +system.iobus.trans_dist::WriteResp 29913 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2300,13 +2324,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122628 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122716 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231218 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231218 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354014 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2321,13 +2345,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155735 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338856 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155823 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496677 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36212000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496797 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36274000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2355,71 +2379,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 607542087 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607607215 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92736000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92806000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148516061 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148515621 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115606 # number of replacements -system.iocache.tags.tagsinuse 11.280528 # Cycle average of tags in use +system.iocache.tags.replacements 115613 # number of replacements +system.iocache.tags.tagsinuse 11.298152 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115622 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115629 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9179145722000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.421794 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.858734 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463862 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.241171 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705033 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9179138787000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.392909 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.905243 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.462057 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.244078 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706135 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040802 # Number of tag accesses -system.iocache.tags.data_accesses 1040802 # Number of data accesses +system.iocache.tags.tag_accesses 1040838 # Number of tag accesses +system.iocache.tags.data_accesses 1040838 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8881 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8918 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses -system.iocache.demand_misses::total 8917 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8881 # number of demand (read+write) misses +system.iocache.demand_misses::total 8921 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8877 # number of overall misses -system.iocache.overall_misses::total 8917 # number of overall misses +system.iocache.overall_misses::realview.ide 8881 # number of overall misses +system.iocache.overall_misses::total 8921 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1629440754 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1634636254 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1629816861 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1635012361 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19888935272 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19888935272 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19901379733 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19901379733 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1629440754 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1635005254 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1629816861 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1635381361 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1629440754 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1635005254 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1629816861 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1635381361 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8881 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8918 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8881 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8921 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8881 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8921 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2434,54 +2458,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 183557.593106 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 183378.534216 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 183517.268438 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 183338.457165 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186351.615996 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 186351.615996 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186468.215773 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 186468.215773 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 183557.593106 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183358.220702 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 183517.268438 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183318.166237 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 183557.593106 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183358.220702 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 110662 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 183517.268438 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183318.166237 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 110961 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16220 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16203 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.822565 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.848176 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106699 # number of writebacks -system.iocache.writebacks::total 106699 # number of writebacks +system.iocache.writebacks::writebacks 106702 # number of writebacks +system.iocache.writebacks::total 106702 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8877 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8914 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8881 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8918 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8877 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8917 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8881 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8921 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8877 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8917 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8881 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8921 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1166654804 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1169925304 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1166890035 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1170160535 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14339007344 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14339007344 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14351455801 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14351455801 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1166654804 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1170138304 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1166890035 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1170373535 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1166654804 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1170138304 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1166890035 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1170373535 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2496,626 +2520,640 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131424.445646 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 131245.827238 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131391.739106 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 131213.336510 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134350.942058 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134350.942058 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134467.579276 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134467.579276 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 131424.445646 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131225.558372 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 131391.739106 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131193.087658 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 131424.445646 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131225.558372 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 131391.739106 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131193.087658 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1063912 # number of replacements -system.l2c.tags.tagsinuse 64178.177670 # Cycle average of tags in use -system.l2c.tags.total_refs 3766892 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1123413 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.353079 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 11093199000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 24092.358885 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 75.949373 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 107.097830 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4212.805606 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 7550.293396 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7226.795277 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 149.211397 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 222.509709 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4405.039325 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 7865.744621 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8270.372252 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.367620 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001159 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.001634 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.064282 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.115208 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.110272 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002277 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003395 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.067216 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.120022 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.126196 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.979281 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 9644 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 191 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49666 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 226 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9286 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 191 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1430 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4883 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 43236 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.147156 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.002914 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.757843 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 50574940 # Number of tag accesses -system.l2c.tags.data_accesses 50574940 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5180 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4259 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 469863 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 537542 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 313027 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4490 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3587 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 401752 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 405704 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 231220 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2376624 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2047649 # number of Writeback hits -system.l2c.Writeback_hits::total 2047649 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 135493 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 115685 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 251178 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 31239 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 22507 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 53746 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6431 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5062 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 11493 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 47681 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 46115 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 93796 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5180 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4259 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 469863 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 585223 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 313027 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4490 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3587 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 401752 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 451819 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 231220 # number of demand (read+write) hits -system.l2c.demand_hits::total 2470420 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5180 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4259 # number of overall hits -system.l2c.overall_hits::cpu0.inst 469863 # number of overall hits -system.l2c.overall_hits::cpu0.data 585223 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 313027 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4490 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3587 # number of overall hits -system.l2c.overall_hits::cpu1.inst 401752 # number of overall hits -system.l2c.overall_hits::cpu1.data 451819 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 231220 # number of overall hits -system.l2c.overall_hits::total 2470420 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 577 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 634 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 41076 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 94183 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 149529 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1129 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1344 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 39286 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 84710 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 118679 # number of ReadReq misses -system.l2c.ReadReq_misses::total 531147 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 427179 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 105657 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 532836 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 47914 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 38699 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 86613 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 10572 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 7951 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 18523 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 64089 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 43672 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 107761 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 577 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 634 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 41076 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 158272 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 149529 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1129 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1344 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 39286 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 128382 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 118679 # number of demand (read+write) misses -system.l2c.demand_misses::total 638908 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 577 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 634 # number of overall misses -system.l2c.overall_misses::cpu0.inst 41076 # number of overall misses -system.l2c.overall_misses::cpu0.data 158272 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 149529 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1129 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1344 # number of overall misses -system.l2c.overall_misses::cpu1.inst 39286 # number of overall misses -system.l2c.overall_misses::cpu1.data 128382 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 118679 # number of overall misses -system.l2c.overall_misses::total 638908 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 51297750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 55466264 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 3464868273 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 8461586857 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18227791613 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 98269250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 120308250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 3289147097 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 7432991468 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 13847609855 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 55049336677 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 56781694 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 44775578 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 101557272 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 267824472 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 195648800 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 463473272 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 46262535 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 41400197 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 87662732 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5583608052 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3566659435 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9150267487 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 51297750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 55466264 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 3464868273 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 14045194909 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18227791613 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 98269250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 120308250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 3289147097 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 10999650903 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 13847609855 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 64199604164 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 51297750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 55466264 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 3464868273 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 14045194909 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18227791613 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 98269250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 120308250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 3289147097 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 10999650903 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 13847609855 # number of overall miss cycles -system.l2c.overall_miss_latency::total 64199604164 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 5757 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 4893 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 510939 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 631725 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 462556 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5619 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 4931 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 441038 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 490414 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 349899 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2907771 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 2047649 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2047649 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 562672 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 221342 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 784014 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 79153 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 61206 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 140359 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 17003 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 13013 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 30016 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111770 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 89787 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 201557 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 5757 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 4893 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 510939 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 743495 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 462556 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5619 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 4931 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 441038 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 580201 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 349899 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3109328 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 5757 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 4893 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 510939 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 743495 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 462556 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5619 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 4931 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 441038 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 580201 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 349899 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3109328 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.100226 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.129573 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.080393 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.149089 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.323267 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.200925 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.272561 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.089076 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.172732 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.339181 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.182665 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.759197 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.477347 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.679626 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.605334 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.632275 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.617082 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.621773 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.611004 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.617104 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.573401 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.486396 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.534643 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.100226 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.129573 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.080393 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.212876 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.323267 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.200925 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.272561 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.089076 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.221272 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.339181 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.205481 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.100226 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.129573 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.080393 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.212876 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.323267 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.200925 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.272561 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.089076 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.221272 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.339181 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.205481 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 88904.246101 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 87486.220820 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84352.621312 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 89841.976333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 121901.381090 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87040.965456 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89515.066964 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83723.135392 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 87746.328273 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 116681.214495 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 103642.375231 # average ReadReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 132.922484 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 423.782409 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::total 190.597617 # average WriteInvalidateReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5589.691364 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5055.655185 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 5351.082078 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4375.949205 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5206.916992 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 4732.642229 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87122.720779 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81669.248832 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 84912.607409 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88904.246101 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87486.220820 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 84352.621312 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 88740.869573 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 121901.381090 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87040.965456 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89515.066964 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 83723.135392 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 85679.074193 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 116681.214495 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 100483.331190 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88904.246101 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87486.220820 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 84352.621312 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 88740.869573 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 121901.381090 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87040.965456 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89515.066964 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 83723.135392 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 85679.074193 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 116681.214495 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 100483.331190 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 154 # number of cycles access was blocked +system.l2c.tags.replacements 1448041 # number of replacements +system.l2c.tags.tagsinuse 64131.287175 # Cycle average of tags in use +system.l2c.tags.total_refs 4245095 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1507106 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.816720 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 11172879000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 19347.050639 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 116.894544 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 154.865125 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3200.431152 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 7856.746302 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9704.320174 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 227.109782 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 297.906768 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3324.337079 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 8639.334854 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11262.290757 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.295213 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001784 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.002363 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.048835 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.119884 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.148076 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003465 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.004546 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.050725 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.131826 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.171849 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.978566 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10716 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 318 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 48031 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 38 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 439 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 10237 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 318 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1326 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4887 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 41702 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.163513 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.004852 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.732895 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 58352089 # Number of tag accesses +system.l2c.tags.data_accesses 58352089 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 5485 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4305 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 465111 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 536784 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 265347 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5257 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3875 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 485070 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 556488 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 285641 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2613363 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 2374848 # number of Writeback hits +system.l2c.Writeback_hits::total 2374848 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 123464 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 121626 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 245090 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 24332 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 31013 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 55345 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 5518 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 6203 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 11721 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 54595 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 49708 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 104303 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 5485 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4305 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 465111 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 591379 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 265347 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5257 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3875 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 485070 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 606196 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 285641 # number of demand (read+write) hits +system.l2c.demand_hits::total 2717666 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 5485 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4305 # number of overall hits +system.l2c.overall_hits::cpu0.inst 465111 # number of overall hits +system.l2c.overall_hits::cpu0.data 591379 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 265347 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5257 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3875 # number of overall hits +system.l2c.overall_hits::cpu1.inst 485070 # number of overall hits +system.l2c.overall_hits::cpu1.data 606196 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 285641 # number of overall hits +system.l2c.overall_hits::total 2717666 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 1889 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1930 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 50597 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 131294 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 216525 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 2185 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 2247 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 47637 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 122248 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 240093 # number of ReadReq misses +system.l2c.ReadReq_misses::total 816645 # number of ReadReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.data 431801 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.data 136823 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::total 568624 # number of WriteInvalidateReq misses +system.l2c.UpgradeReq_misses::cpu0.data 44180 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 43907 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 88087 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 9646 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 11002 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 20648 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 78703 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 53921 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 132624 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 1889 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1930 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 50597 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 209997 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 216525 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 2185 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2247 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 47637 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 176169 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 240093 # number of demand (read+write) misses +system.l2c.demand_misses::total 949269 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 1889 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1930 # number of overall misses +system.l2c.overall_misses::cpu0.inst 50597 # number of overall misses +system.l2c.overall_misses::cpu0.data 209997 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 216525 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 2185 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2247 # number of overall misses +system.l2c.overall_misses::cpu1.inst 47637 # number of overall misses +system.l2c.overall_misses::cpu1.data 176169 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 240093 # number of overall misses +system.l2c.overall_misses::total 949269 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 170785750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 176668500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 4301026862 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 11907133634 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 27854403488 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 192678771 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 202084771 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 4020493910 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 11059922872 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 30832642419 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 90717840977 # number of ReadReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 51822854 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 41218687 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::total 93041541 # number of WriteInvalidateReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 233428095 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 271641854 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 505069949 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 51474876 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 56093222 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 107568098 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6900295884 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4492674608 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 11392970492 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 170785750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 176668500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 4301026862 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 18807429518 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 27854403488 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 192678771 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 202084771 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 4020493910 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 15552597480 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 30832642419 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 102110811469 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 170785750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 176668500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 4301026862 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 18807429518 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 27854403488 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 192678771 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 202084771 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 4020493910 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 15552597480 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 30832642419 # number of overall miss cycles +system.l2c.overall_miss_latency::total 102110811469 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 7374 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 6235 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 515708 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 668078 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 481872 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 7442 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6122 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 532707 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 678736 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 525734 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 3430008 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 2374848 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 2374848 # number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.data 555265 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.data 258449 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 813714 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 68512 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 74920 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 143432 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 15164 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 17205 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 32369 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 133298 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 103629 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 236927 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 7374 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6235 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 515708 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 801376 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 481872 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 7442 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6122 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 532707 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 782365 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 525734 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3666935 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 7374 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6235 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 515708 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 801376 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 481872 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 7442 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6122 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 532707 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 782365 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 525734 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3666935 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.256170 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.309543 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.098112 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.196525 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.449341 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.293604 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.367037 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.089424 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.180111 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.456682 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.238088 # miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.777649 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.529400 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::total 0.698801 # miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.644851 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.586052 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.614138 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.636112 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.639465 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.637894 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.590429 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.520327 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.559767 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.256170 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.309543 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.098112 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.262046 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.449341 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.293604 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.367037 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.089424 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.225175 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.456682 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.258873 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.256170 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.309543 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.098112 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.262046 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.449341 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.293604 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.367037 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.089424 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.225175 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.456682 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.258873 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 90410.667020 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 91538.082902 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 85005.570726 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 90690.615215 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 128642.897993 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88182.503890 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89935.367601 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84398.553855 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 90471.196846 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 128419.580825 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 111086.017764 # average ReadReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 120.015595 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 301.255542 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::total 163.625772 # average WriteInvalidateReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5283.569375 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6186.755050 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5733.762632 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5336.396019 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5098.456826 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 5209.613425 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87675.131621 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83319.571373 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 85904.289510 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90410.667020 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 91538.082902 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 85005.570726 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 89560.467616 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 128642.897993 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88182.503890 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89935.367601 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 84398.553855 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 88282.260103 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 128419.580825 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 107567.835323 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90410.667020 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 91538.082902 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 85005.570726 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 89560.467616 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 128642.897993 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88182.503890 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89935.367601 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 84398.553855 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 88282.260103 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 128419.580825 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 107567.835323 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 328 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 14 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 154 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 23.428571 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 850996 # number of writebacks -system.l2c.writebacks::total 850996 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 92 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 20 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 88 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 21 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 92 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 20 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 88 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 21 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 92 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 20 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 88 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 21 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 223 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 577 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 634 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 40984 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 94163 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 149527 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1129 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1344 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 39198 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 84689 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 118679 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 530924 # number of ReadReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 427179 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 105657 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::total 532836 # number of WriteInvalidateReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 47914 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 38699 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 86613 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 10572 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 7951 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 18523 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 64089 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 43672 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 107761 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 577 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 634 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 40984 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 158252 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 149527 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 1129 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1344 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 39198 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 128361 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 118679 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 638685 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 577 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 634 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 40984 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 158252 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 149527 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 1129 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1344 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 39198 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 128361 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 118679 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 638685 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 44023250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 47468736 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 2944278477 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 7281223143 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16390258603 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 84050250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 103357750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2790521653 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 6370080782 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 12386298511 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 48441561155 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 13848705306 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 3323050924 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::total 17171756230 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 851924300 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 688614575 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 1540538875 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 188348548 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 142101429 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 330449977 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4782492948 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3019981565 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7802474513 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 44023250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 47468736 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 2944278477 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 12063716091 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16390258603 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 84050250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 103357750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 2790521653 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 9390062347 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 12386298511 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 56244035668 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 44023250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 47468736 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 2944278477 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 12063716091 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16390258603 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 84050250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 103357750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 2790521653 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 9390062347 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 12386298511 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 56244035668 # number of overall MSHR miss cycles +system.l2c.writebacks::writebacks 1121159 # number of writebacks +system.l2c.writebacks::total 1121159 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 120 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 25 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 120 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 30 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 296 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 120 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 25 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 120 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 30 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 296 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 120 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 25 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 120 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 30 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 296 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1889 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1930 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 50477 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 131269 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 216525 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2184 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2247 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 47517 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 122218 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 240093 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 816349 # number of ReadReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 431801 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 136823 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::total 568624 # number of WriteInvalidateReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 44180 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 43907 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 88087 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9646 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11002 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 20648 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 78703 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 53921 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 132624 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 1889 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 1930 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 50477 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 209972 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 216525 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 2184 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 2247 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 47517 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 176139 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 240093 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 948973 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 1889 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 1930 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 50477 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 209972 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 216525 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 2184 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 2247 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 47517 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 176139 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 240093 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 948973 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16584 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 21723 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 81542 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 18033 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 20113 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 38146 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34617 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 41836 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 119688 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 146937750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 152273500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 3658828888 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10259837116 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 25193281260 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 165099729 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 173733729 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3415229090 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 9525126628 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27878676483 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 80569024173 # number of ReadReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 13996588148 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 4310102313 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::total 18306690461 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 786063539 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 780665261 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1566728800 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 172133111 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 196209961 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 368343072 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5916837616 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3817995892 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 9734833508 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 146937750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 152273500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 3658828888 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 16176674732 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 25193281260 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 165099729 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 173733729 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3415229090 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 13343122520 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 27878676483 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 90303857681 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 146937750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 152273500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 3658828888 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 16176674732 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 25193281260 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 165099729 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 173733729 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 3415229090 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 13343122520 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27878676483 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 90303857681 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2605759500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3774730500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6744750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1609448501 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 7996683251 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3450397000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1827911500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5278308500 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2243809000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7049250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3129187250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 7985805000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2322501000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2942063000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5264564000 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2605759500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 7225127500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6744750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3437360001 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 13274991751 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.149057 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.172689 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.182588 # mshr miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.759197 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.477347 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.679626 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.605334 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.632275 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.617082 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.621773 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.611004 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.617104 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.573401 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.486396 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.534643 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.212849 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.221235 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.205409 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.212849 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.221235 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.205409 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 77325.734556 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75217.333798 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 91240.104337 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32418.974964 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31451.308706 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 32227.094697 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17780.279250 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17794.118065 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17786.462483 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17815.791525 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17872.145516 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17839.981482 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74622.680148 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69151.437191 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 72405.364770 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76231.049788 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73153.546225 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 88062.246128 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76231.049788 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73153.546225 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 88062.246128 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4566310000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7049250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6071250250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 13250369000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.256170 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.309543 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.097879 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.196488 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.449341 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.293469 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.367037 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.089199 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.180067 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456682 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.238002 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.777649 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.529400 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.698801 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.644851 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.586052 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.614138 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.636112 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.639465 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.637894 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.590429 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.520327 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.559767 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.256170 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.309543 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097879 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.262014 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.449341 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.293469 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.367037 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.089199 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.225137 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456682 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.258792 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.256170 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.309543 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097879 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.262014 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.449341 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.293469 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.367037 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.089199 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.225137 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456682 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.258792 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77785.997882 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78898.186528 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72485.070190 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 78158.873123 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116352.759543 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75595.114011 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77318.081442 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71873.836522 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77935.546548 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116116.157002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 98694.338050 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32414.441254 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31501.299584 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 32194.719992 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17792.293775 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17779.972692 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17786.152327 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17845.024984 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17834.026632 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17839.164665 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75179.314842 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70807.215964 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 73401.748613 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77785.997882 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78898.186528 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72485.070190 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77042.056712 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116352.759543 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75595.114011 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77318.081442 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71873.836522 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75753.368192 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116116.157002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 95159.564794 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77785.997882 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78898.186528 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72485.070190 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77042.056712 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116352.759543 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75595.114011 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77318.081442 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71873.836522 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75753.368192 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116116.157002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 95159.564794 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60423.408696 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 135299.626146 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64084.090909 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 144049.498228 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 97934.867921 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 128791.715189 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146276.686720 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138010.905468 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60423.408696 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 131909.466447 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64084.090909 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145120.237355 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 110707.581378 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 622157 # Transaction distribution -system.membus.trans_dist::ReadResp 622157 # Transaction distribution -system.membus.trans_dist::WriteReq 38973 # Transaction distribution -system.membus.trans_dist::WriteResp 38973 # Transaction distribution -system.membus.trans_dist::Writeback 957695 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 636331 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 636331 # Transaction distribution -system.membus.trans_dist::UpgradeReq 382471 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 288753 # Transaction distribution -system.membus.trans_dist::UpgradeResp 111723 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution -system.membus.trans_dist::ReadExReq 123220 # Transaction distribution -system.membus.trans_dist::ReadExResp 104410 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122628 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 906809 # Transaction distribution +system.membus.trans_dist::ReadResp 906809 # Transaction distribution +system.membus.trans_dist::WriteReq 38146 # Transaction distribution +system.membus.trans_dist::WriteResp 38146 # Transaction distribution +system.membus.trans_dist::Writeback 1227861 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 672387 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 672387 # Transaction distribution +system.membus.trans_dist::UpgradeReq 370275 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 320224 # Transaction distribution +system.membus.trans_dist::UpgradeResp 115346 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 24 # Transaction distribution +system.membus.trans_dist::ReadExReq 145002 # Transaction distribution +system.membus.trans_dist::ReadExResp 128981 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122716 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 28184 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4073596 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4224500 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335903 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335903 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4560403 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155735 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24970 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5055890 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5203668 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335590 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335590 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5539258 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155823 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 56368 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 129167796 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 129380103 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14096512 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14096512 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 143476615 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 581158 # Total snoops (count) -system.membus.snoop_fanout::samples 2928688 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49940 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 168605292 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 168811259 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14076224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14076224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 182887483 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 594337 # Total snoops (count) +system.membus.snoop_fanout::samples 3681134 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2928688 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3681134 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2928688 # Request fanout histogram -system.membus.reqLayer0.occupancy 100579500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3681134 # Request fanout histogram +system.membus.reqLayer0.occupancy 100790999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 24544499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21573500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9168550783 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 11112792344 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4323654540 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5991933811 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 151928439 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151912879 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3159,45 +3197,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 3783137 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3775909 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38973 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38973 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2047649 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 890925 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 784014 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 429633 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 300246 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 729879 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 258637 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 258637 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 6917142 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4903000 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 11820142 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 229102843 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 151634764 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 380737607 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1518303 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 7628101 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.015184 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.122286 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 4327568 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4320333 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38146 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38146 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2374848 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 920665 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 813714 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 419012 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 331945 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 750957 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 86 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 292509 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 292509 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7096014 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6270717 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 13366731 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 236480377 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 202778754 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 439259131 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1555479 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8704899 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.013311 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.114603 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 7512273 98.48% 98.48% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115828 1.52% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 8589027 98.67% 98.67% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115872 1.33% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7628101 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 6924291534 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8704899 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 7795939791 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2530500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2526000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3796276244 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3978610795 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3095093071 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3846379763 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index d577712e0..7790849b2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.824462 # Nu sim_ticks 51824462100500 # Number of ticks simulated final_tick 51824462100500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 723017 # Simulator instruction rate (inst/s) -host_op_rate 849578 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41937024652 # Simulator tick rate (ticks/s) -host_mem_usage 712044 # Number of bytes of host memory used -host_seconds 1235.77 # Real time elapsed on the host +host_inst_rate 684695 # Simulator instruction rate (inst/s) +host_op_rate 804548 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39714246392 # Simulator tick rate (ticks/s) +host_mem_usage 713112 # Number of bytes of host memory used +host_seconds 1304.93 # Real time elapsed on the host sim_insts 893481288 # Number of instructions simulated sim_ops 1049881338 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -731,6 +731,12 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 7497734 system.cpu.dcache.demand_mshr_misses::total 7497734 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 8793254 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 8793254 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75489557525 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 75489557525 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62224351540 # number of WriteReq MSHR miss cycles @@ -785,12 +791,12 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18367.403947 system.cpu.dcache.demand_avg_mshr_miss_latency::total 18367.403947 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17953.193816 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 17953.193816 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170628.204177 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170628.204177 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166674.110056 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166674.110056 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168651.039813 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168651.039813 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13753173 # number of replacements system.cpu.icache.tags.tagsinuse 511.880059 # Cycle average of tags in use @@ -859,6 +865,10 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 13753690 system.cpu.icache.demand_mshr_misses::total 13753690 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 13753690 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 13753690 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable +system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable +system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 163860958817 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 163860958817 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 163860958817 # number of demand (read+write) MSHR miss cycles @@ -881,10 +891,10 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11913.963367 system.cpu.icache.demand_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11913.963367 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74459.988406 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74459.988406 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74459.988406 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74459.988406 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1292250 # number of replacements system.cpu.l2cache.tags.tagsinuse 65291.754390 # Cycle average of tags in use @@ -1089,6 +1099,14 @@ system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4054 system.cpu.l2cache.overall_mshr_misses::cpu.inst 79532 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 787946 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 875689 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76831 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110541 # number of overall MSHR uncacheable misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 305614500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 305848750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5531016720 # number of ReadReq MSHR miss cycles @@ -1166,14 +1184,14 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59960.023188 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156621.714235 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102365.809374 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153666.360131 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153666.360131 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59960.023188 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155143.949508 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 118010.154603 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 21652739 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 21644705 # Transaction distribution @@ -1198,19 +1216,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_si system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3006288 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 2043660850 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 470306 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 32992382 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.003506 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.059104 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 33102923 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.033230 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.179236 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 32876724 99.65% 99.65% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 115658 0.35% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 32002916 96.68% 96.68% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1100007 3.32% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 32992382 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 33102923 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 25622352750 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 1278000 # Layer occupancy (ticks) @@ -1481,17 +1497,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14049088 system.membus.pkt_size_system.iocache.mem_side::total 14049088 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 173882714 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 3324 # Total snoops (count) -system.membus.snoop_fanout::samples 2750930 # Request fanout histogram +system.membus.snoop_fanout::samples 2861471 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2750930 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2861471 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2750930 # Request fanout histogram +system.membus.snoop_fanout::total 2861471 # Request fanout histogram system.membus.reqLayer0.occupancy 107107000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index f36b7859c..1bcf52f34 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111153 # Nu sim_ticks 51111152682000 # Number of ticks simulated final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1095499 # Simulator instruction rate (inst/s) -host_op_rate 1287391 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56869697369 # Simulator tick rate (ticks/s) -host_mem_usage 728040 # Number of bytes of host memory used -host_seconds 898.74 # Real time elapsed on the host +host_inst_rate 1028340 # Simulator instruction rate (inst/s) +host_op_rate 1208468 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53383325140 # Simulator tick rate (ticks/s) +host_mem_usage 714148 # Number of bytes of host memory used +host_seconds 957.44 # Real time elapsed on the host sim_insts 984570519 # Number of instructions simulated sim_ops 1157031967 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1018,17 +1018,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 227116986 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3583531 # Request fanout histogram +system.membus.snoop_fanout::samples 3693816 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3583531 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3693816 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3583531 # Request fanout histogram +system.membus.snoop_fanout::total 3693816 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1094,18 +1094,16 @@ system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 332 system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6620864 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 2239440306 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 116338 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 36240472 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.003188 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.056369 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 36350757 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.037391 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.189718 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 36124951 99.68% 99.68% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 34991565 96.26% 96.26% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1359192 3.74% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 36240472 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 36350757 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt index 753b1a595..b8531e2cf 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.274696 # Nu sim_ticks 51274696167500 # Number of ticks simulated final_tick 51274696167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 281052 # Simulator instruction rate (inst/s) -host_op_rate 330247 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16260391227 # Simulator tick rate (ticks/s) -host_mem_usage 656704 # Number of bytes of host memory used -host_seconds 3153.35 # Real time elapsed on the host +host_inst_rate 293957 # Simulator instruction rate (inst/s) +host_op_rate 345410 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17006997815 # Simulator tick rate (ticks/s) +host_mem_usage 724900 # Number of bytes of host memory used +host_seconds 3014.92 # Real time elapsed on the host sim_insts 886256415 # Number of instructions simulated sim_ops 1041383802 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -830,6 +830,15 @@ system.cpu0.dcache.demand_mshr_misses::total 3911848 system.cpu0.dcache.overall_mshr_misses::cpu1.data 1288838 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu2.data 3261967 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 4550805 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 5448 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 8279 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 13727 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 5373 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 7916 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 13289 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 10821 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 16195 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 27016 # number of overall MSHR uncacheable misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 10846992750 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 30627833111 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41474825861 # number of ReadReq MSHR miss cycles @@ -911,15 +920,15 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19118.200690 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17677.220786 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19254.630415 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18807.890668 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164300.431351 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 178149.293514 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172652.928608 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166593.057882 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 181697.568974 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 175590.522688 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 165438.799556 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 179883.665144 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174097.912607 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 14550991 # number of replacements system.cpu0.icache.tags.tagsinuse 511.976833 # Cycle average of tags in use @@ -2434,6 +2443,15 @@ system.l2c.overall_mshr_misses::cpu2.itb.walker 1470 system.l2c.overall_mshr_misses::cpu2.inst 34248 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.data 279438 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 440923 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5448 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2.data 8279 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 13727 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5373 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2.data 7916 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 13289 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10821 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2.data 16195 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 27016 # number of overall MSHR uncacheable misses system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 45139750 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 44046000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 809585750 # number of ReadReq MSHR miss cycles @@ -2557,15 +2575,15 @@ system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 77340.992517 system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73676.090575 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 85155.613786 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 79627.010818 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150300.018355 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 164140.053147 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 158647.191666 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 153591.103666 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 168686.141486 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 162582.925427 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 151934.155808 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 166362.148564 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 160583.154279 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 465050 # Transaction distribution system.membus.trans_dist::ReadResp 465050 # Transaction distribution @@ -2596,17 +2614,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14192960 system.membus.pkt_size_system.iocache.mem_side::total 14192960 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 173983314 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 541 # Total snoops (count) -system.membus.snoop_fanout::samples 2749696 # Request fanout histogram +system.membus.snoop_fanout::samples 2860073 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2749696 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2860073 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2749696 # Request fanout histogram +system.membus.snoop_fanout::total 2860073 # Request fanout histogram system.membus.reqLayer0.occupancy 47655000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 1500 # Layer occupancy (ticks) @@ -2684,19 +2702,17 @@ system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 309 system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6299696 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 2099087298 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 376855 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 34241641 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.003374 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.057992 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 34352020 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.045142 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.207615 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 34126094 99.66% 99.66% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 115547 0.34% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 32801302 95.49% 95.49% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1550718 4.51% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 34241641 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 34352020 # Request fanout histogram system.toL2Bus.reqLayer0.occupancy 13384646524 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 375000 # Layer occupancy (ticks) diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index ad85907fd..ca2a7bbb6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.318118 # Nu sim_ticks 51318118168000 # Number of ticks simulated final_tick 51318118168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135924 # Simulator instruction rate (inst/s) -host_op_rate 159711 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7679227340 # Simulator tick rate (ticks/s) -host_mem_usage 666876 # Number of bytes of host memory used -host_seconds 6682.72 # Real time elapsed on the host +host_inst_rate 134879 # Simulator instruction rate (inst/s) +host_op_rate 158483 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7620199718 # Simulator tick rate (ticks/s) +host_mem_usage 732720 # Number of bytes of host memory used +host_seconds 6734.48 # Real time elapsed on the host sim_insts 908340493 # Number of instructions simulated sim_ops 1067303522 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1100,6 +1100,15 @@ system.cpu0.dcache.demand_mshr_misses::total 7984165 system.cpu0.dcache.overall_mshr_misses::cpu0.data 4712310 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu1.data 4585034 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 9297344 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16397 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 17283 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33680 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17951 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 15746 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33697 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34348 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 33029 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67377 # number of overall MSHR uncacheable misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43556644701 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 43095096417 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 86651741118 # number of ReadReq MSHR miss cycles @@ -1181,15 +1190,15 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20667.469137 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20069.856975 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20098.578829 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20084.021308 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170531.469171 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171562.706127 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171060.651722 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157771.853156 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176775.368792 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166651.853073 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 163863.020729 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174047.752187 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 168855.696202 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 16169102 # number of replacements system.cpu0.icache.tags.tagsinuse 511.955735 # Cycle average of tags in use @@ -1289,6 +1298,12 @@ system.cpu0.icache.demand_mshr_misses::total 16169736 system.cpu0.icache.overall_mshr_misses::cpu0.inst 8013787 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::cpu1.inst 8155949 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 16169736 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 12341 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 8298 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 20639 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 12341 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 8298 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 20639 # number of overall MSHR uncacheable misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 95968094429 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 97614087232 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::total 193582181661 # number of ReadReq MSHR miss cycles @@ -1322,12 +1337,12 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 11971.882637 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11975.373744 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11968.452381 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 11971.882637 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 77088.546390 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 77014.461316 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 77058.760163 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 77088.546390 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 77014.461316 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 77058.760163 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.branchPred.lookups 133788555 # Number of BP lookups system.cpu1.branchPred.condPredicted 90573571 # Number of conditional branches predicted @@ -2445,6 +2460,19 @@ system.l2c.overall_mshr_misses::cpu1.itb.walker 2269 system.l2c.overall_mshr_misses::cpu1.inst 48527 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 437424 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 987592 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 12341 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16397 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 8298 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17283 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 54319 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 17951 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 15746 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 33697 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 12341 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34348 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 8298 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 33029 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 88016 # number of overall MSHR uncacheable misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 193190761 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 175148007 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 3515798206 # number of ReadReq MSHR miss cycles @@ -2575,19 +2603,19 @@ system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76434.667695 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72551.661137 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 85230.972836 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 84210.269261 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 59586.844502 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156516.496920 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 59515.606170 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 157547.431002 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 120004.326258 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144678.402317 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163761.748762 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153595.705730 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 59586.844502 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 150329.655293 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 59515.606170 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160509.998668 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 132864.814284 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 483310 # Transaction distribution system.membus.trans_dist::ReadResp 483310 # Transaction distribution @@ -2618,17 +2646,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14081472 system.membus.pkt_size_system.iocache.mem_side::total 14081472 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 188425258 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 2786 # Total snoops (count) -system.membus.snoop_fanout::samples 2961350 # Request fanout histogram +system.membus.snoop_fanout::samples 3049369 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2961350 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3049369 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2961350 # Request fanout histogram +system.membus.snoop_fanout::total 3049369 # Request fanout histogram system.membus.reqLayer0.occupancy 113801500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 51156 # Layer occupancy (ticks) @@ -2706,19 +2734,17 @@ system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 305 system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8762408 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 2260875858 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 669395 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 37310136 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.003099 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.055581 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 37398155 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.057385 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.232578 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 37194516 99.69% 99.69% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 115620 0.31% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 35252045 94.26% 94.26% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 2146110 5.74% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 37310136 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 37398155 # Request fanout histogram system.toL2Bus.reqLayer0.occupancy 28102852815 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 1161000 # Layer occupancy (ticks) diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt index 943a39f7a..793637493 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.824541 # Nu sim_ticks 51824540977500 # Number of ticks simulated final_tick 51824540977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 650287 # Simulator instruction rate (inst/s) -host_op_rate 764161 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37795835393 # Simulator tick rate (ticks/s) -host_mem_usage 728296 # Number of bytes of host memory used -host_seconds 1371.17 # Real time elapsed on the host +host_inst_rate 636803 # Simulator instruction rate (inst/s) +host_op_rate 748315 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37012113234 # Simulator tick rate (ticks/s) +host_mem_usage 715168 # Number of bytes of host memory used +host_seconds 1400.21 # Real time elapsed on the host sim_insts 891654507 # Number of instructions simulated sim_ops 1047794539 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -814,6 +814,15 @@ system.cpu0.dcache.demand_mshr_misses::total 7479901 system.cpu0.dcache.overall_mshr_misses::cpu0.data 4385256 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu1.data 4391055 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 8776311 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17713 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 15993 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16112 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 17598 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 33825 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 33591 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37598794000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 37923223247 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 75522017247 # number of ReadReq MSHR miss cycles @@ -895,15 +904,15 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18399.677139 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17717.750699 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18240.177055 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17979.136475 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168981.143793 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172453.964234 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170628.945885 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175756.144489 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 158359.117513 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166674.184218 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 172208.307465 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 165069.810366 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 168651.447728 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 13976964 # number of replacements system.cpu0.icache.tags.tagsinuse 511.880033 # Cycle average of tags in use @@ -995,6 +1004,12 @@ system.cpu0.icache.demand_mshr_misses::total 13977481 system.cpu0.icache.overall_mshr_misses::cpu0.inst 7004074 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::cpu1.inst 6973407 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 13977481 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 25928 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 17197 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 25928 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 17197 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 83323187568 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 83088246273 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::total 166411433841 # number of ReadReq MSHR miss cycles @@ -1028,12 +1043,12 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 11905.681277 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11896.388811 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11915.014608 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 11905.681277 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 74379.377507 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74577.935105 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 74458.556522 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 74379.377507 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 74577.935105 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 74458.556522 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1833,6 +1848,19 @@ system.l2c.overall_mshr_misses::cpu1.itb.walker 2035 system.l2c.overall_mshr_misses::cpu1.inst 40460 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 410262 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 878082 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 25928 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 17713 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 17197 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 15993 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 76831 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16112 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 17598 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 25928 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 33825 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 17197 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 33591 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 110541 # number of overall MSHR uncacheable misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 145388500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 152020000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 2697284444 # number of ReadReq MSHR miss cycles @@ -1963,19 +1991,19 @@ system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 74810.687961 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69486.369056 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69620.930581 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 69446.512064 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 59879.454644 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154974.947778 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60077.876955 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158447.133121 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102365.321290 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162747.486346 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145352.227526 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153666.449125 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 59879.454644 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 158677.272727 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60077.876955 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 151586.838737 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 118009.842502 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 450083 # Transaction distribution system.membus.trans_dist::ReadResp 450083 # Transaction distribution @@ -2006,17 +2034,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14048000 system.membus.pkt_size_system.iocache.mem_side::total 14048000 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 174054362 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 3335 # Total snoops (count) -system.membus.snoop_fanout::samples 2753479 # Request fanout histogram +system.membus.snoop_fanout::samples 2864020 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2753479 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2864020 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2753479 # Request fanout histogram +system.membus.snoop_fanout::total 2864020 # Request fanout histogram system.membus.reqLayer0.occupancy 107121000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) @@ -2094,19 +2122,17 @@ system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 268 system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3951520 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 2057658738 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 492069 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 33406949 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.003462 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.058735 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 33517490 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.039407 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.194561 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 33291303 99.65% 99.65% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 115646 0.35% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 32196665 96.06% 96.06% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1320825 3.94% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 33406949 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 33517490 # Request fanout histogram system.toL2Bus.reqLayer0.occupancy 25817690750 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 1207500 # Layer occupancy (ticks) diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 04b362cea..ebffe6201 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.122213 # Nu sim_ticks 5122212682000 # Number of ticks simulated final_tick 5122212682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132606 # Simulator instruction rate (inst/s) -host_op_rate 262116 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1665061517 # Simulator tick rate (ticks/s) -host_mem_usage 804736 # Number of bytes of host memory used -host_seconds 3076.29 # Real time elapsed on the host +host_inst_rate 178126 # Simulator instruction rate (inst/s) +host_op_rate 352092 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2236626113 # Simulator tick rate (ticks/s) +host_mem_usage 810964 # Number of bytes of host memory used +host_seconds 2290.15 # Real time elapsed on the host sim_insts 407934867 # Number of instructions simulated sim_ops 806343968 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -717,6 +717,12 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1259107 system.cpu.dcache.demand_mshr_misses::total 1259107 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1662065 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1662065 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 604701 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 604701 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13919 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 13919 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 618620 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 618620 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12834468768 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 12834468768 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12344104823 # number of WriteReq MSHR miss cycles @@ -753,12 +759,12 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19997.167509 system.cpu.dcache.demand_avg_mshr_miss_latency::total 19997.167509 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18735.342987 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 18735.342987 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161161.122604 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 161161.122604 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 186317.120483 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186317.120483 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 161727.134590 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 161727.134590 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.tags.replacements 77765 # number of replacements system.cpu.dtb_walker_cache.tags.tagsinuse 13.263782 # Cycle average of tags in use @@ -1211,6 +1217,12 @@ system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 system.cpu.l2cache.overall_mshr_misses::cpu.inst 16361 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 169729 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 186163 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 604701 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 604701 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13919 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13919 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 618620 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 618620 # number of overall MSHR uncacheable misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5264500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 578000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1161518218 # number of ReadReq MSHR miss cycles @@ -1274,12 +1286,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 147161.069686 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 147161.069686 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173241.755873 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173241.755873 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 147747.887233 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 147747.887233 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 3067430 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 3066889 # Transaction distribution @@ -1291,6 +1303,7 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 2230 # T system.cpu.toL2Bus.trans_dist::UpgradeResp 2230 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 288754 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 288754 # Transaction distribution +system.cpu.toL2Bus.trans_dist::MessageReq 1643 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 4 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1994880 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6121448 # Packet count per connected master and slave (bytes) @@ -1302,20 +1315,20 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 973632 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5848896 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 278538304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 61672 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4387054 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.010870 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103692 # Request fanout histogram +system.cpu.toL2Bus.snoops 63315 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5007317 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.009852 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.098766 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4339366 98.91% 98.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47688 1.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4957986 99.01% 99.01% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 49331 0.99% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4387054 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5007317 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4072528967 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 555000 # Layer occupancy (ticks) @@ -1560,17 +1573,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 26225708 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 1635 # Total snoops (count) -system.membus.snoop_fanout::samples 385314 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 1005577 # Request fanout histogram +system.membus.snoop_fanout::mean 1.001634 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.040388 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 385314 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 1003934 99.84% 99.84% # Request fanout histogram +system.membus.snoop_fanout::2 1643 0.16% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 385314 # Request fanout histogram +system.membus.snoop_fanout::max_value 2 # Request fanout histogram +system.membus.snoop_fanout::total 1005577 # Request fanout histogram system.membus.reqLayer0.occupancy 357821000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 388531000 # Layer occupancy (ticks) diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index b91cf4fab..81562c0f3 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.133731 # Nu sim_ticks 5133731116500 # Number of ticks simulated final_tick 5133731116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 201130 # Simulator instruction rate (inst/s) -host_op_rate 399856 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4230291451 # Simulator tick rate (ticks/s) -host_mem_usage 1019904 # Number of bytes of host memory used -host_seconds 1213.56 # Real time elapsed on the host +host_inst_rate 268887 # Simulator instruction rate (inst/s) +host_op_rate 534560 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5655392824 # Simulator tick rate (ticks/s) +host_mem_usage 1025452 # Number of bytes of host memory used +host_seconds 907.76 # Real time elapsed on the host sim_insts 244084329 # Number of instructions simulated sim_ops 485251122 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -559,6 +559,15 @@ system.cpu0.dcache.demand_mshr_misses::total 764859 system.cpu0.dcache.overall_mshr_misses::cpu1.data 287154 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu2.data 734585 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 1021739 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 186614 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 205311 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 391925 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 3448 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 3872 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 7320 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 190062 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 209183 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 399245 # number of overall MSHR uncacheable misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1988518250 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5713340764 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7701859014 # number of ReadReq MSHR miss cycles @@ -613,15 +622,15 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18052.198644 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18773.696132 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16498.435737 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17137.884876 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163421.889569 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 160883.484080 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162092.138802 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174047.418794 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 196782.670455 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186073.497268 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 163614.652061 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 161547.981911 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 162531.827575 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 871419 # number of replacements system.cpu0.icache.tags.tagsinuse 510.241344 # Cycle average of tags in use @@ -1630,6 +1639,15 @@ system.l2c.overall_mshr_misses::cpu2.dtb.walker 35 system.l2c.overall_mshr_misses::cpu2.inst 5224 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.data 49327 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 88886 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 186614 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2.data 205311 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 391925 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3448 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2.data 3872 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 7320 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 190062 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2.data 209183 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 399245 # number of overall MSHR uncacheable misses system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 70000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 193782500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.data 330037250 # number of ReadReq MSHR miss cycles @@ -1720,15 +1738,15 @@ system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75228.542857 system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73703.244640 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69123.677398 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 67612.992451 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 149115.529917 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 146883.437809 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 147946.242266 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 160916.038283 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 183774.535124 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 173007.308743 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 149329.608233 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 147566.296018 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 148405.727060 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 5117226 # Transaction distribution system.membus.trans_dist::ReadResp 5117226 # Transaction distribution @@ -1762,17 +1780,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6011648 system.membus.pkt_size_system.iocache.mem_side::total 6011648 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 33300229 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 820 # Total snoops (count) -system.membus.snoop_fanout::samples 372049 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 5455844 # Request fanout histogram +system.membus.snoop_fanout::mean 1.000311 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.017639 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 372049 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 5454146 99.97% 99.97% # Request fanout histogram +system.membus.snoop_fanout::2 1698 0.03% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 372049 # Request fanout histogram +system.membus.snoop_fanout::max_value 2 # Request fanout histogram +system.membus.snoop_fanout::total 5455844 # Request fanout histogram system.membus.reqLayer0.occupancy 234105000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 304102500 # Layer occupancy (ticks) @@ -1809,6 +1827,7 @@ system.toL2Bus.trans_dist::UpgradeReq 1672 # Tr system.toL2Bus.trans_dist::UpgradeResp 1672 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 290026 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 290026 # Transaction distribution +system.toL2Bus.trans_dist::MessageReq 1151 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1743864 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14988008 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73882 # Packet count per connected master and slave (bytes) @@ -1819,20 +1838,18 @@ system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2133 system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 274152 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 823488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 270293669 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 72565 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4266300 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.011166 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.105077 # Request fanout histogram +system.toL2Bus.snoops 74263 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9350095 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.022573 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.148538 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 4218663 98.88% 98.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 47637 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 9139035 97.74% 97.74% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 211060 2.26% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4266300 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 9350095 # Request fanout histogram system.toL2Bus.reqLayer0.occupancy 2511915480 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 402000 # Layer occupancy (ticks) diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 4eaa033e0..b7910ff50 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061594 # Nu sim_ticks 61594138500 # Number of ticks simulated final_tick 61594138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196979 # Simulator instruction rate (inst/s) -host_op_rate 197960 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 133911114 # Simulator tick rate (ticks/s) -host_mem_usage 438496 # Number of bytes of host memory used -host_seconds 459.96 # Real time elapsed on the host +host_inst_rate 265976 # Simulator instruction rate (inst/s) +host_op_rate 267300 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 180817037 # Simulator tick rate (ticks/s) +host_mem_usage 446692 # Number of bytes of host memory used +host_seconds 340.64 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -779,17 +779,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 121232128 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1894252 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 1894252 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1894252 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1894252 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1890392000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index a297b8e5d..cb0d7cfc4 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.058203 # Nu sim_ticks 58203290500 # Number of ticks simulated final_tick 58203290500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98982 # Simulator instruction rate (inst/s) -host_op_rate 99475 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63595388 # Simulator tick rate (ticks/s) -host_mem_usage 438244 # Number of bytes of host memory used -host_seconds 915.21 # Real time elapsed on the host +host_inst_rate 131910 # Simulator instruction rate (inst/s) +host_op_rate 132567 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 84750962 # Simulator tick rate (ticks/s) +host_mem_usage 445160 # Number of bytes of host memory used +host_seconds 686.76 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1154,17 +1154,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 698173056 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 22116 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 10931068 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.002023 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.002023 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.044933 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 10908954 99.80% 99.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 22114 0.20% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 10908954 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 22114 0.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 10931068 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 10892444998 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 4697b1e09..1d5681a17 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.062108 # Nu sim_ticks 62108139000 # Number of ticks simulated final_tick 62108139000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88749 # Simulator instruction rate (inst/s) -host_op_rate 156272 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34888646 # Simulator tick rate (ticks/s) -host_mem_usage 448856 # Number of bytes of host memory used -host_seconds 1780.18 # Real time elapsed on the host +host_inst_rate 114338 # Simulator instruction rate (inst/s) +host_op_rate 201331 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44948395 # Simulator tick rate (ticks/s) +host_mem_usage 455560 # Number of bytes of host memory used +host_seconds 1381.77 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -946,17 +946,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 265234496 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 4144289 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4144289 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4144289 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 4144289 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4138867500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 05a346173..02993075a 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu sim_ticks 365989065500 # Number of ticks simulated final_tick 365989065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 638452 # Simulator instruction rate (inst/s) -host_op_rate 1124211 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1479007835 # Simulator tick rate (ticks/s) -host_mem_usage 450980 # Number of bytes of host memory used -host_seconds 247.46 # Real time elapsed on the host +host_inst_rate 678113 # Simulator instruction rate (inst/s) +host_op_rate 1194048 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1570885616 # Simulator tick rate (ticks/s) +host_mem_usage 451452 # Number of bytes of host memory used +host_seconds 232.98 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -452,17 +452,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 4130121 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4130121 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4130121 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 4130121 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index e29c8c27b..a54a6c0d4 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.366340 # Nu sim_ticks 366339500500 # Number of ticks simulated final_tick 366339500500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 174606 # Simulator instruction rate (inst/s) -host_op_rate 189122 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 126268215 # Simulator tick rate (ticks/s) -host_mem_usage 309684 # Number of bytes of host memory used -host_seconds 2901.28 # Real time elapsed on the host +host_inst_rate 237525 # Simulator instruction rate (inst/s) +host_op_rate 257271 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171768388 # Simulator tick rate (ticks/s) +host_mem_usage 317860 # Number of bytes of host memory used +host_seconds 2132.75 # Real time elapsed on the host sim_insts 506582156 # Number of instructions simulated sim_ops 548695379 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -824,17 +824,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 142850048 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 2232032 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 2232032 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2232032 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 2232032 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2184563000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index f6e4f2ecd..12498d68b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.233457 # Nu sim_ticks 233457400500 # Number of ticks simulated final_tick 233457400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105147 # Simulator instruction rate (inst/s) -host_op_rate 113911 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48585649 # Simulator tick rate (ticks/s) -host_mem_usage 312624 # Number of bytes of host memory used -host_seconds 4805.07 # Real time elapsed on the host +host_inst_rate 140578 # Simulator instruction rate (inst/s) +host_op_rate 152296 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64957541 # Simulator tick rate (ticks/s) +host_mem_usage 319412 # Number of bytes of host memory used +host_seconds 3594.00 # Real time elapsed on the host sim_insts 505237724 # Number of instructions simulated sim_ops 547350945 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1159,17 +1159,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 335917632 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 317126 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 5565869 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.056971 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.056971 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.231787 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 5248777 94.30% 94.30% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 317092 5.70% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5248777 94.30% 94.30% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 317092 5.70% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 5565869 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4977148500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index 7518311dc..04541cf46 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.279362 # Nu sim_ticks 279362298000 # Number of ticks simulated final_tick 279362298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1382525 # Simulator instruction rate (inst/s) -host_op_rate 1497457 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 762414599 # Simulator tick rate (ticks/s) -host_mem_usage 298924 # Number of bytes of host memory used -host_seconds 366.42 # Real time elapsed on the host +host_inst_rate 1944100 # Simulator instruction rate (inst/s) +host_op_rate 2105717 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1072104103 # Simulator tick rate (ticks/s) +host_mem_usage 306580 # Number of bytes of host memory used +host_seconds 260.57 # Real time elapsed on the host sim_insts 506581608 # Number of instructions simulated sim_ops 548694829 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 system.membus.pkt_size::total 2705365829 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 687930750 # Request fanout histogram -system.membus.snoop_fanout::mean 2.750964 # Request fanout histogram +system.membus.snoop_fanout::mean 0.750964 # Request fanout histogram system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 171319374 24.90% 24.90% # Request fanout histogram -system.membus.snoop_fanout::3 516611376 75.10% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 171319374 24.90% 24.90% # Request fanout histogram +system.membus.snoop_fanout::1 516611376 75.10% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 687930750 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 93937d49d..5ab6bd474 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -593,17 +593,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 2215344 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 2215344 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2215344 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 2215344 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 5165f82f6..3384a1591 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.417785 # Number of seconds simulated -sim_ticks 417784645500 # Number of ticks simulated -final_tick 417784645500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.417996 # Number of seconds simulated +sim_ticks 417996021500 # Number of ticks simulated +final_tick 417996021500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77548 # Simulator instruction rate (inst/s) -host_op_rate 143396 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39181823 # Simulator tick rate (ticks/s) -host_mem_usage 423644 # Number of bytes of host memory used -host_seconds 10662.72 # Real time elapsed on the host +host_inst_rate 98610 # Simulator instruction rate (inst/s) +host_op_rate 182341 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49848381 # Simulator tick rate (ticks/s) +host_mem_usage 430328 # Number of bytes of host memory used +host_seconds 8385.35 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 225536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 227200 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24536320 # Number of bytes read from this memory -system.physmem.bytes_read::total 24761856 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 225536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 225536 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18818176 # Number of bytes written to this memory -system.physmem.bytes_written::total 18818176 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3524 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 24763520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 227200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 227200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18818240 # Number of bytes written to this memory +system.physmem.bytes_written::total 18818240 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3550 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 383380 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386904 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294034 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 539838 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 58729588 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 59269426 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 539838 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 539838 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45042766 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45042766 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45042766 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 539838 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 58729588 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 104312192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386904 # Number of read requests accepted -system.physmem.writeReqs 294034 # Number of write requests accepted -system.physmem.readBursts 386904 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294034 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24739840 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22016 # Total number of bytes read from write queue -system.physmem.bytesWritten 18816320 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24761856 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18818176 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 344 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 386930 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 294035 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294035 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 543546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 58699889 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 59243435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 543546 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 543546 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45020141 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45020141 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45020141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 543546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 58699889 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104263576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386930 # Number of read requests accepted +system.physmem.writeReqs 294035 # Number of write requests accepted +system.physmem.readBursts 386930 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 294035 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24740928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22592 # Total number of bytes read from write queue +system.physmem.bytesWritten 18817024 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24763520 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18818240 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 353 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 194832 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24113 # Per bank write bursts -system.physmem.perBankRdBursts::1 26506 # Per bank write bursts -system.physmem.perBankRdBursts::2 24704 # Per bank write bursts -system.physmem.perBankRdBursts::3 24585 # Per bank write bursts -system.physmem.perBankRdBursts::4 23284 # Per bank write bursts -system.physmem.perBankRdBursts::5 23758 # Per bank write bursts -system.physmem.perBankRdBursts::6 24455 # Per bank write bursts -system.physmem.perBankRdBursts::7 24304 # Per bank write bursts -system.physmem.perBankRdBursts::8 23622 # Per bank write bursts -system.physmem.perBankRdBursts::9 23951 # Per bank write bursts -system.physmem.perBankRdBursts::10 24786 # Per bank write bursts -system.physmem.perBankRdBursts::11 24077 # Per bank write bursts -system.physmem.perBankRdBursts::12 23364 # Per bank write bursts -system.physmem.perBankRdBursts::13 22990 # Per bank write bursts -system.physmem.perBankRdBursts::14 24090 # Per bank write bursts -system.physmem.perBankRdBursts::15 23971 # Per bank write bursts -system.physmem.perBankWrBursts::0 18545 # Per bank write bursts -system.physmem.perBankWrBursts::1 19845 # Per bank write bursts -system.physmem.perBankWrBursts::2 18943 # Per bank write bursts -system.physmem.perBankWrBursts::3 18938 # Per bank write bursts -system.physmem.perBankWrBursts::4 18040 # Per bank write bursts -system.physmem.perBankWrBursts::5 18456 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 195133 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24110 # Per bank write bursts +system.physmem.perBankRdBursts::1 26511 # Per bank write bursts +system.physmem.perBankRdBursts::2 24689 # Per bank write bursts +system.physmem.perBankRdBursts::3 24586 # Per bank write bursts +system.physmem.perBankRdBursts::4 23301 # Per bank write bursts +system.physmem.perBankRdBursts::5 23773 # Per bank write bursts +system.physmem.perBankRdBursts::6 24463 # Per bank write bursts +system.physmem.perBankRdBursts::7 24300 # Per bank write bursts +system.physmem.perBankRdBursts::8 23625 # Per bank write bursts +system.physmem.perBankRdBursts::9 23952 # Per bank write bursts +system.physmem.perBankRdBursts::10 24787 # Per bank write bursts +system.physmem.perBankRdBursts::11 24070 # Per bank write bursts +system.physmem.perBankRdBursts::12 23353 # Per bank write bursts +system.physmem.perBankRdBursts::13 22981 # Per bank write bursts +system.physmem.perBankRdBursts::14 24097 # Per bank write bursts +system.physmem.perBankRdBursts::15 23979 # Per bank write bursts +system.physmem.perBankWrBursts::0 18543 # Per bank write bursts +system.physmem.perBankWrBursts::1 19847 # Per bank write bursts +system.physmem.perBankWrBursts::2 18947 # Per bank write bursts +system.physmem.perBankWrBursts::3 18939 # Per bank write bursts +system.physmem.perBankWrBursts::4 18047 # Per bank write bursts +system.physmem.perBankWrBursts::5 18457 # Per bank write bursts system.physmem.perBankWrBursts::6 18996 # Per bank write bursts -system.physmem.perBankWrBursts::7 18987 # Per bank write bursts -system.physmem.perBankWrBursts::8 18549 # Per bank write bursts -system.physmem.perBankWrBursts::9 18172 # Per bank write bursts -system.physmem.perBankWrBursts::10 18834 # Per bank write bursts -system.physmem.perBankWrBursts::11 17732 # Per bank write bursts -system.physmem.perBankWrBursts::12 17374 # Per bank write bursts -system.physmem.perBankWrBursts::13 16972 # Per bank write bursts +system.physmem.perBankWrBursts::7 18981 # Per bank write bursts +system.physmem.perBankWrBursts::8 18548 # Per bank write bursts +system.physmem.perBankWrBursts::9 18168 # Per bank write bursts +system.physmem.perBankWrBursts::10 18839 # Per bank write bursts +system.physmem.perBankWrBursts::11 17728 # Per bank write bursts +system.physmem.perBankWrBursts::12 17372 # Per bank write bursts +system.physmem.perBankWrBursts::13 16973 # Per bank write bursts system.physmem.perBankWrBursts::14 17820 # Per bank write bursts -system.physmem.perBankWrBursts::15 17802 # Per bank write bursts +system.physmem.perBankWrBursts::15 17811 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 417784619000 # Total gap between requests +system.physmem.totGap 417995980500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386904 # Read request sizes (log2) +system.physmem.readPktSize::6 386930 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294034 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381510 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4656 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 294035 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381501 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,33 +144,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17645 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 17645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see @@ -193,37 +193,37 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147384 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 295.518428 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.412890 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.590500 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54886 37.24% 37.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39792 27.00% 64.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13719 9.31% 73.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7560 5.13% 78.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5573 3.78% 82.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3862 2.62% 85.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3103 2.11% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2674 1.81% 89.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16215 11.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147384 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17444 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.159252 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 209.918601 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17431 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 147449 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 295.402912 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.387317 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 322.474139 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54872 37.21% 37.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 39881 27.05% 64.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13729 9.31% 73.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7544 5.12% 78.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5538 3.76% 82.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3897 2.64% 85.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3110 2.11% 87.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2694 1.83% 89.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16184 10.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147449 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17448 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.155834 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 209.387263 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17435 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17444 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17444 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.854219 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.780353 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.660093 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17244 98.85% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 141 0.81% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 26 0.15% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 11 0.06% 99.87% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17448 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17448 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.850986 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.777295 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.658929 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17245 98.84% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 147 0.84% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 24 0.14% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 10 0.06% 99.87% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-35 5 0.03% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 3 0.02% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 3 0.02% 99.94% # Writes before turning the bus around for reads @@ -237,202 +237,202 @@ system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Wr system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17444 # Writes before turning the bus around for reads -system.physmem.totQLat 4274781750 # Total ticks spent queuing -system.physmem.totMemAccLat 11522781750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1932800000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11058.52 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17448 # Writes before turning the bus around for reads +system.physmem.totQLat 4282714250 # Total ticks spent queuing +system.physmem.totMemAccLat 11531033000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1932885000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11078.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29808.52 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 59.22 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.04 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 59.27 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.04 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29828.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 59.19 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.02 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 59.24 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.81 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.29 # Average write queue length when enqueuing -system.physmem.readRowHits 318043 # Number of row buffer hits during reads -system.physmem.writeRowHits 215127 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.28 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.16 # Row buffer hit rate for writes -system.physmem.avgGap 613542.82 # Average gap between requests -system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 567476280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 309634875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1526389800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 976691520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 27287295360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63728995635 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 194764938000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 289161421470 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.139218 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 323446024000 # Time in different power states -system.physmem_0.memoryStateTime::REF 13950560000 # Time in different power states +system.physmem.avgWrQLen 21.74 # Average write queue length when enqueuing +system.physmem.readRowHits 318033 # Number of row buffer hits during reads +system.physmem.writeRowHits 215097 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.27 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes +system.physmem.avgGap 613828.88 # Average gap between requests +system.physmem.pageHitRate 78.33 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 567967680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 309903000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1526584800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 976607280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 27301026480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63862686000 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 194773803000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 289318578240 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.167087 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 323459791500 # Time in different power states +system.physmem_0.memoryStateTime::REF 13957580000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 80384174500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 80574068000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 546399000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 298134375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1488177600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 928104480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 27287295360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61807042845 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 196450861500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 288806015160 # Total energy per rank (pJ) -system.physmem_1.averagePower 691.288514 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 326265955250 # Time in different power states -system.physmem_1.memoryStateTime::REF 13950560000 # Time in different power states +system.physmem_1.actEnergy 546278040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 298068375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1488138600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 928098000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 27301026480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 61813739205 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 196571124750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 288946473450 # Total energy per rank (pJ) +system.physmem_1.averagePower 691.276862 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 326467583000 # Time in different power states +system.physmem_1.memoryStateTime::REF 13957580000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 77563900250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 77566206500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 230228501 # Number of BP lookups -system.cpu.branchPred.condPredicted 230228501 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9739021 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131459692 # Number of BTB lookups -system.cpu.branchPred.BTBHits 128773186 # Number of BTB hits +system.cpu.branchPred.lookups 230262495 # Number of BP lookups +system.cpu.branchPred.condPredicted 230262495 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9742888 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 131521089 # Number of BTB lookups +system.cpu.branchPred.BTBHits 128797905 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.956403 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 27739164 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1472550 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.929470 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 27751403 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1472504 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 835569292 # number of cpu cycles simulated +system.cpu.numCycles 835992044 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 185184379 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1269166320 # Number of instructions fetch has processed -system.cpu.fetch.Branches 230228501 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 156512350 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 639147953 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20213743 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 511 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 99253 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 822297 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1772 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 179484418 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2740851 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 185232757 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1269385486 # Number of instructions fetch has processed +system.cpu.fetch.Branches 230262495 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 156549308 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 639500926 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20224879 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 485 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 100878 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 834249 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1640 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 179526470 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2741098 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 835363066 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.826562 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.382493 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 835783416 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.825648 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.381813 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 427868247 51.22% 51.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 33702021 4.03% 55.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 32929710 3.94% 59.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33265996 3.98% 63.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 27012416 3.23% 66.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 27748723 3.32% 69.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 36992796 4.43% 74.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 33648824 4.03% 78.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 182194333 21.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 428043161 51.21% 51.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 33828750 4.05% 55.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 32944896 3.94% 59.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33232373 3.98% 63.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 27262474 3.26% 66.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 27644327 3.31% 69.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 36950250 4.42% 74.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33776724 4.04% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 182100461 21.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 835363066 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.275535 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.518924 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127510375 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 375947418 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 240571925 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81226477 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10106871 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2225382694 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 10106871 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 159640008 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 160513488 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 42854 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 285557624 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 219502221 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2175351414 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 185986 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 136028392 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24255750 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 49096014 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2279465980 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5501874168 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3499442561 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 66867 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 835783416 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.275436 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.518418 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127710765 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 376117098 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 240273770 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 81569344 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10112439 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2225700133 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 10112439 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 159685424 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 160601450 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 42674 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 285796855 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 219544574 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2175664077 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 185857 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 136149821 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24262583 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 49140413 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2279803570 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5502723498 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3499975195 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 67752 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 665425126 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3167 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2999 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 415602419 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 528341229 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 209838821 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 239501304 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 72157646 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2101036293 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25395 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1826926557 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 429463 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 572072987 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 974001425 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24843 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 835363066 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.186985 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.073368 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 665762716 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3202 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3008 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 414696821 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 528426075 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 209872279 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 239265917 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 72168406 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2101339198 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25266 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1827025844 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 429417 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 572375763 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 974716036 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24714 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 835783416 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.186004 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.072692 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 255962202 30.64% 30.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 125607638 15.04% 45.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 118770145 14.22% 59.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 111086257 13.30% 73.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 92824001 11.11% 84.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 61460839 7.36% 91.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 43056890 5.15% 96.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19182433 2.30% 99.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7412661 0.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 256113706 30.64% 30.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 125601677 15.03% 45.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 119268677 14.27% 59.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 111065913 13.29% 73.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 92467369 11.06% 84.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 61706105 7.38% 91.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 43038473 5.15% 96.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 19113733 2.29% 99.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7407763 0.89% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 835363066 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 835783416 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11317596 42.46% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12272214 46.05% 88.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3062486 11.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11312018 42.37% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12328079 46.18% 88.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3055344 11.45% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2719434 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1211207278 66.30% 66.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 389699 0.02% 66.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880989 0.21% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 135 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2717945 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1211291441 66.30% 66.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 390219 0.02% 66.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881058 0.21% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 119 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 39 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 410 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 36 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 409 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued @@ -454,84 +454,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 435021653 23.81% 90.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173706920 9.51% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 435052343 23.81% 90.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173692274 9.51% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1826926557 # Type of FU issued -system.cpu.iq.rate 2.186445 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26652296 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014589 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4516265766 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2673396604 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1796798251 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 32173 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 70520 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7153 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1850844448 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 14971 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 185549711 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1827025844 # Type of FU issued +system.cpu.iq.rate 2.185458 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26695441 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014611 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4516927324 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2674001021 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1796885315 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 32638 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 71794 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7253 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1850988135 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 15205 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 185719617 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 144242393 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 210251 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 386532 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 60678635 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 144326663 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 210089 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 386690 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 60712093 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19153 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1029 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19150 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1058 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10106871 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 107291908 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6438859 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2101061688 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 392799 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 528344550 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 209838821 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7385 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1906737 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3653179 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 386532 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5738958 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4581595 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10320553 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1805492449 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 428838978 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 21434108 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10112439 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 107482997 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6407343 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2101364464 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 396756 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 528428820 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 209872279 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7401 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1872023 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3639843 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 386690 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5742846 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4583278 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10326124 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1805593119 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 428868135 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21432725 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 598981338 # number of memory reference insts executed -system.cpu.iew.exec_branches 171787473 # Number of branches executed -system.cpu.iew.exec_stores 170142360 # Number of stores executed -system.cpu.iew.exec_rate 2.160793 # Inst execution rate -system.cpu.iew.wb_sent 1802094257 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1796805404 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1368063103 # num instructions producing a value -system.cpu.iew.wb_consumers 2090238527 # num instructions consuming a value +system.cpu.iew.exec_refs 598999412 # number of memory reference insts executed +system.cpu.iew.exec_branches 171793179 # Number of branches executed +system.cpu.iew.exec_stores 170131277 # Number of stores executed +system.cpu.iew.exec_rate 2.159821 # Inst execution rate +system.cpu.iew.wb_sent 1802187162 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1796892568 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1367992688 # num instructions producing a value +system.cpu.iew.wb_consumers 2090178306 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.150397 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.654501 # average fanout of values written-back +system.cpu.iew.wb_rate 2.149413 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.654486 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 572152437 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 572454923 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9826757 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 757699482 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.017936 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.547497 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9832210 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 758082487 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.016916 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.546878 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 289066041 38.15% 38.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 175144894 23.12% 61.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57411271 7.58% 68.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86235215 11.38% 80.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 27150149 3.58% 83.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27136057 3.58% 87.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9784065 1.29% 88.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8843971 1.17% 89.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 76927819 10.15% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 289327383 38.17% 38.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 175257093 23.12% 61.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57420140 7.57% 68.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86252758 11.38% 80.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 27155131 3.58% 83.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27117110 3.58% 87.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9822533 1.30% 88.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8850930 1.17% 89.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 76879409 10.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 757699482 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 758082487 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -577,338 +577,338 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 76927819 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2781912801 # The number of ROB reads -system.cpu.rob.rob_writes 4280130406 # The number of ROB writes -system.cpu.timesIdled 2299 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 206226 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 76879409 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2782646702 # The number of ROB reads +system.cpu.rob.rob_writes 4280772798 # The number of ROB writes +system.cpu.timesIdled 2318 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 208628 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.010512 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.010512 # CPI: Total CPI of All Threads -system.cpu.ipc 0.989597 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.989597 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2761971319 # number of integer regfile reads -system.cpu.int_regfile_writes 1465030124 # number of integer regfile writes -system.cpu.fp_regfile_reads 7481 # number of floating regfile reads -system.cpu.fp_regfile_writes 493 # number of floating regfile writes -system.cpu.cc_regfile_reads 600902917 # number of cc regfile reads -system.cpu.cc_regfile_writes 409659635 # number of cc regfile writes -system.cpu.misc_regfile_reads 990136590 # number of misc regfile reads +system.cpu.cpi 1.011023 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.011023 # CPI: Total CPI of All Threads +system.cpu.ipc 0.989097 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.989097 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2762036439 # number of integer regfile reads +system.cpu.int_regfile_writes 1465125360 # number of integer regfile writes +system.cpu.fp_regfile_reads 7563 # number of floating regfile reads +system.cpu.fp_regfile_writes 476 # number of floating regfile writes +system.cpu.cc_regfile_reads 600921582 # number of cc regfile reads +system.cpu.cc_regfile_writes 409666959 # number of cc regfile writes +system.cpu.misc_regfile_reads 990189445 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2534249 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.994933 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 387820460 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2538345 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 152.784771 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2534281 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.998981 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 387677401 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2538377 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 152.726487 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1688557250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.994933 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998046 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998046 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.998981 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998047 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998047 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 869 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3173 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 873 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3167 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 784768509 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 784768509 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 239165062 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 239165062 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148173846 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148173846 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 387338908 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 387338908 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 387338908 # number of overall hits -system.cpu.dcache.overall_hits::total 387338908 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2789818 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2789818 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 986356 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 986356 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3776174 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3776174 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3776174 # number of overall misses -system.cpu.dcache.overall_misses::total 3776174 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 60126724251 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 60126724251 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31294703774 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31294703774 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91421428025 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91421428025 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91421428025 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91421428025 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 241954880 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 241954880 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 784481905 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 784481905 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 239023256 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 239023256 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148173502 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148173502 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 387196758 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 387196758 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 387196758 # number of overall hits +system.cpu.dcache.overall_hits::total 387196758 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2788306 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2788306 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 986700 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 986700 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3775006 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3775006 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3775006 # number of overall misses +system.cpu.dcache.overall_misses::total 3775006 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 60089695608 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 60089695608 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31307364104 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31307364104 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91397059712 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91397059712 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91397059712 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91397059712 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 241811562 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 241811562 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 391115082 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 391115082 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 391115082 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 391115082 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011530 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011530 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006613 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006613 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 390971764 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 390971764 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 390971764 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 390971764 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011531 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011531 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006615 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006615 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.009655 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.009655 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009655 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009655 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21552.203137 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21552.203137 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31727.595081 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31727.595081 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24210.067657 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24210.067657 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24210.067657 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24210.067657 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10621 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 71 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1078 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21550.610158 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21550.610158 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31729.364654 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31729.364654 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24211.103164 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24211.103164 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24211.103164 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24211.103164 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10735 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 46 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1081 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.852505 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 14.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.930620 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 9.200000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2332976 # number of writebacks -system.cpu.dcache.writebacks::total 2332976 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1022764 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1022764 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18373 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18373 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1041137 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1041137 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1041137 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1041137 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 2332980 # number of writebacks +system.cpu.dcache.writebacks::total 2332980 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1021252 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1021252 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18400 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18400 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1039652 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1039652 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1039652 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1039652 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767054 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1767054 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 967983 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 967983 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2735037 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2735037 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2735037 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2735037 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32779636252 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32779636252 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29507402723 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 29507402723 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62287038975 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 62287038975 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62287038975 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 62287038975 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007303 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007303 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006993 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006993 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006993 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006993 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18550.443989 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18550.443989 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30483.389401 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30483.389401 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22773.746379 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22773.746379 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22773.746379 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22773.746379 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 968300 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 968300 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2735354 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2735354 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2735354 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2735354 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32779677502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32779677502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29519299643 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 29519299643 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62298977145 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 62298977145 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62298977145 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 62298977145 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007308 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007308 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006492 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006492 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006996 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006996 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006996 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006996 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18550.467333 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18550.467333 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30485.696213 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30485.696213 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22775.471528 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22775.471528 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22775.471528 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22775.471528 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 7023 # number of replacements -system.cpu.icache.tags.tagsinuse 1053.963479 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 179273130 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8620 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20797.346868 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 7107 # number of replacements +system.cpu.icache.tags.tagsinuse 1054.726418 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 179314504 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8709 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20589.562981 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1053.963479 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.514631 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.514631 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1597 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 319 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1155 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.779785 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 359174294 # Number of tag accesses -system.cpu.icache.tags.data_accesses 359174294 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 179276307 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 179276307 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 179276307 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 179276307 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 179276307 # number of overall hits -system.cpu.icache.overall_hits::total 179276307 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 208110 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 208110 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 208110 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 208110 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 208110 # number of overall misses -system.cpu.icache.overall_misses::total 208110 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1327923993 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1327923993 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1327923993 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1327923993 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1327923993 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1327923993 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 179484417 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 179484417 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 179484417 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 179484417 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 179484417 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 179484417 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001159 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001159 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001159 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001159 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001159 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001159 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6380.875465 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6380.875465 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6380.875465 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6380.875465 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6380.875465 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6380.875465 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 695 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1054.726418 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.515003 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.515003 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1602 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 330 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1149 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.782227 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 359258778 # Number of tag accesses +system.cpu.icache.tags.data_accesses 359258778 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 179317997 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 179317997 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 179317997 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 179317997 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 179317997 # number of overall hits +system.cpu.icache.overall_hits::total 179317997 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 208472 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 208472 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 208472 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 208472 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 208472 # number of overall misses +system.cpu.icache.overall_misses::total 208472 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1336227738 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1336227738 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1336227738 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1336227738 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1336227738 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1336227738 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 179526469 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 179526469 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 179526469 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 179526469 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 179526469 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 179526469 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001161 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001161 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001161 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001161 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001161 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001161 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6409.626895 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6409.626895 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6409.626895 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6409.626895 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6409.626895 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6409.626895 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1217 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 57.916667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 81.133333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2649 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2649 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2649 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2649 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2649 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2649 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205461 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 205461 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 205461 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 205461 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 205461 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 205461 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 892683754 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 892683754 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 892683754 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 892683754 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 892683754 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 892683754 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001145 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001145 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001145 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001145 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001145 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001145 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4344.784431 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4344.784431 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4344.784431 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4344.784431 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4344.784431 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4344.784431 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2630 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2630 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2630 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2630 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2630 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2630 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205842 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 205842 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 205842 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 205842 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 205842 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 205842 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 900667759 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 900667759 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 900667759 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 900667759 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 900667759 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 900667759 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001147 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001147 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001147 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001147 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001147 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001147 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4375.529576 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4375.529576 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4375.529576 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4375.529576 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4375.529576 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4375.529576 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 354223 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29619.061304 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3704244 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 386583 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.582015 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 354249 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29619.496841 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3704141 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 386604 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.581228 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 197893481000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21085.370146 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 251.812049 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8281.879109 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.643474 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007685 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.252743 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.903902 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 21082.499774 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 254.372713 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8282.624354 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.643387 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007763 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.252766 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.903915 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32355 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 242 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13363 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18671 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41773644 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41773644 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 5119 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1590451 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1595570 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2332976 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2332976 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1900 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1900 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 564474 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 564474 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5119 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2154925 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2160044 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 5119 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2154925 # number of overall hits -system.cpu.l2cache.overall_hits::total 2160044 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3526 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 176410 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 179936 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 194792 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 194792 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 207010 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 207010 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3526 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 383420 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 386946 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3526 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 383420 # number of overall misses -system.cpu.l2cache.overall_misses::total 386946 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 288437750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14275708250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14564146000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 12898587 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 12898587 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16427155710 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16427155710 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 288437750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 30702863960 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30991301710 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 288437750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 30702863960 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30991301710 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 8645 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1766861 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1775506 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2332976 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2332976 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 196692 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 196692 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 771484 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 771484 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 8645 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2538345 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2546990 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 8645 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2538345 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2546990 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.407866 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099844 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.101344 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990340 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990340 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268327 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.268327 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.407866 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.151051 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151923 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.407866 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.151051 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151923 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81803.105502 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80923.463806 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 80940.701138 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 66.217232 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 66.217232 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79354.406599 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79354.406599 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81803.105502 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80076.323509 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80092.058608 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81803.105502 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80076.323509 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80092.058608 # average overall miss latency +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13370 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18660 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987396 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 41777056 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 41777056 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 5192 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1590453 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1595645 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2332980 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2332980 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1881 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1881 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 564507 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 564507 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5192 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2154960 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2160152 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5192 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2154960 # number of overall hits +system.cpu.l2cache.overall_hits::total 2160152 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3552 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 176400 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 179952 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 195096 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 195096 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 207017 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 207017 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3552 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 383417 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 386969 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3552 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 383417 # number of overall misses +system.cpu.l2cache.overall_misses::total 386969 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 294540500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14275679000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14570219500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13220077 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 13220077 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16430030463 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16430030463 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 294540500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 30705709463 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31000249963 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 294540500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 30705709463 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31000249963 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 8744 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1766853 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1775597 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2332980 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2332980 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 196977 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 196977 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 771524 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 771524 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 8744 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2538377 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2547121 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 8744 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2538377 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2547121 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.406221 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099839 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.101347 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990451 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990451 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268322 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.268322 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.406221 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.151048 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151924 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.406221 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.151048 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151924 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82922.438063 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80927.885488 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80967.255157 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 67.761907 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 67.761907 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79365.609892 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79365.609892 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82922.438063 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80084.371488 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80110.422186 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82922.438063 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80084.371488 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80110.422186 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -917,127 +917,125 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 294034 # number of writebacks -system.cpu.l2cache.writebacks::total 294034 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 294035 # number of writebacks +system.cpu.l2cache.writebacks::total 294035 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3525 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176410 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 179935 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 194792 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 194792 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207010 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 207010 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3525 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 383420 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 386945 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3525 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 383420 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 386945 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 244319250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12068297250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12312616500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3517284221 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3517284221 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13838517790 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13838517790 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 244319250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25906815040 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26151134290 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 244319250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25906815040 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26151134290 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.407750 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099844 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101343 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990340 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990340 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268327 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268327 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.407750 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151051 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151922 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.407750 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151051 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151922 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69310.425532 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68410.505357 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68428.135160 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18056.615369 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18056.615369 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66849.513502 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66849.513502 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69310.425532 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67567.719576 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67583.595317 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69310.425532 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67567.719576 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67583.595317 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3551 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176400 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 179951 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 195096 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 195096 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207017 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 207017 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3551 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 383417 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 386968 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3551 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 383417 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 386968 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 250130000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12068381000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12318511000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3521803787 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3521803787 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13841306537 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13841306537 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 250130000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25909687537 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26159817537 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 250130000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25909687537 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26159817537 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.406107 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099839 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101347 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990451 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990451 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268322 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268322 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.406107 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151048 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151924 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.406107 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151048 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151924 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70439.312870 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68414.858277 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68454.807142 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18051.645277 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18051.645277 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66860.724177 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66860.724177 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70439.312870 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67575.740087 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67602.017575 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70439.312870 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67575.740087 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67602.017575 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1972322 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1972321 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2332976 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 196692 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 196692 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771484 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771484 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 214105 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7803050 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8017155 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 553216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311764544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312317760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 196816 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5273474 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 1972695 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1972693 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2332980 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 196977 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 196977 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771524 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771524 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 214584 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7803688 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8018272 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311766848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312326336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 197098 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5274176 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 5273474 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5274176 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5273474 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4998709391 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5274176 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4998685151 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 308726995 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 309293990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3988953025 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3989146355 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 179934 # Transaction distribution -system.membus.trans_dist::ReadResp 179934 # Transaction distribution -system.membus.trans_dist::Writeback 294034 # Transaction distribution -system.membus.trans_dist::UpgradeReq 194832 # Transaction distribution -system.membus.trans_dist::UpgradeResp 194832 # Transaction distribution -system.membus.trans_dist::ReadExReq 206970 # Transaction distribution -system.membus.trans_dist::ReadExResp 206970 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1457506 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1457506 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1457506 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43580032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43580032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43580032 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 179950 # Transaction distribution +system.membus.trans_dist::ReadResp 179949 # Transaction distribution +system.membus.trans_dist::Writeback 294035 # Transaction distribution +system.membus.trans_dist::UpgradeReq 195133 # Transaction distribution +system.membus.trans_dist::UpgradeResp 195133 # Transaction distribution +system.membus.trans_dist::ReadExReq 206980 # Transaction distribution +system.membus.trans_dist::ReadExResp 206980 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1458160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1458160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1458160 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43581696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43581696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43581696 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 875770 # Request fanout histogram +system.membus.snoop_fanout::samples 876098 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 875770 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 876098 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 875770 # Request fanout histogram -system.membus.reqLayer0.occupancy 2246779030 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 876098 # Request fanout histogram +system.membus.reqLayer0.occupancy 2246796268 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2437213959 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2437948408 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 9a6a9e0dc..1702837e8 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.885229 # Nu sim_ticks 885229328000 # Number of ticks simulated final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1229934 # Simulator instruction rate (inst/s) -host_op_rate 2274285 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1316729165 # Simulator tick rate (ticks/s) -host_mem_usage 308776 # Number of bytes of host memory used -host_seconds 672.29 # Real time elapsed on the host +host_inst_rate 1361574 # Simulator instruction rate (inst/s) +host_op_rate 2517703 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1457659146 # Simulator tick rate (ticks/s) +host_mem_usage 313840 # Number of bytes of host memory used +host_seconds 607.30 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,33 +35,6 @@ system.physmem.bw_write::total 1120443517 # Wr system.physmem.bw_total::cpu.inst 9654872754 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13357308966 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1452449251 # Transaction distribution -system.membus.trans_dist::ReadResp 1452449251 # Transaction distribution -system.membus.trans_dist::WriteReq 149160202 # Transaction distribution -system.membus.trans_dist::WriteResp 149160202 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136694130 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 2136694130 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066524776 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 1066524776 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3203218906 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546776520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 8546776520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277505120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 3277505120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 11824281640 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1601609453 # Request fanout histogram -system.membus.snoop_fanout::mean 2.667046 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 533262388 33.30% 33.30% # Request fanout histogram -system.membus.snoop_fanout::3 1068347065 66.70% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram -system.membus.snoop_fanout::total 1601609453 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls @@ -125,5 +98,30 @@ system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1528988702 # Class of executed instruction +system.membus.trans_dist::ReadReq 1452449251 # Transaction distribution +system.membus.trans_dist::ReadResp 1452449251 # Transaction distribution +system.membus.trans_dist::WriteReq 149160202 # Transaction distribution +system.membus.trans_dist::WriteResp 149160202 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136694130 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 2136694130 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066524776 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 1066524776 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3203218906 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546776520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 8546776520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277505120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 3277505120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 11824281640 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1601609453 # Request fanout histogram +system.membus.snoop_fanout::mean 0.667046 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 533262388 33.30% 33.30% # Request fanout histogram +system.membus.snoop_fanout::1 1068347065 66.70% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 1601609453 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 43971ad10..d2da1780a 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.647873 # Nu sim_ticks 1647872738500 # Number of ticks simulated final_tick 1647872738500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 730118 # Simulator instruction rate (inst/s) -host_op_rate 1350071 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1455043701 # Simulator tick rate (ticks/s) -host_mem_usage 323120 # Number of bytes of host memory used -host_seconds 1132.52 # Real time elapsed on the host +host_inst_rate 720688 # Simulator instruction rate (inst/s) +host_op_rate 1332632 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1436248802 # Simulator tick rate (ticks/s) +host_mem_usage 323576 # Number of bytes of host memory used +host_seconds 1147.35 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -454,17 +454,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 310066880 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 4844795 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4844795 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4844795 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 4844795 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 5070249ec..592625271 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.216744 # Nu sim_ticks 216744260000 # Number of ticks simulated final_tick 216744260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123383 # Simulator instruction rate (inst/s) -host_op_rate 148134 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 97944157 # Simulator tick rate (ticks/s) -host_mem_usage 314844 # Number of bytes of host memory used -host_seconds 2212.94 # Real time elapsed on the host +host_inst_rate 172626 # Simulator instruction rate (inst/s) +host_op_rate 207257 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 137034779 # Simulator tick rate (ticks/s) +host_mem_usage 322768 # Number of bytes of host memory used +host_seconds 1581.67 # Real time elapsed on the host sim_insts 273037857 # Number of instructions simulated sim_ops 327812214 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -783,17 +783,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 2840064 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 44377 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 44377 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 44377 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 44377 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 23198500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 4230ac10b..94f7097ff 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.112557 # Nu sim_ticks 112556618500 # Number of ticks simulated final_tick 112556618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95501 # Simulator instruction rate (inst/s) -host_op_rate 114659 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39369115 # Simulator tick rate (ticks/s) -host_mem_usage 319836 # Number of bytes of host memory used -host_seconds 2859.01 # Real time elapsed on the host +host_inst_rate 125639 # Simulator instruction rate (inst/s) +host_op_rate 150843 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51793233 # Simulator tick rate (ticks/s) +host_mem_usage 327772 # Number of bytes of host memory used +host_seconds 2173.19 # Real time elapsed on the host sim_insts 273037220 # Number of instructions simulated sim_ops 327811602 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1134,17 +1134,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 205825792 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 32515 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 3248545 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.009730 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.009730 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.098161 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3216936 99.03% 99.03% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 31609 0.97% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3216936 99.03% 99.03% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 31609 0.97% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 3248545 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2574809000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index 08c45e0cd..e3d32f84d 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.201717 # Nu sim_ticks 201717314000 # Number of ticks simulated final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 854590 # Simulator instruction rate (inst/s) -host_op_rate 1026030 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 631341281 # Simulator tick rate (ticks/s) -host_mem_usage 304088 # Number of bytes of host memory used -host_seconds 319.51 # Real time elapsed on the host +host_inst_rate 1265309 # Simulator instruction rate (inst/s) +host_op_rate 1519144 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 934796791 # Simulator tick rate (ticks/s) +host_mem_usage 311752 # Number of bytes of host memory used +host_seconds 215.79 # Real time elapsed on the host sim_insts 273037595 # Number of instructions simulated sim_ops 327811950 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 system.membus.pkt_size::total 2275398075 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 517024352 # Request fanout histogram -system.membus.snoop_fanout::mean 2.674359 # Request fanout histogram +system.membus.snoop_fanout::mean 0.674359 # Request fanout histogram system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 168364078 32.56% 32.56% # Request fanout histogram -system.membus.snoop_fanout::3 348660274 67.44% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 168364078 32.56% 32.56% # Request fanout histogram +system.membus.snoop_fanout::1 348660274 67.44% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 517024352 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index eb13035d6..cfbe2044c 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -591,17 +591,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 21079 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 21079 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 21079 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 5cc3f8bc2..f250ad066 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.545048 # Nu sim_ticks 545048444500 # Number of ticks simulated final_tick 545048444500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131789 # Simulator instruction rate (inst/s) -host_op_rate 162250 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 112122004 # Simulator tick rate (ticks/s) -host_mem_usage 314432 # Number of bytes of host memory used -host_seconds 4861.21 # Real time elapsed on the host +host_inst_rate 177094 # Simulator instruction rate (inst/s) +host_op_rate 218026 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 150665678 # Simulator tick rate (ticks/s) +host_mem_usage 323140 # Number of bytes of host memory used +host_seconds 3617.60 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -808,17 +808,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 57537024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 899017 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 899017 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 899017 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 899017 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 540928500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index d04be0b82..bdaafd38c 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.409388 # Number of seconds simulated -sim_ticks 409388341000 # Number of ticks simulated -final_tick 409388341000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 409388416000 # Number of ticks simulated +final_tick 409388416000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75979 # Simulator instruction rate (inst/s) -host_op_rate 93540 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48552243 # Simulator tick rate (ticks/s) -host_mem_usage 312124 # Number of bytes of host memory used -host_seconds 8431.91 # Real time elapsed on the host +host_inst_rate 93306 # Simulator instruction rate (inst/s) +host_op_rate 114872 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59624294 # Simulator tick rate (ticks/s) +host_mem_usage 320320 # Number of bytes of host memory used +host_seconds 6866.13 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 226496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 226560 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7024000 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 12938624 # Number of bytes read from this memory -system.physmem.bytes_read::total 20189120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 226496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 226496 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 20189184 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 226560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 226560 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4245888 # Number of bytes written to this memory system.physmem.bytes_written::total 4245888 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3539 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 3540 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 109750 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 202166 # Number of read requests responded to by this memory -system.physmem.num_reads::total 315455 # Number of read requests responded to by this memory +system.physmem.num_reads::total 315456 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66342 # Number of write requests responded to by this memory system.physmem.num_writes::total 66342 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 553255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17157303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 31604769 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 49315327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 553255 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 553255 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 10371297 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 10371297 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 10371297 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 553255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17157303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 31604769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59686624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 315455 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 553411 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17157300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 31604763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 49315475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 553411 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 553411 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 10371295 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 10371295 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 10371295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 553411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17157300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 31604763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 59686769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 315456 # Number of read requests accepted system.physmem.writeReqs 66342 # Number of write requests accepted -system.physmem.readBursts 315455 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 315456 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66342 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 20169536 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 20169600 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 19584 # Total number of bytes read from write queue system.physmem.bytesWritten 4238784 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 20189120 # Total read bytes from the system interface side +system.physmem.bytesReadSys 20189184 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4245888 # Total written bytes from the system interface side system.physmem.servicedByWrQ 306 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 81 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 18 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 19 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 19899 # Per bank write bursts system.physmem.perBankRdBursts::1 19575 # Per bank write bursts system.physmem.perBankRdBursts::2 19715 # Per bank write bursts @@ -67,7 +67,7 @@ system.physmem.perBankRdBursts::11 19765 # Pe system.physmem.perBankRdBursts::12 19604 # Per bank write bursts system.physmem.perBankRdBursts::13 19959 # Per bank write bursts system.physmem.perBankRdBursts::14 19457 # Per bank write bursts -system.physmem.perBankRdBursts::15 19977 # Per bank write bursts +system.physmem.perBankRdBursts::15 19978 # Per bank write bursts system.physmem.perBankWrBursts::0 4260 # Per bank write bursts system.physmem.perBankWrBursts::1 4107 # Per bank write bursts system.physmem.perBankWrBursts::2 4142 # Per bank write bursts @@ -86,14 +86,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4150 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 409388286500 # Total gap between requests +system.physmem.totGap 409388361500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 315455 # Read request sizes (log2) +system.physmem.readPktSize::6 315456 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -101,7 +101,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66342 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 122393 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 122394 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 117234 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 14139 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 6795 # What read queue length does an incoming req see @@ -197,20 +197,20 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 136711 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.525503 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 128.653130 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 198.190580 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 136710 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 178.527277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 128.653997 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 198.191580 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 54126 39.59% 39.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 57416 42.00% 81.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14736 10.78% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57414 42.00% 81.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14737 10.78% 92.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 1353 0.99% 93.36% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 1490 1.09% 94.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1455 1.06% 95.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 1216 0.89% 96.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1169 0.86% 97.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3750 2.74% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 136711 # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 136710 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4038 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 65.701585 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::gmean 34.708310 # Reads before turning the bus around for writes @@ -248,12 +248,12 @@ system.physmem.wrPerTurnAround::27 2 0.05% 99.93% # Wr system.physmem.wrPerTurnAround::28 2 0.05% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::31 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4038 # Writes before turning the bus around for reads -system.physmem.totQLat 9474891317 # Total ticks spent queuing -system.physmem.totMemAccLat 15383935067 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1575745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 30064.80 # Average queueing delay per DRAM burst +system.physmem.totQLat 9474850817 # Total ticks spent queuing +system.physmem.totMemAccLat 15383913317 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1575750000 # Total ticks spent in databus transfers +system.physmem.avgQLat 30064.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 48814.80 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 48814.58 # Average memory access latency per DRAM burst system.physmem.avgRdBW 49.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 10.35 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 49.32 # Average system read bandwidth in MiByte/s @@ -264,11 +264,11 @@ system.physmem.busUtilRead 0.38 # Da system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.70 # Average write queue length when enqueuing -system.physmem.readRowHits 218193 # Number of row buffer hits during reads +system.physmem.readRowHits 218195 # Number of row buffer hits during reads system.physmem.writeRowHits 26465 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.23 # Row buffer hit rate for reads +system.physmem.readRowHitRate 69.24 # Row buffer hit rate for reads system.physmem.writeRowHitRate 39.94 # Row buffer hit rate for writes -system.physmem.avgGap 1072266.90 # Average gap between requests +system.physmem.avgGap 1072264.29 # Average gap between requests system.physmem.pageHitRate 64.15 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 518729400 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 283036875 # Energy for precharge commands per rank (pJ) @@ -279,32 +279,32 @@ system.physmem_0.actBackEnergy 96374211480 # En system.physmem_0.preBackEnergy 161092645500 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 286455220215 # Total energy per rank (pJ) system.physmem_0.averagePower 699.719632 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 267357168520 # Time in different power states +system.physmem_0.memoryStateTime::IDLE 267357262270 # Time in different power states system.physmem_0.memoryStateTime::REF 13670280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 128358277730 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 514715040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 280846500 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 514722600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 280850625 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1226721600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 212706000 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 26739067680 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 96210213075 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 161236503750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 286420773645 # Total energy per rank (pJ) -system.physmem_1.averagePower 699.635490 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 267598080337 # Time in different power states +system.physmem_1.totalEnergy 286420785330 # Total energy per rank (pJ) +system.physmem_1.averagePower 699.635519 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 267597865087 # Time in different power states system.physmem_1.memoryStateTime::REF 13670280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 128117581163 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 233960254 # Number of BP lookups -system.cpu.branchPred.condPredicted 161822373 # Number of conditional branches predicted +system.cpu.branchPred.lookups 233960267 # Number of BP lookups +system.cpu.branchPred.condPredicted 161822378 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15514618 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 121575796 # Number of BTB lookups -system.cpu.branchPred.BTBHits 108259792 # Number of BTB hits +system.cpu.branchPred.BTBLookups 121575807 # Number of BTB lookups +system.cpu.branchPred.BTBHits 108259798 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.047159 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 89.047156 # BTB Hit Percentage system.cpu.branchPred.usedRAS 25036830 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1300193 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -425,84 +425,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 818776683 # number of cpu cycles simulated +system.cpu.numCycles 818776833 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 84080283 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1200690611 # Number of instructions fetch has processed -system.cpu.fetch.Branches 233960254 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 133296622 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 718833631 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 84080281 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1200690651 # Number of instructions fetch has processed +system.cpu.fetch.Branches 233960267 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133296628 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 718834157 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 31063665 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2156 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.MiscStallCycles 2157 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3279 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 370702181 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652815 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 818451212 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.833527 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3294 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 370702196 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652814 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 818451752 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.833525 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 1.163546 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 136785734 16.71% 16.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 223134622 27.26% 43.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 98075130 11.98% 55.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 360455726 44.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 136786252 16.71% 16.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 223134631 27.26% 43.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 98075133 11.98% 55.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 360455736 44.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 818451212 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 818451752 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.285744 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.466445 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 119992571 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 159648210 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484662538 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38629741 # Number of cycles decode is unblocking +system.cpu.fetch.rate 1.466444 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 119992574 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 159648734 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484662553 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38629739 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 15518152 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 25181026 # Number of times decode resolved a branch +system.cpu.decode.BranchResolved 25181029 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 13828 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248127712 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39967189 # Number of squashed instructions handled by decode +system.cpu.decode.DecodedInsts 1248127732 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39967182 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 15518152 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 177000170 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 78888622 # Number of cycles rename is blocking +system.cpu.rename.IdleCycles 177000175 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 78889127 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 210704 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464955823 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 81877741 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190635480 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 25549977 # Number of squashed instructions processed by rename +system.cpu.rename.RunCycles 464955834 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81877760 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190635501 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 25549976 # Number of squashed instructions processed by rename system.cpu.rename.ROBFullEvents 24948594 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2267380 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 41534187 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1694220 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1225376851 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5812387634 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358166964 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1694237 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1225376861 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5812387733 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358166990 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 40876517 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 350598621 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 350598631 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 7265 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108139964 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 366113107 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236095924 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 108139973 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 366113111 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236095933 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1592417 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 5322589 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1168545112 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 1168545131 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 12357 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017136895 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18518107 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 379832511 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1032101117 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1017136914 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18518110 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 379832530 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1032101126 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 203 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 818451212 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.242758 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 818451752 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.242757 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.084999 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 260801504 31.87% 31.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 227738074 27.83% 59.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 216482418 26.45% 86.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 97282888 11.89% 98.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16146319 1.97% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 260802028 31.87% 31.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 227738086 27.83% 59.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 216482422 26.45% 86.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 97282889 11.89% 98.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16146318 1.97% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -510,7 +510,7 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 818451212 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 818451752 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 64511713 19.12% 19.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 18146 0.01% 19.13% # attempts to use FU when none available @@ -541,12 +541,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 155540663 46.10% 65.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 116678902 34.58% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 155540667 46.10% 65.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116678907 34.58% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456370981 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456370990 44.87% 44.87% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 5195830 0.51% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued @@ -575,40 +575,40 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 11478993 1.13% 47.13% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322128329 31.67% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215587412 21.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322128333 31.67% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215587418 21.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017136895 # Type of FU issued +system.cpu.iq.FU_type_0::total 1017136914 # Type of FU issued system.cpu.iq.rate 1.242264 # Inst issue rate -system.cpu.iq.fu_busy_cnt 337386313 # FU busy when requested +system.cpu.iq.fu_busy_cnt 337386322 # FU busy when requested system.cpu.iq.fu_busy_rate 0.331702 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3146752380 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1504842501 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934271178 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 3146752970 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1504842539 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934271199 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 61877042 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 43565869 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 26152443 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1320712858 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 1320712886 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 33810350 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 9960171 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 113872169 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 113872173 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1090 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 18393 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107115428 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 107115437 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2065797 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 22350 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 15518152 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35325435 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 35325436 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 42128 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1168563023 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 1168563042 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 366113107 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236095924 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 366113111 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236095933 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6617 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 102 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 45749 # Number of times the LSQ has become full, causing a stall @@ -616,43 +616,43 @@ system.cpu.iew.memOrderViolationEvents 18393 # Nu system.cpu.iew.predictedTakenIncorrect 15437385 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 3784510 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 19221895 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974751162 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303297617 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42385733 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 974751184 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303297622 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42385730 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 5554 # number of nop insts executed -system.cpu.iew.exec_refs 497765227 # number of memory reference insts executed -system.cpu.iew.exec_branches 150613464 # Number of branches executed -system.cpu.iew.exec_stores 194467610 # Number of stores executed +system.cpu.iew.exec_refs 497765238 # number of memory reference insts executed +system.cpu.iew.exec_branches 150613469 # Number of branches executed +system.cpu.iew.exec_stores 194467616 # Number of stores executed system.cpu.iew.exec_rate 1.190497 # Inst execution rate -system.cpu.iew.wb_sent 963723916 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960423621 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536680580 # num instructions producing a value -system.cpu.iew.wb_consumers 893282190 # num instructions consuming a value +system.cpu.iew.wb_sent 963723937 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960423642 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536680583 # num instructions producing a value +system.cpu.iew.wb_consumers 893282195 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.172998 # insts written-back per cycle system.cpu.iew.wb_fanout 0.600796 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 357407190 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 357407209 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 15500938 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 767630958 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.027486 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.786865 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 767631497 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.027485 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.786864 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 430922921 56.14% 56.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 172477665 22.47% 78.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 430923455 56.14% 56.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 172477669 22.47% 78.61% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 73566542 9.58% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 31624091 4.12% 92.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 31624094 4.12% 92.31% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 8540357 1.11% 93.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14250533 1.86% 95.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14250532 1.86% 95.28% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 7269334 0.95% 96.22% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 6619169 0.86% 97.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22360346 2.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22360345 2.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 767630958 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 767631497 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -698,30 +698,30 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 22360346 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1891399121 # The number of ROB reads -system.cpu.rob.rob_writes 2343098694 # The number of ROB writes -system.cpu.timesIdled 647342 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 325471 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 22360345 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1891399680 # The number of ROB reads +system.cpu.rob.rob_writes 2343098733 # The number of ROB writes +system.cpu.timesIdled 647345 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 325081 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated system.cpu.cpi 1.278042 # CPI: Cycles Per Instruction system.cpu.cpi_total 1.278042 # CPI: Total CPI of All Threads system.cpu.ipc 0.782447 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.782447 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995806500 # number of integer regfile reads -system.cpu.int_regfile_writes 567906149 # number of integer regfile writes +system.cpu.int_regfile_reads 995806519 # number of integer regfile reads +system.cpu.int_regfile_writes 567906159 # number of integer regfile writes system.cpu.fp_regfile_reads 31889841 # number of floating regfile reads system.cpu.fp_regfile_writes 22959492 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794435390 # number of cc regfile reads -system.cpu.cc_regfile_writes 384898944 # number of cc regfile writes -system.cpu.misc_regfile_reads 715817585 # number of misc regfile reads +system.cpu.cc_regfile_reads 3794435468 # number of cc regfile reads +system.cpu.cc_regfile_writes 384898950 # number of cc regfile writes +system.cpu.misc_regfile_reads 715817595 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes system.cpu.dcache.tags.replacements 2756184 # number of replacements system.cpu.dcache.tags.tagsinuse 511.932971 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414226707 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 414226712 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2756696 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.262019 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.262021 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 257775000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.932971 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999869 # Average percentage of cache occupancy @@ -732,10 +732,10 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 224 system.cpu.dcache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839343974 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839343974 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286295255 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286295255 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 839343984 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839343984 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286295259 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286295259 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 127916705 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 127916705 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3174 # number of SoftPFReq hits @@ -744,34 +744,34 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414211960 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414211960 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414215134 # number of overall hits -system.cpu.dcache.overall_hits::total 414215134 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3031607 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3031607 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 414211964 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414211964 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414215138 # number of overall hits +system.cpu.dcache.overall_hits::total 414215138 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3031608 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3031608 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1034772 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1034772 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4066379 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4066379 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4067026 # number of overall misses -system.cpu.dcache.overall_misses::total 4067026 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35304231919 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35304231919 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9981686625 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9981686625 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 4066380 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4066380 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4067027 # number of overall misses +system.cpu.dcache.overall_misses::total 4067027 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35305181420 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35305181420 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9981703626 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9981703626 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 189500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45285918544 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45285918544 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45285918544 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45285918544 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289326862 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289326862 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 45286885046 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45286885046 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45286885046 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45286885046 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289326867 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289326867 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3821 # number of SoftPFReq accesses(hits+misses) @@ -780,10 +780,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418278339 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418278339 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418282160 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418282160 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 418278344 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418278344 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418282165 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418282165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010478 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.010478 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008025 # miss rate for WriteReq accesses @@ -796,16 +796,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.009722 system.cpu.dcache.demand_miss_rate::total 0.009722 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009723 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11645.385407 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11645.385407 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9646.266641 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9646.266641 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11645.694767 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11645.694767 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9646.283071 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9646.283071 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63166.666667 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11136.669392 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11136.669392 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11134.897722 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11134.897722 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11136.904334 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11136.904334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11135.132628 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11135.132628 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 343566 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -816,16 +816,16 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 735673 # number of writebacks system.cpu.dcache.writebacks::total 735673 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 996398 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 996398 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 996399 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 996399 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 313907 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 313907 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1310305 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1310305 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1310305 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1310305 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1310306 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1310306 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1310306 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1310306 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035209 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 2035209 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720865 # number of WriteReq MSHR misses @@ -836,16 +836,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2756074 system.cpu.dcache.demand_mshr_misses::total 2756074 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2756715 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2756715 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23117834450 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23117834450 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5596502782 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5596502782 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23118028700 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23118028700 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5596519781 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5596519781 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5770003 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5770003 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28714337232 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28714337232 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28720107235 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28720107235 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28714548481 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28714548481 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28720318484 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28720318484 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses @@ -856,108 +856,108 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11358.948614 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11358.948614 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7763.593436 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7763.593436 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11359.044059 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11359.044059 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7763.617017 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7763.617017 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9001.564743 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9001.564743 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10418.565406 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10418.565406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10418.235920 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10418.235920 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10418.642054 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10418.642054 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10418.312551 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10418.312551 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5169973 # number of replacements +system.cpu.icache.tags.replacements 5169974 # number of replacements system.cpu.icache.tags.tagsinuse 511.005918 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 365527993 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5170483 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.695135 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 365528009 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5170484 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.695124 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 247768250 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.005918 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998058 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998058 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 328 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 746574800 # Number of tag accesses -system.cpu.icache.tags.data_accesses 746574800 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 365528016 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 365528016 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 365528016 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 365528016 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 365528016 # number of overall hits -system.cpu.icache.overall_hits::total 365528016 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5174133 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5174133 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5174133 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5174133 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5174133 # number of overall misses -system.cpu.icache.overall_misses::total 5174133 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 41647669446 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 41647669446 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 41647669446 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 41647669446 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 41647669446 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 41647669446 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 370702149 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 370702149 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 370702149 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 370702149 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 370702149 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 370702149 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 746574831 # Number of tag accesses +system.cpu.icache.tags.data_accesses 746574831 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 365528032 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 365528032 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 365528032 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 365528032 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 365528032 # number of overall hits +system.cpu.icache.overall_hits::total 365528032 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5174132 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5174132 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5174132 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5174132 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5174132 # number of overall misses +system.cpu.icache.overall_misses::total 5174132 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 41647443196 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 41647443196 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 41647443196 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 41647443196 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 41647443196 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 41647443196 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 370702164 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 370702164 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 370702164 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 370702164 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 370702164 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 370702164 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013958 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013958 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013958 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013958 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013958 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013958 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8049.207364 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8049.207364 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8049.207364 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8049.207364 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8049.207364 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8049.207364 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 75182 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8049.165193 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8049.165193 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8049.165193 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8049.165193 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8049.165193 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8049.165193 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 75254 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 145 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3130 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 24.019808 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 24.042812 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 29 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3630 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3630 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3630 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3630 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3630 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3630 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5170503 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5170503 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5170503 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5170503 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5170503 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5170503 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36431563436 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36431563436 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36431563436 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36431563436 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36431563436 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36431563436 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3628 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3628 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3628 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3628 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3628 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3628 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5170504 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 5170504 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 5170504 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 5170504 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 5170504 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 5170504 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36431387686 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36431387686 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36431387686 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36431387686 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36431387686 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36431387686 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013948 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013948 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013948 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.013948 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013948 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013948 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7046.038545 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7046.038545 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7046.038545 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7046.038545 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7046.038545 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7046.038545 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7046.003192 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7046.003192 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7046.003192 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7046.003192 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7046.003192 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7046.003192 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.prefetcher.num_hwpf_issued 1347095 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 1354943 # number of prefetch candidates identified @@ -965,43 +965,41 @@ system.cpu.l2cache.prefetcher.pfBufferHit 6866 # n system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 4789921 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 299164 # number of replacements +system.cpu.l2cache.tags.replacements 299165 # number of replacements system.cpu.l2cache.tags.tagsinuse 16361.556320 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7824806 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 315528 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.799086 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 315529 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 24.799007 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 13406100000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 743.987058 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.512594 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8771.582471 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6718.474196 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 743.986923 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.512620 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8771.582614 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6718.474164 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.045409 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007783 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.535375 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.410063 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.998630 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 6518 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 9846 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1022 6520 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 9844 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 171 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1451 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 170 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1454 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4880 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 225 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2089 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7268 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.397827 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.600952 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 139642343 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 139642343 # Number of data accesses +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2085 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7271 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.397949 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.600830 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 139642360 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 139642360 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 5166932 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1926211 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7093143 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 735673 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 735673 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 717988 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 717988 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 5166932 # number of demand (read+write) hits @@ -1010,50 +1008,52 @@ system.cpu.l2cache.demand_hits::total 7811131 # nu system.cpu.l2cache.overall_hits::cpu.inst 5166932 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 2644199 # number of overall hits system.cpu.l2cache.overall_hits::total 7811131 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3553 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 3554 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 109639 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 113192 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 18 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 18 # number of UpgradeReq misses +system.cpu.l2cache.ReadReq_misses::total 113193 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 19 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 19 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 2858 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 2858 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3553 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 3554 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 112497 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 116050 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3553 # number of overall misses +system.cpu.l2cache.demand_misses::total 116051 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3554 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 112497 # number of overall misses -system.cpu.l2cache.overall_misses::total 116050 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 261165964 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8561744931 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 8822910895 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::total 116051 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 260989714 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8561938681 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 8822928395 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23499 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 23499 # number of UpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 205223699 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 205223699 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 261165964 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8766968630 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9028134594 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 261165964 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8766968630 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9028134594 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 5170485 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_miss_latency::cpu.inst 260989714 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8767162380 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9028152094 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 260989714 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8767162380 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9028152094 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 5170486 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 2035850 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7206335 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7206336 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 735673 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 735673 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 19 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 19 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 720846 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 720846 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5170485 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 5170486 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2756696 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 7927181 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5170485 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 7927182 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 5170486 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2756696 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 7927181 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 7927182 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000687 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.053854 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.015707 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.947368 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.947368 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003965 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.003965 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000687 # miss rate for demand accesses @@ -1062,17 +1062,19 @@ system.cpu.l2cache.demand_miss_rate::total 0.014640 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000687 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.040809 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014640 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73505.759640 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78090.323069 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 77946.417547 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73435.485087 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78092.090232 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 77945.883535 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1236.789474 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1236.789474 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71806.752624 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71806.752624 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73505.759640 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77930.688196 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77795.214080 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73505.759640 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77930.688196 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77795.214080 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73435.485087 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77932.410464 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77794.694522 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73435.485087 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77932.410464 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77794.694522 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1094,130 +1096,128 @@ system.cpu.l2cache.demand_mshr_hits::total 2761 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 2747 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 2761 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3539 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3540 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108352 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 111891 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 111892 # number of ReadReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202242 # number of HardPFReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::total 202242 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 19 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 19 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1398 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1398 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3539 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3540 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 109750 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 113289 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3539 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 113290 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3540 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 109750 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202242 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 315531 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 230067036 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7609571000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7839638036 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 315532 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 229882786 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7609765250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7839648036 # number of ReadReq MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 17078829649 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 17078829649 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 248018 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 248018 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 262019 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 262019 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114010508 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114010508 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 230067036 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7723581508 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7953648544 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 230067036 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7723581508 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 229882786 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7723775758 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7953658544 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 229882786 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7723775758 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 17078829649 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25032478193 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_miss_latency::total 25032488193 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000685 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053222 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015527 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947368 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947368 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001939 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001939 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000685 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039812 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.014291 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000685 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039812 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.039804 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65009.052275 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70230.092661 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70064.956395 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64938.640113 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70231.885429 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70064.419583 # average ReadReq mshr miss latency system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861 # average HardPFReq mshr miss latency system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84447.491861 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13778.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13778.777778 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13790.473684 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13790.473684 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81552.580830 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81552.580830 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65009.052275 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70374.318979 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70206.715074 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65009.052275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70374.318979 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64938.640113 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70376.088911 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70206.183635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64938.640113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70376.088911 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79334.449525 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79334.229787 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7206353 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7206352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 7206354 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7206353 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 735673 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFReq 248887 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 19 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 19 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10340987 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10340989 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6249103 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16590090 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330910976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16590092 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330911040 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223511616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 554422592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 554422656 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 248905 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 8911778 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.027928 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 8911779 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.027928 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.164766 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 8662891 97.21% 97.21% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 248887 2.79% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 8662892 97.21% 97.21% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 248887 2.79% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8911778 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5067118500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 8911779 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5067119000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7756291499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7756292749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4138722865 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4138723116 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 314057 # Transaction distribution -system.membus.trans_dist::ReadResp 314057 # Transaction distribution +system.membus.trans_dist::ReadReq 314058 # Transaction distribution +system.membus.trans_dist::ReadResp 314058 # Transaction distribution system.membus.trans_dist::Writeback 66342 # Transaction distribution -system.membus.trans_dist::UpgradeReq 18 # Transaction distribution -system.membus.trans_dist::UpgradeResp 18 # Transaction distribution +system.membus.trans_dist::UpgradeReq 19 # Transaction distribution +system.membus.trans_dist::UpgradeResp 19 # Transaction distribution system.membus.trans_dist::ReadExReq 1398 # Transaction distribution system.membus.trans_dist::ReadExResp 1398 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 697288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 697288 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24435008 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24435008 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 697292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 697292 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24435072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24435072 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 381815 # Request fanout histogram +system.membus.snoop_fanout::samples 381817 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 381815 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 381817 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 381815 # Request fanout histogram -system.membus.reqLayer0.occupancy 746604866 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 381817 # Request fanout histogram +system.membus.reqLayer0.occupancy 746606366 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1648190996 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1648197495 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 790f4a782..f8c904908 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.395727 # Nu sim_ticks 395726778500 # Number of ticks simulated final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1109777 # Simulator instruction rate (inst/s) -host_op_rate 1366282 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 685499869 # Simulator tick rate (ticks/s) -host_mem_usage 303676 # Number of bytes of host memory used -host_seconds 577.28 # Real time elapsed on the host +host_inst_rate 1575908 # Simulator instruction rate (inst/s) +host_op_rate 1940150 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 973424664 # Simulator tick rate (ticks/s) +host_mem_usage 311080 # Number of bytes of host memory used +host_seconds 406.53 # Real time elapsed on the host sim_insts 640654411 # Number of instructions simulated sim_ops 788730070 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram -system.membus.snoop_fanout::mean 2.629116 # Request fanout histogram +system.membus.snoop_fanout::mean 0.629116 # Request fanout histogram system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 379292454 37.09% 37.09% # Request fanout histogram -system.membus.snoop_fanout::3 643377899 62.91% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 379292454 37.09% 37.09% # Request fanout histogram +system.membus.snoop_fanout::1 643377899 62.91% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 1022670353 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index e0c0a3846..4a7e6f230 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -598,17 +598,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 883911 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 883911 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 883911 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 22befaf24..12a478a63 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.057717 # Nu sim_ticks 57716694500 # Number of ticks simulated final_tick 57716694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141604 # Simulator instruction rate (inst/s) -host_op_rate 181090 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 115249030 # Simulator tick rate (ticks/s) -host_mem_usage 314220 # Number of bytes of host memory used -host_seconds 500.80 # Real time elapsed on the host +host_inst_rate 194770 # Simulator instruction rate (inst/s) +host_op_rate 249082 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 158520150 # Simulator tick rate (ticks/s) +host_mem_usage 322420 # Number of bytes of host memory used +host_seconds 364.10 # Real time elapsed on the host sim_insts 70915128 # Number of instructions simulated sim_ops 90690084 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -809,17 +809,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 21367424 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 333867 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 333867 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 333867 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 333867 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 295378500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index e0d8233d1..3b7597919 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.033331 # Nu sim_ticks 33330913000 # Number of ticks simulated final_tick 33330913000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93420 # Simulator instruction rate (inst/s) -host_op_rate 119473 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43913176 # Simulator tick rate (ticks/s) -host_mem_usage 317168 # Number of bytes of host memory used -host_seconds 759.02 # Real time elapsed on the host +host_inst_rate 123947 # Simulator instruction rate (inst/s) +host_op_rate 158514 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58262578 # Simulator tick rate (ticks/s) +host_mem_usage 323704 # Number of bytes of host memory used +host_seconds 572.08 # Real time elapsed on the host sim_insts 70907630 # Number of instructions simulated sim_ops 90682585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1158,17 +1158,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 68691776 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 151304 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1224624 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.123542 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.123542 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.329058 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 1073332 87.65% 87.65% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 151292 12.35% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1073332 87.65% 87.65% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 151292 12.35% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1224624 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 801075000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index abad5bc99..fd03f6311 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.121265 # Nu sim_ticks 1121265462500 # Number of ticks simulated final_tick 1121265462500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 175724 # Simulator instruction rate (inst/s) -host_op_rate 189316 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 127565822 # Simulator tick rate (ticks/s) -host_mem_usage 306448 # Number of bytes of host memory used -host_seconds 8789.70 # Real time elapsed on the host +host_inst_rate 238084 # Simulator instruction rate (inst/s) +host_op_rate 256500 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 172835636 # Simulator tick rate (ticks/s) +host_mem_usage 314372 # Number of bytes of host memory used +host_seconds 6487.47 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -816,17 +816,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 827453184 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 12928956 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 12928956 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12928956 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 12928956 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 10165090000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index ddc6d4e58..d2f403426 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.771725 # Nu sim_ticks 771725169000 # Number of ticks simulated final_tick 771725169000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109963 # Simulator instruction rate (inst/s) -host_op_rate 118469 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54942138 # Simulator tick rate (ticks/s) -host_mem_usage 305172 # Number of bytes of host memory used -host_seconds 14046.14 # Real time elapsed on the host +host_inst_rate 137392 # Simulator instruction rate (inst/s) +host_op_rate 148019 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68646343 # Simulator tick rate (ticks/s) +host_mem_usage 311812 # Number of bytes of host memory used +host_seconds 11242.04 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1153,17 +1153,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 1397638528 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 1298291 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 23136394 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.056115 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.056115 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.230143 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 21838103 94.39% 94.39% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 1298291 5.61% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 21838103 94.39% 94.39% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1298291 5.61% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 23136394 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 15749679999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index 93ba57c1e..39b8c8798 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.832017 # Nu sim_ticks 832017490500 # Number of ticks simulated final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1379227 # Simulator instruction rate (inst/s) -host_op_rate 1485908 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 742955189 # Simulator tick rate (ticks/s) -host_mem_usage 295688 # Number of bytes of host memory used -host_seconds 1119.88 # Real time elapsed on the host +host_inst_rate 1936914 # Simulator instruction rate (inst/s) +host_op_rate 2086731 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1043366913 # Simulator tick rate (ticks/s) +host_mem_usage 303348 # Number of bytes of host memory used +host_seconds 797.44 # Real time elapsed on the host sim_insts 1544563042 # Number of instructions simulated sim_ops 1664032434 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 system.membus.pkt_size::total 8383808423 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 2172060895 # Request fanout histogram -system.membus.snoop_fanout::mean 2.711106 # Request fanout histogram +system.membus.snoop_fanout::mean 0.711106 # Request fanout histogram system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 627495305 28.89% 28.89% # Request fanout histogram -system.membus.snoop_fanout::3 1544565590 71.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 627495305 28.89% 28.89% # Request fanout histogram +system.membus.snoop_fanout::1 1544565590 71.11% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 2172060895 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 15b1ad4ad..144026919 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -590,17 +590,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 12813292 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 12813292 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12813292 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 12813292 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 566338996..08e41bb17 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007227500 # Number of ticks simulated final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1299561 # Simulator instruction rate (inst/s) -host_op_rate 2024834 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1229541445 # Simulator tick rate (ticks/s) -host_mem_usage 299440 # Number of bytes of host memory used -host_seconds 2314.69 # Real time elapsed on the host +host_inst_rate 1464727 # Simulator instruction rate (inst/s) +host_op_rate 2282177 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1385807923 # Simulator tick rate (ticks/s) +host_mem_usage 304512 # Number of bytes of host memory used +host_seconds 2053.68 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,33 +35,6 @@ system.physmem.bw_write::total 542745211 # Wr system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution -system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution -system.membus.trans_dist::WriteReq 438528338 # Transaction distribution -system.membus.trans_dist::WriteResp 438528338 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 8026465764 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11381891932 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 32105863056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 38674388193 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram -system.membus.snoop_fanout::mean 2.705196 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.455955 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 1677713084 29.48% 29.48% # Request fanout histogram -system.membus.snoop_fanout::3 4013232882 70.52% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram -system.membus.snoop_fanout::total 5690945966 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 46 # Number of system calls @@ -125,5 +98,30 @@ system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 4686862596 # Class of executed instruction +system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution +system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution +system.membus.trans_dist::WriteReq 438528338 # Transaction distribution +system.membus.trans_dist::WriteResp 438528338 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 8026465764 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11381891932 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 32105863056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 38674388193 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram +system.membus.snoop_fanout::mean 0.705196 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.455955 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1677713084 29.48% 29.48% # Request fanout histogram +system.membus.snoop_fanout::1 4013232882 70.52% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 5690945966 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 9a9ddb0f1..b101e64c0 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.882580 # Nu sim_ticks 5882580398500 # Number of ticks simulated final_tick 5882580398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 733187 # Simulator instruction rate (inst/s) -host_op_rate 1142372 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1433815394 # Simulator tick rate (ticks/s) -host_mem_usage 313792 # Number of bytes of host memory used -host_seconds 4102.75 # Real time elapsed on the host +host_inst_rate 739516 # Simulator instruction rate (inst/s) +host_op_rate 1152234 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1446192754 # Simulator tick rate (ticks/s) +host_mem_usage 314252 # Number of bytes of host memory used +host_seconds 4067.63 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -449,17 +449,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 12811308 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 12811308 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12811308 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 12811308 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index fc0b314ed..da5e39914 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131767 # Nu sim_ticks 131767151500 # Number of ticks simulated final_tick 131767151500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 176753 # Simulator instruction rate (inst/s) -host_op_rate 186327 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 135158895 # Simulator tick rate (ticks/s) -host_mem_usage 309748 # Number of bytes of host memory used -host_seconds 974.91 # Real time elapsed on the host +host_inst_rate 244794 # Simulator instruction rate (inst/s) +host_op_rate 258052 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 187187675 # Simulator tick rate (ticks/s) +host_mem_usage 317932 # Number of bytes of host memory used +host_seconds 703.93 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -783,17 +783,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 417024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 6517 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 6517 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 6517 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 6517 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 3274500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index e84c7e623..a8c1caea2 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.085032 # Nu sim_ticks 85032044000 # Number of ticks simulated final_tick 85032044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98638 # Simulator instruction rate (inst/s) -host_op_rate 103981 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48678127 # Simulator tick rate (ticks/s) -host_mem_usage 307440 # Number of bytes of host memory used -host_seconds 1746.82 # Real time elapsed on the host +host_inst_rate 135904 # Simulator instruction rate (inst/s) +host_op_rate 143266 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67069129 # Simulator tick rate (ticks/s) +host_mem_usage 314096 # Number of bytes of host memory used +host_seconds 1267.83 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1113,17 +1113,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 12368832 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 2153 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 195416 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011018 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.011018 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.104385 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 193263 98.90% 98.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 2153 1.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 193263 98.90% 98.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 2153 1.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 195416 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 161509500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 00f8f6a2f..1d32cdbce 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.081225 # Nu sim_ticks 81224844500 # Number of ticks simulated final_tick 81224844500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72712 # Simulator instruction rate (inst/s) -host_op_rate 121872 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44718419 # Simulator tick rate (ticks/s) -host_mem_usage 340792 # Number of bytes of host memory used -host_seconds 1816.36 # Real time elapsed on the host +host_inst_rate 91947 # Simulator instruction rate (inst/s) +host_op_rate 154111 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56548085 # Simulator tick rate (ticks/s) +host_mem_usage 347388 # Number of bytes of host memory used +host_seconds 1436.39 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -944,17 +944,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 631040 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 299 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 10459 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 10459 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 10459 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 10459 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 5242500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |