diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
| commit | 8b4b1dcb86b0799a8c32056427581a8b6249a3bf (patch) | |
| tree | 96016b415513dc6c2c29877e1a76220e0edae629 /tests/long | |
| parent | a00383a40aeb8347af7e05f3966ab141484921a5 (diff) | |
| download | gem5-8b4b1dcb86b0799a8c32056427581a8b6249a3bf.tar.xz | |
stats: Update stats for DRAM changes
This patch updates the stats to reflect the changes to the DRAM
controller.
Diffstat (limited to 'tests/long')
31 files changed, 27046 insertions, 29996 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 4177c2e35..bc7291548 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.903338 # Number of seconds simulated -sim_ticks 1903338216000 # Number of ticks simulated -final_tick 1903338216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.905240 # Number of seconds simulated +sim_ticks 1905239522500 # Number of ticks simulated +final_tick 1905239522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 150214 # Simulator instruction rate (inst/s) -host_op_rate 150214 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5096064990 # Simulator tick rate (ticks/s) -host_mem_usage 314972 # Number of bytes of host memory used -host_seconds 373.49 # Real time elapsed on the host -sim_insts 56103611 # Number of instructions simulated -sim_ops 56103611 # Number of ops (including micro ops) simulated +host_inst_rate 125426 # Simulator instruction rate (inst/s) +host_op_rate 125426 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4213194084 # Simulator tick rate (ticks/s) +host_mem_usage 351852 # Number of bytes of host memory used +host_seconds 452.21 # Real time elapsed on the host +sim_insts 56718526 # Number of instructions simulated +sim_ops 56718526 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 740992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24346432 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 236544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 996032 # Number of bytes read from this memory -system.physmem.bytes_read::total 28970176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 740992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 236544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977536 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7923904 # Number of bytes written to this memory -system.physmem.bytes_written::total 7923904 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11578 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 380413 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41409 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3696 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 15563 # Number of read requests responded to by this memory -system.physmem.num_reads::total 452659 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123811 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123811 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 389312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12791438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1392383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 124278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 523308 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15220719 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 389312 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 124278 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513590 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4163161 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4163161 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4163161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 389312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12791438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1392383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 124278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 523308 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19383880 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 452659 # Number of read requests accepted -system.physmem.writeReqs 123811 # Number of write requests accepted -system.physmem.readBursts 452659 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123811 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28966400 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3776 # Total number of bytes read from write queue -system.physmem.bytesWritten 7923264 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28970176 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7923904 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 59 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu0.inst 764480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24384256 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2649344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 214080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 925440 # Number of bytes read from this memory +system.physmem.bytes_read::total 28937600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 764480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 214080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 978560 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7885248 # Number of bytes written to this memory +system.physmem.bytes_written::total 7885248 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11945 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 381004 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41396 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3345 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 14460 # Number of read requests responded to by this memory +system.physmem.num_reads::total 452150 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123207 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123207 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 401251 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12798525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1390557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 112364 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 485734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15188432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 401251 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 112364 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513615 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4138717 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4138717 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4138717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 401251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12798525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1390557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 112364 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 485734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19327149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 452150 # Number of read requests accepted +system.physmem.writeReqs 123207 # Number of write requests accepted +system.physmem.readBursts 452150 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123207 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28929984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue +system.physmem.bytesWritten 7883136 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28937600 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7885248 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3474 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28542 # Per bank write bursts -system.physmem.perBankRdBursts::1 28115 # Per bank write bursts -system.physmem.perBankRdBursts::2 28449 # Per bank write bursts -system.physmem.perBankRdBursts::3 28319 # Per bank write bursts -system.physmem.perBankRdBursts::4 28001 # Per bank write bursts -system.physmem.perBankRdBursts::5 28388 # Per bank write bursts -system.physmem.perBankRdBursts::6 28437 # Per bank write bursts -system.physmem.perBankRdBursts::7 28681 # Per bank write bursts -system.physmem.perBankRdBursts::8 28670 # Per bank write bursts -system.physmem.perBankRdBursts::9 28576 # Per bank write bursts -system.physmem.perBankRdBursts::10 28034 # Per bank write bursts -system.physmem.perBankRdBursts::11 27899 # Per bank write bursts -system.physmem.perBankRdBursts::12 27884 # Per bank write bursts -system.physmem.perBankRdBursts::13 28245 # Per bank write bursts -system.physmem.perBankRdBursts::14 28268 # Per bank write bursts -system.physmem.perBankRdBursts::15 28092 # Per bank write bursts -system.physmem.perBankWrBursts::0 8222 # Per bank write bursts -system.physmem.perBankWrBursts::1 7571 # Per bank write bursts -system.physmem.perBankWrBursts::2 7821 # Per bank write bursts -system.physmem.perBankWrBursts::3 7782 # Per bank write bursts -system.physmem.perBankWrBursts::4 7428 # Per bank write bursts -system.physmem.perBankWrBursts::5 7859 # Per bank write bursts -system.physmem.perBankWrBursts::6 7924 # Per bank write bursts -system.physmem.perBankWrBursts::7 7992 # Per bank write bursts -system.physmem.perBankWrBursts::8 7912 # Per bank write bursts -system.physmem.perBankWrBursts::9 7920 # Per bank write bursts -system.physmem.perBankWrBursts::10 7418 # Per bank write bursts -system.physmem.perBankWrBursts::11 7297 # Per bank write bursts -system.physmem.perBankWrBursts::12 7319 # Per bank write bursts -system.physmem.perBankWrBursts::13 7829 # Per bank write bursts -system.physmem.perBankWrBursts::14 7922 # Per bank write bursts -system.physmem.perBankWrBursts::15 7585 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 5017 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28700 # Per bank write bursts +system.physmem.perBankRdBursts::1 28863 # Per bank write bursts +system.physmem.perBankRdBursts::2 29008 # Per bank write bursts +system.physmem.perBankRdBursts::3 28541 # Per bank write bursts +system.physmem.perBankRdBursts::4 28135 # Per bank write bursts +system.physmem.perBankRdBursts::5 28059 # Per bank write bursts +system.physmem.perBankRdBursts::6 27918 # Per bank write bursts +system.physmem.perBankRdBursts::7 27861 # Per bank write bursts +system.physmem.perBankRdBursts::8 27885 # Per bank write bursts +system.physmem.perBankRdBursts::9 28003 # Per bank write bursts +system.physmem.perBankRdBursts::10 27955 # Per bank write bursts +system.physmem.perBankRdBursts::11 28030 # Per bank write bursts +system.physmem.perBankRdBursts::12 28165 # Per bank write bursts +system.physmem.perBankRdBursts::13 28514 # Per bank write bursts +system.physmem.perBankRdBursts::14 28239 # Per bank write bursts +system.physmem.perBankRdBursts::15 28155 # Per bank write bursts +system.physmem.perBankWrBursts::0 8383 # Per bank write bursts +system.physmem.perBankWrBursts::1 8222 # Per bank write bursts +system.physmem.perBankWrBursts::2 8291 # Per bank write bursts +system.physmem.perBankWrBursts::3 7900 # Per bank write bursts +system.physmem.perBankWrBursts::4 7506 # Per bank write bursts +system.physmem.perBankWrBursts::5 7518 # Per bank write bursts +system.physmem.perBankWrBursts::6 7426 # Per bank write bursts +system.physmem.perBankWrBursts::7 7231 # Per bank write bursts +system.physmem.perBankWrBursts::8 7193 # Per bank write bursts +system.physmem.perBankWrBursts::9 7295 # Per bank write bursts +system.physmem.perBankWrBursts::10 7315 # Per bank write bursts +system.physmem.perBankWrBursts::11 7381 # Per bank write bursts +system.physmem.perBankWrBursts::12 7680 # Per bank write bursts +system.physmem.perBankWrBursts::13 8142 # Per bank write bursts +system.physmem.perBankWrBursts::14 8013 # Per bank write bursts +system.physmem.perBankWrBursts::15 7678 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 1903333578000 # Total gap between requests +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 1905235063000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 452659 # Read request sizes (log2) +system.physmem.readPktSize::6 452150 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 123811 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 323009 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 67548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 34699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1491 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1342 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 975 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 964 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 964 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 123207 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 319865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54341 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 31702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9495 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3776 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3798 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3977 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2606 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1493 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1685 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -143,461 +143,375 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 24 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 47120 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 782.856367 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 226.112166 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1866.075506 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 16751 35.55% 35.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6847 14.53% 50.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 4876 10.35% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2833 6.01% 66.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1808 3.84% 70.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1449 3.08% 73.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1103 2.34% 75.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 806 1.71% 77.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 633 1.34% 78.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 628 1.33% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 650 1.38% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 508 1.08% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 311 0.66% 83.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 305 0.65% 83.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 262 0.56% 84.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 366 0.78% 85.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 155 0.33% 85.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 210 0.45% 85.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 130 0.28% 86.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 135 0.29% 86.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 148 0.31% 86.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 388 0.82% 87.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 228 0.48% 88.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 713 1.51% 89.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 124 0.26% 89.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 79 0.17% 90.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 68 0.14% 90.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 140 0.30% 90.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 59 0.13% 90.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 90 0.19% 90.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 49 0.10% 90.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 89 0.19% 91.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 69 0.15% 91.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 88 0.19% 91.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 28 0.06% 91.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 26 0.06% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 54 0.11% 91.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 52 0.11% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 27 0.06% 91.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 28 0.06% 91.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 27 0.06% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 54 0.11% 92.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 53 0.11% 92.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 17 0.04% 92.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 31 0.07% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 83 0.18% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 40 0.08% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 35 0.07% 92.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 42 0.09% 92.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 86 0.18% 92.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 24 0.05% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 15 0.03% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 51 0.11% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 50 0.11% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 24 0.05% 93.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 22 0.05% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 24 0.05% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 52 0.11% 93.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 51 0.11% 93.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 12 0.03% 93.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 29 0.06% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 84 0.18% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 41 0.09% 93.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 31 0.07% 94.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 38 0.08% 94.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 87 0.18% 94.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 24 0.05% 94.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 17 0.04% 94.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 52 0.11% 94.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 51 0.11% 94.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 24 0.05% 94.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 22 0.05% 94.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 23 0.05% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 50 0.11% 94.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 51 0.11% 94.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 12 0.03% 94.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 27 0.06% 95.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 86 0.18% 95.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 41 0.09% 95.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 30 0.06% 95.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 39 0.08% 95.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 84 0.18% 95.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 24 0.05% 95.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 9 0.02% 95.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 53 0.11% 95.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 50 0.11% 95.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 23 0.05% 95.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 22 0.05% 95.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 22 0.05% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 49 0.10% 96.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 50 0.11% 96.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 9 0.02% 96.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 25 0.05% 96.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 85 0.18% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 41 0.09% 96.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 30 0.06% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 42 0.09% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 84 0.18% 96.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 24 0.05% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 10 0.02% 96.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 52 0.11% 97.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 52 0.11% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 24 0.05% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 22 0.05% 97.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 25 0.05% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 49 0.10% 97.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 49 0.10% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 8 0.02% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 27 0.06% 97.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 87 0.18% 97.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 41 0.09% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 317 0.67% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.00% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 1 0.00% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 6 0.01% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7491 1 0.00% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 14 0.03% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 2 0.00% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 8 0.02% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 1 0.00% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 3 0.01% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 322 0.68% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 2 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 2 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 3 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9731 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 3 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10307 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11331 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11587 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11907 2 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 4 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12483 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 2 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13315 3 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 3 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 3 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 39 0.08% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 175 0.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 47120 # Bytes accessed per row activation -system.physmem.totQLat 8783315250 # Total ticks spent queuing -system.physmem.totMemAccLat 16310447750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2263000000 # Total ticks spent in databus transfers -system.physmem.totBankLat 5264132500 # Total ticks spent accessing banks -system.physmem.avgQLat 19406.35 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 11630.87 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 51367 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 630.908404 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 404.510586 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 424.248985 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 9707 18.90% 18.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6974 13.58% 32.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3124 6.08% 38.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1892 3.68% 42.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1518 2.96% 45.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 943 1.84% 47.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 823 1.60% 48.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 886 1.72% 50.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25500 49.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 51367 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7232 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 62.502074 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2469.163441 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 7229 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7232 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7232 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.031803 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.787924 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.763450 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6148 85.01% 85.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 35 0.48% 85.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 69 0.95% 86.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 422 5.84% 92.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 144 1.99% 94.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 50 0.69% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 33 0.46% 95.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 29 0.40% 95.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 50 0.69% 96.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 33 0.46% 96.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 22 0.30% 97.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 30 0.41% 97.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 23 0.32% 98.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 33 0.46% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 3 0.04% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 10 0.14% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 7 0.10% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 5 0.07% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 2 0.03% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 3 0.04% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 4 0.06% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 3 0.04% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 4 0.06% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 6 0.08% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 7 0.10% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 2 0.03% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 5 0.07% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 4 0.06% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 2 0.03% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 2 0.03% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 2 0.03% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 9 0.12% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 8 0.11% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 6 0.08% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 1 0.01% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 4 0.06% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 3 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 2 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 4 0.06% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7232 # Writes before turning the bus around for reads +system.physmem.totQLat 10473139750 # Total ticks spent queuing +system.physmem.totMemAccLat 18209837250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2260155000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5476542500 # Total ticks spent accessing banks +system.physmem.avgQLat 23169.07 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 12115.41 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 36037.22 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.22 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.16 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.16 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 40284.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.14 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.19 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.14 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.32 # Average write queue length when enqueuing -system.physmem.readRowHits 430734 # Number of row buffer hits during reads -system.physmem.writeRowHits 98547 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.59 # Row buffer hit rate for writes -system.physmem.avgGap 3301704.47 # Average gap between requests -system.physmem.pageHitRate 91.82 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 19439855 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296479 # Transaction distribution -system.membus.trans_dist::ReadResp 296230 # Transaction distribution -system.membus.trans_dist::WriteReq 12351 # Transaction distribution -system.membus.trans_dist::WriteResp 12351 # Transaction distribution -system.membus.trans_dist::Writeback 123811 # Transaction distribution -system.membus.trans_dist::UpgradeReq 5304 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1475 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3474 # Transaction distribution -system.membus.trans_dist::ReadExReq 164353 # Transaction distribution -system.membus.trans_dist::ReadExResp 164224 # Transaction distribution -system.membus.trans_dist::BadAddressError 249 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39094 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 915454 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 498 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 955046 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124656 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124656 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1079702 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68202 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31586624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31654826 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307456 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5307456 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36962282 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36962282 # Total data (bytes) -system.membus.snoop_data_through_bus 38336 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 36252500 # Layer occupancy (ticks) +system.physmem.avgRdQLen 1.83 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.68 # Average write queue length when enqueuing +system.physmem.readRowHits 407908 # Number of row buffer hits during reads +system.physmem.writeRowHits 99848 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.24 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.04 # Row buffer hit rate for writes +system.physmem.avgGap 3311396.34 # Average gap between requests +system.physmem.pageHitRate 88.27 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.40 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 19386335 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296672 # Transaction distribution +system.membus.trans_dist::ReadResp 296448 # Transaction distribution +system.membus.trans_dist::WriteReq 13044 # Transaction distribution +system.membus.trans_dist::WriteResp 13044 # Transaction distribution +system.membus.trans_dist::Writeback 123207 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9628 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5545 # Transaction distribution +system.membus.trans_dist::UpgradeResp 5017 # Transaction distribution +system.membus.trans_dist::ReadExReq 163957 # Transaction distribution +system.membus.trans_dist::ReadExResp 163513 # Transaction distribution +system.membus.trans_dist::BadAddressError 224 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40492 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 924104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 448 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 965044 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124646 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124646 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1089690 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73787 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31516032 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31589819 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306816 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5306816 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36896635 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36896635 # Total data (bytes) +system.membus.snoop_data_through_bus 38976 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 37949499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1624596499 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1621348498 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 317500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 283500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3836772510 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3837196476 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376321991 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376708248 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 345713 # number of replacements -system.l2c.tags.tagsinuse 65292.619294 # Cycle average of tags in use -system.l2c.tags.total_refs 2607692 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 410924 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.345923 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7069563750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53648.503329 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4120.078366 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5598.798644 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1365.340117 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 559.898838 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.818611 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.062867 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.085431 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.020833 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008543 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996286 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65211 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2154 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5524 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6881 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 50473 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.995041 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27399611 # Number of tag accesses -system.l2c.tags.data_accesses 27399611 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 754547 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 572386 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 313557 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 249669 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1890159 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 840492 # number of Writeback hits -system.l2c.Writeback_hits::total 840492 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 130 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 74 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 204 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 33 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 70 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 144073 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 44330 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 188403 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 754547 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 716459 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 313557 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 293999 # number of demand (read+write) hits -system.l2c.demand_hits::total 2078562 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 754547 # number of overall hits -system.l2c.overall_hits::cpu0.data 716459 # number of overall hits -system.l2c.overall_hits::cpu1.inst 313557 # number of overall hits -system.l2c.overall_hits::cpu1.data 293999 # number of overall hits -system.l2c.overall_hits::total 2078562 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11586 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 272059 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3706 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1775 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289126 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2565 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 587 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3152 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 58 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 107 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 165 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 108741 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 14088 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122829 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 11586 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 380800 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3706 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 15863 # number of demand (read+write) misses -system.l2c.demand_misses::total 411955 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11586 # number of overall misses -system.l2c.overall_misses::cpu0.data 380800 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3706 # number of overall misses -system.l2c.overall_misses::cpu1.data 15863 # number of overall misses -system.l2c.overall_misses::total 411955 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 929054999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17693461250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 314236981 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 144928247 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 19081681477 # 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mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64110.329818 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53070.867711 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67735.355456 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76765.153760 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 53842.237225 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10019.190521 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.523416 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10018.881135 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.298153 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10010.343458 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10022.063197 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70714.722875 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 87695.479725 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72530.037020 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64110.329818 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58121.888530 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67735.355456 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86384.017237 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59393.760756 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64110.329818 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58121.888530 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67735.355456 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86384.017237 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59393.760756 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -735,15 +649,15 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.213166 # Cycle average of tags in use +system.iocache.tags.replacements 41698 # number of replacements +system.iocache.tags.tagsinuse 0.475429 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1712301131000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.213166 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.013323 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.013323 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1712299730000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.475429 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.029714 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.029714 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -757,14 +671,14 @@ system.iocache.demand_misses::tsunami.ide 41727 # n system.iocache.demand_misses::total 41727 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21368383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21368383 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 13021515788 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 13021515788 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 13042884171 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 13042884171 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 13042884171 # number of overall miss cycles -system.iocache.overall_miss_latency::total 13042884171 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21363133 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21363133 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 13166015946 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 13166015946 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13187379079 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13187379079 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13187379079 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13187379079 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -781,24 +695,24 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122105.045714 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122105.045714 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 313378.797362 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 313378.797362 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 312576.609174 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 312576.609174 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 312576.609174 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 312576.609174 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 407057 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122075.045714 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122075.045714 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 316856.371438 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 316856.371438 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 316039.472739 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 316039.472739 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 316039.472739 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 316039.472739 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 391077 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 29358 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28468 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.865284 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.737424 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks +system.iocache.writebacks::writebacks 41523 # number of writebacks +system.iocache.writebacks::total 41523 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses @@ -807,14 +721,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41727 system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12267383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12267383 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10859254806 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10859254806 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10871522189 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10871522189 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10871522189 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10871522189 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12262133 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12262133 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 11002982450 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 11002982450 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 11015244583 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 11015244583 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 11015244583 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 11015244583 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -823,14 +737,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70099.331429 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70099.331429 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 261341.326675 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 261341.326675 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 260539.271671 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 260539.271671 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 260539.271671 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 260539.271671 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70069.331429 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70069.331429 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 264800.309251 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 264800.309251 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263983.621708 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 263983.621708 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263983.621708 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 263983.621708 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -844,35 +758,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 11006012 # Number of BP lookups -system.cpu0.branchPred.condPredicted 9319545 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 291548 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 7161716 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4729334 # Number of BTB hits +system.cpu0.branchPred.lookups 12197818 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10301308 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 323625 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 8091894 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5160475 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.036324 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 682987 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 26515 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 63.773389 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 773216 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29770 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7888949 # DTB read hits -system.cpu0.dtb.read_misses 30101 # DTB read misses -system.cpu0.dtb.read_acv 574 # DTB read access violations -system.cpu0.dtb.read_accesses 665608 # DTB read accesses -system.cpu0.dtb.write_hits 5247941 # DTB write hits -system.cpu0.dtb.write_misses 8093 # DTB write misses -system.cpu0.dtb.write_acv 365 # DTB write access violations -system.cpu0.dtb.write_accesses 232480 # DTB write accesses -system.cpu0.dtb.data_hits 13136890 # DTB hits -system.cpu0.dtb.data_misses 38194 # DTB misses -system.cpu0.dtb.data_acv 939 # DTB access violations -system.cpu0.dtb.data_accesses 898088 # DTB accesses -system.cpu0.itb.fetch_hits 973403 # ITB hits -system.cpu0.itb.fetch_misses 31216 # ITB misses -system.cpu0.itb.fetch_acv 1004 # ITB acv -system.cpu0.itb.fetch_accesses 1004619 # ITB accesses +system.cpu0.dtb.read_hits 8724392 # DTB read hits +system.cpu0.dtb.read_misses 30821 # DTB read misses +system.cpu0.dtb.read_acv 561 # DTB read access violations +system.cpu0.dtb.read_accesses 667825 # DTB read accesses +system.cpu0.dtb.write_hits 5867379 # DTB write hits +system.cpu0.dtb.write_misses 8333 # DTB write misses +system.cpu0.dtb.write_acv 362 # DTB write access violations +system.cpu0.dtb.write_accesses 233878 # DTB write accesses +system.cpu0.dtb.data_hits 14591771 # DTB hits +system.cpu0.dtb.data_misses 39154 # DTB misses +system.cpu0.dtb.data_acv 923 # DTB access violations +system.cpu0.dtb.data_accesses 901703 # DTB accesses +system.cpu0.itb.fetch_hits 1047253 # ITB hits +system.cpu0.itb.fetch_misses 31067 # ITB misses +system.cpu0.itb.fetch_acv 998 # ITB acv +system.cpu0.itb.fetch_accesses 1078320 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -885,269 +799,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 104578589 # number of cpu cycles simulated +system.cpu0.numCycles 112262549 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 21960114 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 56555379 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 11006012 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5412321 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10656012 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1518801 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 32354382 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 30030 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 204805 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 243991 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 103 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6896028 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 198863 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 66418859 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.851496 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.187669 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 25337690 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 62232975 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12197818 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5933691 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11660813 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1669062 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 34963299 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31852 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 204835 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 245581 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 284 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7519019 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 220862 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 73507816 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.846617 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.186991 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 55762847 83.96% 83.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 696881 1.05% 85.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1363707 2.05% 87.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 607827 0.92% 87.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2362378 3.56% 91.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 460793 0.69% 92.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 493104 0.74% 92.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 775074 1.17% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3896248 5.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 61847003 84.14% 84.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 769960 1.05% 85.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1463561 1.99% 87.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 676221 0.92% 88.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2490968 3.39% 91.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 505392 0.69% 92.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 543861 0.74% 92.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 933568 1.27% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4277282 5.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 66418859 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.105242 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.540793 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 23145338 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 31820288 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9657130 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 858074 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 938028 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 439220 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 31710 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 55497748 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 98418 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 938028 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 24047696 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12280609 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 16434779 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9089203 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3628542 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 52477613 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6876 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 427894 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1374075 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 35152162 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 63950241 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 63830636 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 110747 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30925813 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4226341 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1321793 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 195129 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 9844333 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 8256385 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5476723 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1002198 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 667476 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 46574896 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1622063 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 45553168 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 69417 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5159281 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2712846 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1098313 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 66418859 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.685847 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.329893 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 73507816 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.108654 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.554352 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26369028 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 34601594 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10599753 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 908827 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1028613 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 489342 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35202 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 61098455 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 108348 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1028613 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27370799 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12650473 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18559497 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9975684 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3922748 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 57686354 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6807 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 465136 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1446625 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 38461887 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 70023385 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 69867874 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 145011 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33864047 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4597832 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1504040 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 221397 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10820518 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9135753 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6149920 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1079808 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 706714 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 51077926 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1853906 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 49994907 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 110749 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5661802 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2962344 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1252355 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 73507816 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.680130 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.328001 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 46042875 69.32% 69.32% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9328009 14.04% 83.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4252197 6.40% 89.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2720710 4.10% 93.86% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2085310 3.14% 97.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1089347 1.64% 98.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 576580 0.87% 99.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 279468 0.42% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 44363 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 51188064 69.64% 69.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10233888 13.92% 83.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4604901 6.26% 89.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2962380 4.03% 93.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2331848 3.17% 97.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1189595 1.62% 98.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 642601 0.87% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 303208 0.41% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 51331 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 66418859 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 73507816 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 65077 10.66% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 284948 46.66% 57.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 260601 42.68% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 67972 10.01% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 320913 47.27% 57.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 290070 42.72% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 31229788 68.56% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47289 0.10% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 14649 0.03% 68.70% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.70% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.70% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.70% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 8205422 18.01% 86.72% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5307142 11.65% 98.37% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 743210 1.63% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3770 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 34052559 68.11% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 53588 0.11% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 16727 0.03% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9088781 18.18% 86.44% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5934753 11.87% 98.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 842846 1.69% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 45553168 # Type of FU issued -system.cpu0.iq.rate 0.435588 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 610626 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013405 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 157729759 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 53136035 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 44625486 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 475478 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 231159 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 224228 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 45911492 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 248517 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 497947 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 49994907 # Type of FU issued +system.cpu0.iq.rate 0.445339 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 678955 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013580 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 173664474 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 58303886 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 48932524 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 622859 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 301167 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 293964 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 50344041 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 326051 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 531595 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1006840 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3517 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 11189 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 378910 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1104780 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2697 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 11676 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 443054 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 13584 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 146356 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 13921 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 147330 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 938028 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8572601 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 702117 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50999649 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 565079 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 8256385 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5476723 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1432117 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 572819 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5269 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 11189 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 141170 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 315582 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 456752 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 45215846 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 7939970 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 337321 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1028613 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8821962 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 743484 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 56052726 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 628552 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9135753 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6149920 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1633160 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 601804 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5465 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 11676 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 157790 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 354691 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 512481 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 49615767 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8780349 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 379139 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 2802690 # number of nop insts executed -system.cpu0.iew.exec_refs 13207799 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7146234 # Number of branches executed -system.cpu0.iew.exec_stores 5267829 # Number of stores executed -system.cpu0.iew.exec_rate 0.432362 # Inst execution rate -system.cpu0.iew.wb_sent 44934571 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44849714 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 22315831 # num instructions producing a value -system.cpu0.iew.wb_consumers 29845824 # num instructions consuming a value +system.cpu0.iew.exec_nop 3120894 # number of nop insts executed +system.cpu0.iew.exec_refs 14670742 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7826693 # Number of branches executed +system.cpu0.iew.exec_stores 5890393 # Number of stores executed +system.cpu0.iew.exec_rate 0.441962 # Inst execution rate +system.cpu0.iew.wb_sent 49317778 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 49226488 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24274382 # num instructions producing a value +system.cpu0.iew.wb_consumers 32670143 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.428861 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.747704 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.438494 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.743014 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 5562563 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 523750 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 426483 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 65480831 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.692465 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.608721 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6126865 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 601551 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 478401 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 72479203 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.687487 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.606917 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 48404249 73.92% 73.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7174588 10.96% 84.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3839849 5.86% 90.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2141053 3.27% 94.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1161993 1.77% 95.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 481151 0.73% 96.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 411214 0.63% 97.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 389126 0.59% 97.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1477608 2.26% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 53761554 74.18% 74.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7891628 10.89% 85.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4152119 5.73% 90.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2321486 3.20% 93.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1304265 1.80% 95.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 530677 0.73% 96.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 447192 0.62% 97.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 447640 0.62% 97.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1622642 2.24% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 65480831 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 45343202 # Number of instructions committed -system.cpu0.commit.committedOps 45343202 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 72479203 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 49828537 # Number of instructions committed +system.cpu0.commit.committedOps 49828537 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 12347358 # Number of memory references committed -system.cpu0.commit.loads 7249545 # Number of loads committed -system.cpu0.commit.membars 175312 # Number of memory barriers committed -system.cpu0.commit.branches 6808554 # Number of branches committed -system.cpu0.commit.fp_insts 222342 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 42040123 # Number of committed integer instructions. -system.cpu0.commit.function_calls 564734 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1477608 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13737839 # Number of memory references committed +system.cpu0.commit.loads 8030973 # Number of loads committed +system.cpu0.commit.membars 204358 # Number of memory barriers committed +system.cpu0.commit.branches 7461649 # Number of branches committed +system.cpu0.commit.fp_insts 291974 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 46136165 # Number of committed integer instructions. +system.cpu0.commit.function_calls 636945 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1622642 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 114710793 # The number of ROB reads -system.cpu0.rob.rob_writes 102749676 # The number of ROB writes -system.cpu0.timesIdled 949561 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 38159730 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3702093008 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 42781436 # Number of Instructions Simulated -system.cpu0.committedOps 42781436 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 42781436 # Number of Instructions Simulated -system.cpu0.cpi 2.444485 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.444485 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.409084 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.409084 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 59516377 # number of integer regfile reads -system.cpu0.int_regfile_writes 32453910 # number of integer regfile writes -system.cpu0.fp_regfile_reads 110308 # number of floating regfile reads -system.cpu0.fp_regfile_writes 111090 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1625466 # number of misc regfile reads -system.cpu0.misc_regfile_writes 747841 # number of misc regfile writes +system.cpu0.rob.rob_reads 126610557 # The number of ROB reads +system.cpu0.rob.rob_writes 112939421 # The number of ROB writes +system.cpu0.timesIdled 1039659 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 38754733 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3698211471 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 46979170 # Number of Instructions Simulated +system.cpu0.committedOps 46979170 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 46979170 # Number of Instructions Simulated +system.cpu0.cpi 2.389624 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.389624 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.418476 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.418476 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 65113755 # number of integer regfile reads +system.cpu0.int_regfile_writes 35503571 # number of integer regfile writes +system.cpu0.fp_regfile_reads 144629 # number of floating regfile reads +system.cpu0.fp_regfile_writes 146446 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1885764 # number of misc regfile reads +system.cpu0.misc_regfile_writes 851290 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1179,81 +1093,81 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 112873708 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2210500 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2210236 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12351 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12351 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 840492 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 5351 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1545 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 6896 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 353777 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 312228 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 249 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1532372 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2827999 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 634560 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 901176 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5896107 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 49032512 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 108336621 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20304832 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 35573309 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 213247274 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 213236842 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 1600000 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5059383343 # Layer occupancy (ticks) +system.toL2Bus.throughput 110236199 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2184890 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2184651 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13044 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13044 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 807199 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 9705 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5617 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 15322 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 337408 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295861 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 224 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1805066 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3017885 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 369158 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 600045 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5792154 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 57759168 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 115626954 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 11812096 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23360753 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 208558971 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 208548411 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 1477952 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4893610631 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 733500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 742500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3452114362 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4065813860 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5048329138 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5358512161 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1429282335 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1486623569 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 831641640 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 971081953 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1434231 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7371 # Transaction distribution -system.iobus.trans_dist::ReadResp 7371 # Transaction distribution -system.iobus.trans_dist::WriteReq 53903 # Transaction distribution -system.iobus.trans_dist::WriteResp 53903 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10490 # Packet count per connected master and slave (bytes) +system.iobus.throughput 1435731 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7377 # Transaction distribution +system.iobus.trans_dist::ReadResp 7377 # Transaction distribution +system.iobus.trans_dist::WriteReq 54596 # Transaction distribution +system.iobus.trans_dist::WriteResp 54596 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11886 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39094 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40492 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122548 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41960 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 123946 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47544 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 68202 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 73787 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2729826 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2729826 # Total data (bytes) -system.iobus.reqLayer0.occupancy 9845000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2735411 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2735411 # Total data (bytes) +system.iobus.reqLayer0.occupancy 11236000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1267,7 +1181,7 @@ system.iobus.reqLayer23.occupancy 13505000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) @@ -1275,267 +1189,267 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 377802180 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 379995831 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26743000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27448000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42660009 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43184752 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 765570 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.693534 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6090993 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 766079 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.950868 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 26716185250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.693534 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995495 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995495 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 7662265 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 7662265 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6090993 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6090993 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6090993 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6090993 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6090993 # number of overall hits -system.cpu0.icache.overall_hits::total 6090993 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 805033 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 805033 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 805033 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 805033 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 805033 # number of overall misses -system.cpu0.icache.overall_misses::total 805033 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11432598915 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11432598915 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11432598915 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11432598915 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11432598915 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11432598915 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6896026 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6896026 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6896026 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6896026 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6896026 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6896026 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116739 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.116739 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116739 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.116739 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116739 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.116739 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14201.404060 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14201.404060 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14201.404060 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14201.404060 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14201.404060 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14201.404060 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4227 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 138 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.630435 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.tags.replacements 901902 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.676111 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6573395 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 902414 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.284234 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26905725250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.676111 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995461 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995461 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 428 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 8421597 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 8421597 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 6573395 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6573395 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6573395 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6573395 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6573395 # number of overall hits +system.cpu0.icache.overall_hits::total 6573395 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 945623 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 945623 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 945623 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 945623 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 945623 # number of overall misses +system.cpu0.icache.overall_misses::total 945623 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13224491137 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13224491137 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13224491137 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13224491137 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13224491137 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13224491137 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7519018 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7519018 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7519018 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7519018 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7519018 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7519018 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125764 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.125764 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125764 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.125764 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125764 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.125764 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13984.950807 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13984.950807 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13984.950807 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13984.950807 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13984.950807 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13984.950807 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3461 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 139 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 144 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.034722 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 139 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 38794 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 38794 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 38794 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 38794 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 38794 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 38794 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 766239 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 766239 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 766239 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 766239 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 766239 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 766239 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9400829636 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9400829636 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9400829636 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9400829636 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9400829636 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9400829636 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111113 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111113 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111113 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.111113 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111113 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.111113 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12268.795553 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12268.795553 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12268.795553 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12268.795553 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12268.795553 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12268.795553 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43044 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 43044 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 43044 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 43044 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 43044 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 43044 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 902579 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 902579 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 902579 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 902579 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 902579 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 902579 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10909532635 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10909532635 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10909532635 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10909532635 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10909532635 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10909532635 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.120039 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.120039 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.120039 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.120039 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.120039 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.120039 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12087.066766 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12087.066766 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12087.066766 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12087.066766 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12087.066766 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12087.066766 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1099493 # number of replacements -system.cpu0.dcache.tags.tagsinuse 471.490981 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9327298 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1100005 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.479323 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 25754000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.490981 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.920881 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.920881 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 1164537 # number of replacements +system.cpu0.dcache.tags.tagsinuse 498.695388 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10555909 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1165049 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.060485 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 26173000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.695388 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.974014 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.974014 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 50559091 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 50559091 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5751167 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5751167 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3244504 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3244504 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151160 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 151160 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 174499 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 174499 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8995671 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8995671 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8995671 # number of overall hits -system.cpu0.dcache.overall_hits::total 8995671 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1359261 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1359261 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1665675 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1665675 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 17016 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 17016 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 764 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 764 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3024936 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3024936 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3024936 # number of overall misses -system.cpu0.dcache.overall_misses::total 3024936 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36687958870 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 36687958870 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 74828467074 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 74828467074 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 254575245 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 254575245 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4747557 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4747557 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 111516425944 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 111516425944 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 111516425944 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 111516425944 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7110428 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7110428 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4910179 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4910179 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 168176 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 168176 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 175263 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 175263 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12020607 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12020607 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12020607 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12020607 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.191164 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.191164 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.339229 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.339229 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101180 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101180 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004359 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004359 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.251646 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.251646 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.251646 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.251646 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26991.106837 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26991.106837 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44923.809911 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44923.809911 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14960.933533 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14960.933533 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6214.079843 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6214.079843 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36865.714165 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36865.714165 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36865.714165 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36865.714165 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2890749 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 819 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 46898 # number of cycles access was blocked +system.cpu0.dcache.tags.tag_accesses 56283368 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 56283368 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6422745 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6422745 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3752316 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3752316 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172180 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 172180 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 196241 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 196241 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10175061 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10175061 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10175061 # number of overall hits +system.cpu0.dcache.overall_hits::total 10175061 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1468970 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1468970 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1742020 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1742020 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20433 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20433 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2875 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2875 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3210990 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3210990 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3210990 # number of overall misses +system.cpu0.dcache.overall_misses::total 3210990 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 38326965830 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 38326965830 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76755016444 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 76755016444 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 286872989 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 286872989 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20380878 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 20380878 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 115081982274 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 115081982274 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 115081982274 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 115081982274 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7891715 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7891715 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5494336 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5494336 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 192613 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 192613 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 199116 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 199116 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13386051 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13386051 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13386051 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13386051 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186141 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.186141 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.317057 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.317057 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.106083 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.106083 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014439 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014439 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239876 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.239876 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239876 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.239876 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26091.047353 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 26091.047353 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44060.927225 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44060.927225 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14039.690158 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14039.690158 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7089.001043 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7089.001043 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35840.031353 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35840.031353 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35840.031353 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35840.031353 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2903843 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 789 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 48428 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 61.639068 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 117 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 59.962067 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 112.714286 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 594718 # number of writebacks -system.cpu0.dcache.writebacks::total 594718 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 521771 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 521771 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1409219 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1409219 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4206 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4206 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1930990 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1930990 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1930990 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1930990 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 837490 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 837490 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256456 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 256456 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12810 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12810 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 764 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 764 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1093946 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1093946 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1093946 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1093946 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24898598196 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24898598196 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10973118276 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10973118276 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 152117754 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 152117754 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3219443 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3219443 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35871716472 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 35871716472 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35871716472 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 35871716472 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 993486001 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 993486001 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1673832998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1673832998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2667318999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2667318999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117783 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117783 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052229 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052229 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.076170 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.076170 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004359 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004359 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091006 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.091006 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091006 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.091006 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29730.024473 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29730.024473 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42787.527981 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42787.527981 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11874.922248 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11874.922248 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4213.930628 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4213.930628 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32791.121748 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32791.121748 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32791.121748 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32791.121748 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 644423 # number of writebacks +system.cpu0.dcache.writebacks::total 644423 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 578811 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 578811 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1469624 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1469624 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4269 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4269 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2048435 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2048435 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2048435 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2048435 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 890159 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 890159 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 272396 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 272396 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16164 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16164 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2875 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2875 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1162555 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1162555 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1162555 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1162555 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25660783347 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25660783347 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11256320137 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11256320137 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 175450760 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 175450760 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14630122 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14630122 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 36917103484 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 36917103484 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 36917103484 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 36917103484 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 999097000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 999097000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1765340999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1765340999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2764437999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2764437999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.112797 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.112797 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049578 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049578 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.083920 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.083920 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014439 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014439 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086848 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.086848 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086848 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.086848 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28827.190813 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28827.190813 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41323.367953 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41323.367953 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10854.414749 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10854.414749 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5088.738087 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5088.738087 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31755.145764 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31755.145764 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31755.145764 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31755.145764 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1543,35 +1457,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 3875512 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3181518 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 119538 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2413999 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1363069 # Number of BTB hits +system.cpu1.branchPred.lookups 2770041 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2267711 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 80921 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1482926 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 969002 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 56.465185 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 281270 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 11131 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 65.343921 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 198874 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 6522 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2756439 # DTB read hits -system.cpu1.dtb.read_misses 11971 # DTB read misses +system.cpu1.dtb.read_hits 2016743 # DTB read hits +system.cpu1.dtb.read_misses 9789 # DTB read misses system.cpu1.dtb.read_acv 6 # DTB read access violations -system.cpu1.dtb.read_accesses 281635 # DTB read accesses -system.cpu1.dtb.write_hits 1697476 # DTB write hits -system.cpu1.dtb.write_misses 2261 # DTB write misses -system.cpu1.dtb.write_acv 35 # DTB write access violations -system.cpu1.dtb.write_accesses 106637 # DTB write accesses -system.cpu1.dtb.data_hits 4453915 # DTB hits -system.cpu1.dtb.data_misses 14232 # DTB misses -system.cpu1.dtb.data_acv 41 # DTB access violations -system.cpu1.dtb.data_accesses 388272 # DTB accesses -system.cpu1.itb.fetch_hits 435796 # ITB hits -system.cpu1.itb.fetch_misses 5916 # ITB misses -system.cpu1.itb.fetch_acv 132 # ITB acv -system.cpu1.itb.fetch_accesses 441712 # ITB accesses +system.cpu1.dtb.read_accesses 278621 # DTB read accesses +system.cpu1.dtb.write_hits 1132288 # DTB write hits +system.cpu1.dtb.write_misses 1938 # DTB write misses +system.cpu1.dtb.write_acv 37 # DTB write access violations +system.cpu1.dtb.write_accesses 105909 # DTB write accesses +system.cpu1.dtb.data_hits 3149031 # DTB hits +system.cpu1.dtb.data_misses 11727 # DTB misses +system.cpu1.dtb.data_acv 43 # DTB access violations +system.cpu1.dtb.data_accesses 384530 # DTB accesses +system.cpu1.itb.fetch_hits 369710 # ITB hits +system.cpu1.itb.fetch_misses 5636 # ITB misses +system.cpu1.itb.fetch_acv 119 # ITB acv +system.cpu1.itb.fetch_accesses 375346 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1584,520 +1498,519 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 25703316 # number of cpu cycles simulated +system.cpu1.numCycles 18798992 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 8513027 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 18550498 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3875512 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1644339 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 3370867 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 594419 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 10509044 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 24053 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 56236 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 158916 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 118 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 2181303 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 77306 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 23021613 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.805786 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.167146 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 5357256 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 13511342 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2770041 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1167876 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2476292 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 427198 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 8263333 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 26082 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 54640 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 162618 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1630522 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 50477 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 16624070 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.812758 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.170685 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 19650746 85.36% 85.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 192109 0.83% 86.19% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 424155 1.84% 88.03% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 258878 1.12% 89.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 512227 2.22% 91.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 176251 0.77% 92.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 202668 0.88% 93.03% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 249358 1.08% 94.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1355221 5.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 14147778 85.10% 85.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 131100 0.79% 85.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 332329 2.00% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 198517 1.19% 89.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 395957 2.38% 91.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 132924 0.80% 92.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 159356 0.96% 93.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 93423 0.56% 93.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1032686 6.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 23021613 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.150779 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.721716 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 8599650 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 10723354 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 3129491 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 191921 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 377196 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 176309 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 12258 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 18185515 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 36387 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 377196 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 8917984 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 3106321 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6595327 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2921217 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1103566 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 17011608 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 230 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 267059 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 236234 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 11254383 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 20310939 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 20246817 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 58360 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 9542826 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1711557 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 544600 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 54677 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 3272980 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2918733 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1792509 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 312208 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 170960 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 14943030 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 650638 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 14484391 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 37394 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2166782 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1088105 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 467114 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 23021613 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.629165 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.310842 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 16624070 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.147351 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.718727 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5556172 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 8353280 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2307081 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 131115 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 276421 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 130911 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7501 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 13245951 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 18855 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 276421 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5775463 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2664230 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 4961239 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2147700 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 799015 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 12421307 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 241 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 220838 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 145988 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 8355946 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 15113763 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 15073339 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 35607 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 7070748 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1285198 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 385003 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 30758 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2314294 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2123178 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1208247 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 244787 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 150121 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 10996175 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 428151 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 10636944 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 28046 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1617836 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 831016 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 312637 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 16624070 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.639852 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.326685 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 16750827 72.76% 72.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2784830 12.10% 84.86% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1224236 5.32% 90.18% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 874900 3.80% 93.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 759442 3.30% 97.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 313710 1.36% 98.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 192948 0.84% 99.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 103377 0.45% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 17343 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 12087523 72.71% 72.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1967089 11.83% 84.54% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 877391 5.28% 89.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 655455 3.94% 93.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 567827 3.42% 97.18% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 232884 1.40% 98.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 149324 0.90% 99.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 75580 0.45% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 10997 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 23021613 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 16624070 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 19111 7.55% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 130840 51.68% 59.23% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 103199 40.77% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 16676 8.84% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 99378 52.65% 61.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 72683 38.51% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 9521262 65.73% 65.76% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 23052 0.16% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 11116 0.08% 65.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2876494 19.86% 85.87% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1724250 11.90% 97.77% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 322940 2.23% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.03% 0.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 7118581 66.92% 66.96% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 18880 0.18% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 9739 0.09% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2093745 19.68% 86.93% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1155572 10.86% 97.79% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 235150 2.21% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 14484391 # Type of FU issued -system.cpu1.iq.rate 0.563522 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 253150 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.017477 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 52052620 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 17652734 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 14115090 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 228319 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 110924 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 107745 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 14614655 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 119368 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 134347 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 10636944 # Type of FU issued +system.cpu1.iq.rate 0.565825 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 188737 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.017744 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 37986289 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 12982235 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 10383881 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 128452 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 62754 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 61527 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 10755461 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 66702 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 101929 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 418294 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 981 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 3304 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 169372 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 306426 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 815 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 2923 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 138344 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 5236 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 20861 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 4845 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 18286 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 377196 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2407064 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 140680 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 16469424 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 189598 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2918733 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1792509 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 583051 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 52184 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2431 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 3304 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 57543 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 133828 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 191371 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 14348807 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2776029 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 135584 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 276421 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2089253 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 85247 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 12015910 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 137996 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2123178 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1208247 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 388932 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 10076 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1666 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 2923 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 39900 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 91880 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 131780 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 10541126 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2031671 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 95818 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 875756 # number of nop insts executed -system.cpu1.iew.exec_refs 4481633 # number of memory reference insts executed -system.cpu1.iew.exec_branches 2254475 # Number of branches executed -system.cpu1.iew.exec_stores 1705604 # Number of stores executed -system.cpu1.iew.exec_rate 0.558247 # Inst execution rate -system.cpu1.iew.wb_sent 14259530 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 14222835 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 6903248 # num instructions producing a value -system.cpu1.iew.wb_consumers 9726426 # num instructions consuming a value +system.cpu1.iew.exec_nop 591584 # number of nop insts executed +system.cpu1.iew.exec_refs 3170643 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1658996 # Number of branches executed +system.cpu1.iew.exec_stores 1138972 # Number of stores executed +system.cpu1.iew.exec_rate 0.560728 # Inst execution rate +system.cpu1.iew.wb_sent 10475567 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 10445408 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5214693 # num instructions producing a value +system.cpu1.iew.wb_consumers 7314185 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.553346 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.709741 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.555637 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.712956 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 2312839 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 183524 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 178531 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 22644417 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.622505 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.551942 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1685534 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 115514 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 123376 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 16347649 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.627728 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.542862 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 17386197 76.78% 76.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2263939 10.00% 86.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1130304 4.99% 91.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 578693 2.56% 94.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 365284 1.61% 95.94% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 174241 0.77% 96.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 166825 0.74% 97.44% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 129123 0.57% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 449811 1.99% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 12457643 76.20% 76.20% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1697144 10.38% 86.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 844179 5.16% 91.75% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 419187 2.56% 94.31% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 268727 1.64% 95.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 133453 0.82% 96.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 126834 0.78% 97.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 88227 0.54% 98.09% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 312255 1.91% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 22644417 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 14096266 # Number of instructions committed -system.cpu1.commit.committedOps 14096266 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 16347649 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 10261869 # Number of instructions committed +system.cpu1.commit.committedOps 10261869 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 4123576 # Number of memory references committed -system.cpu1.commit.loads 2500439 # Number of loads committed -system.cpu1.commit.membars 61456 # Number of memory barriers committed -system.cpu1.commit.branches 2105755 # Number of branches committed -system.cpu1.commit.fp_insts 106451 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 13014804 # Number of committed integer instructions. -system.cpu1.commit.function_calls 225813 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 449811 # number cycles where commit BW limit reached +system.cpu1.commit.refs 2886655 # Number of memory references committed +system.cpu1.commit.loads 1816752 # Number of loads committed +system.cpu1.commit.membars 36648 # Number of memory barriers committed +system.cpu1.commit.branches 1542101 # Number of branches committed +system.cpu1.commit.fp_insts 60269 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 9518406 # Number of committed integer instructions. +system.cpu1.commit.function_calls 159983 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 312255 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 38521772 # The number of ROB reads -system.cpu1.rob.rob_writes 33194220 # The number of ROB writes -system.cpu1.timesIdled 266846 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2681703 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3780938744 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 13322175 # Number of Instructions Simulated -system.cpu1.committedOps 13322175 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 13322175 # Number of Instructions Simulated -system.cpu1.cpi 1.929363 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.929363 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.518306 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.518306 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 18552962 # number of integer regfile reads -system.cpu1.int_regfile_writes 10191479 # number of integer regfile writes -system.cpu1.fp_regfile_reads 58039 # number of floating regfile reads -system.cpu1.fp_regfile_writes 58174 # number of floating regfile writes -system.cpu1.misc_regfile_reads 1024653 # number of misc regfile reads -system.cpu1.misc_regfile_writes 265032 # number of misc regfile writes -system.cpu1.icache.tags.replacements 316719 # number of replacements -system.cpu1.icache.tags.tagsinuse 504.225697 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1849767 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 317231 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 5.830978 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 49140510500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.225697 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.984816 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.984816 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 27899142 # The number of ROB reads +system.cpu1.rob.rob_writes 24169847 # The number of ROB writes +system.cpu1.timesIdled 181051 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2174922 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3790987217 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 9739356 # Number of Instructions Simulated +system.cpu1.committedOps 9739356 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 9739356 # Number of Instructions Simulated +system.cpu1.cpi 1.930209 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.930209 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.518079 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.518079 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 13792462 # number of integer regfile reads +system.cpu1.int_regfile_writes 7586165 # number of integer regfile writes +system.cpu1.fp_regfile_reads 35303 # number of floating regfile reads +system.cpu1.fp_regfile_writes 34737 # number of floating regfile writes +system.cpu1.misc_regfile_reads 829246 # number of misc regfile reads +system.cpu1.misc_regfile_writes 174995 # number of misc regfile writes +system.cpu1.icache.tags.replacements 184023 # number of replacements +system.cpu1.icache.tags.tagsinuse 502.144736 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1436916 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 184535 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 7.786685 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1712232500000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 502.144736 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980751 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.980751 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 420 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 2498600 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 2498600 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1849767 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1849767 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1849767 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1849767 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1849767 # number of overall hits -system.cpu1.icache.overall_hits::total 1849767 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 331536 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 331536 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 331536 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 331536 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 331536 # number of overall misses -system.cpu1.icache.overall_misses::total 331536 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4647513106 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4647513106 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4647513106 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4647513106 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4647513106 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4647513106 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 2181303 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 2181303 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 2181303 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 2181303 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 2181303 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 2181303 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.151990 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.151990 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.151990 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.151990 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.151990 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.151990 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14018.125048 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14018.125048 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14018.125048 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14018.125048 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14018.125048 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14018.125048 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1365 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 1815116 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 1815116 # 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number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 2794361223 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 2794361223 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 2794361223 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 2794361223 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 2794361223 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1630522 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1630522 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1630522 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1630522 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1630522 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1630522 # 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average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14433.236692 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1663 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 71 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 63 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 19.225352 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 26.396825 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 14239 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 14239 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 14239 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 14239 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 14239 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 14239 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 317297 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 317297 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 317297 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 317297 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 317297 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 317297 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3842042413 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3842042413 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3842042413 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3842042413 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3842042413 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3842042413 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.145462 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.145462 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.145462 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.145462 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.145462 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.145462 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12108.662903 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12108.662903 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12108.662903 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9012 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 9012 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 9012 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 9012 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 9012 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 9012 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 184594 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 184594 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 184594 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 184594 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 184594 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 184594 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2304763360 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2304763360 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2304763360 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2304763360 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2304763360 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2304763360 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.113212 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.113212 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.113212 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.113212 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.113212 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.113212 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12485.581113 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12485.581113 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12485.581113 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12485.581113 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12485.581113 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12485.581113 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 323504 # number of replacements -system.cpu1.dcache.tags.tagsinuse 495.920224 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3389718 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 323845 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 10.467100 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 42037852500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 495.920224 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968594 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.968594 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.666016 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 17217310 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 17217310 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2089496 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2089496 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1222054 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1222054 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 41428 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 41428 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 44398 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 44398 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3311550 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3311550 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3311550 # number of overall hits -system.cpu1.dcache.overall_hits::total 3311550 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 467553 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 467553 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 348721 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 348721 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7730 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 7730 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 782 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 782 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 816274 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 816274 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 816274 # number of overall misses -system.cpu1.dcache.overall_misses::total 816274 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7286969700 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 7286969700 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13547153677 # 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number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1570775 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1570775 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 49158 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 49158 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 45180 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 45180 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4127824 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4127824 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4127824 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4127824 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.182849 # 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Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 324 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.632812 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 12059624 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 12059624 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1586410 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1586410 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 857564 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 857564 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 22125 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 22125 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 21120 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 21120 # 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number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 467030 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 467030 # number of overall misses +system.cpu1.dcache.overall_misses::total 467030 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4578373047 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4578373047 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10436073649 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 10436073649 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 56388497 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 56388497 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 20553927 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 20553927 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 15014446696 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 15014446696 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 15014446696 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 15014446696 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1872141 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1872141 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1038863 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1038863 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 26609 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 26609 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 23862 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 23862 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2911004 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2911004 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2911004 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2911004 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.152623 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.152623 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.174517 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.174517 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.168514 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.168514 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.114911 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.114911 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.160436 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.160436 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.160436 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.160436 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16023.368297 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16023.368297 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 57562.775575 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 57562.775575 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12575.489964 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12575.489964 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7495.961707 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7495.961707 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32148.784224 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 32148.784224 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32148.784224 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 32148.784224 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 370227 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 7447 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6127 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 56.862226 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 60.425494 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 245774 # number of writebacks -system.cpu1.dcache.writebacks::total 245774 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 203756 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 203756 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 288423 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 288423 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1420 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1420 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 492179 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 492179 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 492179 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 492179 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 263797 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 263797 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 60298 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 60298 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6310 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6310 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 781 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 781 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 324095 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 324095 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 324095 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 324095 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3377520942 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3377520942 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2032860866 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2032860866 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70443003 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70443003 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4174394 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4174394 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5410381808 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5410381808 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5410381808 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5410381808 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 489946000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 489946000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 936242002 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 936242002 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1426188002 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1426188002 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.103165 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.103165 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038387 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038387 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.128362 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.128362 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.017286 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.017286 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.078515 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.078515 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.078515 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.078515 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12803.485036 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12803.485036 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33713.570367 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33713.570367 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11163.708875 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11163.708875 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5344.934699 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5344.934699 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16693.814493 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16693.814493 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16693.814493 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16693.814493 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 162776 # number of writebacks +system.cpu1.dcache.writebacks::total 162776 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 104604 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 104604 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 148843 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 148843 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 899 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 899 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 253447 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 253447 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 253447 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 253447 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 181127 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 181127 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 32456 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 32456 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 3585 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 3585 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2742 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2742 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 213583 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 213583 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 213583 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 213583 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2418933900 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2418933900 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1545787184 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1545787184 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 26756251 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 26756251 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 15069073 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 15069073 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3964721084 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3964721084 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3964721084 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3964721084 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 485705000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 485705000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 998872003 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 998872003 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1484577003 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1484577003 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.096749 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.096749 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.031242 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.031242 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.134729 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.134729 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.114911 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.114911 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.073371 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.073371 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.073371 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.073371 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13354.905122 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13354.905122 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47627.162435 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 47627.162435 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7463.389400 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7463.389400 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5495.650255 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5495.650255 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18562.905681 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18562.905681 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18562.905681 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18562.905681 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2106,161 +2019,161 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4836 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 166329 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 57049 39.81% 39.81% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 39.90% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1924 1.34% 41.24% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 16 0.01% 41.25% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 84196 58.75% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 143316 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56102 49.10% 49.10% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.11% 49.22% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1924 1.68% 50.90% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 16 0.01% 50.91% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 56086 49.09% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114259 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1865433154000 98.01% 98.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 62620000 0.00% 98.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 558222500 0.03% 98.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 8649500 0.00% 98.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 37274722500 1.96% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1903337368500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983400 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 5026 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 189626 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 66604 40.25% 40.25% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 133 0.08% 40.33% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1926 1.16% 41.49% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 191 0.12% 41.61% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 96634 58.39% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 165488 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 65244 49.22% 49.22% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 133 0.10% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1926 1.45% 50.78% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 191 0.14% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 65055 49.08% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 132549 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1865394285500 97.91% 97.91% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63356500 0.00% 97.91% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 573165000 0.03% 97.94% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 85999500 0.00% 97.95% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 39121861000 2.05% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1905238667500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.979581 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.666136 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.797252 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.67% 28.44% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.44% 28.89% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.00% 32.89% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.44% 37.33% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.67% 40.00% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.44% 40.44% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.33% 41.78% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.11% 44.89% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.89% 45.78% # number of syscalls executed -system.cpu0.kern.syscall::45 36 16.00% 61.78% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.33% 63.11% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.44% 67.56% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.44% 72.00% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.44% 72.44% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.67% 75.11% # number of syscalls executed -system.cpu0.kern.syscall::71 25 11.11% 86.22% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.33% 87.56% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.67% 90.22% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.44% 90.67% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.33% 92.00% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.00% 96.00% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.89% 96.89% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.89% 97.78% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.44% 98.22% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.89% 99.11% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 225 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.673210 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.800958 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.45% 3.45% # number of syscalls executed +system.cpu0.kern.syscall::3 20 8.62% 12.07% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.72% 13.79% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.22% 28.02% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.43% 28.45% # number of syscalls executed +system.cpu0.kern.syscall::17 9 3.88% 32.33% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.31% 36.64% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.59% 39.22% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.43% 39.66% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.29% 40.95% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.02% 43.97% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.86% 44.83% # number of syscalls executed +system.cpu0.kern.syscall::45 39 16.81% 61.64% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.29% 62.93% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.31% 67.24% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.31% 71.55% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.43% 71.98% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.59% 74.57% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.64% 86.21% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.29% 87.50% # number of syscalls executed +system.cpu0.kern.syscall::74 7 3.02% 90.52% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.43% 90.95% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.29% 92.24% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.88% 96.12% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.86% 96.98% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.86% 97.84% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.43% 98.28% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.86% 99.14% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.86% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 232 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 104 0.07% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3010 1.99% 2.06% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.09% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.10% # number of callpals executed -system.cpu0.kern.callpal::swpipl 136886 90.50% 92.60% # number of callpals executed -system.cpu0.kern.callpal::rdps 6293 4.16% 96.76% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.77% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.77% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.77% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed -system.cpu0.kern.callpal::rti 4358 2.88% 99.66% # number of callpals executed -system.cpu0.kern.callpal::callsys 382 0.25% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 151247 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6436 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1343 # number of protection mode switches +system.cpu0.kern.callpal::wripir 273 0.16% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3846 2.21% 2.37% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.39% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.40% # number of callpals executed +system.cpu0.kern.callpal::swpipl 158278 90.80% 93.20% # number of callpals executed +system.cpu0.kern.callpal::rdps 6346 3.64% 96.84% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.84% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.84% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.85% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.85% # number of callpals executed +system.cpu0.kern.callpal::rti 4961 2.85% 99.70% # number of callpals executed +system.cpu0.kern.callpal::callsys 391 0.22% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 174309 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7462 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1354 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1342 -system.cpu0.kern.mode_good::user 1343 +system.cpu0.kern.mode_good::kernel 1353 +system.cpu0.kern.mode_good::user 1354 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.208515 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.181319 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.345160 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1901289587500 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2047773000 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.307055 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1903211741000 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2026918500 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3011 # number of times the context was actually changed +system.cpu0.kern.swap_context 3847 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3850 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 71149 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 24567 38.92% 38.92% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1923 3.05% 41.97% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 104 0.16% 42.13% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 36529 57.87% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 63123 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 24137 48.08% 48.08% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1923 3.83% 51.92% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 104 0.21% 52.12% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 24033 47.88% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 50197 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1869107624500 98.20% 98.20% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533184500 0.03% 98.23% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 48972500 0.00% 98.23% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 33633158500 1.77% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1903322940000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.982497 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3999 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 49848 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 15658 37.06% 37.06% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1924 4.55% 41.62% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 273 0.65% 42.26% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 24392 57.74% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 42247 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 15641 47.10% 47.10% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1924 5.79% 52.90% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 273 0.82% 53.72% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 15369 46.28% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 33207 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1871713408000 98.26% 98.26% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 533048500 0.03% 98.29% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 128777500 0.01% 98.29% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 32519855000 1.71% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1904895089000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998914 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.657916 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.795225 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed -system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.94% 26.73% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.97% 29.70% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.97% 32.67% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.96% 36.63% # number of syscalls executed -system.cpu1.kern.syscall::45 18 17.82% 54.46% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.97% 57.43% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.99% 58.42% # number of syscalls executed -system.cpu1.kern.syscall::71 29 28.71% 87.13% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.90% 97.03% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 101 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.630084 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.786020 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 10 10.64% 10.64% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.57% 20.21% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.06% 21.28% # number of syscalls executed +system.cpu1.kern.syscall::17 6 6.38% 27.66% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.19% 30.85% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.19% 34.04% # number of syscalls executed +system.cpu1.kern.syscall::33 4 4.26% 38.30% # number of syscalls executed +system.cpu1.kern.syscall::45 15 15.96% 54.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.19% 57.45% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.06% 58.51% # number of syscalls executed +system.cpu1.kern.syscall::71 27 28.72% 87.23% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.57% 96.81% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.19% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 94 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 16 0.02% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1228 1.89% 1.92% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 1.92% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 1.93% # number of callpals executed -system.cpu1.kern.callpal::swpipl 58251 89.62% 91.55% # number of callpals executed -system.cpu1.kern.callpal::rdps 2464 3.79% 95.34% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 95.34% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 95.35% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 95.35% # number of callpals executed -system.cpu1.kern.callpal::rti 2844 4.38% 99.73% # number of callpals executed -system.cpu1.kern.callpal::callsys 133 0.20% 99.93% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 191 0.44% 0.44% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.44% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.45% # number of callpals executed +system.cpu1.kern.callpal::swpctx 742 1.70% 2.15% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 2.15% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 2.17% # number of callpals executed +system.cpu1.kern.callpal::swpipl 37463 85.96% 88.13% # number of callpals executed +system.cpu1.kern.callpal::rdps 2409 5.53% 93.66% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.66% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.67% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.68% # number of callpals executed +system.cpu1.kern.callpal::rti 2587 5.94% 99.62% # number of callpals executed +system.cpu1.kern.callpal::callsys 124 0.28% 99.90% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.10% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 65000 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1608 # number of protection mode switches -system.cpu1.kern.mode_switch::user 397 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 463 -system.cpu1.kern.mode_good::user 397 -system.cpu1.kern.mode_good::idle 66 -system.cpu1.kern.mode_switch_good::kernel 0.287935 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 43580 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 937 # number of protection mode switches +system.cpu1.kern.mode_switch::user 383 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2395 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 617 +system.cpu1.kern.mode_good::user 383 +system.cpu1.kern.mode_good::idle 234 +system.cpu1.kern.mode_switch_good::kernel 0.658485 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.032132 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.228135 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 38501499500 2.02% 2.02% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 724848000 0.04% 2.06% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1863406690000 97.94% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1229 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.097704 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.332167 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 34875641000 1.83% 1.83% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 708299500 0.04% 1.87% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1868990228500 98.13% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 743 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 674a7dfd5..0b1609ec3 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,128 +1,128 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.860198 # Number of seconds simulated -sim_ticks 1860197780500 # Number of ticks simulated -final_tick 1860197780500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.860192 # Number of seconds simulated +sim_ticks 1860191785500 # Number of ticks simulated +final_tick 1860191785500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 153122 # Simulator instruction rate (inst/s) -host_op_rate 153122 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5376333902 # Simulator tick rate (ticks/s) -host_mem_usage 310876 # Number of bytes of host memory used -host_seconds 346.00 # Real time elapsed on the host -sim_insts 52979882 # Number of instructions simulated -sim_ops 52979882 # Number of ops (including micro ops) simulated +host_inst_rate 128947 # Simulator instruction rate (inst/s) +host_op_rate 128947 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4527634915 # Simulator tick rate (ticks/s) +host_mem_usage 347764 # Number of bytes of host memory used +host_seconds 410.85 # Real time elapsed on the host +sim_insts 52978349 # Number of instructions simulated +sim_ops 52978349 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24878976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 963264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24877248 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28495232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 963968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 963968 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7515456 # Number of bytes written to this memory -system.physmem.bytes_written::total 7515456 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15062 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388734 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28492800 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 963264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 963264 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7515392 # Number of bytes written to this memory +system.physmem.bytes_written::total 7515392 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15051 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388707 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445238 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117429 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117429 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 518207 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13374371 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1425810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15318388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 518207 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 518207 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4040138 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4040138 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4040138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 518207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13374371 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1425810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19358526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445238 # Number of read requests accepted -system.physmem.writeReqs 117429 # Number of write requests accepted -system.physmem.readBursts 445238 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117429 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28492032 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3200 # Total number of bytes read from write queue -system.physmem.bytesWritten 7514752 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28495232 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7515456 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 445200 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117428 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117428 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 517830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13373486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1425814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15317130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 517830 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517830 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4040117 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4040117 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4040117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 517830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13373486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1425814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19357247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445200 # Number of read requests accepted +system.physmem.writeReqs 117428 # Number of write requests accepted +system.physmem.readBursts 445200 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117428 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28485504 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue +system.physmem.bytesWritten 7513728 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28492800 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7515392 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 179 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28229 # Per bank write bursts -system.physmem.perBankRdBursts::1 27970 # Per bank write bursts -system.physmem.perBankRdBursts::2 28433 # Per bank write bursts -system.physmem.perBankRdBursts::3 28029 # Per bank write bursts -system.physmem.perBankRdBursts::4 27802 # Per bank write bursts -system.physmem.perBankRdBursts::5 27222 # Per bank write bursts -system.physmem.perBankRdBursts::6 27248 # Per bank write bursts -system.physmem.perBankRdBursts::7 27296 # Per bank write bursts -system.physmem.perBankRdBursts::8 27665 # Per bank write bursts -system.physmem.perBankRdBursts::9 27395 # Per bank write bursts -system.physmem.perBankRdBursts::10 27922 # Per bank write bursts -system.physmem.perBankRdBursts::11 27539 # Per bank write bursts -system.physmem.perBankRdBursts::12 27561 # Per bank write bursts -system.physmem.perBankRdBursts::13 28227 # Per bank write bursts -system.physmem.perBankRdBursts::14 28327 # Per bank write bursts -system.physmem.perBankRdBursts::15 28323 # Per bank write bursts -system.physmem.perBankWrBursts::0 7932 # Per bank write bursts -system.physmem.perBankWrBursts::1 7497 # Per bank write bursts -system.physmem.perBankWrBursts::2 7944 # Per bank write bursts -system.physmem.perBankWrBursts::3 7517 # Per bank write bursts -system.physmem.perBankWrBursts::4 7343 # Per bank write bursts -system.physmem.perBankWrBursts::5 6680 # Per bank write bursts -system.physmem.perBankWrBursts::6 6761 # Per bank write bursts -system.physmem.perBankWrBursts::7 6683 # Per bank write bursts -system.physmem.perBankWrBursts::8 7104 # Per bank write bursts -system.physmem.perBankWrBursts::9 6801 # Per bank write bursts -system.physmem.perBankWrBursts::10 7313 # Per bank write bursts -system.physmem.perBankWrBursts::11 6981 # Per bank write bursts -system.physmem.perBankWrBursts::12 7123 # Per bank write bursts -system.physmem.perBankWrBursts::13 7875 # Per bank write bursts -system.physmem.perBankWrBursts::14 8050 # Per bank write bursts -system.physmem.perBankWrBursts::15 7814 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 178 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28210 # Per bank write bursts +system.physmem.perBankRdBursts::1 27995 # Per bank write bursts +system.physmem.perBankRdBursts::2 28357 # Per bank write bursts +system.physmem.perBankRdBursts::3 27829 # Per bank write bursts +system.physmem.perBankRdBursts::4 27761 # Per bank write bursts +system.physmem.perBankRdBursts::5 27267 # Per bank write bursts +system.physmem.perBankRdBursts::6 27371 # Per bank write bursts +system.physmem.perBankRdBursts::7 27375 # Per bank write bursts +system.physmem.perBankRdBursts::8 27696 # Per bank write bursts +system.physmem.perBankRdBursts::9 27269 # Per bank write bursts +system.physmem.perBankRdBursts::10 28017 # Per bank write bursts +system.physmem.perBankRdBursts::11 27509 # Per bank write bursts +system.physmem.perBankRdBursts::12 27546 # Per bank write bursts +system.physmem.perBankRdBursts::13 28232 # Per bank write bursts +system.physmem.perBankRdBursts::14 28342 # Per bank write bursts +system.physmem.perBankRdBursts::15 28310 # Per bank write bursts +system.physmem.perBankWrBursts::0 7920 # Per bank write bursts +system.physmem.perBankWrBursts::1 7516 # Per bank write bursts +system.physmem.perBankWrBursts::2 7873 # Per bank write bursts +system.physmem.perBankWrBursts::3 7373 # Per bank write bursts +system.physmem.perBankWrBursts::4 7309 # Per bank write bursts +system.physmem.perBankWrBursts::5 6720 # Per bank write bursts +system.physmem.perBankWrBursts::6 6881 # Per bank write bursts +system.physmem.perBankWrBursts::7 6774 # Per bank write bursts +system.physmem.perBankWrBursts::8 7136 # Per bank write bursts +system.physmem.perBankWrBursts::9 6679 # Per bank write bursts +system.physmem.perBankWrBursts::10 7411 # Per bank write bursts +system.physmem.perBankWrBursts::11 6967 # Per bank write bursts +system.physmem.perBankWrBursts::12 7107 # Per bank write bursts +system.physmem.perBankWrBursts::13 7877 # Per bank write bursts +system.physmem.perBankWrBursts::14 8064 # Per bank write bursts +system.physmem.perBankWrBursts::15 7795 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 1860192344000 # Total gap between requests +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 1860186344000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 445238 # Read request sizes (log2) +system.physmem.readPktSize::6 445200 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117429 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 332275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66533 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2385 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2335 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1090 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 964 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 958 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117428 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 322906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56729 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 22897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5869 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3757 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1891 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1835 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1567 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -133,230 +133,147 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 43301 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 831.507817 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 237.255649 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1940.687281 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 14819 34.22% 34.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6274 14.49% 48.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 4433 10.24% 58.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2614 6.04% 64.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1636 3.78% 68.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1435 3.31% 72.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 928 2.14% 74.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 854 1.97% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 632 1.46% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 524 1.21% 78.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 594 1.37% 80.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 623 1.44% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 284 0.66% 82.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 262 0.61% 82.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 268 0.62% 83.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 398 0.92% 84.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 204 0.47% 84.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 163 0.38% 85.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 93 0.21% 85.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 193 0.45% 85.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 100 0.23% 86.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 353 0.82% 87.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 186 0.43% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 655 1.51% 88.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 89 0.21% 89.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 28 0.06% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 40 0.09% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 175 0.40% 89.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 41 0.09% 89.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 79 0.18% 90.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 86 0.20% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 82 0.19% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 104 0.24% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 73 0.17% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 16 0.04% 90.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 102 0.24% 91.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 26 0.06% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 14 0.03% 91.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 2 0.00% 91.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 17 0.04% 91.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 4 0.01% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 13 0.03% 91.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 25 0.06% 91.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 100 0.23% 91.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 15 0.03% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 67 0.15% 91.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 82 0.19% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 42 0.10% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 83 0.19% 92.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 68 0.16% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 12 0.03% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 94 0.22% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 22 0.05% 92.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 9 0.02% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 5 0.01% 92.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 12 0.03% 92.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 4 0.01% 92.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 11 0.03% 92.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 22 0.05% 92.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 92 0.21% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 13 0.03% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 66 0.15% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 81 0.19% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 40 0.09% 93.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 80 0.18% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 68 0.16% 93.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 12 0.03% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 95 0.22% 94.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 21 0.05% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 10 0.02% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 1 0.00% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 11 0.03% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 4 0.01% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 13 0.03% 94.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 21 0.05% 94.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 92 0.21% 94.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 14 0.03% 94.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 68 0.16% 94.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 81 0.19% 94.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 35 0.08% 94.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 79 0.18% 95.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 65 0.15% 95.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 12 0.03% 95.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 98 0.23% 95.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 22 0.05% 95.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 10 0.02% 95.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 1 0.00% 95.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 12 0.03% 95.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 11 0.03% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 21 0.05% 95.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 92 0.21% 95.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 13 0.03% 95.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 64 0.15% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 81 0.19% 96.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 41 0.09% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 82 0.19% 96.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 69 0.16% 96.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 14 0.03% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 94 0.22% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 21 0.05% 97.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 8 0.02% 97.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 12 0.03% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 2 0.00% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 10 0.02% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 22 0.05% 97.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 89 0.21% 97.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 14 0.03% 97.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 66 0.15% 97.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 80 0.18% 97.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 307 0.71% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 1 0.00% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 1 0.00% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 17 0.04% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7491 2 0.00% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 5 0.01% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 1 0.00% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 16 0.04% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 1 0.00% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 2 0.00% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 330 0.76% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 2 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9411 2 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11459 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11651 2 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 4 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12483 2 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12739 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13315 4 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 7 0.02% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13891 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 4 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 3 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 40 0.09% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 2 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 174 0.40% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 43301 # Bytes accessed per row activation -system.physmem.totQLat 8362787000 # Total ticks spent queuing -system.physmem.totMemAccLat 15768695750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2225940000 # Total ticks spent in databus transfers -system.physmem.totBankLat 5179968750 # Total ticks spent accessing banks -system.physmem.avgQLat 18784.84 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 11635.46 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 48603 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 651.388927 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 428.580055 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 419.495686 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8350 17.18% 17.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6347 13.06% 30.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 2940 6.05% 36.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1813 3.73% 40.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1501 3.09% 43.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 899 1.85% 44.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 723 1.49% 46.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 886 1.82% 48.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25144 51.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 48603 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6893 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 64.568403 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2543.170744 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 6890 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6893 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6893 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.032062 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.789521 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.768510 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 5850 84.87% 84.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 28 0.41% 85.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 70 1.02% 86.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 418 6.06% 92.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 134 1.94% 94.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 49 0.71% 95.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 24 0.35% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 22 0.32% 95.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 53 0.77% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 38 0.55% 97.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 20 0.29% 97.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 34 0.49% 97.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 19 0.28% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 34 0.49% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 7 0.10% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 10 0.15% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 2 0.03% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 2 0.03% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 3 0.04% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 6 0.09% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 5 0.07% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 5 0.07% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 8 0.12% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 4 0.06% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 2 0.03% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 1 0.01% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 2 0.03% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 5 0.07% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 2 0.03% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 6 0.09% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 6 0.09% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 4 0.06% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 2 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 1 0.01% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 2 0.03% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 2 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54 3 0.04% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 6 0.09% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6893 # Writes before turning the bus around for reads +system.physmem.totQLat 10196532000 # Total ticks spent queuing +system.physmem.totMemAccLat 17805650750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2225430000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5383688750 # Total ticks spent accessing banks +system.physmem.avgQLat 22909.13 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 12095.84 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35420.31 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 40004.97 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.31 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s @@ -364,61 +281,60 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.24 # Average write queue length when enqueuing -system.physmem.readRowHits 424550 # Number of row buffer hits during reads -system.physmem.writeRowHits 94755 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.69 # Row buffer hit rate for writes -system.physmem.avgGap 3306027.09 # Average gap between requests -system.physmem.pageHitRate 92.30 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.39 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 19401389 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 295980 # Transaction distribution -system.membus.trans_dist::ReadResp 295901 # Transaction distribution -system.membus.trans_dist::WriteReq 9598 # Transaction distribution -system.membus.trans_dist::WriteResp 9598 # Transaction distribution -system.membus.trans_dist::Writeback 117429 # Transaction distribution +system.physmem.avgRdQLen 1.54 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.57 # Average write queue length when enqueuing +system.physmem.readRowHits 402462 # Number of row buffer hits during reads +system.physmem.writeRowHits 96189 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.42 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.91 # Row buffer hit rate for writes +system.physmem.avgGap 3306245.59 # Average gap between requests +system.physmem.pageHitRate 88.65 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 19400105 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 295926 # Transaction distribution +system.membus.trans_dist::ReadResp 295846 # Transaction distribution +system.membus.trans_dist::WriteReq 9597 # Transaction distribution +system.membus.trans_dist::WriteResp 9597 # Transaction distribution +system.membus.trans_dist::Writeback 117428 # Transaction distribution system.membus.trans_dist::UpgradeReq 181 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 182 # Transaction distribution -system.membus.trans_dist::ReadExReq 156823 # Transaction distribution -system.membus.trans_dist::ReadExResp 156823 # Transaction distribution -system.membus.trans_dist::BadAddressError 79 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884143 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917357 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 181 # Transaction distribution +system.membus.trans_dist::ReadExReq 156840 # Transaction distribution +system.membus.trans_dist::ReadExResp 156840 # Transaction distribution +system.membus.trans_dist::BadAddressError 80 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884064 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917278 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1042036 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30701632 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30745780 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1041957 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30699136 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30743276 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36054836 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36054836 # Total data (bytes) +system.membus.tot_pkt_size::total 36052332 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36052332 # Total data (bytes) system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29837500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 29929000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1551324500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1552530249 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 96500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 100500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3763216294 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3767548549 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376313495 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376726994 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.261116 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.261130 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710341603000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.261116 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078820 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078820 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1710337661000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.261130 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078821 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078821 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -434,12 +350,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21133883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21133883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12974928560 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12974928560 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 12996062443 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12996062443 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 12996062443 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12996062443 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 13194182648 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 13194182648 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13215316531 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13215316531 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13215316531 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13215316531 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -458,17 +374,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122161.173410 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 122161.173410 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312257.618406 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 312257.618406 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 311469.441414 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 311469.441414 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 311469.441414 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 311469.441414 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 401483 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 317534.237774 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 317534.237774 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 316724.182888 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 316724.182888 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 316724.182888 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 316724.182888 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 393531 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 29284 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28535 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.709978 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.791169 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -484,12 +400,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12136883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10812648570 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10812648570 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10824785453 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10824785453 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10824785453 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10824785453 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 11031075660 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 11031075660 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 11043212543 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 11043212543 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 11043212543 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 11043212543 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -500,12 +416,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70155.393064 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 70155.393064 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260219.690268 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 260219.690268 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259431.646567 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 259431.646567 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259431.646567 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 259431.646567 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 265476.406912 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 265476.406912 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 264666.567837 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 264666.567837 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 264666.567837 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 264666.567837 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -519,36 +435,36 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13863448 # Number of BP lookups -system.cpu.branchPred.condPredicted 11631259 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 399718 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9400932 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5821857 # Number of BTB hits +system.cpu.branchPred.lookups 13847711 # Number of BP lookups +system.cpu.branchPred.condPredicted 11622265 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 397151 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9355929 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5809145 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.928509 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 906521 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 39211 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 62.090520 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 903416 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 38861 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9926517 # DTB read hits -system.cpu.dtb.read_misses 41406 # DTB read misses -system.cpu.dtb.read_acv 531 # DTB read access violations -system.cpu.dtb.read_accesses 940700 # DTB read accesses -system.cpu.dtb.write_hits 6593963 # DTB write hits -system.cpu.dtb.write_misses 10630 # DTB write misses -system.cpu.dtb.write_acv 410 # DTB write access violations -system.cpu.dtb.write_accesses 338096 # DTB write accesses -system.cpu.dtb.data_hits 16520480 # DTB hits -system.cpu.dtb.data_misses 52036 # DTB misses -system.cpu.dtb.data_acv 941 # DTB access violations -system.cpu.dtb.data_accesses 1278796 # DTB accesses -system.cpu.itb.fetch_hits 1306353 # ITB hits -system.cpu.itb.fetch_misses 36823 # ITB misses -system.cpu.itb.fetch_acv 1069 # ITB acv -system.cpu.itb.fetch_accesses 1343176 # ITB accesses +system.cpu.dtb.read_hits 9926060 # DTB read hits +system.cpu.dtb.read_misses 41229 # DTB read misses +system.cpu.dtb.read_acv 545 # DTB read access violations +system.cpu.dtb.read_accesses 943227 # DTB read accesses +system.cpu.dtb.write_hits 6592681 # DTB write hits +system.cpu.dtb.write_misses 10567 # DTB write misses +system.cpu.dtb.write_acv 408 # DTB write access violations +system.cpu.dtb.write_accesses 338977 # DTB write accesses +system.cpu.dtb.data_hits 16518741 # DTB hits +system.cpu.dtb.data_misses 51796 # DTB misses +system.cpu.dtb.data_acv 953 # DTB access violations +system.cpu.dtb.data_accesses 1282204 # DTB accesses +system.cpu.itb.fetch_hits 1307907 # ITB hits +system.cpu.itb.fetch_misses 36763 # ITB misses +system.cpu.itb.fetch_acv 1058 # ITB acv +system.cpu.itb.fetch_accesses 1344670 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -561,269 +477,269 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 121966998 # number of cpu cycles simulated +system.cpu.numCycles 122133073 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28067964 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70813073 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13863448 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6728378 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13263425 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1999195 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 38181411 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33091 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 255000 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 364206 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 297 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8556045 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 264477 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 81457086 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.869330 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.212823 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28029052 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70711644 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13847711 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6712561 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13244944 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1986135 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 38034896 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 253831 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 364385 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 294 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8541461 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 263003 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 81242947 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.870373 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.213979 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68193661 83.72% 83.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 852857 1.05% 84.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1696439 2.08% 86.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 825181 1.01% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2758325 3.39% 91.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 561473 0.69% 91.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 645881 0.79% 92.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1010308 1.24% 93.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4912961 6.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67998003 83.70% 83.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 851901 1.05% 84.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1695578 2.09% 86.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 822984 1.01% 87.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2755109 3.39% 91.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 560259 0.69% 91.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 643349 0.79% 92.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1008302 1.24% 93.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4907462 6.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81457086 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.113666 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.580592 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29256938 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37863691 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12127839 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 959156 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1249461 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 584263 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42640 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69481989 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129319 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1249461 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30407522 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14148846 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20005990 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11332374 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4312891 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65679549 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7211 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 504797 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1541440 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43855166 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79746051 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79567055 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 166544 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38180329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5674829 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682909 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 240455 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12257327 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10441163 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6908790 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1318239 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 851396 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58211664 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2050007 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56814932 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 114609 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6922962 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3587498 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1389025 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 81457086 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.697483 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.359485 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 81242947 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.113382 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.578972 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29204589 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37726390 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12112827 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 958015 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1241125 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 582779 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42656 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69393384 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129440 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1241125 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30348079 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14012797 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20034433 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11321379 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4285132 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65602946 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7156 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 505213 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1511728 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43797820 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79654521 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79475437 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 166633 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38179156 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5618656 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1682920 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 240154 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12205182 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10434201 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6904424 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1321264 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 860087 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58162225 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2049609 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56784496 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 110090 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6876207 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3554384 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1388666 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 81242947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.698947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.361354 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56746030 69.66% 69.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10887232 13.37% 83.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5162469 6.34% 89.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3392471 4.16% 93.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2625915 3.22% 96.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1461124 1.79% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 753330 0.92% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 332031 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 96484 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56591956 69.66% 69.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10816248 13.31% 82.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5164366 6.36% 89.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3390360 4.17% 93.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2636798 3.25% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1463129 1.80% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 751413 0.92% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 332295 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 96382 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 81457086 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 81242947 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 91940 11.62% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 373423 47.20% 58.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 325849 41.18% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91428 11.57% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 372699 47.16% 58.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326088 41.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38737583 68.18% 68.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61738 0.11% 68.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10357242 18.23% 86.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6672763 11.74% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949077 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38710597 68.17% 68.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61705 0.11% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10355398 18.24% 86.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6671255 11.75% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949012 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56814932 # Type of FU issued -system.cpu.iq.rate 0.465822 # Inst issue rate -system.cpu.iq.fu_busy_cnt 791212 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013926 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 195300199 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66861892 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55573336 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692571 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336551 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327871 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57237458 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361400 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 598272 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56784496 # Type of FU issued +system.cpu.iq.rate 0.464940 # Inst issue rate +system.cpu.iq.fu_busy_cnt 790215 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013916 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 195020122 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66766340 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55549754 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692121 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 335594 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327937 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57205980 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361445 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 599867 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1348718 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3201 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14139 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 530806 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1342082 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3325 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14250 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 526611 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17937 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 182742 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17915 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 172386 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1249461 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10237116 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 702035 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63785040 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 690324 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10441163 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6908790 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1805677 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512237 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17569 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14139 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 202047 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 411314 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 613361 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56348369 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9996094 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 466562 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1241125 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10205447 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 698563 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63733516 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 684669 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10434201 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6904424 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1805473 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512478 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17546 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14250 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 200257 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411476 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 611733 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56321962 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 9995488 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 462533 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3523369 # number of nop insts executed -system.cpu.iew.exec_refs 16615920 # number of memory reference insts executed -system.cpu.iew.exec_branches 8927027 # Number of branches executed -system.cpu.iew.exec_stores 6619826 # Number of stores executed -system.cpu.iew.exec_rate 0.461997 # Inst execution rate -system.cpu.iew.wb_sent 56016387 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55901207 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27709617 # num instructions producing a value -system.cpu.iew.wb_consumers 37531222 # num instructions consuming a value +system.cpu.iew.exec_nop 3521682 # number of nop insts executed +system.cpu.iew.exec_refs 16613940 # number of memory reference insts executed +system.cpu.iew.exec_branches 8922207 # Number of branches executed +system.cpu.iew.exec_stores 6618452 # Number of stores executed +system.cpu.iew.exec_rate 0.461152 # Inst execution rate +system.cpu.iew.wb_sent 55993079 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55877691 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27722224 # num instructions producing a value +system.cpu.iew.wb_consumers 37565081 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.458331 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738308 # average fanout of values written-back +system.cpu.iew.wb_rate 0.457515 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.737979 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7496348 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660982 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 568504 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80207625 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.700316 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.629380 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7447390 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660943 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 565908 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80001822 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.702098 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.631989 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59390670 74.05% 74.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8659340 10.80% 84.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4620197 5.76% 90.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2517886 3.14% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1507376 1.88% 95.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 612052 0.76% 96.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 525608 0.66% 97.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 522089 0.65% 97.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1852407 2.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59240837 74.05% 74.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8588333 10.74% 84.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4609463 5.76% 90.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2533581 3.17% 93.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1517845 1.90% 95.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 611107 0.76% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 522353 0.65% 97.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 526375 0.66% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1851928 2.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80207625 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56170683 # Number of instructions committed -system.cpu.commit.committedOps 56170683 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 80001822 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56169084 # Number of instructions committed +system.cpu.commit.committedOps 56169084 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15470429 # Number of memory references committed -system.cpu.commit.loads 9092445 # Number of loads committed -system.cpu.commit.membars 226358 # Number of memory barriers committed -system.cpu.commit.branches 8439899 # Number of branches committed +system.cpu.commit.refs 15469932 # Number of memory references committed +system.cpu.commit.loads 9092119 # Number of loads committed +system.cpu.commit.membars 226344 # Number of memory barriers committed +system.cpu.commit.branches 8439731 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52020266 # Number of committed integer instructions. -system.cpu.commit.function_calls 740581 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1852407 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52018783 # Number of committed integer instructions. +system.cpu.commit.function_calls 740550 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1851928 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141772543 # The number of ROB reads -system.cpu.rob.rob_writes 128585215 # The number of ROB writes -system.cpu.timesIdled 1193212 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 40509912 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3598422122 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52979882 # Number of Instructions Simulated -system.cpu.committedOps 52979882 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52979882 # Number of Instructions Simulated -system.cpu.cpi 2.302138 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.302138 # CPI: Total CPI of All Threads -system.cpu.ipc 0.434379 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.434379 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73881277 # number of integer regfile reads -system.cpu.int_regfile_writes 40316653 # number of integer regfile writes -system.cpu.fp_regfile_reads 166009 # number of floating regfile reads -system.cpu.fp_regfile_writes 167434 # number of floating regfile writes -system.cpu.misc_regfile_reads 2028435 # number of misc regfile reads -system.cpu.misc_regfile_writes 938984 # number of misc regfile writes +system.cpu.rob.rob_reads 141516799 # The number of ROB reads +system.cpu.rob.rob_writes 128475885 # The number of ROB writes +system.cpu.timesIdled 1198400 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 40890126 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3598244060 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52978349 # Number of Instructions Simulated +system.cpu.committedOps 52978349 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52978349 # Number of Instructions Simulated +system.cpu.cpi 2.305339 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.305339 # CPI: Total CPI of All Threads +system.cpu.ipc 0.433776 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.433776 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73853807 # number of integer regfile reads +system.cpu.int_regfile_writes 40298046 # number of integer regfile writes +system.cpu.fp_regfile_reads 166062 # number of floating regfile reads +system.cpu.fp_regfile_writes 167446 # number of floating regfile writes +system.cpu.misc_regfile_reads 2027357 # number of misc regfile reads +system.cpu.misc_regfile_writes 938942 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -858,9 +774,9 @@ system.tsunami.ethernet.droppedPackets 0 # nu system.iobus.throughput 1454553 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51150 # Transaction distribution -system.iobus.trans_dist::WriteResp 51150 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51149 # Transaction distribution +system.iobus.trans_dist::WriteResp 51149 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -872,11 +788,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33054 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116504 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20200 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -888,12 +804,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 44140 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2705756 # Total data (bytes) -system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2705748 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2705748 # Total data (bytes) +system.iobus.reqLayer0.occupancy 4661000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -915,249 +831,241 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 377738948 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 380111537 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42679505 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43192006 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.throughput 111941811 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2118263 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2118167 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 840743 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 66 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 342536 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 300985 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 79 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2020543 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677710 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5698253 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64653440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143572596 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 208226036 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 208215988 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 17920 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2480284498 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 111856774 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2116112 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2116015 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 840541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 62 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 63 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 342408 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 300857 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2017437 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3676056 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5693493 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64554304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143513388 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 208067692 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 208057644 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 17408 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2478840496 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1518802860 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1516414125 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2192631666 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2186111163 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 1009602 # number of replacements -system.cpu.icache.tags.tagsinuse 509.660060 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7489391 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1010110 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.414431 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 26489829250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.660060 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.995430 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.995430 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1008048 # number of replacements +system.cpu.icache.tags.tagsinuse 509.665585 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7476650 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1008556 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.413222 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 26682759250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.665585 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.995441 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.995441 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9566377 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9566377 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7489392 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7489392 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7489392 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7489392 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7489392 # number of overall hits -system.cpu.icache.overall_hits::total 7489392 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1066652 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1066652 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1066652 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1066652 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1066652 # number of overall misses -system.cpu.icache.overall_misses::total 1066652 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14896343949 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14896343949 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14896343949 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14896343949 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14896343949 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14896343949 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8556044 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8556044 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8556044 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8556044 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8556044 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8556044 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124666 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124666 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124666 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124666 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124666 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124666 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13965.514478 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13965.514478 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13965.514478 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13965.514478 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13965.514478 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13965.514478 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4660 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 199 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 23.417085 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 9550236 # Number of tag accesses +system.cpu.icache.tags.data_accesses 9550236 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7476651 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7476651 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7476651 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7476651 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7476651 # number of overall hits +system.cpu.icache.overall_hits::total 7476651 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1064809 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1064809 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1064809 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1064809 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1064809 # number of overall misses +system.cpu.icache.overall_misses::total 1064809 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14791038698 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14791038698 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14791038698 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14791038698 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14791038698 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14791038698 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8541460 # 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average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13643.738095 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71068.072375 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71068.072375 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64551.472030 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58467.981996 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58694.497004 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64551.472030 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58467.981996 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58694.497004 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1247,13 +1147,13 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1401219 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994567 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11810743 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1401731 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.425827 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25477000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994567 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1400496 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994513 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11811358 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1401008 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.430614 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25856000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994513 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1261,154 +1161,154 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 system.cpu.dcache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63738376 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63738376 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7205308 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7205308 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4203634 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4203634 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186044 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186044 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215517 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215517 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11408942 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11408942 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11408942 # number of overall hits -system.cpu.dcache.overall_hits::total 11408942 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1806790 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1806790 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1944128 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1944128 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22738 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22738 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3750918 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3750918 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3750918 # number of overall misses -system.cpu.dcache.overall_misses::total 3750918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 40335866684 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 40335866684 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 77256495609 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 77256495609 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 322518001 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 322518001 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 39001 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 39001 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 117592362293 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 117592362293 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 117592362293 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 117592362293 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9012098 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9012098 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147762 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147762 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208782 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 208782 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215519 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215519 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15159860 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15159860 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15159860 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15159860 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200485 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.200485 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316233 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316233 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108908 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108908 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247424 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247424 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247424 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247424 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22324.601467 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22324.601467 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39738.379165 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39738.379165 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14184.097150 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14184.097150 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19500.500000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31350.288727 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31350.288727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31350.288727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31350.288727 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3041849 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 733 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 98391 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 63734677 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63734677 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7206132 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7206132 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4203012 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4203012 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186466 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186466 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215515 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215515 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11409144 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11409144 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11409144 # number of overall hits +system.cpu.dcache.overall_hits::total 11409144 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1805019 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1805019 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1944584 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1944584 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22688 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22688 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3749603 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3749603 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3749603 # number of overall misses +system.cpu.dcache.overall_misses::total 3749603 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40356893890 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40356893890 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 77719104532 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 77719104532 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 321753501 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 321753501 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 118075998422 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 118075998422 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 118075998422 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 118075998422 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9011151 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9011151 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147596 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147596 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209154 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209154 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215516 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215516 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15158747 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15158747 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15158747 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15158747 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200309 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.200309 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316316 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316316 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108475 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108475 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.247356 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247356 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247356 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247356 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22358.154618 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22358.154618 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39966.956702 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39966.956702 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14181.659952 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14181.659952 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31490.266682 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31490.266682 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31490.266682 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31490.266682 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3050951 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 663 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 86776 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.915927 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 104.714286 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.158926 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 94.714286 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840743 # number of writebacks -system.cpu.dcache.writebacks::total 840743 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722826 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 722826 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643736 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1643736 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5220 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5220 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2366562 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2366562 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2366562 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2366562 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083964 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1083964 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300392 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300392 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17518 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17518 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384356 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384356 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384356 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384356 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27183263254 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27183263254 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11761438359 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11761438359 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200916999 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200916999 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 34999 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 34999 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38944701613 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 38944701613 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38944701613 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 38944701613 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424030000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424030000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997779498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997779498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421809498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421809498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120279 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120279 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048862 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048862 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083906 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083906 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091317 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091317 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091317 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091317 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25077.643957 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25077.643957 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39153.633782 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39153.633782 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11469.174506 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11469.174506 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17499.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17499.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28131.999004 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28131.999004 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28131.999004 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28131.999004 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 840541 # number of writebacks +system.cpu.dcache.writebacks::total 840541 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 721694 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 721694 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1644324 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1644324 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5123 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5123 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2366018 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2366018 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2366018 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2366018 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083325 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083325 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300260 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300260 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17565 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17565 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1383585 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1383585 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1383585 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1383585 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27323478009 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27323478009 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11844407335 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11844407335 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200869499 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200869499 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39167885344 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 39167885344 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39167885344 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 39167885344 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424097000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424097000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997590998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997590998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421687998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421687998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120220 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120220 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048842 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048842 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083981 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083981 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091273 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091273 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25221.866023 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25221.866023 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39447.170236 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39447.170236 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11435.781327 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11435.781327 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28308.983795 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28308.983795 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28308.983795 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28308.983795 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1417,28 +1317,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211017 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211003 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182248 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73298 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105563 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182234 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148607 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818029044000 97.73% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64103000 0.00% 97.74% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 561251500 0.03% 97.77% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41542545500 2.23% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1860196944000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817851866500 97.72% 97.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64172000 0.00% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 559556500 0.03% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 41715361500 2.24% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1860190956500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694294 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694315 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815424 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1477,29 +1377,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175131 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175119 91.23% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191976 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches +system.cpu.kern.callpal::total 191963 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches system.cpu.kern.mode_switch::user 1740 # number of protection mode switches system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches system.cpu.kern.mode_good::kernel 1910 system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326384 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326440 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394343 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29636227500 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2736556500 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827824152000 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29573655500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2713841000 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827903452000 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 76117c4c2..d0170b803 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,147 +1,147 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.842697 # Number of seconds simulated -sim_ticks 1842697218000 # Number of ticks simulated -final_tick 1842697218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.842694 # Number of seconds simulated +sim_ticks 1842693728000 # Number of ticks simulated +final_tick 1842693728000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 281851 # Simulator instruction rate (inst/s) -host_op_rate 281851 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7098045398 # Simulator tick rate (ticks/s) -host_mem_usage 310872 # Number of bytes of host memory used -host_seconds 259.61 # Real time elapsed on the host -sim_insts 73170192 # Number of instructions simulated -sim_ops 73170192 # Number of ops (including micro ops) simulated +host_inst_rate 239111 # Simulator instruction rate (inst/s) +host_op_rate 239111 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5964368765 # Simulator tick rate (ticks/s) +host_mem_usage 346744 # Number of bytes of host memory used +host_seconds 308.95 # Real time elapsed on the host +sim_insts 73873335 # Number of instructions simulated +sim_ops 73873335 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 489152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20102912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 489024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20126208 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 144448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2236224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 284928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2526528 # Number of bytes read from this memory -system.physmem.bytes_read::total 28436544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 489152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 144448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 284928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 918528 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7459712 # Number of bytes written to this memory -system.physmem.bytes_written::total 7459712 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7643 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 314108 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 143680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2232768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 285376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2509376 # Number of bytes read from this memory +system.physmem.bytes_read::total 28438784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 489024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 143680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 285376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 918080 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7463104 # Number of bytes written to this memory +system.physmem.bytes_written::total 7463104 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7641 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 314472 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2257 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 34941 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4452 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39477 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444321 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116558 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116558 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 265454 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10909504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1439386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 78389 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1213560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 154626 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1371103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15432022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 265454 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 78389 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 154626 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498469 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4048257 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4048257 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4048257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 265454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10909504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1439386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 78389 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1213560 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 154626 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1371103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19480279 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 98018 # Number of read requests accepted -system.physmem.writeReqs 44365 # Number of write requests accepted -system.physmem.readBursts 98018 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 44365 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6272576 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue -system.physmem.bytesWritten 2838464 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6273152 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2839360 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu1.inst 2245 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 34887 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4459 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39209 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444356 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116611 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116611 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 265385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10922167 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1439388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 77973 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1211687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 154869 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1361798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15433267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 265385 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 77973 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 154869 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498227 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4050105 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4050105 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4050105 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 265385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10922167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1439388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 77973 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1211687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 154869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1361798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19483372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 97691 # Number of read requests accepted +system.physmem.writeReqs 44282 # Number of write requests accepted +system.physmem.readBursts 97691 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 44282 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6250944 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1280 # Total number of bytes read from write queue +system.physmem.bytesWritten 2832576 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6252224 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2834048 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 20 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 42 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6238 # Per bank write bursts -system.physmem.perBankRdBursts::1 6029 # Per bank write bursts -system.physmem.perBankRdBursts::2 6222 # Per bank write bursts -system.physmem.perBankRdBursts::3 6415 # Per bank write bursts -system.physmem.perBankRdBursts::4 5671 # Per bank write bursts -system.physmem.perBankRdBursts::5 6259 # Per bank write bursts -system.physmem.perBankRdBursts::6 6020 # Per bank write bursts -system.physmem.perBankRdBursts::7 6028 # Per bank write bursts -system.physmem.perBankRdBursts::8 6370 # Per bank write bursts -system.physmem.perBankRdBursts::9 6122 # Per bank write bursts -system.physmem.perBankRdBursts::10 6366 # Per bank write bursts -system.physmem.perBankRdBursts::11 5871 # Per bank write bursts -system.physmem.perBankRdBursts::12 5882 # Per bank write bursts -system.physmem.perBankRdBursts::13 6242 # Per bank write bursts -system.physmem.perBankRdBursts::14 6237 # Per bank write bursts -system.physmem.perBankRdBursts::15 6037 # Per bank write bursts -system.physmem.perBankWrBursts::0 2849 # Per bank write bursts -system.physmem.perBankWrBursts::1 2656 # Per bank write bursts -system.physmem.perBankWrBursts::2 2849 # Per bank write bursts -system.physmem.perBankWrBursts::3 3015 # Per bank write bursts -system.physmem.perBankWrBursts::4 2565 # Per bank write bursts -system.physmem.perBankWrBursts::5 2994 # Per bank write bursts -system.physmem.perBankWrBursts::6 2937 # Per bank write bursts -system.physmem.perBankWrBursts::7 2695 # Per bank write bursts -system.physmem.perBankWrBursts::8 3093 # Per bank write bursts -system.physmem.perBankWrBursts::9 2622 # Per bank write bursts -system.physmem.perBankWrBursts::10 2879 # Per bank write bursts -system.physmem.perBankWrBursts::11 2436 # Per bank write bursts -system.physmem.perBankWrBursts::12 2462 # Per bank write bursts -system.physmem.perBankWrBursts::13 2714 # Per bank write bursts -system.physmem.perBankWrBursts::14 2848 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 39 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6114 # Per bank write bursts +system.physmem.perBankRdBursts::1 5899 # Per bank write bursts +system.physmem.perBankRdBursts::2 6060 # Per bank write bursts +system.physmem.perBankRdBursts::3 6276 # Per bank write bursts +system.physmem.perBankRdBursts::4 5549 # Per bank write bursts +system.physmem.perBankRdBursts::5 6233 # Per bank write bursts +system.physmem.perBankRdBursts::6 6082 # Per bank write bursts +system.physmem.perBankRdBursts::7 6075 # Per bank write bursts +system.physmem.perBankRdBursts::8 6372 # Per bank write bursts +system.physmem.perBankRdBursts::9 6119 # Per bank write bursts +system.physmem.perBankRdBursts::10 6443 # Per bank write bursts +system.physmem.perBankRdBursts::11 5953 # Per bank write bursts +system.physmem.perBankRdBursts::12 5846 # Per bank write bursts +system.physmem.perBankRdBursts::13 6273 # Per bank write bursts +system.physmem.perBankRdBursts::14 6335 # Per bank write bursts +system.physmem.perBankRdBursts::15 6042 # Per bank write bursts +system.physmem.perBankWrBursts::0 2746 # Per bank write bursts +system.physmem.perBankWrBursts::1 2526 # Per bank write bursts +system.physmem.perBankWrBursts::2 2727 # Per bank write bursts +system.physmem.perBankWrBursts::3 3010 # Per bank write bursts +system.physmem.perBankWrBursts::4 2533 # Per bank write bursts +system.physmem.perBankWrBursts::5 2968 # Per bank write bursts +system.physmem.perBankWrBursts::6 2994 # Per bank write bursts +system.physmem.perBankWrBursts::7 2697 # Per bank write bursts +system.physmem.perBankWrBursts::8 3092 # Per bank write bursts +system.physmem.perBankWrBursts::9 2617 # Per bank write bursts +system.physmem.perBankWrBursts::10 2969 # Per bank write bursts +system.physmem.perBankWrBursts::11 2522 # Per bank write bursts +system.physmem.perBankWrBursts::12 2428 # Per bank write bursts +system.physmem.perBankWrBursts::13 2745 # Per bank write bursts +system.physmem.perBankWrBursts::14 2948 # Per bank write bursts system.physmem.perBankWrBursts::15 2737 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 4 # Number of times write queue was full causing retry -system.physmem.totGap 1841684892500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 1841681402500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 98018 # Read request sizes (log2) +system.physmem.readPktSize::6 97691 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 44365 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 66438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 14086 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6897 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2022 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 553 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 609 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 552 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 44282 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 65712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9632 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 488 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1780 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1567 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1624 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 859 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 829 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 762 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 744 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 609 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 495 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -153,423 +153,391 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 2181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 2225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 2215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 17929 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 508.069831 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 168.315652 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1577.422962 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 7580 42.28% 42.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 2972 16.58% 58.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 1827 10.19% 69.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 983 5.48% 74.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 676 3.77% 78.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 569 3.17% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 353 1.97% 83.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 316 1.76% 85.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 239 1.33% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 212 1.18% 87.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 225 1.25% 88.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 207 1.15% 90.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 92 0.51% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 80 0.45% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 62 0.35% 91.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 115 0.64% 92.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 35 0.20% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 50 0.28% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 54 0.30% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 63 0.35% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 30 0.17% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 123 0.69% 94.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 74 0.41% 94.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 80 0.45% 94.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 19 0.11% 95.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 17 0.09% 95.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 7 0.04% 95.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 37 0.21% 95.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 7 0.04% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 18 0.10% 95.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 6 0.03% 95.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 15 0.08% 95.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 9 0.05% 95.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 16 0.09% 95.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 1 0.01% 95.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 23 0.13% 95.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 12 0.07% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 4 0.02% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 9 0.05% 96.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 2 0.01% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 15 0.08% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 22 0.12% 96.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 1 0.01% 96.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 14 0.08% 96.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 3 0.02% 96.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 12 0.07% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.01% 96.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 12 0.07% 96.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.01% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 20 0.11% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 11 0.06% 96.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 2 0.01% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 9 0.05% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 1 0.01% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 13 0.07% 96.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 21 0.12% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 1 0.01% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 13 0.07% 97.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 2 0.01% 97.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 8 0.04% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 3 0.02% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 14 0.08% 97.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 22 0.12% 97.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 13 0.07% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 1 0.01% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 77 0.43% 97.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 3 0.02% 97.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 19 0.11% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 5 0.03% 97.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.01% 97.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 8 0.04% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 4 0.02% 98.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 21 0.12% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 6 0.03% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 9 0.05% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 2 0.01% 98.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 3 0.02% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 21 0.12% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 3 0.02% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 6 0.03% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 5 0.03% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 19 0.11% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 6 0.03% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 6 0.03% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 25 0.14% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.01% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 15 0.08% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 1 0.01% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.01% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 21 0.12% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 4 0.02% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 1 0.01% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 52 0.29% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 1 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 1 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9411 1 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 1 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 2 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11011 1 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11331 1 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11395 1 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 1 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 1 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12099 1 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 1 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12803 2 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 1 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13315 2 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 2 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 1 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 2 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 1 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 1 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 1 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 1 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 1 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 16 0.09% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 1 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15683 1 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 1 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 75 0.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 17929 # Bytes accessed per row activation -system.physmem.totQLat 2679388500 # Total ticks spent queuing -system.physmem.totMemAccLat 4331514750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 490045000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1162081250 # Total ticks spent accessing banks -system.physmem.avgQLat 27338.19 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 11856.88 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 10 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 15110 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 511.250298 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 300.938727 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 421.415256 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3831 25.35% 25.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 2740 18.13% 43.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1074 7.11% 50.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 703 4.65% 55.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 520 3.44% 58.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 360 2.38% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 225 1.49% 62.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 226 1.50% 64.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5431 35.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 15110 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2571 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.985220 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 914.533013 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2569 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.04% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.04% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 2571 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2571 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.214702 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.506808 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 4.396297 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 28 1.09% 1.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 8 0.31% 1.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 1 0.04% 1.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 1 0.04% 1.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 1 0.04% 1.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 1 0.04% 1.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 2 0.08% 1.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 2 0.08% 1.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 1 0.04% 1.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 1 0.04% 1.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1798 69.93% 71.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 69 2.68% 74.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 74 2.88% 77.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 370 14.39% 91.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 34 1.32% 93.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 19 0.74% 93.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 12 0.47% 94.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 7 0.27% 94.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 34 1.32% 95.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 15 0.58% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.19% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 15 0.58% 97.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 11 0.43% 97.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 14 0.54% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.16% 98.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 5 0.19% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 6 0.23% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 3 0.12% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.04% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.04% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 2 0.08% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 2 0.08% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 3 0.12% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 4 0.16% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 3 0.12% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 5 0.19% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 2 0.08% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 1 0.04% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 2 0.08% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 2 0.08% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 2 0.08% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2571 # Writes before turning the bus around for reads +system.physmem.totQLat 3372876000 # Total ticks spent queuing +system.physmem.totMemAccLat 5050468500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 488355000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1189237500 # Total ticks spent accessing banks +system.physmem.avgQLat 34533.03 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 12175.95 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44195.07 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 51708.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.39 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.40 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.39 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.16 # Average write queue length when enqueuing -system.physmem.readRowHits 89637 # Number of row buffer hits during reads -system.physmem.writeRowHits 34794 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.46 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.43 # Row buffer hit rate for writes -system.physmem.avgGap 12934724.60 # Average gap between requests -system.physmem.pageHitRate 87.40 # Row buffer hit rate, read and write combined +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 4.13 # Average write queue length when enqueuing +system.physmem.readRowHits 85060 # Number of row buffer hits during reads +system.physmem.writeRowHits 35225 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.55 # Row buffer hit rate for writes +system.physmem.avgGap 12972053.86 # Average gap between requests +system.physmem.pageHitRate 84.74 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 0.21 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 19524219 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 44737 # Transaction distribution -system.membus.trans_dist::ReadResp 44533 # Transaction distribution -system.membus.trans_dist::WriteReq 3749 # Transaction distribution -system.membus.trans_dist::WriteResp 3749 # Transaction distribution -system.membus.trans_dist::Writeback 44365 # Transaction distribution -system.membus.trans_dist::UpgradeReq 45 # Transaction distribution -system.membus.trans_dist::UpgradeResp 45 # Transaction distribution -system.membus.trans_dist::ReadExReq 56547 # Transaction distribution -system.membus.trans_dist::ReadExResp 56547 # Transaction distribution -system.membus.trans_dist::BadAddressError 204 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13310 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 189932 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 408 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 203650 # Packet count per connected master and slave (bytes) +system.membus.throughput 19527312 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 44337 # Transaction distribution +system.membus.trans_dist::ReadResp 44306 # Transaction distribution +system.membus.trans_dist::WriteReq 3779 # Transaction distribution +system.membus.trans_dist::WriteResp 3779 # Transaction distribution +system.membus.trans_dist::Writeback 44282 # Transaction distribution +system.membus.trans_dist::UpgradeReq 42 # Transaction distribution +system.membus.trans_dist::UpgradeResp 42 # Transaction distribution +system.membus.trans_dist::ReadExReq 56476 # Transaction distribution +system.membus.trans_dist::ReadExResp 56476 # Transaction distribution +system.membus.trans_dist::BadAddressError 31 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13428 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 189189 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 62 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 202679 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 50712 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 50712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 254362 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15689 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6952704 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 6968393 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 253391 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15748 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6926464 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 6942212 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2159808 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 2159808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 9128201 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35967240 # Total data (bytes) +system.membus.tot_pkt_size::total 9102020 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35972872 # Total data (bytes) system.membus.snoop_data_through_bus 9984 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12468500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 12574500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 514332500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 513408250 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 252500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 40000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 764298954 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 761373958 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 152995500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 153163000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 337398 # number of replacements -system.l2c.tags.tagsinuse 65420.701532 # Cycle average of tags in use -system.l2c.tags.total_refs 2472173 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402561 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.141114 # Average number of references to valid blocks. +system.l2c.tags.replacements 337430 # number of replacements +system.l2c.tags.tagsinuse 65422.148259 # Cycle average of tags in use +system.l2c.tags.total_refs 2473441 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402593 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.143775 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54886.932182 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2458.825580 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2703.778525 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 528.462620 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 622.296328 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2148.830278 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2071.576019 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.837508 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 54880.563920 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2458.853214 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2711.613848 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 517.416897 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 618.305247 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2161.633442 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2073.761691 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.837411 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.037519 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041256 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008064 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009495 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.032789 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.031610 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998241 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.041376 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.007895 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009435 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.032984 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.031643 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998263 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 988 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5636 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2991 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55380 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1047 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5588 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2973 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55387 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26143118 # Number of tag accesses -system.l2c.tags.data_accesses 26143118 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 520243 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 493553 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 124286 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 83912 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 292769 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 239004 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1753767 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835523 # number of Writeback hits -system.l2c.Writeback_hits::total 835523 # number of Writeback hits +system.l2c.tags.tag_accesses 26153114 # Number of tag accesses +system.l2c.tags.data_accesses 26153114 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 521024 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 493028 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 125251 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 84722 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 291154 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 239311 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1754490 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 836107 # number of Writeback hits +system.l2c.Writeback_hits::total 836107 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 7 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu2.data 1 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 92938 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 26217 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 67761 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186916 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 520243 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 586491 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 124286 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 110129 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 292769 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 306765 # number of demand (read+write) hits -system.l2c.demand_hits::total 1940683 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 520243 # number of overall hits -system.l2c.overall_hits::cpu0.data 586491 # number of overall hits -system.l2c.overall_hits::cpu1.inst 124286 # number of overall hits -system.l2c.overall_hits::cpu1.data 110129 # number of overall hits -system.l2c.overall_hits::cpu2.inst 292769 # number of overall hits -system.l2c.overall_hits::cpu2.data 306765 # number of overall hits -system.l2c.overall_hits::total 1940683 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 7643 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 238324 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2257 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 16911 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 4452 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 18142 # number of ReadReq misses -system.l2c.ReadReq_misses::total 287729 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu0.data 93137 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 26426 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 67420 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 186983 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 521024 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 586165 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 125251 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 111148 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 291154 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 306731 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 4834368536 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 279416000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 295991000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 575407000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 345820000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 406371500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 752191500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 625236000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 702362500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1327598500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.017608 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.165448 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015084 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.069350 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020241 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.750000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.375000 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.407037 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.241560 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.130844 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017608 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.239150 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015084 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.113589 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034521 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017608 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.239150 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015084 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.113589 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034521 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59847.551448 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54323.484758 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63710.417134 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54576.837885 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 55745.493988 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 26778.444444 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 26778.444444 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55577.191841 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 70882.958739 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63873.981597 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59847.551448 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 54974.453572 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63710.417134 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63484.926551 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59723.377758 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59847.551448 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 54974.453572 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63710.417134 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63484.926551 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59723.377758 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -680,14 +648,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254904 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254944 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1694870354000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254904 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078431 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078431 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1694864715000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254944 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078434 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078434 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -703,12 +671,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 9303463 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 9303463 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5314732731 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5314732731 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5324036194 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5324036194 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5324036194 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5324036194 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5375933278 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5375933278 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5385236741 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5385236741 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5385236741 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5385236741 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -727,17 +695,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53777.242775 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 53777.242775 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 127905.581705 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 127905.581705 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 127598.231132 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 127598.231132 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 127598.231132 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 127598.231132 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 168308 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 129378.448161 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 129378.448161 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 129064.990797 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129064.990797 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 129064.990797 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129064.990797 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 158120 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 12241 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11558 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.749530 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.680568 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -753,12 +721,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 16965 system.iocache.overall_mshr_misses::total 16965 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5714463 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 5714463 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4435520731 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4435520731 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 4441235194 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4441235194 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 4441235194 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4441235194 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4496386278 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4496386278 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 4502100741 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4502100741 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 4502100741 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4502100741 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.406623 # mshr miss rate for WriteReq accesses @@ -769,12 +737,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 0.406591 system.iocache.overall_mshr_miss_rate::total 0.406591 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82818.304348 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 82818.304348 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 262518.982659 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 262518.982659 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 261788.104568 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 261788.104568 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 261788.104568 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 261788.104568 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 266121.346946 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 266121.346946 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 265375.817330 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 265375.817330 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 265375.817330 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 265375.817330 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -792,22 +760,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4920578 # DTB read hits +system.cpu0.dtb.read_hits 4928404 # DTB read hits system.cpu0.dtb.read_misses 6099 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations system.cpu0.dtb.read_accesses 428233 # DTB read accesses -system.cpu0.dtb.write_hits 3510258 # DTB write hits +system.cpu0.dtb.write_hits 3518338 # DTB write hits system.cpu0.dtb.write_misses 670 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations system.cpu0.dtb.write_accesses 163777 # DTB write accesses -system.cpu0.dtb.data_hits 8430836 # DTB hits +system.cpu0.dtb.data_hits 8446742 # DTB hits system.cpu0.dtb.data_misses 6769 # DTB misses system.cpu0.dtb.data_acv 210 # DTB access violations system.cpu0.dtb.data_accesses 592010 # DTB accesses -system.cpu0.itb.fetch_hits 2762930 # ITB hits +system.cpu0.itb.fetch_hits 2763962 # ITB hits system.cpu0.itb.fetch_misses 3034 # ITB misses system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2765964 # ITB accesses +system.cpu0.itb.fetch_accesses 2766996 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -820,52 +788,52 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928345000 # number of cpu cycles simulated +system.cpu0.numCycles 928692350 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 33879417 # Number of instructions committed -system.cpu0.committedOps 33879417 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 31738664 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 170028 # Number of float alu accesses -system.cpu0.num_func_calls 812853 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4700164 # number of instructions that are conditional controls -system.cpu0.num_int_insts 31738664 # number of integer instructions -system.cpu0.num_fp_insts 170028 # number of float instructions -system.cpu0.num_int_register_reads 44595421 # number of times the integer registers were read -system.cpu0.num_int_register_writes 23158595 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 87794 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 89338 # number of times the floating registers were written -system.cpu0.num_mem_refs 8461010 # number of memory refs -system.cpu0.num_load_insts 4941975 # Number of load instructions -system.cpu0.num_store_insts 3519035 # Number of store instructions -system.cpu0.num_idle_cycles 904626845.998199 # Number of idle cycles -system.cpu0.num_busy_cycles 23718154.001801 # Number of busy cycles -system.cpu0.not_idle_fraction 0.025549 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.974451 # Percentage of idle cycles -system.cpu0.Branches 5776800 # Number of branches fetched +system.cpu0.committedInsts 34273964 # Number of instructions committed +system.cpu0.committedOps 34273964 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 32130742 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 169948 # Number of float alu accesses +system.cpu0.num_func_calls 813899 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4819398 # number of instructions that are conditional controls +system.cpu0.num_int_insts 32130742 # number of integer instructions +system.cpu0.num_fp_insts 169948 # number of float instructions +system.cpu0.num_int_register_reads 45237353 # number of times the integer registers were read +system.cpu0.num_int_register_writes 23423813 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 87792 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 89256 # number of times the floating registers were written +system.cpu0.num_mem_refs 8476912 # number of memory refs +system.cpu0.num_load_insts 4949798 # Number of load instructions +system.cpu0.num_store_insts 3527114 # Number of store instructions +system.cpu0.num_idle_cycles 904863863.789935 # Number of idle cycles +system.cpu0.num_busy_cycles 23828486.210065 # Number of busy cycles +system.cpu0.not_idle_fraction 0.025658 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.974342 # Percentage of idle cycles +system.cpu0.Branches 5897308 # Number of branches fetched system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6418 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211383 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74805 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6415 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211374 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74800 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105697 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182584 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73438 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 105691 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182573 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73433 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73438 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148958 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1819507118500 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38781000 0.00% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 365071000 0.02% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22785478000 1.24% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1842696448500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 73433 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148948 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1819462416000 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38889500 0.00% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 365010500 0.02% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22826642500 1.24% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1842692958500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694797 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815833 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694790 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815827 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -901,10 +869,10 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175325 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175314 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -913,21 +881,21 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192238 # number of callpals executed +system.cpu0.kern.callpal::total 192229 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1907 -system.cpu0.kern.mode_good::user 1738 -system.cpu0.kern.mode_good::idle 169 +system.cpu0.kern.mode_good::user 1737 +system.cpu0.kern.mode_good::idle 170 system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391019 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29794763000 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2592746500 0.14% 1.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810308934500 98.24% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4175 # number of times the context was actually changed +system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.390979 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29759204500 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2578304000 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1810355445500 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -959,59 +927,59 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 110459996 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 784722 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 784503 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 3749 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 3749 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 371354 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution +system.toL2Bus.throughput 110509038 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 784786 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 784740 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 3779 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 3779 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 372271 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 13 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 150558 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 133662 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 204 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 847542 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1368014 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 2215556 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27120896 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55237129 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 82358025 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 203533320 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 11008 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2134008000 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 150355 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 133459 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 31 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 846229 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370023 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 2216252 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27078976 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55338308 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 82417284 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 203623496 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 10816 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2138093500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1908780020 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1905810483 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2230620167 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2232783145 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1469142 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 2975 # Transaction distribution -system.iobus.trans_dist::ReadResp 2975 # Transaction distribution -system.iobus.trans_dist::WriteReq 20645 # Transaction distribution -system.iobus.trans_dist::WriteResp 20645 # Transaction distribution +system.iobus.throughput 1469145 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 3004 # Transaction distribution +system.iobus.trans_dist::ReadResp 3004 # Transaction distribution +system.iobus.trans_dist::WriteReq 20675 # Transaction distribution +system.iobus.trans_dist::WriteResp 20675 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2330 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 136 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8370 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8488 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2374 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 13310 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 13428 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 33930 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 33930 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 47240 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 47358 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9320 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 544 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4185 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4244 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1548 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 15689 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 15748 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1082792 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1082792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1098481 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1098540 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 2707184 # Total data (bytes) system.iobus.reqLayer0.occupancy 2199000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) @@ -1019,398 +987,398 @@ system.iobus.reqLayer1.occupancy 102000 # La system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6237000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6326000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 1789000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 153613694 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 154493741 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9561000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9649000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17409500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17628000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 951005 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.190319 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43429541 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 951516 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 45.642471 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10399272250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 251.342896 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 99.592582 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 160.254842 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.490904 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.194517 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.312998 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998419 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 951123 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.189701 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 44044625 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 951634 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 46.283156 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10406456250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 252.370031 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 94.623296 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 164.196374 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.492910 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.184811 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.320696 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998417 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 45349405 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 45349405 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 33358489 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7831408 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2239644 # 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average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12225.579648 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12205.383827 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1391788 # number of replacements +system.cpu0.dcache.tags.replacements 1392490 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13285278 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1392300 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.541965 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 13295207 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393002 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.544284 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 249.411553 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 131.959093 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 130.627166 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.487132 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.257733 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.255131 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 249.168016 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 132.479618 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 130.350177 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.486656 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.258749 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.254590 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63261634 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63261634 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4082373 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1085171 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2396693 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7564237 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3213874 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 832734 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1291048 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5337656 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117262 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19372 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47406 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184040 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126440 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21396 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 51446 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7296247 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1917905 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3687741 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12901893 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7296247 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1917905 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3687741 # number of overall hits -system.cpu0.dcache.overall_hits::total 12901893 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 722135 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 98671 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 532767 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1353573 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 169009 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 44296 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 596502 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 809807 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9742 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2152 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6843 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18737 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 63289936 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63289936 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4090319 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1090270 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2387407 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7567996 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3221527 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 836656 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1285562 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5343745 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117421 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19406 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47293 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184120 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126604 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21447 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 51238 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199289 # 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number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 44567 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 593518 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 807386 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9749 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2170 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6797 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 18716 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu2.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 891144 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 142967 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1129269 # 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number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 102729249 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 131218249 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 891176 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 143915 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1125275 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2160366 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 891176 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 143915 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1125275 # number of overall misses +system.cpu0.dcache.overall_misses::total 2160366 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2256659500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9313664253 # 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miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069372 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.234434 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.143600 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108843 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069372 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.234434 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.143600 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22860.582137 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17546.677570 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8572.841856 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37450.723745 # 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number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 310560000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 607082000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 364175500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 426698000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 790873500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 660697500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 737258000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1397955500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083348 # 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number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 431165001 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 797542001 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 664630500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 746482001 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1411112501 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083513 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086327 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039385 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050574 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047182 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021659 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100575 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099593 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037257 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000020 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069372 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070813 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032132 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069372 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070813 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032132 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20779.393135 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16909.565995 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17998.529801 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35258.527655 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29455.363865 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31381.923082 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11237.918216 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12112.592251 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11864.005547 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069496 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070997 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032150 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069496 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070997 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032150 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20639.031485 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16811.977655 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17894.118381 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34679.443086 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29666.299104 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31343.317591 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11179.608295 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12106.553369 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11840.380177 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25265.517504 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20187.819839 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21687.476300 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25265.517504 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20187.819839 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21687.476300 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24987.007887 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20157.361413 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21591.728791 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24987.007887 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20157.361413 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21591.728791 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1425,22 +1393,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1203332 # DTB read hits -system.cpu1.dtb.read_misses 1366 # DTB read misses +system.cpu1.dtb.read_hits 1209129 # DTB read hits +system.cpu1.dtb.read_misses 1367 # DTB read misses system.cpu1.dtb.read_acv 34 # DTB read access violations -system.cpu1.dtb.read_accesses 142940 # DTB read accesses -system.cpu1.dtb.write_hits 898898 # DTB write hits -system.cpu1.dtb.write_misses 183 # DTB write misses -system.cpu1.dtb.write_acv 22 # DTB write access violations -system.cpu1.dtb.write_accesses 58529 # DTB write accesses -system.cpu1.dtb.data_hits 2102230 # DTB hits -system.cpu1.dtb.data_misses 1549 # DTB misses -system.cpu1.dtb.data_acv 56 # DTB access violations -system.cpu1.dtb.data_accesses 201469 # DTB accesses -system.cpu1.itb.fetch_hits 859402 # ITB hits -system.cpu1.itb.fetch_misses 692 # ITB misses +system.cpu1.dtb.read_accesses 142945 # DTB read accesses +system.cpu1.dtb.write_hits 903134 # DTB write hits +system.cpu1.dtb.write_misses 185 # DTB write misses +system.cpu1.dtb.write_acv 23 # DTB write access violations +system.cpu1.dtb.write_accesses 58533 # DTB write accesses +system.cpu1.dtb.data_hits 2112263 # DTB hits +system.cpu1.dtb.data_misses 1552 # DTB misses +system.cpu1.dtb.data_acv 57 # DTB access violations +system.cpu1.dtb.data_accesses 201478 # DTB accesses +system.cpu1.itb.fetch_hits 860790 # ITB hits +system.cpu1.itb.fetch_misses 693 # ITB misses system.cpu1.itb.fetch_acv 30 # ITB acv -system.cpu1.itb.fetch_accesses 860094 # ITB accesses +system.cpu1.itb.fetch_accesses 861483 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1453,29 +1421,29 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953617285 # number of cpu cycles simulated +system.cpu1.numCycles 953612854 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7956345 # Number of instructions committed -system.cpu1.committedOps 7956345 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7412681 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 44901 # Number of float alu accesses -system.cpu1.num_func_calls 213028 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1020887 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7412681 # number of integer instructions -system.cpu1.num_fp_insts 44901 # number of float instructions -system.cpu1.num_int_register_reads 10388601 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5388855 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24208 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24605 # number of times the floating registers were written -system.cpu1.num_mem_refs 2109439 # number of memory refs -system.cpu1.num_load_insts 1208206 # Number of load instructions -system.cpu1.num_store_insts 901233 # Number of store instructions -system.cpu1.num_idle_cycles 922131579.439540 # Number of idle cycles -system.cpu1.num_busy_cycles 31485705.560460 # Number of busy cycles -system.cpu1.not_idle_fraction 0.033017 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.966983 # Percentage of idle cycles -system.cpu1.Branches 1300702 # Number of branches fetched +system.cpu1.committedInsts 8186270 # Number of instructions committed +system.cpu1.committedOps 8186270 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7639715 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45422 # Number of float alu accesses +system.cpu1.num_func_calls 213980 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1089106 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7639715 # number of integer instructions +system.cpu1.num_fp_insts 45422 # number of float instructions +system.cpu1.num_int_register_reads 10757840 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5542682 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24502 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24833 # number of times the floating registers were written +system.cpu1.num_mem_refs 2119540 # number of memory refs +system.cpu1.num_load_insts 1214044 # Number of load instructions +system.cpu1.num_store_insts 905496 # Number of store instructions +system.cpu1.num_idle_cycles 923510145.865154 # Number of idle cycles +system.cpu1.num_busy_cycles 30102708.134846 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031567 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968433 # Percentage of idle cycles +system.cpu1.Branches 1370105 # Number of branches fetched system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1493,35 +1461,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 9131296 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8453261 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 124867 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7606484 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6524985 # Number of BTB hits +system.cpu2.branchPred.lookups 9158053 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8481927 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 123683 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7604727 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6560922 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 85.781880 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 282035 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 13344 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 86.274261 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 280761 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 13305 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3186348 # DTB read hits -system.cpu2.dtb.read_misses 11810 # DTB read misses -system.cpu2.dtb.read_acv 124 # DTB read access violations -system.cpu2.dtb.read_accesses 217745 # DTB read accesses -system.cpu2.dtb.write_hits 2009701 # DTB write hits -system.cpu2.dtb.write_misses 2606 # DTB write misses -system.cpu2.dtb.write_acv 109 # DTB write access violations -system.cpu2.dtb.write_accesses 82375 # DTB write accesses -system.cpu2.dtb.data_hits 5196049 # DTB hits -system.cpu2.dtb.data_misses 14416 # DTB misses -system.cpu2.dtb.data_acv 233 # DTB access violations -system.cpu2.dtb.data_accesses 300120 # DTB accesses -system.cpu2.itb.fetch_hits 370442 # ITB hits -system.cpu2.itb.fetch_misses 5628 # ITB misses -system.cpu2.itb.fetch_acv 253 # ITB acv -system.cpu2.itb.fetch_accesses 376070 # ITB accesses +system.cpu2.dtb.read_hits 3175061 # DTB read hits +system.cpu2.dtb.read_misses 11717 # DTB read misses +system.cpu2.dtb.read_acv 122 # DTB read access violations +system.cpu2.dtb.read_accesses 217137 # DTB read accesses +system.cpu2.dtb.write_hits 2001578 # DTB write hits +system.cpu2.dtb.write_misses 2618 # DTB write misses +system.cpu2.dtb.write_acv 106 # DTB write access violations +system.cpu2.dtb.write_accesses 82142 # DTB write accesses +system.cpu2.dtb.data_hits 5176639 # DTB hits +system.cpu2.dtb.data_misses 14335 # DTB misses +system.cpu2.dtb.data_acv 228 # DTB access violations +system.cpu2.dtb.data_accesses 299279 # DTB accesses +system.cpu2.itb.fetch_hits 368924 # ITB hits +system.cpu2.itb.fetch_misses 5740 # ITB misses +system.cpu2.itb.fetch_acv 243 # ITB acv +system.cpu2.itb.fetch_accesses 374664 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1534,270 +1502,270 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 31313073 # number of cpu cycles simulated +system.cpu2.numCycles 31279022 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8328585 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 37006400 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 9131296 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6807020 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8851345 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 606644 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9641968 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 10046 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1931 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 63228 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 87070 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 340 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2553376 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 86779 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 27379324 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.351618 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.293970 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8287542 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 37055340 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 9158053 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6841683 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8878582 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 603474 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9658598 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 9919 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1948 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 63764 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 87901 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 585 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2543899 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 85179 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 27382085 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.353269 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.291783 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18527979 67.67% 67.67% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 269262 0.98% 68.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 428968 1.57% 70.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 5000608 18.26% 88.49% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 759354 2.77% 91.26% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 165275 0.60% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 190932 0.70% 92.56% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 427573 1.56% 94.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1609373 5.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18503503 67.58% 67.58% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 267960 0.98% 68.55% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 427466 1.56% 70.11% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 5038940 18.40% 88.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 758703 2.77% 91.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 165190 0.60% 91.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 190909 0.70% 92.59% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 425900 1.56% 94.14% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1603514 5.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 27379324 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.291613 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.181819 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8475609 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9724872 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8241247 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 308907 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 382752 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 165606 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12712 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36612854 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 39749 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 382752 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 8834671 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2773280 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5760129 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 8113478 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1269087 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35472103 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2436 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 230799 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 444723 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 23769376 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 44394567 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 44338159 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 52651 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 21967508 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1801868 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 500326 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 58967 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3713170 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3346051 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2099971 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 366369 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 258671 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32979578 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 619087 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 32529976 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 34753 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2147129 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1082645 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 436861 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 27379324 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.188122 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.575744 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 27382085 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.292786 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.184671 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8439244 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9737555 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 8269995 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 308345 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 381075 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 165536 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12831 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36664015 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 39751 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 381075 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 8796739 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2804819 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5741072 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 8142606 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1269911 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35531036 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2469 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 231647 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 446543 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 23808302 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 44475961 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 44419812 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 52401 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 22020270 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1788032 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 498319 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 58753 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3705896 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3335757 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2091143 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 366529 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 285241 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 33051386 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 616780 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32598005 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 35098 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2143170 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1082478 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 435207 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 27382085 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.190487 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.575531 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15104518 55.17% 55.17% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3059496 11.17% 66.34% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1557193 5.69% 72.03% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5827645 21.28% 93.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 904106 3.30% 96.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 480512 1.76% 98.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 285612 1.04% 99.41% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 141433 0.52% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18809 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15085778 55.09% 55.09% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3054879 11.16% 66.25% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1548873 5.66% 71.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5868849 21.43% 93.34% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 901287 3.29% 96.63% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 476925 1.74% 98.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 288026 1.05% 99.42% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 138840 0.51% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18628 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 27379324 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 27382085 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 32920 13.41% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 112185 45.69% 59.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 100449 40.91% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 33655 13.83% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 111431 45.78% 59.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 98340 40.40% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 26864472 82.58% 82.59% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20045 0.06% 82.65% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.65% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8419 0.03% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3313279 10.19% 92.87% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2032055 6.25% 99.11% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 288046 0.89% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 26953534 82.68% 82.69% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 19910 0.06% 82.75% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.75% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8410 0.03% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3301438 10.13% 92.91% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2024047 6.21% 99.12% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 287006 0.88% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 32529976 # Type of FU issued -system.cpu2.iq.rate 1.038862 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 245554 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007549 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 92485827 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 35635212 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 32132884 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 233756 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 114401 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 110529 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 32651329 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 121761 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 186414 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32598005 # Type of FU issued +system.cpu2.iq.rate 1.042168 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 243426 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007468 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 92623863 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 35700994 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 32205742 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 232756 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 114085 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 110215 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32717888 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 121103 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 185687 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 413956 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1112 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 3936 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 157547 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 410803 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1083 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 3827 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 157383 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4151 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 27254 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4176 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 27619 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 382752 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2003866 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 204399 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 34866454 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 220221 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3346051 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2099971 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 549960 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 142228 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 1969 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 3936 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 63951 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 128015 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 191966 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 32372492 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3206448 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 157484 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 381075 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2023183 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 204607 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 34934170 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 220301 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3335757 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2091143 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 547666 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 141469 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2123 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 3827 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 63090 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 127121 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 190211 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 32442083 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3195032 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 155922 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1267789 # number of nop insts executed -system.cpu2.iew.exec_refs 5223192 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7564928 # Number of branches executed -system.cpu2.iew.exec_stores 2016744 # Number of stores executed -system.cpu2.iew.exec_rate 1.033833 # Inst execution rate -system.cpu2.iew.wb_sent 32276755 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 32243413 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 18781769 # num instructions producing a value -system.cpu2.iew.wb_consumers 21976070 # num instructions consuming a value +system.cpu2.iew.exec_nop 1266004 # number of nop insts executed +system.cpu2.iew.exec_refs 5203645 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7597485 # Number of branches executed +system.cpu2.iew.exec_stores 2008613 # Number of stores executed +system.cpu2.iew.exec_rate 1.037183 # Inst execution rate +system.cpu2.iew.wb_sent 32348485 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 32315957 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18839799 # num instructions producing a value +system.cpu2.iew.wb_consumers 22025525 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.029711 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.854646 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.033151 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.855362 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2322975 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 182226 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 177336 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26996572 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.203754 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.846865 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2315429 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 181573 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 175784 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 27001010 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.206363 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.845727 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16110852 59.68% 59.68% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2323792 8.61% 68.29% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1227035 4.55% 72.83% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5572191 20.64% 93.47% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 501625 1.86% 95.33% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 185779 0.69% 96.02% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 177561 0.66% 96.67% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 179863 0.67% 97.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 717874 2.66% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16087817 59.58% 59.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2320535 8.59% 68.18% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1221811 4.53% 72.70% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5612171 20.79% 93.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 500601 1.85% 95.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 184383 0.68% 96.02% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 174610 0.65% 96.67% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 192284 0.71% 97.38% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 706798 2.62% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26996572 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 32497229 # Number of instructions committed -system.cpu2.commit.committedOps 32497229 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 27001010 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32573021 # Number of instructions committed +system.cpu2.commit.committedOps 32573021 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4874519 # Number of memory references committed -system.cpu2.commit.loads 2932095 # Number of loads committed -system.cpu2.commit.membars 63814 # Number of memory barriers committed -system.cpu2.commit.branches 7417113 # Number of branches committed -system.cpu2.commit.fp_insts 109328 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 31054650 # Number of committed integer instructions. -system.cpu2.commit.function_calls 228340 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 717874 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4858714 # Number of memory references committed +system.cpu2.commit.loads 2924954 # Number of loads committed +system.cpu2.commit.membars 63567 # Number of memory barriers committed +system.cpu2.commit.branches 7451291 # Number of branches committed +system.cpu2.commit.fp_insts 109021 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 31134232 # Number of committed integer instructions. +system.cpu2.commit.function_calls 227850 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 706798 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 61024976 # The number of ROB reads -system.cpu2.rob.rob_writes 70022633 # The number of ROB writes -system.cpu2.timesIdled 244840 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3933749 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1746460059 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 31334430 # Number of Instructions Simulated -system.cpu2.committedOps 31334430 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 31334430 # Number of Instructions Simulated -system.cpu2.cpi 0.999318 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.999318 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.000682 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.000682 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 42582766 # number of integer regfile reads -system.cpu2.int_regfile_writes 22654603 # number of integer regfile writes -system.cpu2.fp_regfile_reads 67639 # number of floating regfile reads -system.cpu2.fp_regfile_writes 67817 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5361637 # number of misc regfile reads -system.cpu2.misc_regfile_writes 256988 # number of misc regfile writes +system.cpu2.rob.rob_reads 61108801 # The number of ROB reads +system.cpu2.rob.rob_writes 70157468 # The number of ROB writes +system.cpu2.timesIdled 244589 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3896937 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1746488839 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 31413101 # Number of Instructions Simulated +system.cpu2.committedOps 31413101 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 31413101 # Number of Instructions Simulated +system.cpu2.cpi 0.995732 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.995732 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.004287 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.004287 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42678646 # number of integer regfile reads +system.cpu2.int_regfile_writes 22701958 # number of integer regfile writes +system.cpu2.fp_regfile_reads 67399 # number of floating regfile reads +system.cpu2.fp_regfile_writes 67744 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5400058 # number of misc regfile reads +system.cpu2.misc_regfile_writes 256035 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index a0de7ff7f..5f9799ffe 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.526127 # Number of seconds simulated -sim_ticks 2526126762000 # Number of ticks simulated -final_tick 2526126762000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.526170 # Number of seconds simulated +sim_ticks 2526169857500 # Number of ticks simulated +final_tick 2526169857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50904 # Simulator instruction rate (inst/s) -host_op_rate 65499 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2132173780 # Simulator tick rate (ticks/s) -host_mem_usage 425424 # Number of bytes of host memory used -host_seconds 1184.77 # Real time elapsed on the host -sim_insts 60309150 # Number of instructions simulated -sim_ops 77600646 # Number of ops (including micro ops) simulated +host_inst_rate 46796 # Simulator instruction rate (inst/s) +host_op_rate 60213 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1960134913 # Simulator tick rate (ticks/s) +host_mem_usage 468616 # Number of bytes of host memory used +host_seconds 1288.77 # Real time elapsed on the host +sim_insts 60309637 # Number of instructions simulated +sim_ops 77601213 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093912 # Number of bytes read from this memory -system.physmem.bytes_read::total 129432344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 797632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9095320 # Number of bytes read from this memory +system.physmem.bytes_read::total 129433624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785024 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799624 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801096 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 43 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12467 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142128 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096848 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12463 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142150 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096868 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59141 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47320533 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1089 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813159 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47319725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1140 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3599943 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51237470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1497768 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1193951 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2691719 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1497768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47320533 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1089 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3600439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51237103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315748 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315748 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1193931 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2692256 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47319725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1140 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4793894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53929189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096848 # Number of read requests accepted -system.physmem.writeReqs 813136 # Number of write requests accepted -system.physmem.readBursts 15096848 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813136 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 963809856 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2388416 # Total number of bytes read from write queue -system.physmem.bytesWritten 6900096 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 129432344 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6799624 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 37319 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 705316 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4693 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943581 # Per bank write bursts -system.physmem.perBankRdBursts::1 943177 # Per bank write bursts -system.physmem.perBankRdBursts::2 939217 # Per bank write bursts -system.physmem.perBankRdBursts::3 939246 # Per bank write bursts -system.physmem.perBankRdBursts::4 943119 # Per bank write bursts -system.physmem.perBankRdBursts::5 943143 # Per bank write bursts -system.physmem.perBankRdBursts::6 939192 # Per bank write bursts -system.physmem.perBankRdBursts::7 938854 # Per bank write bursts -system.physmem.perBankRdBursts::8 943994 # Per bank write bursts -system.physmem.perBankRdBursts::9 943547 # Per bank write bursts -system.physmem.perBankRdBursts::10 939009 # Per bank write bursts -system.physmem.perBankRdBursts::11 937977 # Per bank write bursts -system.physmem.perBankRdBursts::12 943925 # Per bank write bursts -system.physmem.perBankRdBursts::13 943586 # Per bank write bursts -system.physmem.perBankRdBursts::14 939160 # Per bank write bursts -system.physmem.perBankRdBursts::15 938802 # Per bank write bursts -system.physmem.perBankWrBursts::0 6706 # Per bank write bursts -system.physmem.perBankWrBursts::1 6463 # Per bank write bursts -system.physmem.perBankWrBursts::2 6599 # Per bank write bursts -system.physmem.perBankWrBursts::3 6631 # Per bank write bursts -system.physmem.perBankWrBursts::4 6542 # Per bank write bursts -system.physmem.perBankWrBursts::5 6795 # Per bank write bursts -system.physmem.perBankWrBursts::6 6787 # Per bank write bursts -system.physmem.perBankWrBursts::7 6728 # Per bank write bursts -system.physmem.perBankWrBursts::8 7129 # Per bank write bursts -system.physmem.perBankWrBursts::9 6879 # Per bank write bursts -system.physmem.perBankWrBursts::10 6534 # Per bank write bursts -system.physmem.perBankWrBursts::11 6185 # Per bank write bursts -system.physmem.perBankWrBursts::12 7139 # Per bank write bursts -system.physmem.perBankWrBursts::13 6761 # Per bank write bursts -system.physmem.perBankWrBursts::14 7032 # Per bank write bursts -system.physmem.perBankWrBursts::15 6904 # Per bank write bursts +system.physmem.bw_total::cpu.inst 315748 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4794370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53929359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096868 # Number of read requests accepted +system.physmem.writeReqs 813159 # Number of write requests accepted +system.physmem.readBursts 15096868 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813159 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 960809152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5390400 # Total number of bytes read from write queue +system.physmem.bytesWritten 6824768 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129433624 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6801096 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 84225 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706499 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943297 # Per bank write bursts +system.physmem.perBankRdBursts::1 937033 # Per bank write bursts +system.physmem.perBankRdBursts::2 936962 # Per bank write bursts +system.physmem.perBankRdBursts::3 936535 # Per bank write bursts +system.physmem.perBankRdBursts::4 942693 # Per bank write bursts +system.physmem.perBankRdBursts::5 936569 # Per bank write bursts +system.physmem.perBankRdBursts::6 936319 # Per bank write bursts +system.physmem.perBankRdBursts::7 936043 # Per bank write bursts +system.physmem.perBankRdBursts::8 943596 # Per bank write bursts +system.physmem.perBankRdBursts::9 936992 # Per bank write bursts +system.physmem.perBankRdBursts::10 936414 # Per bank write bursts +system.physmem.perBankRdBursts::11 935912 # Per bank write bursts +system.physmem.perBankRdBursts::12 943556 # Per bank write bursts +system.physmem.perBankRdBursts::13 937007 # Per bank write bursts +system.physmem.perBankRdBursts::14 937039 # Per bank write bursts +system.physmem.perBankRdBursts::15 936676 # Per bank write bursts +system.physmem.perBankWrBursts::0 6606 # Per bank write bursts +system.physmem.perBankWrBursts::1 6375 # Per bank write bursts +system.physmem.perBankWrBursts::2 6521 # Per bank write bursts +system.physmem.perBankWrBursts::3 6552 # Per bank write bursts +system.physmem.perBankWrBursts::4 6461 # Per bank write bursts +system.physmem.perBankWrBursts::5 6711 # Per bank write bursts +system.physmem.perBankWrBursts::6 6720 # Per bank write bursts +system.physmem.perBankWrBursts::7 6668 # Per bank write bursts +system.physmem.perBankWrBursts::8 7045 # Per bank write bursts +system.physmem.perBankWrBursts::9 6826 # Per bank write bursts +system.physmem.perBankWrBursts::10 6497 # Per bank write bursts +system.physmem.perBankWrBursts::11 6136 # Per bank write bursts +system.physmem.perBankWrBursts::12 7072 # Per bank write bursts +system.physmem.perBankWrBursts::13 6672 # Per bank write bursts +system.physmem.perBankWrBursts::14 6956 # Per bank write bursts +system.physmem.perBankWrBursts::15 6819 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2526125654500 # Total gap between requests +system.physmem.totGap 2526168741500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 38 # Read request sizes (log2) system.physmem.readPktSize::3 14942208 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154602 # Read request sizes (log2) +system.physmem.readPktSize::6 154622 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59118 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1175583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1121241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1077080 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3628602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2607512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2594359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2599949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 53287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 57711 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 21124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20900 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20768 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 91 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59141 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1044851 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 985737 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 938636 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 947948 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 933228 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 933834 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2717841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2709185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3589675 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 37568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 33871 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 34960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 32201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 30053 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 21726 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 21191 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -144,619 +144,147 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 85983 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11289.547748 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1006.032615 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16787.302098 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23431 27.25% 27.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14045 16.33% 43.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2670 3.11% 46.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2200 2.56% 49.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1296 1.51% 50.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1149 1.34% 52.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 926 1.08% 53.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 910 1.06% 54.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 583 0.68% 54.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 573 0.67% 55.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 527 0.61% 56.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 540 0.63% 56.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 283 0.33% 57.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 315 0.37% 57.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 148 0.17% 57.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 512 0.60% 58.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 103 0.12% 58.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 143 0.17% 58.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 77 0.09% 58.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 250 0.29% 58.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 57 0.07% 59.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 507 0.59% 59.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 36 0.04% 59.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 193 0.22% 59.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 17 0.02% 59.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 103 0.12% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 71 0.08% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 17 0.02% 60.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 58 0.07% 60.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 16 0.02% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 468 0.54% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 10 0.01% 60.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 32 0.04% 60.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 249 0.29% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 8 0.01% 61.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 28 0.03% 61.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 7 0.01% 61.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 30 0.03% 61.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 8 0.01% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 18 0.02% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 6 0.01% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 116 0.13% 61.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 10 0.01% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 18 0.02% 61.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 4 0.00% 61.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 420 0.49% 61.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 24 0.03% 61.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 6 0.01% 61.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 25 0.03% 61.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 6 0.01% 61.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 21 0.02% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 6 0.01% 62.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 157 0.18% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 5 0.01% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 17 0.02% 62.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 9 0.01% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 20 0.02% 62.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 11 0.01% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 15 0.02% 62.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 13 0.02% 62.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 363 0.42% 62.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 9 0.01% 62.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 13 0.02% 62.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 7 0.01% 62.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 108 0.13% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 18 0.02% 62.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 14 0.02% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 12 0.01% 62.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 161 0.19% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 8 0.01% 63.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 15 0.02% 63.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 23 0.03% 63.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 6 0.01% 63.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 14 0.02% 63.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 4 0.00% 63.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 356 0.41% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 11 0.01% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 11 0.01% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 163 0.19% 63.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 2 0.00% 63.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 16 0.02% 63.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 2 0.00% 63.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 50 0.06% 63.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 6 0.01% 63.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 13 0.02% 63.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 4 0.00% 63.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 197 0.23% 64.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 3 0.00% 64.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 9 0.01% 64.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 7 0.01% 64.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 223 0.26% 64.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 4 0.00% 64.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 13 0.02% 64.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 5 0.01% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 140 0.16% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 2 0.00% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 8 0.01% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 2 0.00% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 88 0.10% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 2 0.00% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 3 0.00% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 158 0.18% 64.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 6 0.01% 64.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 14 0.02% 64.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 1 0.00% 64.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 345 0.40% 65.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 1 0.00% 65.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 5 0.01% 65.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 8 0.01% 65.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 13 0.02% 65.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 4 0.00% 65.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 18 0.02% 65.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 6 0.01% 65.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 141 0.16% 65.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 2 0.00% 65.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 6 0.01% 65.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 41 0.05% 65.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 2 0.00% 65.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 10 0.01% 65.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 399 0.46% 66.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 36 0.04% 66.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8583 2 0.00% 66.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 130 0.15% 66.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8903 2 0.00% 66.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 5 0.01% 66.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 1 0.00% 66.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 341 0.40% 66.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9351 3 0.00% 66.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 145 0.17% 66.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9543 1 0.00% 66.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9607 2 0.00% 66.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 78 0.09% 67.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9799 2 0.00% 67.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9863 3 0.00% 67.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 133 0.15% 67.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10055 2 0.00% 67.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 3 0.00% 67.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 212 0.25% 67.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10375 2 0.00% 67.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 150 0.17% 67.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10695 1 0.00% 67.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 41 0.05% 67.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10887 1 0.00% 67.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10951 2 0.00% 67.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 153 0.18% 67.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 4 0.00% 67.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 349 0.41% 68.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 8 0.01% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11655 3 0.00% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 141 0.16% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11911 3 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 94 0.11% 68.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12103 2 0.00% 68.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12167 4 0.00% 68.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 334 0.39% 68.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12359 1 0.00% 68.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 13 0.02% 68.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12679 3 0.00% 68.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12743 1 0.00% 68.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 141 0.16% 69.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 6 0.01% 69.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13127 1 0.00% 69.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 2 0.00% 69.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 399 0.46% 69.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13376-13383 1 0.00% 69.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13447 1 0.00% 69.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 94 0.11% 69.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13767 2 0.00% 69.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 2 0.00% 69.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13959 3 0.00% 69.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14023 1 0.00% 69.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 214 0.25% 69.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14151 2 0.00% 69.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 4 0.00% 69.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14279 1 0.00% 69.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 420 0.49% 70.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 5 0.01% 70.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14727 1 0.00% 70.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 22 0.03% 70.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 141 0.16% 70.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15175 1 0.00% 70.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 1 0.00% 70.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 335 0.39% 71.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15495 1 0.00% 71.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 80 0.09% 71.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15815 2 0.00% 71.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 5 0.01% 71.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15943 2 0.00% 71.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16007 2 0.00% 71.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16071 1 0.00% 71.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 143 0.17% 71.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16263 6 0.01% 71.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 673 0.78% 72.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16519 1 0.00% 72.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 144 0.17% 72.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 7 0.01% 72.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16967 2 0.00% 72.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 81 0.09% 72.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17287 2 0.00% 72.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 336 0.39% 72.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17543 2 0.00% 72.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 135 0.16% 72.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17735 1 0.00% 72.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17792-17799 4 0.00% 72.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 25 0.03% 72.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18048-18055 1 0.00% 72.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18112-18119 1 0.00% 72.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 6 0.01% 72.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 1 0.00% 72.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 2 0.00% 72.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 419 0.49% 73.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18560-18567 2 0.00% 73.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 214 0.25% 73.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18752-18759 1 0.00% 73.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 4 0.00% 73.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 97 0.11% 73.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19264-19271 2 0.00% 73.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 2 0.00% 73.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 391 0.45% 74.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19591 1 0.00% 74.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 10 0.01% 74.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19840-19847 3 0.00% 74.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19904-19911 1 0.00% 74.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 139 0.16% 74.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20032-20039 1 0.00% 74.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20160-20167 2 0.00% 74.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 13 0.02% 74.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 4 0.00% 74.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 331 0.38% 74.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20608-20615 1 0.00% 74.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20672-20679 1 0.00% 74.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 94 0.11% 75.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20800-20807 1 0.00% 75.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20864-20871 1 0.00% 75.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20928-20935 2 0.00% 75.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 142 0.17% 75.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21120-21127 2 0.00% 75.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 13 0.02% 75.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 2 0.00% 75.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 343 0.40% 75.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21632-21639 3 0.00% 75.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21696-21703 1 0.00% 75.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 150 0.17% 75.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 1 0.00% 75.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21952-21959 1 0.00% 75.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 38 0.04% 75.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22080-22087 1 0.00% 75.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22144-22151 3 0.00% 75.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 148 0.17% 76.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 2 0.00% 76.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22464-22471 1 0.00% 76.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 208 0.24% 76.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22656-22663 1 0.00% 76.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22720-22727 2 0.00% 76.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 129 0.15% 76.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 76 0.09% 76.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23104-23111 1 0.00% 76.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23168-23175 2 0.00% 76.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 148 0.17% 76.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23424-23431 1 0.00% 76.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23488-23495 1 0.00% 76.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 338 0.39% 77.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 10 0.01% 77.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23936-23943 2 0.00% 77.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 128 0.15% 77.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24128-24135 1 0.00% 77.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24256-24263 2 0.00% 77.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 34 0.04% 77.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24448-24455 4 0.00% 77.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24512-24519 1 0.00% 77.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 281 0.33% 77.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24640-24647 2 0.00% 77.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24704-24711 3 0.00% 77.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24768-24775 1 0.00% 77.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 36 0.04% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24960-24967 1 0.00% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 132 0.15% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25152-25159 1 0.00% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25216-25223 1 0.00% 77.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 9 0.01% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 2 0.00% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25536-25543 1 0.00% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 331 0.38% 78.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25792-25799 1 0.00% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 146 0.17% 78.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25920-25927 1 0.00% 78.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25984-25991 1 0.00% 78.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 78 0.09% 78.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26240-26247 2 0.00% 78.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26304-26311 1 0.00% 78.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 128 0.15% 78.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 6 0.01% 78.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 207 0.24% 78.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26688-26695 1 0.00% 78.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26752-26759 3 0.00% 78.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26816-26823 1 0.00% 78.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 146 0.17% 79.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26944-26951 3 0.00% 79.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27008-27015 1 0.00% 79.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 38 0.04% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27264-27271 1 0.00% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 151 0.18% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27463 1 0.00% 79.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27584-27591 2 0.00% 79.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 337 0.39% 79.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27712-27719 1 0.00% 79.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27840-27847 2 0.00% 79.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 13 0.02% 79.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27968-27975 1 0.00% 79.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 141 0.16% 79.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28224-28231 1 0.00% 79.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28288-28295 1 0.00% 79.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 97 0.11% 79.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 5 0.01% 79.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28608-28615 4 0.00% 79.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 328 0.38% 80.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28800-28807 1 0.00% 80.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28864-28871 1 0.00% 80.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 12 0.01% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29056-29063 2 0.00% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 141 0.16% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 7 0.01% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29575 3 0.00% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 399 0.46% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 90 0.10% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30144-30151 2 0.00% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 5 0.01% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30400-30407 1 0.00% 81.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 214 0.25% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30528-30535 1 0.00% 81.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 3 0.00% 81.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 415 0.48% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30848-30855 2 0.00% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 5 0.01% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31040-31047 1 0.00% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31111 1 0.00% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31168-31175 3 0.00% 81.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 21 0.02% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31367 2 0.00% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31424-31431 1 0.00% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 138 0.16% 82.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 3 0.00% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 338 0.39% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31872-31879 2 0.00% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31936-31943 1 0.00% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 78 0.09% 82.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32192-32199 1 0.00% 82.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 9 0.01% 82.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32384-32391 1 0.00% 82.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32448-32455 2 0.00% 82.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 145 0.17% 82.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32576-32583 1 0.00% 82.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32640-32647 1 0.00% 82.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 671 0.78% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32960-32967 1 0.00% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 141 0.16% 83.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 7 0.01% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33344-33351 1 0.00% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 4 0.00% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 85 0.10% 83.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33607 2 0.00% 83.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33671 1 0.00% 83.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33735 1 0.00% 83.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 348 0.40% 84.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 136 0.16% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 21 0.02% 84.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34432-34439 3 0.00% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34496-34503 2 0.00% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 8 0.01% 84.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34688-34695 2 0.00% 84.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 412 0.48% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 212 0.25% 85.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 5 0.01% 85.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35456-35463 3 0.00% 85.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 91 0.11% 85.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 392 0.46% 85.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35904-35911 1 0.00% 85.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35968-35975 2 0.00% 85.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 8 0.01% 85.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 140 0.16% 85.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36480-36487 4 0.00% 85.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36544-36551 1 0.00% 85.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 12 0.01% 85.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 327 0.38% 86.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36928-36935 1 0.00% 86.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 90 0.10% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37312-37319 1 0.00% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 141 0.16% 86.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37440-37447 1 0.00% 86.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37511 3 0.00% 86.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 10 0.01% 86.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37696-37703 1 0.00% 86.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37760-37767 1 0.00% 86.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 334 0.39% 86.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38080-38087 1 0.00% 86.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 149 0.17% 87.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38272-38279 1 0.00% 87.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 37 0.04% 87.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 2 0.00% 87.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 150 0.17% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38784-38791 1 0.00% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 205 0.24% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 127 0.15% 87.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 76 0.09% 87.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 2 0.00% 87.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39616-39623 1 0.00% 87.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 146 0.17% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 330 0.38% 88.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40000-40007 1 0.00% 88.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40064-40071 1 0.00% 88.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 7 0.01% 88.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40384-40391 1 0.00% 88.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 132 0.15% 88.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40576-40583 4 0.00% 88.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 37 0.04% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40896-40903 1 0.00% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 277 0.32% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41088-41095 1 0.00% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41152-41159 1 0.00% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 34 0.04% 88.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 128 0.15% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41600-41607 1 0.00% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 10 0.01% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41856-41863 1 0.00% 89.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41920-41927 1 0.00% 89.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 332 0.39% 89.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 142 0.17% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42432-42439 1 0.00% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 76 0.09% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42624-42631 2 0.00% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 131 0.15% 89.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42816-42823 1 0.00% 89.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42880-42887 2 0.00% 89.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 208 0.24% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 145 0.17% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43392-43399 1 0.00% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43456-43463 1 0.00% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 36 0.04% 90.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 2 0.00% 90.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 152 0.18% 90.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43840-43847 1 0.00% 90.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 340 0.40% 90.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44160-44167 1 0.00% 90.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 1 0.00% 90.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 8 0.01% 91.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44416-44423 2 0.00% 91.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 144 0.17% 91.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44608-44615 2 0.00% 91.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 94 0.11% 91.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 328 0.38% 91.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45191 3 0.00% 91.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 12 0.01% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45376-45383 1 0.00% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 141 0.16% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45632-45639 1 0.00% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 1 0.00% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45760-45767 1 0.00% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 11 0.01% 91.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45952-45959 1 0.00% 91.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 393 0.46% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 91 0.11% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46528-46535 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 4 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 211 0.25% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47040-47047 2 0.00% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 416 0.48% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47239 1 0.00% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 4 0.00% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47488-47495 2 0.00% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47552-47559 1 0.00% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 32 0.04% 93.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 1 0.00% 93.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47808-47815 2 0.00% 93.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 141 0.16% 93.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 335 0.39% 93.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48192-48199 1 0.00% 93.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 74 0.09% 93.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 4 0.00% 93.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 71 0.08% 93.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 140 0.16% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 4 0.00% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5017 5.83% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49280-49287 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49792-49799 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50304-50311 3 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50368-50375 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50432-50439 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50560-50567 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50695 4 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50880-50887 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51008-51015 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51136-51143 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51207 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51328-51335 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 85983 # Bytes accessed per row activation -system.physmem.totQLat 365185132750 # Total ticks spent queuing -system.physmem.totMemAccLat 457949856500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 75297645000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17467078750 # Total ticks spent accessing banks -system.physmem.avgQLat 24249.44 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1159.87 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 949853 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 1012.832967 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 998.129194 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 95.600820 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 4614 0.49% 0.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 3555 0.37% 0.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1868 0.20% 1.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1270 0.13% 1.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 998 0.11% 1.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 697 0.07% 1.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 628 0.07% 1.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 802 0.08% 1.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 935421 98.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 949853 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5541 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2709.372676 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 121858.968991 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 5537 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.04% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5541 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5541 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.245082 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.302826 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.619957 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3691 66.61% 66.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 16 0.29% 66.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 178 3.21% 70.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1008 18.19% 88.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 44 0.79% 89.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 25 0.45% 89.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 20 0.36% 89.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 16 0.29% 90.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 5 0.09% 90.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.04% 90.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.02% 90.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.02% 90.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.02% 90.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 2 0.04% 90.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 1 0.02% 90.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 143 2.58% 93.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 305 5.50% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 21 0.38% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 14 0.25% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 20 0.36% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 15 0.27% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 5 0.09% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 3 0.05% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 3 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5541 # Writes before turning the bus around for reads +system.physmem.totQLat 571195583500 # Total ticks spent queuing +system.physmem.totMemAccLat 674382869750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75063215000 # Total ticks spent in databus transfers +system.physmem.totBankLat 28124071250 # Total ticks spent accessing banks +system.physmem.avgQLat 38047.64 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1873.36 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30409.31 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.54 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44921.00 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.34 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.00 # Data bus utilization in percentage -system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads +system.physmem.busUtil 2.99 # Data bus utilization in percentage +system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.56 # Average write queue length when enqueuing -system.physmem.readRowHits 14988012 # Number of row buffer hits during reads -system.physmem.writeRowHits 93348 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.58 # Row buffer hit rate for writes -system.physmem.avgGap 158776.13 # Average gap between requests -system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 2.53 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.avgRdQLen 7.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.53 # Average write queue length when enqueuing +system.physmem.readRowHits 14041195 # Number of row buffer hits during reads +system.physmem.writeRowHits 91389 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.68 # Row buffer hit rate for writes +system.physmem.avgGap 158778.41 # Average gap between requests +system.physmem.pageHitRate 93.47 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.34 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -769,58 +297,58 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54878485 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149469 # Transaction distribution -system.membus.trans_dist::ReadResp 16149469 # Transaction distribution +system.membus.throughput 54878638 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149508 # Transaction distribution +system.membus.trans_dist::ReadResp 16149508 # Transaction distribution system.membus.trans_dist::WriteReq 763349 # Transaction distribution system.membus.trans_dist::WriteResp 763349 # Transaction distribution -system.membus.trans_dist::Writeback 59118 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4690 # Transaction distribution +system.membus.trans_dist::Writeback 59141 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4693 # Transaction distribution -system.membus.trans_dist::ReadExReq 131452 # Transaction distribution -system.membus.trans_dist::ReadExResp 131452 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution +system.membus.trans_dist::ReadExReq 131433 # Transaction distribution +system.membus.trans_dist::ReadExResp 131433 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885820 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272628 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885845 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272653 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34157044 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34157069 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694304 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092346 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16697056 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19095098 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138630010 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138630010 # Total data (bytes) +system.membus.tot_pkt_size::total 138632762 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138632762 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486866000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487078000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3686500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3653000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17361359500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17362845500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4731205438 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4737809043 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33737720957 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.membus.respLayer2.occupancy 37210156152 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48266825 # Throughput (bytes/s) +system.iobus.throughput 48266001 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16125556 # Transaction distribution system.iobus.trans_dist::ReadResp 16125556 # Transaction distribution system.iobus.trans_dist::WriteReq 8174 # Transaction distribution @@ -930,18 +458,18 @@ system.iobus.reqLayer25.occupancy 14942208000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374870000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40922322043 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) +system.iobus.respLayer1.occupancy 37245686848 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14743416 # Number of BP lookups -system.cpu.branchPred.condPredicted 11827380 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704687 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9504018 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7655579 # Number of BTB hits +system.cpu.branchPred.lookups 14755327 # Number of BP lookups +system.cpu.branchPred.condPredicted 11837490 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 706705 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9530563 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7665782 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.550973 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1397368 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72480 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.433674 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1400618 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72971 # Number of incorrect RAS predictions. system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -965,9 +493,9 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14987484 # DTB read hits -system.cpu.checker.dtb.read_misses 7307 # DTB read misses -system.cpu.checker.dtb.write_hits 11227618 # DTB write hits +system.cpu.checker.dtb.read_hits 14987589 # DTB read hits +system.cpu.checker.dtb.read_misses 7306 # DTB read misses +system.cpu.checker.dtb.write_hits 11227681 # DTB write hits system.cpu.checker.dtb.write_misses 2191 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -978,12 +506,12 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994791 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229809 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994895 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229872 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26215102 # DTB hits -system.cpu.checker.dtb.misses 9498 # DTB misses -system.cpu.checker.dtb.accesses 26224600 # DTB accesses +system.cpu.checker.dtb.hits 26215270 # DTB hits +system.cpu.checker.dtb.misses 9497 # DTB misses +system.cpu.checker.dtb.accesses 26224767 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1005,7 +533,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.inst_hits 61483125 # ITB inst hits +system.cpu.checker.itb.inst_hits 61483612 # ITB inst hits system.cpu.checker.itb.inst_misses 4473 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -1022,11 +550,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61487598 # ITB inst accesses -system.cpu.checker.itb.hits 61483125 # DTB hits +system.cpu.checker.itb.inst_accesses 61488085 # ITB inst accesses +system.cpu.checker.itb.hits 61483612 # DTB hits system.cpu.checker.itb.misses 4473 # DTB misses -system.cpu.checker.itb.accesses 61487598 # DTB accesses -system.cpu.checker.numCycles 77886440 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61488085 # DTB accesses +system.cpu.checker.numCycles 77887007 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -1052,25 +580,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51180405 # DTB read hits -system.cpu.dtb.read_misses 65067 # DTB read misses -system.cpu.dtb.write_hits 11700451 # DTB write hits -system.cpu.dtb.write_misses 15748 # DTB write misses +system.cpu.dtb.read_hits 51187284 # DTB read hits +system.cpu.dtb.read_misses 65383 # DTB read misses +system.cpu.dtb.write_hits 11703682 # DTB write hits +system.cpu.dtb.write_misses 15916 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3477 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2401 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 399 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3484 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2464 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1377 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51245472 # DTB read accesses -system.cpu.dtb.write_accesses 11716199 # DTB write accesses +system.cpu.dtb.perms_faults 1363 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51252667 # DTB read accesses +system.cpu.dtb.write_accesses 11719598 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62880856 # DTB hits -system.cpu.dtb.misses 80815 # DTB misses -system.cpu.dtb.accesses 62961671 # DTB accesses +system.cpu.dtb.hits 62890966 # DTB hits +system.cpu.dtb.misses 81299 # DTB misses +system.cpu.dtb.accesses 62972265 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1092,8 +620,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 11521970 # ITB inst hits -system.cpu.itb.inst_misses 11115 # ITB inst misses +system.cpu.itb.inst_hits 11527099 # ITB inst hits +system.cpu.itb.inst_misses 11249 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -1102,114 +630,114 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2502 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2504 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2960 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2978 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11533085 # ITB inst accesses -system.cpu.itb.hits 11521970 # DTB hits -system.cpu.itb.misses 11115 # DTB misses -system.cpu.itb.accesses 11533085 # DTB accesses -system.cpu.numCycles 477047952 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11538348 # ITB inst accesses +system.cpu.itb.hits 11527099 # DTB hits +system.cpu.itb.misses 11249 # DTB misses +system.cpu.itb.accesses 11538348 # DTB accesses +system.cpu.numCycles 477119451 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29756603 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90277136 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14743416 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9052947 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20141800 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4650225 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 121200 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 98195863 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2631 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87675 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2688966 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11518528 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 709932 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5147 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 154198551 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.729959 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.081572 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29745347 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90343663 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14755327 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9066400 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20160515 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4659374 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 121718 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 98274067 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2638 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 88444 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2690508 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 430 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11523637 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 709778 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5230 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 154294046 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.730147 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.081756 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 134072201 86.95% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1305405 0.85% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1710070 1.11% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2294026 1.49% 90.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2104673 1.36% 91.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1102818 0.72% 92.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2555300 1.66% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 746086 0.48% 94.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8307972 5.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 134149007 86.94% 86.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1305162 0.85% 87.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1712027 1.11% 88.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2298089 1.49% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2109453 1.37% 91.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1103374 0.72% 92.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2555030 1.66% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 746204 0.48% 94.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8315700 5.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154198551 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030906 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.189241 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31769851 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 100064901 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18067338 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1262749 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3033712 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1957542 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172175 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107250920 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 570386 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3033712 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33504513 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38619180 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 55176666 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17578446 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6286034 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102244327 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 450 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 980082 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4063460 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 782 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106315700 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 473686161 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432563323 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10440 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78727135 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27588564 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1170552 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1076872 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12591466 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19711121 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13300191 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1936389 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2436828 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95079446 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983827 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122895781 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 165904 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18895197 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47144933 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501515 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154198551 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.796997 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.515893 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 154294046 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030926 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.189352 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31777956 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 100129696 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18080387 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1265250 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3040757 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1958128 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172070 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107328179 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 570705 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3040757 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33516419 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38693091 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 55142047 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17591419 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6310313 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102323009 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 472 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1000039 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4066050 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 733 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106393961 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 474042454 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432890289 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10421 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78727775 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27666185 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1171025 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1077190 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12642564 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19725934 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13308899 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1965192 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2472766 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95138203 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1987496 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122932074 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 165549 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18954995 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47273204 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 505173 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154294046 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.796739 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.515436 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 109876529 71.26% 71.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14361592 9.31% 80.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6875815 4.46% 85.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5666847 3.68% 88.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12323021 7.99% 96.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2802995 1.82% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1694666 1.10% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 469725 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127361 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 109928517 71.25% 71.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14405522 9.34% 80.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6874407 4.46% 85.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5677816 3.68% 88.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12311103 7.98% 96.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2805861 1.82% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1693952 1.10% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 468083 0.30% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128785 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154198551 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154294046 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61834 0.70% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61713 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available @@ -1237,437 +765,436 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8368136 94.62% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413820 4.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365366 94.65% 95.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 411034 4.65% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57946622 47.15% 47.17% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93414 0.08% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52506141 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12318913 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57971139 47.16% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93360 0.08% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 25 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52513425 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12323457 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122895781 # Type of FU issued -system.cpu.iq.rate 0.257617 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8843793 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071962 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409057037 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 115975062 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85458771 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23247 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12478 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10297 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131698673 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12383 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624051 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122932074 # Type of FU issued +system.cpu.iq.rate 0.257655 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8838117 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071894 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409219406 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116097301 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85490758 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23382 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10288 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131729199 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12474 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624027 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4056444 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6518 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30236 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1568197 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4071144 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6793 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30196 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1576838 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34108054 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 680529 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107946 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 680806 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3033712 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30168583 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 433803 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97285878 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 203457 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19711121 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13300191 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1411588 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113159 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3352 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30236 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 349021 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 270487 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619508 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120819447 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51867420 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2076334 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3040757 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30225758 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434257 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97346977 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205962 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19725934 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13308899 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1415361 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3429 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30196 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 351437 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 270055 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 621492 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120854906 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51874598 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2077168 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 222605 # number of nop insts executed -system.cpu.iew.exec_refs 64079545 # number of memory reference insts executed -system.cpu.iew.exec_branches 11817660 # Number of branches executed -system.cpu.iew.exec_stores 12212125 # Number of stores executed -system.cpu.iew.exec_rate 0.253265 # Inst execution rate -system.cpu.iew.wb_sent 119878750 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85469068 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47006672 # num instructions producing a value -system.cpu.iew.wb_consumers 87538881 # num instructions consuming a value +system.cpu.iew.exec_nop 221278 # number of nop insts executed +system.cpu.iew.exec_refs 64090111 # number of memory reference insts executed +system.cpu.iew.exec_branches 11821235 # Number of branches executed +system.cpu.iew.exec_stores 12215513 # Number of stores executed +system.cpu.iew.exec_rate 0.253301 # Inst execution rate +system.cpu.iew.wb_sent 119911072 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85501046 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47029089 # num instructions producing a value +system.cpu.iew.wb_consumers 87607932 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179162 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536980 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179203 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536813 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18642428 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482312 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 534972 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151164839 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.514346 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.491788 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18687715 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482323 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 537083 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151253289 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.514049 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.489960 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122735782 81.19% 81.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14630083 9.68% 90.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3890528 2.57% 93.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2132680 1.41% 94.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1607271 1.06% 95.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 973341 0.64% 96.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1599818 1.06% 97.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 715537 0.47% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2879799 1.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 122784132 81.18% 81.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14644365 9.68% 90.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3917692 2.59% 93.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2132798 1.41% 94.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1620432 1.07% 95.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 975760 0.65% 96.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1598249 1.06% 97.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 715459 0.47% 98.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2864402 1.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151164839 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60459531 # Number of instructions committed -system.cpu.commit.committedOps 77751027 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151253289 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60460018 # Number of instructions committed +system.cpu.commit.committedOps 77751594 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386671 # Number of memory references committed -system.cpu.commit.loads 15654677 # Number of loads committed -system.cpu.commit.membars 403573 # Number of memory barriers committed -system.cpu.commit.branches 10306328 # Number of branches committed +system.cpu.commit.refs 27386851 # Number of memory references committed +system.cpu.commit.loads 15654790 # Number of loads committed +system.cpu.commit.membars 403577 # Number of memory barriers committed +system.cpu.commit.branches 10306380 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69191102 # Number of committed integer instructions. -system.cpu.commit.function_calls 991248 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2879799 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69191623 # Number of committed integer instructions. +system.cpu.commit.function_calls 991253 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2864402 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242830080 # The number of ROB reads -system.cpu.rob.rob_writes 195907164 # The number of ROB writes -system.cpu.timesIdled 1776346 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322849401 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575122538 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60309150 # Number of Instructions Simulated -system.cpu.committedOps 77600646 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60309150 # Number of Instructions Simulated -system.cpu.cpi 7.910043 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.910043 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126422 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126422 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 548535748 # number of integer regfile reads -system.cpu.int_regfile_writes 87515633 # number of integer regfile writes -system.cpu.fp_regfile_reads 8349 # number of floating regfile reads -system.cpu.fp_regfile_writes 2926 # number of floating regfile writes -system.cpu.misc_regfile_reads 268179441 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173225 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58877700 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658609 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658608 # Transaction distribution +system.cpu.rob.rob_reads 242979782 # The number of ROB reads +system.cpu.rob.rob_writes 196005989 # The number of ROB writes +system.cpu.timesIdled 1777234 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322825405 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575137230 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60309637 # Number of Instructions Simulated +system.cpu.committedOps 77601213 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60309637 # Number of Instructions Simulated +system.cpu.cpi 7.911164 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.911164 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126404 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126404 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 548698002 # number of integer regfile reads +system.cpu.int_regfile_writes 87552826 # number of integer regfile writes +system.cpu.fp_regfile_reads 8408 # number of floating regfile reads +system.cpu.fp_regfile_writes 2932 # number of floating regfile writes +system.cpu.misc_regfile_reads 268236665 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173235 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58867266 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2659080 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2659079 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607534 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2957 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2969 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246101 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246101 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963183 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795840 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30059 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 127673 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7916755 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62784704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85494778 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 211580 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148531598 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148531598 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 200936 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128807668 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 607635 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2959 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2975 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246069 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246069 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961962 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796085 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30498 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129069 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7917614 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62744960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85505466 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214572 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148505990 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148505990 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 202724 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3129185667 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1475592252 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474638965 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2550083892 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2549207556 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19930988 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20255489 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74876053 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 75530794 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 981505 # number of replacements -system.cpu.icache.tags.tagsinuse 511.575357 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10456797 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 982017 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.648285 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6907075250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.575357 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999171 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999171 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 980897 # number of replacements +system.cpu.icache.tags.tagsinuse 511.570903 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10462766 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981409 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.660964 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6958078250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.570903 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999162 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999162 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 12500448 # Number of tag accesses -system.cpu.icache.tags.data_accesses 12500448 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 10456797 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10456797 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10456797 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10456797 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10456797 # number of overall hits -system.cpu.icache.overall_hits::total 10456797 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1061602 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1061602 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1061602 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1061602 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1061602 # number of overall misses -system.cpu.icache.overall_misses::total 1061602 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14273209676 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14273209676 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14273209676 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14273209676 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14273209676 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14273209676 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11518399 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11518399 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11518399 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11518399 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11518399 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11518399 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092166 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092166 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092166 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092166 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092166 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092166 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13444.972481 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13444.972481 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13444.972481 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13444.972481 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13444.972481 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13444.972481 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6382 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 12504958 # Number of tag accesses +system.cpu.icache.tags.data_accesses 12504958 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 10462766 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10462766 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10462766 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10462766 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10462766 # number of overall hits +system.cpu.icache.overall_hits::total 10462766 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060743 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060743 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060743 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060743 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060743 # number of overall misses +system.cpu.icache.overall_misses::total 1060743 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14268635888 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14268635888 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14268635888 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14268635888 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14268635888 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14268635888 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11523509 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11523509 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11523509 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11523509 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11523509 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11523509 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092050 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092050 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092050 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092050 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092050 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092050 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13451.548479 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13451.548479 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13451.548479 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13451.548479 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13451.548479 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13451.548479 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7798 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 332 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 344 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.222892 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 22.668605 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79552 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79552 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79552 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79552 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79552 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79552 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 982050 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 982050 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 982050 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 982050 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 982050 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 982050 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11590658741 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11590658741 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11590658741 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11590658741 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11590658741 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11590658741 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8870000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8870000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8870000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 8870000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085259 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085259 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085259 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085259 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085259 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085259 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11802.513865 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11802.513865 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11802.513865 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11802.513865 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11802.513865 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11802.513865 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79293 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79293 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79293 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79293 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79293 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79293 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981450 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 981450 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 981450 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 981450 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 981450 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 981450 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587546773 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11587546773 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587546773 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11587546773 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587546773 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11587546773 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 9345000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 9345000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 9345000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 9345000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085169 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085169 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085169 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.085169 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085169 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.085169 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11806.558432 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11806.558432 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11806.558432 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11806.558432 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11806.558432 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11806.558432 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 64371 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51367.805522 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1886658 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129763 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.539260 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2490785434500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36937.207333 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 28.555690 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000373 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8169.178837 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6232.863288 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563617 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000436 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 64391 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51374.630920 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1887139 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129786 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.540390 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2490832751500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36918.668159 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 31.305745 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000374 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8179.061871 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6245.594773 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.563334 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000478 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61405.960015 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76238.372093 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60372.286571 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61567.461912 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61477.131933 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76238.372093 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60372.286571 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61567.461912 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61477.131933 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61342.279193 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61342.279193 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 193750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60703.107276 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61467.157893 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61412.672268 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 193750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60703.107276 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61467.157893 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61412.672268 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1788,168 +1315,168 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643213 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.993295 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21506846 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 643725 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.409990 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 42602250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.993295 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 643279 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.993228 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21514190 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 643791 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.417973 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 43094250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993228 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 101509393 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 101509393 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13753990 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13753990 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259407 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259407 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242755 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242755 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21013397 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21013397 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21013397 # number of overall hits -system.cpu.dcache.overall_hits::total 21013397 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 736321 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 736321 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2962815 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2962815 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13522 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13522 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3699136 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3699136 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3699136 # number of overall misses -system.cpu.dcache.overall_misses::total 3699136 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10001713308 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10001713308 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 140180267525 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 140180267525 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184727500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 184727500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 150181980833 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 150181980833 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 150181980833 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 150181980833 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14490311 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14490311 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222222 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222222 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256277 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256277 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24712533 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24712533 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24712533 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24712533 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050815 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050815 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289841 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289841 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052763 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052763 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149687 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149687 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149687 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149687 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13583.360121 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13583.360121 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47313.202993 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47313.202993 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13661.255731 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13661.255731 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40599.205012 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40599.205012 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40599.205012 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40599.205012 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30576 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 27091 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2628 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 288 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.634703 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 94.065972 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 101537487 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 101537487 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13760648 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13760648 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7259865 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7259865 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242998 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242998 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247594 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21020513 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21020513 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21020513 # number of overall hits +system.cpu.dcache.overall_hits::total 21020513 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 736359 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 736359 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2962417 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2962417 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13527 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13527 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 16 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 16 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3698776 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3698776 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3698776 # number of overall misses +system.cpu.dcache.overall_misses::total 3698776 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9982812336 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9982812336 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 139744433579 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 139744433579 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185287000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 185287000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 245503 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 245503 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 149727245915 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 149727245915 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 149727245915 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 149727245915 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14497007 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14497007 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222282 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222282 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256525 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256525 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247610 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247610 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24719289 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24719289 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24719289 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24719289 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050794 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050794 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289800 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289800 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052732 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052732 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000065 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000065 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149631 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149631 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149631 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149631 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13556.991000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13556.991000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.438444 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.438444 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13697.567827 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13697.567827 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15343.937500 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15343.937500 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40480.214513 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40480.214513 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40480.214513 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40480.214513 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 31777 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 23524 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2637 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 274 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.050436 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 85.854015 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607534 # number of writebacks -system.cpu.dcache.writebacks::total 607534 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350801 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 350801 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713841 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713841 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1334 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1334 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3064642 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3064642 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3064642 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3064642 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385520 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385520 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248974 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248974 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12188 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12188 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634494 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634494 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634494 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634494 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4971012627 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4971012627 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11323926285 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11323926285 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145258250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145258250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16294938912 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16294938912 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16294938912 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16294938912 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335926750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335926750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26847444003 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26847444003 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209183370753 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209183370753 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026605 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026605 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024356 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024356 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047558 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047558 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025675 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025675 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025675 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025675 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12894.305424 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12894.305424 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45482.364765 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45482.364765 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11918.136692 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11918.136692 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25681.785662 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25681.785662 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25681.785662 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25681.785662 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607635 # number of writebacks +system.cpu.dcache.writebacks::total 607635 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350728 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 350728 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713476 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2713476 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1349 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1349 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3064204 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3064204 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3064204 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3064204 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385631 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385631 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248941 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248941 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12178 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12178 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634572 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634572 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634572 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634572 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4967633608 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4967633608 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11307381788 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11307381788 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145644250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145644250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 213497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 213497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16275015396 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16275015396 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16275015396 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16275015396 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182336207250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182336207250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26867769000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26867769000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209203976250 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209203976250 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026601 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026601 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024353 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047473 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047473 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000065 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000065 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025671 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025671 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025671 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025671 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.831616 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.831616 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45421.934466 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45421.934466 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11959.619806 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11959.619806 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13343.562500 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13343.562500 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25647.232144 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25647.232144 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25647.232144 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25647.232144 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1973,10 +1500,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499139103043 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1499139103043 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499139103043 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1499139103043 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1715151162848 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1715151162848 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1715151162848 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1715151162848 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index d9a1ddbd2..7d13ac1ec 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,156 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.605623 # Number of seconds simulated -sim_ticks 2605623216500 # Number of ticks simulated -final_tick 2605623216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.605649 # Number of seconds simulated +sim_ticks 2605649343000 # Number of ticks simulated +final_tick 2605649343000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60428 # Simulator instruction rate (inst/s) -host_op_rate 77810 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2507107577 # Simulator tick rate (ticks/s) -host_mem_usage 430512 # Number of bytes of host memory used -host_seconds 1039.29 # Real time elapsed on the host -sim_insts 62801984 # Number of instructions simulated -sim_ops 80867321 # Number of ops (including micro ops) simulated +host_inst_rate 57764 # Simulator instruction rate (inst/s) +host_op_rate 74374 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2397402056 # Simulator tick rate (ticks/s) +host_mem_usage 474764 # Number of bytes of host memory used +host_seconds 1086.86 # Real time elapsed on the host +sim_insts 62781325 # Number of instructions simulated +sim_ops 80834116 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1024 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 395008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4350396 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 426880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5253880 # Number of bytes read from this memory -system.physmem.bytes_read::total 131538740 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 395008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 426880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 821888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4261184 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 383680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5448188 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 438080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4125688 # Number of bytes read from this memory +system.physmem.bytes_read::total 131508276 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 383680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 438080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 821760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4229952 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7290320 # Number of bytes written to this memory +system.physmem.bytes_written::total 7259088 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 16 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6172 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68049 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6670 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82120 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15301859 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66581 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 5995 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 85202 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6845 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 64492 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15301383 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66093 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823865 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46480446 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 319 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823377 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46479979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 393 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 151598 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1669618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 163830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2016362 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50482640 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 151598 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 163830 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1635380 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 147249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2090914 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 368 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 168127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1583363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50470443 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 147249 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 168127 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315376 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1623377 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6524 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1156014 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2797918 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1635380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46480446 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1156002 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2785904 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1623377 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46479979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 151598 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1676143 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 163830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3172376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53280558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15301859 # Number of read requests accepted -system.physmem.writeReqs 823865 # Number of write requests accepted -system.physmem.readBursts 15301859 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 823865 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 976840512 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2478464 # Total number of bytes read from write queue -system.physmem.bytesWritten 7393984 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131538740 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7290320 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 38726 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 708315 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14211 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 956322 # Per bank write bursts -system.physmem.perBankRdBursts::1 955904 # Per bank write bursts -system.physmem.perBankRdBursts::2 952374 # Per bank write bursts -system.physmem.perBankRdBursts::3 952254 # Per bank write bursts -system.physmem.perBankRdBursts::4 956762 # Per bank write bursts -system.physmem.perBankRdBursts::5 955994 # Per bank write bursts -system.physmem.perBankRdBursts::6 951679 # Per bank write bursts -system.physmem.perBankRdBursts::7 951390 # Per bank write bursts -system.physmem.perBankRdBursts::8 956653 # Per bank write bursts -system.physmem.perBankRdBursts::9 956558 # Per bank write bursts -system.physmem.perBankRdBursts::10 951325 # Per bank write bursts -system.physmem.perBankRdBursts::11 950816 # Per bank write bursts -system.physmem.perBankRdBursts::12 956256 # Per bank write bursts -system.physmem.perBankRdBursts::13 956091 # Per bank write bursts -system.physmem.perBankRdBursts::14 951432 # Per bank write bursts -system.physmem.perBankRdBursts::15 951323 # Per bank write bursts -system.physmem.perBankWrBursts::0 7131 # Per bank write bursts -system.physmem.perBankWrBursts::1 6969 # Per bank write bursts -system.physmem.perBankWrBursts::2 7487 # Per bank write bursts -system.physmem.perBankWrBursts::3 7380 # Per bank write bursts -system.physmem.perBankWrBursts::4 7843 # Per bank write bursts -system.physmem.perBankWrBursts::5 7402 # Per bank write bursts -system.physmem.perBankWrBursts::6 7084 # Per bank write bursts -system.physmem.perBankWrBursts::7 7084 # Per bank write bursts -system.physmem.perBankWrBursts::8 7461 # Per bank write bursts -system.physmem.perBankWrBursts::9 7519 # Per bank write bursts -system.physmem.perBankWrBursts::10 6987 # Per bank write bursts -system.physmem.perBankWrBursts::11 6657 # Per bank write bursts -system.physmem.perBankWrBursts::12 7185 # Per bank write bursts -system.physmem.perBankWrBursts::13 7089 # Per bank write bursts -system.physmem.perBankWrBursts::14 7212 # Per bank write bursts -system.physmem.perBankWrBursts::15 7041 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 147249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2097438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 368 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 168127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2739365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53256346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15301383 # Number of read requests accepted +system.physmem.writeReqs 823377 # Number of write requests accepted +system.physmem.readBursts 15301383 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 823377 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 973889408 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5399104 # Total number of bytes read from write queue +system.physmem.bytesWritten 7284800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131508276 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7259088 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 84361 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709522 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14082 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 956098 # Per bank write bursts +system.physmem.perBankRdBursts::1 950020 # Per bank write bursts +system.physmem.perBankRdBursts::2 950090 # Per bank write bursts +system.physmem.perBankRdBursts::3 949980 # Per bank write bursts +system.physmem.perBankRdBursts::4 956223 # Per bank write bursts +system.physmem.perBankRdBursts::5 949119 # Per bank write bursts +system.physmem.perBankRdBursts::6 948884 # Per bank write bursts +system.physmem.perBankRdBursts::7 948711 # Per bank write bursts +system.physmem.perBankRdBursts::8 956337 # Per bank write bursts +system.physmem.perBankRdBursts::9 950158 # Per bank write bursts +system.physmem.perBankRdBursts::10 948908 # Per bank write bursts +system.physmem.perBankRdBursts::11 948900 # Per bank write bursts +system.physmem.perBankRdBursts::12 955944 # Per bank write bursts +system.physmem.perBankRdBursts::13 949314 # Per bank write bursts +system.physmem.perBankRdBursts::14 949393 # Per bank write bursts +system.physmem.perBankRdBursts::15 948943 # Per bank write bursts +system.physmem.perBankWrBursts::0 7119 # Per bank write bursts +system.physmem.perBankWrBursts::1 7037 # Per bank write bursts +system.physmem.perBankWrBursts::2 7071 # Per bank write bursts +system.physmem.perBankWrBursts::3 7168 # Per bank write bursts +system.physmem.perBankWrBursts::4 7696 # Per bank write bursts +system.physmem.perBankWrBursts::5 7220 # Per bank write bursts +system.physmem.perBankWrBursts::6 7070 # Per bank write bursts +system.physmem.perBankWrBursts::7 6913 # Per bank write bursts +system.physmem.perBankWrBursts::8 7415 # Per bank write bursts +system.physmem.perBankWrBursts::9 7415 # Per bank write bursts +system.physmem.perBankWrBursts::10 6887 # Per bank write bursts +system.physmem.perBankWrBursts::11 6788 # Per bank write bursts +system.physmem.perBankWrBursts::12 7071 # Per bank write bursts +system.physmem.perBankWrBursts::13 6872 # Per bank write bursts +system.physmem.perBankWrBursts::14 7197 # Per bank write bursts +system.physmem.perBankWrBursts::15 6886 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2605622062000 # Total gap between requests +system.physmem.totGap 2605648115500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 109 # Read request sizes (log2) system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 162934 # Read request sizes (log2) +system.physmem.readPktSize::6 162458 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 757284 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66581 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1184108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1129171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1082709 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3674312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2649053 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2636381 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2643445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 56452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 60541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 21670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 21240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 21122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20880 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20711 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 93 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66093 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1062706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 998935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950903 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 959607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 945820 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 946342 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2754714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2746120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3637640 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 38272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 34182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 34523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 32360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 30630 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 22253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 21644 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -161,609 +161,149 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 91489 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 10757.948868 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 916.821036 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16539.903542 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 25786 28.18% 28.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14910 16.30% 44.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 3164 3.46% 47.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2339 2.56% 50.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1506 1.65% 52.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1246 1.36% 53.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 1021 1.12% 54.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1185 1.30% 55.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 667 0.73% 56.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 658 0.72% 57.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 602 0.66% 58.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 572 0.63% 58.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 315 0.34% 58.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 283 0.31% 59.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 170 0.19% 59.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 580 0.63% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 115 0.13% 60.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 145 0.16% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 84 0.09% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 210 0.23% 60.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 59 0.06% 60.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 551 0.60% 61.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 52 0.06% 61.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 273 0.30% 61.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 29 0.03% 61.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 104 0.11% 61.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 17 0.02% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 169 0.18% 62.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 21 0.02% 62.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 56 0.06% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 21 0.02% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 399 0.44% 62.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 9 0.01% 62.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 43 0.05% 62.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 10 0.01% 62.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 57 0.06% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 5 0.01% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 24 0.03% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 13 0.01% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 166 0.18% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 7 0.01% 63.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 16 0.02% 63.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 4 0.00% 63.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 30 0.03% 63.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 6 0.01% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 23 0.03% 63.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 4 0.00% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 317 0.35% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 3 0.00% 63.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 20 0.02% 63.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 11 0.01% 63.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 167 0.18% 63.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 13 0.01% 63.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 17 0.02% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 7 0.01% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 159 0.17% 63.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 8 0.01% 63.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 17 0.02% 63.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 11 0.01% 63.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 119 0.13% 64.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 7 0.01% 64.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 21 0.02% 64.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 9 0.01% 64.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 498 0.54% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 8 0.01% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 12 0.01% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 9 0.01% 64.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 21 0.02% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 17 0.02% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 15 0.02% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 10 0.01% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 32 0.03% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 2 0.00% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 10 0.01% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 9 0.01% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 144 0.16% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 10 0.01% 64.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 10 0.01% 64.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 5 0.01% 64.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 298 0.33% 65.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 8 0.01% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 12 0.01% 65.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 6 0.01% 65.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 14 0.02% 65.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 7 0.01% 65.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 8 0.01% 65.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 5 0.01% 65.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 74 0.08% 65.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 2 0.00% 65.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 15 0.02% 65.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 4 0.00% 65.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 253 0.28% 65.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 4 0.00% 65.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 13 0.01% 65.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 13 0.01% 65.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 396 0.43% 66.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 4 0.00% 66.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 10 0.01% 66.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 4 0.00% 66.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 85 0.09% 66.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 5 0.01% 66.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 8 0.01% 66.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 5 0.01% 66.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 103 0.11% 66.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 8 0.01% 66.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 22 0.02% 66.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 2 0.00% 66.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 29 0.03% 66.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 4 0.00% 66.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 7 0.01% 66.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 3 0.00% 66.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 296 0.32% 66.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 3 0.00% 66.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 7 0.01% 66.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 10 0.01% 66.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 167 0.18% 67.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 5 0.01% 67.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 11 0.01% 67.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 5 0.01% 67.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 20 0.02% 67.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 1 0.00% 67.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 5 0.01% 67.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 73 0.08% 67.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 3 0.00% 67.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 9 0.01% 67.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 634 0.69% 67.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 2 0.00% 67.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 75 0.08% 67.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8583 2 0.00% 67.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 13 0.01% 68.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 1 0.00% 68.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 157 0.17% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9031 1 0.00% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 2 0.00% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9159 1 0.00% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 285 0.31% 68.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 15 0.02% 68.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9543 1 0.00% 68.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9607 1 0.00% 68.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 93 0.10% 68.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9799 1 0.00% 68.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9863 1 0.00% 68.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 77 0.08% 68.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10055 1 0.00% 68.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 4 0.00% 68.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 396 0.43% 69.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10375 2 0.00% 69.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10439 1 0.00% 69.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 200 0.22% 69.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10695 1 0.00% 69.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 71 0.08% 69.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10823 1 0.00% 69.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10887 1 0.00% 69.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10951 1 0.00% 69.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 10 0.01% 69.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 1 0.00% 69.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 289 0.32% 69.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11335 1 0.00% 69.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11399 1 0.00% 69.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 139 0.15% 69.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11591 1 0.00% 69.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 14 0.02% 69.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 10 0.01% 69.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12167 5 0.01% 69.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12231 2 0.00% 69.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 463 0.51% 70.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12359 1 0.00% 70.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 1 0.00% 70.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 93 0.10% 70.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12615 1 0.00% 70.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12679 1 0.00% 70.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 146 0.16% 70.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12871 1 0.00% 70.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12935 1 0.00% 70.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12999 1 0.00% 70.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 146 0.16% 70.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13127 1 0.00% 70.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 1 0.00% 70.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 294 0.32% 71.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 17 0.02% 71.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13639 1 0.00% 71.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13703 1 0.00% 71.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 141 0.15% 71.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13959 1 0.00% 71.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 14 0.02% 71.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 3 0.00% 71.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 345 0.38% 71.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14407 1 0.00% 71.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14471 2 0.00% 71.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14535 1 0.00% 71.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 78 0.09% 71.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14663 1 0.00% 71.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14727 2 0.00% 71.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 78 0.09% 71.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14983 3 0.00% 71.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 81 0.09% 72.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15175 1 0.00% 72.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 1 0.00% 72.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15303 2 0.00% 72.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 392 0.43% 72.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 92 0.10% 72.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15815 1 0.00% 72.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 13 0.01% 72.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15943 1 0.00% 72.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16007 1 0.00% 72.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 74 0.08% 72.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16199 1 0.00% 72.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16263 10 0.01% 72.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 676 0.74% 73.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 76 0.08% 73.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 13 0.01% 73.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16967 2 0.00% 73.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 98 0.11% 73.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17223 1 0.00% 73.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17287 2 0.00% 73.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17351 1 0.00% 73.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 394 0.43% 74.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17472-17479 4 0.00% 74.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17543 1 0.00% 74.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17600-17607 2 0.00% 74.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 80 0.09% 74.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17735 1 0.00% 74.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17792-17799 1 0.00% 74.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17856-17863 1 0.00% 74.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 77 0.08% 74.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18112-18119 1 0.00% 74.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 83 0.09% 74.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 3 0.00% 74.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 341 0.37% 74.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 14 0.02% 74.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18816-18823 2 0.00% 74.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 141 0.15% 74.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19072-19079 1 0.00% 74.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 23 0.03% 74.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 2 0.00% 74.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 287 0.31% 75.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19520-19527 3 0.00% 75.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19591 3 0.00% 75.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19648-19655 1 0.00% 75.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 144 0.16% 75.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19776-19783 2 0.00% 75.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 144 0.16% 75.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20160-20167 1 0.00% 75.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 97 0.11% 75.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20288-20295 1 0.00% 75.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 3 0.00% 75.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 470 0.51% 76.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20544-20551 1 0.00% 76.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20672-20679 1 0.00% 76.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 10 0.01% 76.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 16 0.02% 76.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21056-21063 1 0.00% 76.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21120-21127 1 0.00% 76.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 142 0.16% 76.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 4 0.00% 76.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21440-21447 3 0.00% 76.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 283 0.31% 76.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 9 0.01% 76.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21824-21831 1 0.00% 76.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 1 0.00% 76.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 72 0.08% 76.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22144-22151 2 0.00% 76.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 194 0.21% 77.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 3 0.00% 77.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22464-22471 1 0.00% 77.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 387 0.42% 77.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22592-22599 2 0.00% 77.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22656-22663 1 0.00% 77.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22720-22727 2 0.00% 77.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 79 0.09% 77.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22848-22855 1 0.00% 77.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22976-22983 2 0.00% 77.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 89 0.10% 77.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23104-23111 1 0.00% 77.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23168-23175 2 0.00% 77.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 21 0.02% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23424-23431 1 0.00% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 286 0.31% 77.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23687 2 0.00% 77.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 151 0.17% 78.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 13 0.01% 78.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24256-24263 2 0.00% 78.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 73 0.08% 78.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24384-24391 1 0.00% 78.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24448-24455 6 0.01% 78.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 527 0.58% 78.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24704-24711 2 0.00% 78.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24768-24775 1 0.00% 78.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 73 0.08% 78.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24896-24903 1 0.00% 78.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 14 0.02% 78.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25152-25159 1 0.00% 78.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25216-25223 1 0.00% 78.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25280-25287 1 0.00% 78.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 156 0.17% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25408-25415 2 0.00% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 3 0.00% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 278 0.30% 79.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25664-25671 2 0.00% 79.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 13 0.01% 79.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25984-25991 3 0.00% 79.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26048-26055 1 0.00% 79.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 89 0.10% 79.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26176-26183 4 0.00% 79.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26240-26247 1 0.00% 79.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 78 0.09% 79.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 4 0.00% 79.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 385 0.42% 80.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26752-26759 1 0.00% 80.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26816-26823 2 0.00% 80.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 196 0.21% 80.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26944-26951 1 0.00% 80.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27008-27015 1 0.00% 80.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27072-27079 2 0.00% 80.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 71 0.08% 80.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27200-27207 1 0.00% 80.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 10 0.01% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27463 2 0.00% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27520-27527 2 0.00% 80.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 285 0.31% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27712-27719 1 0.00% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27776-27783 2 0.00% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 137 0.15% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28096-28103 1 0.00% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 20 0.02% 80.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28224-28231 1 0.00% 80.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28288-28295 1 0.00% 80.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28352-28359 1 0.00% 80.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 15 0.02% 80.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 5 0.01% 80.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 454 0.50% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28800-28807 1 0.00% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28864-28871 1 0.00% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 95 0.10% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29056-29063 2 0.00% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 2 0.00% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 143 0.16% 81.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29312-29319 3 0.00% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29376-29383 2 0.00% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 147 0.16% 81.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29575 5 0.01% 81.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29632-29639 1 0.00% 81.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 291 0.32% 82.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29760-29767 1 0.00% 82.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 1 0.00% 82.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 18 0.02% 82.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30080-30087 2 0.00% 82.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30144-30151 1 0.00% 82.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 139 0.15% 82.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30279 2 0.00% 82.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 17 0.02% 82.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30528-30535 2 0.00% 82.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 5 0.01% 82.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 334 0.37% 82.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30784-30791 2 0.00% 82.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 75 0.08% 82.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31040-31047 2 0.00% 82.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31111 1 0.00% 82.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31168-31175 1 0.00% 82.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 77 0.08% 82.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31424-31431 2 0.00% 82.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 84 0.09% 82.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 6 0.01% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31680-31687 1 0.00% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 392 0.43% 83.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31808-31815 1 0.00% 83.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31872-31879 1 0.00% 83.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 91 0.10% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32135 2 0.00% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 14 0.02% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32384-32391 2 0.00% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 81 0.09% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32576-32583 1 0.00% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32640-32647 2 0.00% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 668 0.73% 84.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 70 0.08% 84.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 13 0.01% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33344-33351 1 0.00% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 3 0.00% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 95 0.10% 84.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33607 1 0.00% 84.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33671 3 0.00% 84.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 402 0.44% 84.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33920-33927 1 0.00% 84.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 82 0.09% 85.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 76 0.08% 85.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34432-34439 4 0.00% 85.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 80 0.09% 85.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34688-34695 1 0.00% 85.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34752-34759 1 0.00% 85.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 334 0.37% 85.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34944-34951 2 0.00% 85.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35008-35015 1 0.00% 85.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 12 0.01% 85.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35200-35207 1 0.00% 85.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35264-35271 1 0.00% 85.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 138 0.15% 85.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35456-35463 3 0.00% 85.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 16 0.02% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35712-35719 3 0.00% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 289 0.32% 86.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35904-35911 1 0.00% 86.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35968-35975 1 0.00% 86.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 143 0.16% 86.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 143 0.16% 86.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36416-36423 2 0.00% 86.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36480-36487 4 0.00% 86.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 101 0.11% 86.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 455 0.50% 87.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37056-37063 1 0.00% 87.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 7 0.01% 87.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37248-37255 2 0.00% 87.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37312-37319 1 0.00% 87.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 19 0.02% 87.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37511 2 0.00% 87.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 137 0.15% 87.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 277 0.30% 87.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38016-38023 1 0.00% 87.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 9 0.01% 87.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38272-38279 1 0.00% 87.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38336-38343 1 0.00% 87.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 70 0.08% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38464-38471 1 0.00% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 2 0.00% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 197 0.22% 87.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38784-38791 1 0.00% 87.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 387 0.42% 88.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39040-39047 2 0.00% 88.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 74 0.08% 88.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 86 0.09% 88.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39488-39495 2 0.00% 88.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 4 0.00% 88.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 16 0.02% 88.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39808-39815 2 0.00% 88.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39872-39879 1 0.00% 88.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 277 0.30% 88.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 154 0.17% 88.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40320-40327 1 0.00% 88.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 11 0.01% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 77 0.08% 89.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 525 0.57% 89.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41088-41095 1 0.00% 89.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 69 0.08% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41344-41351 3 0.00% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 14 0.02% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41600-41607 1 0.00% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 154 0.17% 89.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 280 0.31% 90.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42112-42119 1 0.00% 90.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 18 0.02% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42304-42311 2 0.00% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42368-42375 1 0.00% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 88 0.10% 90.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42624-42631 2 0.00% 90.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 77 0.08% 90.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42880-42887 2 0.00% 90.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 387 0.42% 90.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 193 0.21% 91.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 69 0.08% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 2 0.00% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 13 0.01% 91.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43904-43911 2 0.00% 91.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 277 0.30% 91.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 2 0.00% 91.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 139 0.15% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 17 0.02% 91.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44608-44615 2 0.00% 91.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44679 3 0.00% 91.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 11 0.01% 91.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44992-44999 1 0.00% 91.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 459 0.50% 92.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45191 1 0.00% 92.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 99 0.11% 92.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45376-45383 3 0.00% 92.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45440-45447 3 0.00% 92.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 148 0.16% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 2 0.00% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45760-45767 1 0.00% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 151 0.17% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46016-46023 1 0.00% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 285 0.31% 92.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46208-46215 1 0.00% 92.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 17 0.02% 92.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46528-46535 1 0.00% 92.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 140 0.15% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46720-46727 2 0.00% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 15 0.02% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 339 0.37% 93.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47296-47303 2 0.00% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 80 0.09% 93.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47488-47495 1 0.00% 93.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 79 0.09% 93.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 3 0.00% 93.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 82 0.09% 93.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48064-48071 1 0.00% 93.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 389 0.43% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48192-48199 1 0.00% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48320-48327 1 0.00% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 92 0.10% 94.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 12 0.01% 94.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48704-48711 2 0.00% 94.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 69 0.08% 94.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 72 0.08% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 2 0.00% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 3 0.00% 94.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5070 5.54% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49280-49287 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49344-49351 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49472-49479 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50048-50055 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50112-50119 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50183 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50368-50375 3 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50560-50567 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50624-50631 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50695 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50752-50759 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51008-51015 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51136-51143 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51207 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51264-51271 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51463 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51584-51591 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51648-51655 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51904-51911 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52231 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 91489 # Bytes accessed per row activation -system.physmem.totQLat 370803624750 # Total ticks spent queuing -system.physmem.totMemAccLat 464795231000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76315665000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17675941250 # Total ticks spent accessing banks -system.physmem.avgQLat 24294.07 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1158.08 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 965097 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 1010.691593 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 992.992769 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 104.599429 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 5712 0.59% 0.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4413 0.46% 1.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 2116 0.22% 1.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1499 0.16% 1.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1121 0.12% 1.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 815 0.08% 1.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 661 0.07% 1.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 851 0.09% 1.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 947909 98.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 965097 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5955 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2555.332662 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 92927.024688 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-262143 5949 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::262144-524287 1 0.02% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-786431 1 0.02% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 2 0.03% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6.02931e+06-6.29146e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5955 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5955 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.114190 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.218740 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.431880 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3971 66.68% 66.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 19 0.32% 67.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 175 2.94% 69.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1141 19.16% 89.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 44 0.74% 89.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 19 0.32% 90.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 21 0.35% 90.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.17% 90.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 6 0.10% 90.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 3 0.05% 90.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 4 0.07% 90.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.02% 90.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.02% 90.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.02% 90.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 1 0.02% 90.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 1 0.02% 90.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 146 2.45% 93.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 311 5.22% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 13 0.22% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 13 0.22% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 16 0.27% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 22 0.37% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 9 0.15% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 4 0.07% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 3 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5955 # Writes before turning the bus around for reads +system.physmem.totQLat 579051796250 # Total ticks spent queuing +system.physmem.totMemAccLat 683715373750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76085110000 # Total ticks spent in databus transfers +system.physmem.totBankLat 28578467500 # Total ticks spent accessing banks +system.physmem.avgQLat 38052.90 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1878.06 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30452.15 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 374.90 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.84 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.48 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.80 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44930.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 373.76 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.80 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.47 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.95 # Data bus utilization in percentage -system.physmem.busUtilRead 2.93 # Data bus utilization in percentage for reads +system.physmem.busUtil 2.94 # Data bus utilization in percentage +system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.44 # Average write queue length when enqueuing -system.physmem.readRowHits 15189237 # Number of row buffer hits during reads -system.physmem.writeRowHits 97938 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.76 # Row buffer hit rate for writes -system.physmem.avgGap 161581.71 # Average gap between requests -system.physmem.pageHitRate 99.40 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 2.46 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.avgRdQLen 6.53 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.75 # Average write queue length when enqueuing +system.physmem.readRowHits 14231578 # Number of row buffer hits during reads +system.physmem.writeRowHits 96073 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 84.38 # Row buffer hit rate for writes +system.physmem.avgGap 161592.99 # Average gap between requests +system.physmem.pageHitRate 93.46 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.22 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -782,299 +322,300 @@ system.realview.nvmem.bw_inst_read::total 172 # I system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54211188 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16352626 # Transaction distribution -system.membus.trans_dist::ReadResp 16352626 # Transaction distribution -system.membus.trans_dist::WriteReq 769179 # Transaction distribution -system.membus.trans_dist::WriteResp 769179 # Transaction distribution -system.membus.trans_dist::Writeback 66581 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35757 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 18322 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14211 # Transaction distribution -system.membus.trans_dist::ReadExReq 137874 # Transaction distribution -system.membus.trans_dist::ReadExResp 137463 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384372 # Packet count per connected master and slave (bytes) +system.membus.throughput 54186995 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16352581 # Transaction distribution +system.membus.trans_dist::ReadResp 16352581 # Transaction distribution +system.membus.trans_dist::WriteReq 769189 # Transaction distribution +system.membus.trans_dist::WriteResp 769189 # Transaction distribution +system.membus.trans_dist::Writeback 66093 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35785 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 18271 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14082 # Transaction distribution +system.membus.trans_dist::ReadExReq 137406 # Transaction distribution +system.membus.trans_dist::ReadExResp 137045 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384396 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13818 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13840 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2042 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1975936 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4376186 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1974294 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4374590 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34653818 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392693 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34652222 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392725 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27636 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27680 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4084 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17718532 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20143401 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17656836 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20081781 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141253929 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141253929 # Total data (bytes) +system.membus.tot_pkt_size::total 141192309 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141192309 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1488197499 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1488242000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11766500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11807000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1797499 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1798000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17658492000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17652470999 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4844234238 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4843604815 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34183641699 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.membus.respLayer2.occupancy 37703679634 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 72645 # number of replacements -system.l2c.tags.tagsinuse 53020.689119 # Cycle average of tags in use -system.l2c.tags.total_refs 1874829 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 137818 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.603658 # Average number of references to valid blocks. +system.l2c.tags.replacements 72164 # number of replacements +system.l2c.tags.tagsinuse 53016.131060 # Cycle average of tags in use +system.l2c.tags.total_refs 1876966 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 137304 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.670148 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37720.403327 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.416210 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000363 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4180.066464 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2958.458343 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.364086 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4038.603525 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 4106.376802 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.575568 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000083 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 37702.356015 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 7.377107 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000365 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4186.473555 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2957.675740 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.683393 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4035.806716 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 4115.758170 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.575292 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000113 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063783 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.045142 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000173 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.061624 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.062658 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.809032 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65168 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3126 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8643 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53076 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18857930 # Number of tag accesses -system.l2c.tags.data_accesses 18857930 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 23180 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4676 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 393299 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166186 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 33047 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5717 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 607435 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 201334 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1434874 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 583828 # number of Writeback hits -system.l2c.Writeback_hits::total 583828 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1113 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 796 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1909 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 212 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 162 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 374 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48382 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 59141 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107523 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 23180 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4676 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 393299 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214568 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 33047 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5717 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 607435 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 260475 # number of demand (read+write) hits -system.l2c.demand_hits::total 1542397 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 23180 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4676 # number of overall hits -system.l2c.overall_hits::cpu0.inst 393299 # number of overall hits -system.l2c.overall_hits::cpu0.data 214568 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 33047 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5717 # number of overall hits -system.l2c.overall_hits::cpu1.inst 607435 # number of overall hits -system.l2c.overall_hits::cpu1.data 260475 # number of overall hits -system.l2c.overall_hits::total 1542397 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses +system.l2c.tags.occ_percent::cpu0.inst 0.063881 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.045131 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000163 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.061582 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.062801 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.808962 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65136 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8263 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53454 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.993896 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 18860644 # Number of tag accesses +system.l2c.tags.data_accesses 18860644 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 23595 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 5577 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 409210 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 169724 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 33221 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5824 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 593571 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 196649 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1437371 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 582434 # number of Writeback hits +system.l2c.Writeback_hits::total 582434 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 737 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1202 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1939 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 203 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 149 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 352 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 52746 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 54725 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 107471 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 23595 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 5577 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1239250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 417280250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4362686487 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 10264071435 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6908499 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 110354445727 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2586249 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 56865414992 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167229355467 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1097294498 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16505203944 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17602498442 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6908499 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 111451740225 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2586249 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 73370618936 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184831853909 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000678 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000358 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014146 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.034960 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000451 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011329 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.031468 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017261 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.877330 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.798727 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.838147 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.791152 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.794483 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.792575 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.603935 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.520112 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.565268 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000678 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000358 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014146 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.280110 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000451 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011329 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.207195 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.096489 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000678 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000358 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014146 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.280110 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000451 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011329 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.207195 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.096489 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66437.500000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59674.088896 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61947.154309 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 82616.666667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61346.699500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64822.926291 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62000.069236 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10027.076836 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10074.044444 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10049.388905 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.950585 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10029.633681 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10021.810409 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59061.876923 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66571.148975 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62249.130084 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66437.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59674.088896 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 59266.827961 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82616.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61346.699500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66401.121534 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62211.017983 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66437.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59674.088896 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 59266.827961 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82616.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61346.699500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66401.121534 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62211.017983 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1265,62 +806,62 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58734643 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2740334 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2740333 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 769179 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 769179 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 583828 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 35005 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18696 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 53701 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 259560 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 259560 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 799508 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1075466 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 14045 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 57080 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1228838 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4820247 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 15511 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 75325 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8086020 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25566400 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34789221 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18712 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 92772 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39303552 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 48210820 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 22868 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132256 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148136601 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148136601 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4903748 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4924229951 # Layer occupancy (ticks) +system.toL2Bus.throughput 58721934 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2742702 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2742701 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 769189 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 769189 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 582434 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 35028 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18623 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 53651 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 259025 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 259025 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831060 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2542800 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15169 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 56113 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1201524 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 3348368 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 16175 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 77084 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8088293 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26573504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 39205457 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 22316 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 94444 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38427456 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 43600612 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 23296 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132944 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148080029 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148080029 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4928740 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4918843977 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1801808391 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1872939397 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1518829470 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2324821689 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9386457 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9616940 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 34051657 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 32646700 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2768216654 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 2706859206 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 3257831802 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 2444231662 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer8.occupancy 9819444 # Layer occupancy (ticks) +system.toL2Bus.respLayer8.occupancy 10370957 # Layer occupancy (ticks) system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 42547912 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.occupancy 44131664 # Layer occupancy (ticks) system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 47398726 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322919 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322919 # Transaction distribution -system.iobus.trans_dist::WriteReq 8083 # Transaction distribution -system.iobus.trans_dist::WriteResp 8083 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30944 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8844 # Packet count per connected master and slave (bytes) +system.iobus.throughput 47398263 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322928 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322928 # Transaction distribution +system.iobus.trans_dist::WriteReq 8086 # Transaction distribution +system.iobus.trans_dist::WriteResp 8086 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8852 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -1342,12 +883,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2384372 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2384396 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32662004 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40713 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17688 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 32662028 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40729 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17704 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -1369,14 +910,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2392693 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2392725 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123503221 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123503221 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21713000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 123503253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123503253 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21724000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4428000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4432000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1422,19 +963,19 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2376289000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2376310000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41457903301 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu0.branchPred.lookups 6116113 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4670014 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 294465 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3791796 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2947023 # Number of BTB hits +system.iobus.respLayer1.occupancy 37739478366 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) +system.cpu0.branchPred.lookups 6715650 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5214611 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 297509 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4164563 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3259277 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.721032 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 683382 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28116 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 78.262161 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 722080 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28659 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1458,25 +999,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8971213 # DTB read hits -system.cpu0.dtb.read_misses 29038 # DTB read misses -system.cpu0.dtb.write_hits 5214205 # DTB write hits -system.cpu0.dtb.write_misses 5642 # DTB write misses +system.cpu0.dtb.read_hits 30314049 # DTB read hits +system.cpu0.dtb.read_misses 28675 # DTB read misses +system.cpu0.dtb.write_hits 5612279 # DTB write hits +system.cpu0.dtb.write_misses 4120 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1740 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 972 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 288 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1934 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1024 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 602 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9000251 # DTB read accesses -system.cpu0.dtb.write_accesses 5219847 # DTB write accesses +system.cpu0.dtb.perms_faults 686 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 30342724 # DTB read accesses +system.cpu0.dtb.write_accesses 5616399 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14185418 # DTB hits -system.cpu0.dtb.misses 34680 # DTB misses -system.cpu0.dtb.accesses 14220098 # DTB accesses +system.cpu0.dtb.hits 35926328 # DTB hits +system.cpu0.dtb.misses 32795 # DTB misses +system.cpu0.dtb.accesses 35959123 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1498,8 +1039,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 4275051 # ITB inst hits -system.cpu0.itb.inst_misses 5189 # ITB inst misses +system.cpu0.itb.inst_hits 4601822 # ITB inst hits +system.cpu0.itb.inst_misses 5333 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1508,549 +1049,544 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1217 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1359 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1383 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1531 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4280240 # ITB inst accesses -system.cpu0.itb.hits 4275051 # DTB hits -system.cpu0.itb.misses 5189 # DTB misses -system.cpu0.itb.accesses 4280240 # DTB accesses -system.cpu0.numCycles 70241745 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4607155 # ITB inst accesses +system.cpu0.itb.hits 4601822 # DTB hits +system.cpu0.itb.misses 5333 # DTB misses +system.cpu0.itb.accesses 4607155 # DTB accesses +system.cpu0.numCycles 298758505 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11929498 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32445295 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6116113 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3630405 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7610256 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1455955 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 63581 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20356712 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5910 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 46897 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1384514 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 336 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4273539 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157097 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2132 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 42442805 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.987587 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.368800 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 12556555 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 35349888 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6715650 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3981357 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 8343175 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1485021 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 73668 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 62934939 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 43768 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1358657 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 326 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4600051 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 159705 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2319 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 86381436 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.526874 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.794731 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34839840 82.09% 82.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 572205 1.35% 83.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 825004 1.94% 85.38% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 684840 1.61% 86.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 778500 1.83% 88.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 566486 1.33% 90.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 678699 1.60% 91.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 357241 0.84% 92.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3139990 7.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 78045507 90.35% 90.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 675063 0.78% 91.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 847046 0.98% 92.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 783211 0.91% 93.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1013921 1.17% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 572462 0.66% 94.86% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 659407 0.76% 95.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 359642 0.42% 96.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3425177 3.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 42442805 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.087072 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.461909 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12488007 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 21548451 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6870426 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 554367 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 981554 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 948390 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64682 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40553105 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 211793 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 981554 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 13063645 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5927392 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13516172 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6803229 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2150813 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 39442908 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 349 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 442190 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1172580 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 108 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39856158 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 180580051 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 163873696 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 4140 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31502925 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8353232 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 459972 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 416665 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5510720 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7760142 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5773435 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1130797 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1218383 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37351008 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 906143 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37719109 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 82376 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6300240 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13226792 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 257129 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 42442805 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.888704 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.506616 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 86381436 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.022479 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.118323 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 13622847 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 63604727 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 7412124 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 742617 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 999121 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 974392 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 66422 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 44125799 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 218867 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 999121 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 14363042 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 26099881 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 33731509 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 7356267 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3831616 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 43013829 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 321 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 629927 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2476084 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 94 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 43352703 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 198103413 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 178854732 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5396 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34867311 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8485392 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 643580 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 598183 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 7434614 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8769305 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6206849 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1218439 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1296110 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 40716219 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1133567 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 61584494 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 78672 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6465857 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13399979 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 300001 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 86381436 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.712937 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.420531 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 27084248 63.81% 63.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5900278 13.90% 77.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3162124 7.45% 85.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2465638 5.81% 90.97% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2124054 5.00% 95.98% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 938721 2.21% 98.19% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 522569 1.23% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 188950 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 56223 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 63313818 73.30% 73.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 8088215 9.36% 82.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3310781 3.83% 86.49% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2721682 3.15% 89.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 7122842 8.25% 97.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1038791 1.20% 99.09% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 532976 0.62% 99.71% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 192156 0.22% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 60175 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 42442805 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 86381436 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27701 2.58% 2.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 461 0.04% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 838727 78.09% 80.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 207210 19.29% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 26298 0.46% 0.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 452 0.01% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5416194 95.59% 96.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 223026 3.94% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 14552 0.04% 0.04% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22689290 60.15% 60.19% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 48124 0.13% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9432418 25.01% 85.33% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5534012 14.67% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 15923 0.03% 0.03% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 24790294 40.25% 40.28% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 50109 0.08% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 806 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 40.36% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 30788025 49.99% 90.36% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5939307 9.64% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37719109 # Type of FU issued -system.cpu0.iq.rate 0.536990 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1074099 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028476 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 119063513 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44565262 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34855631 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8367 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4694 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3878 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38774303 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4353 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 316534 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 61584494 # Type of FU issued +system.cpu0.iq.rate 0.206135 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 5665970 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.092003 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 215315704 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 48322789 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 38367249 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11842 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6226 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5089 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 67228191 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6350 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 325894 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1373139 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2492 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13119 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 536810 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1367932 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2587 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13911 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 563678 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149889 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5851 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 22510150 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5899 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 981554 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4303712 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 102086 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 38375609 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 82190 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7760142 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5773435 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 578535 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 41087 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6130 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13119 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 149567 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117143 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 266710 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37339391 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9288472 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 379718 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 999121 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 20412775 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 272757 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 41952562 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 83343 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8769305 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6206849 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 796686 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 50755 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3694 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13911 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 151015 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 116203 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 267218 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 61206576 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 30649831 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 377918 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118458 # number of nop insts executed -system.cpu0.iew.exec_refs 14775675 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4960531 # Number of branches executed -system.cpu0.iew.exec_stores 5487203 # Number of stores executed -system.cpu0.iew.exec_rate 0.531584 # Inst execution rate -system.cpu0.iew.wb_sent 37145263 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34859509 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18586335 # num instructions producing a value -system.cpu0.iew.wb_consumers 35686170 # num instructions consuming a value +system.cpu0.iew.exec_nop 102776 # number of nop insts executed +system.cpu0.iew.exec_refs 36543183 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5550332 # Number of branches executed +system.cpu0.iew.exec_stores 5893352 # Number of stores executed +system.cpu0.iew.exec_rate 0.204870 # Inst execution rate +system.cpu0.iew.wb_sent 61019070 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 38372338 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 20674113 # num instructions producing a value +system.cpu0.iew.wb_consumers 38142518 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.496279 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520827 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.128439 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.542023 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6112161 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 649014 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 230918 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 41461251 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.767144 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.727678 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6195680 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 833566 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 232261 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 85382315 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.412432 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.299663 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 29511356 71.18% 71.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5920392 14.28% 85.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1945303 4.69% 90.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1006881 2.43% 92.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 766693 1.85% 94.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 514145 1.24% 95.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 405651 0.98% 96.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 222934 0.54% 97.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1167896 2.82% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 71262923 83.46% 83.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7740236 9.07% 92.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2004904 2.35% 94.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1114217 1.30% 96.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 806577 0.94% 97.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 503262 0.59% 97.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 497454 0.58% 98.30% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 227564 0.27% 98.57% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1225178 1.43% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 41461251 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24081359 # Number of instructions committed -system.cpu0.commit.committedOps 31806750 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 85382315 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 26835114 # Number of instructions committed +system.cpu0.commit.committedOps 35214409 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11623628 # Number of memory references committed -system.cpu0.commit.loads 6387003 # Number of loads committed -system.cpu0.commit.membars 231881 # Number of memory barriers committed -system.cpu0.commit.branches 4353159 # Number of branches committed -system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28151052 # Number of committed integer instructions. -system.cpu0.commit.function_calls 499153 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1167896 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13044544 # Number of memory references committed +system.cpu0.commit.loads 7401373 # Number of loads committed +system.cpu0.commit.membars 236456 # Number of memory barriers committed +system.cpu0.commit.branches 4918099 # Number of branches committed +system.cpu0.commit.fp_insts 5062 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 31243705 # Number of committed integer instructions. +system.cpu0.commit.function_calls 531450 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1225178 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 77343282 # The number of ROB reads -system.cpu0.rob.rob_writes 76821100 # The number of ROB writes -system.cpu0.timesIdled 366365 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27798940 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5140962052 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 24000617 # Number of Instructions Simulated -system.cpu0.committedOps 31726008 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 24000617 # Number of Instructions Simulated -system.cpu0.cpi 2.926664 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.926664 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.341686 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.341686 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 174312752 # number of integer regfile reads -system.cpu0.int_regfile_writes 34607985 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3310 # number of floating regfile reads -system.cpu0.fp_regfile_writes 918 # number of floating regfile writes -system.cpu0.misc_regfile_reads 79392098 # number of misc regfile reads -system.cpu0.misc_regfile_writes 500989 # number of misc regfile writes -system.cpu0.icache.tags.replacements 399371 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.568929 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 3842185 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 399883 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.608273 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7067442000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.568929 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999158 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999158 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 124649951 # The number of ROB reads +system.cpu0.rob.rob_writes 83821170 # The number of ROB writes +system.cpu0.timesIdled 1018994 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 212377069 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 4911896145 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 26765511 # Number of Instructions Simulated +system.cpu0.committedOps 35144806 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 26765511 # Number of Instructions Simulated +system.cpu0.cpi 11.162070 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 11.162070 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.089589 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.089589 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 273626518 # number of integer regfile reads +system.cpu0.int_regfile_writes 37917674 # number of integer regfile writes +system.cpu0.fp_regfile_reads 4695 # number of floating regfile reads +system.cpu0.fp_regfile_writes 986 # number of floating regfile writes +system.cpu0.misc_regfile_reads 148789996 # number of misc regfile reads +system.cpu0.misc_regfile_writes 678362 # number of misc regfile writes +system.cpu0.icache.tags.replacements 415188 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.568306 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 4152259 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 415700 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.988595 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7103550250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.568306 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999157 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999157 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 4673316 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 4673316 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 3842185 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3842185 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3842185 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3842185 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3842185 # number of overall hits -system.cpu0.icache.overall_hits::total 3842185 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 431224 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 431224 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 431224 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 431224 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 431224 # number of overall misses -system.cpu0.icache.overall_misses::total 431224 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5969029520 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5969029520 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5969029520 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5969029520 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5969029520 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5969029520 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4273409 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4273409 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4273409 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4273409 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4273409 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4273409 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100909 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100909 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100909 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100909 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100909 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100909 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13842.062408 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13842.062408 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13842.062408 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13842.062408 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13842.062408 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13842.062408 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4009 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 5015647 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 5015647 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 4152259 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 4152259 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 4152259 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 4152259 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 4152259 # number of overall hits +system.cpu0.icache.overall_hits::total 4152259 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 447663 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 447663 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 447663 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 447663 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 447663 # number of overall misses +system.cpu0.icache.overall_misses::total 447663 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6158685000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6158685000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6158685000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6158685000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6158685000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6158685000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4599922 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4599922 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4599922 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4599922 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4599922 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4599922 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097320 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.097320 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097320 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.097320 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097320 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.097320 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13757.413501 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13757.413501 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13757.413501 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13757.413501 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13757.413501 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13757.413501 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4464 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 172 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 167 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.308140 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.730539 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31316 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 31316 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 31316 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 31316 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 31316 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 31316 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 399908 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 399908 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 399908 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 399908 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 399908 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 399908 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4860978096 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4860978096 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4860978096 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4860978096 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4860978096 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4860978096 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9448000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9448000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9448000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 9448000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093581 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093581 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093581 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093581 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093581 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093581 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12155.240945 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12155.240945 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12155.240945 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12155.240945 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12155.240945 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12155.240945 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31938 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 31938 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 31938 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 31938 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 31938 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 31938 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 415725 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 415725 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 415725 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 415725 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 415725 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 415725 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5022987594 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5022987594 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5022987594 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5022987594 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5022987594 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5022987594 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9487250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9487250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9487250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 9487250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090377 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090377 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090377 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.090377 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090377 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.090377 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12082.476623 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12082.476623 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12082.476623 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12082.476623 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12082.476623 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12082.476623 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 275793 # number of replacements -system.cpu0.dcache.tags.tagsinuse 480.388822 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9427243 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 276305 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 34.118974 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 43744250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.388822 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938259 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.938259 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 45827663 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 45827663 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5876905 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5876905 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3228758 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3228758 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139532 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139532 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137231 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137231 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9105663 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9105663 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9105663 # number of overall hits -system.cpu0.dcache.overall_hits::total 9105663 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 393187 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 393187 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1586487 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1586487 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8903 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8903 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7768 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7768 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1979674 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1979674 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1979674 # number of overall misses -system.cpu0.dcache.overall_misses::total 1979674 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5526786247 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5526786247 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 79724845605 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 79724845605 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91251732 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 91251732 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50083768 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 50083768 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 85251631852 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 85251631852 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 85251631852 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 85251631852 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6270092 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6270092 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4815245 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4815245 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148435 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 148435 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144999 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144999 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11085337 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11085337 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11085337 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11085337 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062708 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.062708 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.329472 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.329472 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059979 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059979 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053573 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053573 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178585 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.178585 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178585 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.178585 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14056.380926 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14056.380926 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50252.441782 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50252.441782 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10249.548691 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10249.548691 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6447.446962 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6447.446962 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43063.469971 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 43063.469971 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43063.469971 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 43063.469971 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8922 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 7566 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 589 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 136 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.147708 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 55.632353 # average number of cycles each access was blocked +system.cpu0.dcache.tags.replacements 298882 # number of replacements +system.cpu0.dcache.tags.tagsinuse 483.456705 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10027143 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 299266 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.505787 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 44230250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 483.456705 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.944251 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.944251 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 384 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 48541082 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 48541082 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6144970 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6144970 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3563655 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3563655 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 144672 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 144672 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 142233 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 142233 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9708625 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9708625 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9708625 # number of overall hits +system.cpu0.dcache.overall_hits::total 9708625 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 393929 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 393929 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1644577 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1644577 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9244 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9244 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7866 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7866 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2038506 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2038506 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2038506 # number of overall misses +system.cpu0.dcache.overall_misses::total 2038506 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5542234631 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5542234631 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 82471404032 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 82471404032 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 94602484 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 94602484 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50293768 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 50293768 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 88013638663 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 88013638663 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 88013638663 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 88013638663 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6538899 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6538899 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5208232 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5208232 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 153916 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 153916 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 150099 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 150099 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11747131 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11747131 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11747131 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11747131 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.060244 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.060244 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.315765 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.315765 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060059 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.060059 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052405 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052405 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.173532 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.173532 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.173532 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.173532 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14069.120656 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14069.120656 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50147.487185 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50147.487185 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10233.933795 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10233.933795 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6393.817442 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6393.817442 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43175.560270 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 43175.560270 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43175.560270 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 43175.560270 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 10878 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 5936 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 678 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 116 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.044248 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 51.172414 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256103 # number of writebacks -system.cpu0.dcache.writebacks::total 256103 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203673 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 203673 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1455296 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1455296 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 469 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 469 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1658969 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1658969 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1658969 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1658969 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189514 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189514 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131191 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131191 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8434 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8434 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7768 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7768 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 320705 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 320705 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 320705 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 320705 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2409533443 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2409533443 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5292752283 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5292752283 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69541268 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69541268 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34547232 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34547232 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7702285726 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7702285726 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7702285726 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7702285726 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13436185037 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13436185037 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1206083884 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1206083884 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14642268921 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14642268921 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030225 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030225 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027245 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027245 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056819 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056819 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053573 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053573 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028931 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028931 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028931 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028931 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12714.276745 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12714.276745 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40343.867209 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40343.867209 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8245.348352 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8245.348352 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4447.377961 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4447.377961 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 278268 # number of writebacks +system.cpu0.dcache.writebacks::total 278268 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 201648 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 201648 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1493557 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1493557 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 632 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 632 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1695205 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1695205 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1695205 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1695205 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 192281 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 192281 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 151020 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 151020 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8612 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8612 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7866 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7866 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 343301 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 343301 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 343301 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 343301 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2438332267 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2438332267 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6681240000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6681240000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70543016 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 70543016 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34562232 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34562232 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9119572267 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9119572267 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9119572267 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9119572267 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 120538982283 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 120538982283 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1232045382 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1232045382 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 121771027665 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 121771027665 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029406 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029406 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028996 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028996 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055953 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055953 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052405 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052405 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029224 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029224 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029224 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029224 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12681.087923 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12681.087923 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44240.762813 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44240.762813 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8191.246633 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8191.246633 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4393.876430 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4393.876430 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24016.731033 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24016.731033 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24016.731033 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24016.731033 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26564.362664 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26564.362664 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26564.362664 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26564.362664 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -2058,15 +1594,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9293568 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7630023 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 416409 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5939121 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5050753 # Number of BTB hits +system.cpu1.branchPred.lookups 8689698 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7082612 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 415349 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5570453 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 4730059 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 85.042096 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 798930 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 43976 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 84.913363 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 759549 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 43595 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -2090,25 +1626,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42973192 # DTB read hits -system.cpu1.dtb.read_misses 37885 # DTB read misses -system.cpu1.dtb.write_hits 6980403 # DTB write hits -system.cpu1.dtb.write_misses 10788 # DTB write misses +system.cpu1.dtb.read_hits 21626734 # DTB read hits +system.cpu1.dtb.read_misses 38691 # DTB read misses +system.cpu1.dtb.write_hits 6575784 # DTB write hits +system.cpu1.dtb.write_misses 12298 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1925 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2835 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.flush_entries 1712 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3023 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 279 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 681 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43011077 # DTB read accesses -system.cpu1.dtb.write_accesses 6991191 # DTB write accesses +system.cpu1.dtb.perms_faults 600 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 21665425 # DTB read accesses +system.cpu1.dtb.write_accesses 6588082 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49953595 # DTB hits -system.cpu1.dtb.misses 48673 # DTB misses -system.cpu1.dtb.accesses 50002268 # DTB accesses +system.cpu1.dtb.hits 28202518 # DTB hits +system.cpu1.dtb.misses 50989 # DTB misses +system.cpu1.dtb.accesses 28253507 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -2130,8 +1666,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 7723190 # ITB inst hits -system.cpu1.itb.inst_misses 5562 # ITB inst misses +system.cpu1.itb.inst_hits 7394895 # ITB inst hits +system.cpu1.itb.inst_misses 5860 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -2140,544 +1676,546 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1359 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1207 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1471 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1503 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7728752 # ITB inst accesses -system.cpu1.itb.hits 7723190 # DTB hits -system.cpu1.itb.misses 5562 # DTB misses -system.cpu1.itb.accesses 7728752 # DTB accesses -system.cpu1.numCycles 413796923 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7400755 # ITB inst accesses +system.cpu1.itb.hits 7394895 # DTB hits +system.cpu1.itb.misses 5860 # DTB misses +system.cpu1.itb.accesses 7400755 # DTB accesses +system.cpu1.numCycles 185247782 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19367440 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 61322975 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9293568 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5849683 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13369526 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3346649 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 69265 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 80967245 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 6008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 41697 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1506074 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 288 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7721399 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 552563 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2913 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 117616541 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.638291 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.959867 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 18767441 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 58413381 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8689698 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5489608 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 12630025 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3326163 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 70879 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 38401480 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5864 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 46813 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1518730 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7393189 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 549179 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3073 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 73717325 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.969397 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.351920 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 104254528 88.64% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 816257 0.69% 89.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 960958 0.82% 90.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1713992 1.46% 91.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1419991 1.21% 92.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 586388 0.50% 93.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1955965 1.66% 94.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 421912 0.36% 95.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5486550 4.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 61095045 82.88% 82.88% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 712004 0.97% 83.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 939814 1.27% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1614257 2.19% 87.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1180828 1.60% 88.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 579149 0.79% 89.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1971485 2.67% 92.37% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 418985 0.57% 92.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5205758 7.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 117616541 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022459 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.148196 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 20958094 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 81738883 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 11922126 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 807725 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2189713 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1139186 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 101010 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 71114524 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 335626 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2189713 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22150930 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33873368 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 43341870 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11481154 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4579506 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 67156903 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 160 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 681335 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3069410 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 515 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 70770910 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 313189992 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 286825978 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6578 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50413534 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20357376 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 766049 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 705865 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8415941 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 12847707 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8121662 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1063533 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1519311 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 61868936 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1182413 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 88920941 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 95302 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13575964 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 36252507 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 283075 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 117616541 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.756024 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.499146 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 73717325 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.046909 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.315326 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 19856835 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 39689565 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 11370888 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 621997 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2178040 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1113164 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 99384 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 67504859 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 329486 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2178040 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 20884497 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 13732674 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 23091492 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 10921071 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2909551 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 63553177 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 150 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 495727 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 1775459 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 454 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 67243012 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 295535307 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 271726361 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 4962 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 47019288 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20223723 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 581683 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 523637 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6484055 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 11835207 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7683859 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 982260 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1485488 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 58475771 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 951228 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 65019700 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 99369 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13400197 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 36106127 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 236520 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 73717325 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.882014 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.585621 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 86757290 73.76% 73.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 9288969 7.90% 81.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4169197 3.54% 85.21% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3602778 3.06% 88.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10372979 8.82% 97.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1998574 1.70% 98.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1065464 0.91% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 282646 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 78644 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 50542925 68.56% 68.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 7121407 9.66% 78.22% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4031042 5.47% 83.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3362905 4.56% 88.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 5367239 7.28% 95.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1894348 2.57% 98.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1048738 1.42% 99.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 275398 0.37% 99.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 73323 0.10% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 117616541 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 73717325 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32554 0.41% 0.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 991 0.01% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7574498 95.71% 96.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 306293 3.87% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 33869 1.02% 1.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 996 0.03% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 2994112 90.44% 91.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 281623 8.51% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 14269 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37628828 42.32% 42.33% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61233 0.07% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1700 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43862772 49.33% 91.73% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7352107 8.27% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 12895 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 35505233 54.61% 54.63% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59031 0.09% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 14 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1556 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.72% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 22501549 34.61% 89.33% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6939400 10.67% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 88920941 # Type of FU issued -system.cpu1.iq.rate 0.214890 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7914336 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.089004 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 303501191 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 76636250 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 54272980 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15357 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8072 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6822 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96812856 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8152 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 352971 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 65019700 # Type of FU issued +system.cpu1.iq.rate 0.350988 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 3310600 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.050917 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 207206368 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 72837982 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 50730101 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11167 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5978 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5058 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 68311542 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5863 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 343642 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2867339 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 4206 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17562 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1118674 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2877094 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3994 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17361 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1094953 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31965666 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 675765 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 11606945 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 675630 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2189713 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 26359334 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 362918 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 63155083 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 115853 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 12847707 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8121662 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 886435 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 65883 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4133 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17562 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 204959 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 158107 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 363066 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 87182630 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43355393 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1738311 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2178040 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 10295917 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 191116 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 59545170 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 114100 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 11835207 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7683859 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 664311 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 56460 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4454 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17361 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 204103 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 160517 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 364620 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 63283569 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 21990431 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1736131 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 103734 # number of nop insts executed -system.cpu1.iew.exec_refs 50641864 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7379983 # Number of branches executed -system.cpu1.iew.exec_stores 7286471 # Number of stores executed -system.cpu1.iew.exec_rate 0.210689 # Inst execution rate -system.cpu1.iew.wb_sent 86418752 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 54279802 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30301489 # num instructions producing a value -system.cpu1.iew.wb_consumers 53896999 # num instructions consuming a value +system.cpu1.iew.exec_nop 118171 # number of nop insts executed +system.cpu1.iew.exec_refs 28863200 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6787528 # Number of branches executed +system.cpu1.iew.exec_stores 6872769 # Number of stores executed +system.cpu1.iew.exec_rate 0.341616 # Inst execution rate +system.cpu1.iew.wb_sent 62514610 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 50735159 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 28199774 # num instructions producing a value +system.cpu1.iew.wb_consumers 51433237 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131175 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.562211 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.273877 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.548279 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13446942 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 899338 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 317124 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 115426828 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.426339 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.379011 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13377367 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 714708 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 317605 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 71539285 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.639790 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.672504 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 97406330 84.39% 84.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 9593486 8.31% 92.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2169699 1.88% 94.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1301842 1.13% 95.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 990133 0.86% 96.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 584983 0.51% 97.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1011097 0.88% 97.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 533551 0.46% 98.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1835707 1.59% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 55665383 77.81% 77.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 7811223 10.92% 88.73% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2101815 2.94% 91.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1189986 1.66% 93.33% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 946066 1.32% 94.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 613597 0.86% 95.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 912617 1.28% 96.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 531458 0.74% 97.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1767140 2.47% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 115426828 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38871006 # Number of instructions committed -system.cpu1.commit.committedOps 49210952 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 71539285 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 36096592 # Number of instructions committed +system.cpu1.commit.committedOps 45770088 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16983356 # Number of memory references committed -system.cpu1.commit.loads 9980368 # Number of loads committed -system.cpu1.commit.membars 195496 # Number of memory barriers committed -system.cpu1.commit.branches 6424614 # Number of branches committed -system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43923604 # Number of committed integer instructions. -system.cpu1.commit.function_calls 553281 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1835707 # number cycles where commit BW limit reached +system.cpu1.commit.refs 15547019 # Number of memory references committed +system.cpu1.commit.loads 8958113 # Number of loads committed +system.cpu1.commit.membars 191016 # Number of memory barriers committed +system.cpu1.commit.branches 5856523 # Number of branches committed +system.cpu1.commit.fp_insts 5022 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 40800338 # Number of committed integer instructions. +system.cpu1.commit.function_calls 520894 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1767140 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 175182622 # The number of ROB reads -system.cpu1.rob.rob_writes 127588630 # The number of ROB writes -system.cpu1.timesIdled 1428402 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 296180382 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4796803337 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38801367 # Number of Instructions Simulated -system.cpu1.committedOps 49141313 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38801367 # Number of Instructions Simulated -system.cpu1.cpi 10.664493 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.664493 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.093769 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.093769 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 391717330 # number of integer regfile reads -system.cpu1.int_regfile_writes 56386728 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5093 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2344 # number of floating regfile writes -system.cpu1.misc_regfile_reads 202967536 # number of misc regfile reads -system.cpu1.misc_regfile_writes 722997 # number of misc regfile writes -system.cpu1.icache.tags.replacements 614130 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.669942 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 7060189 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 614642 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 11.486669 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 74938249500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.669942 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973965 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973965 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 127901171 # The number of ROB reads +system.cpu1.rob.rob_writes 120555711 # The number of ROB writes +system.cpu1.timesIdled 777241 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 111530457 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5026003021 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 36015814 # Number of Instructions Simulated +system.cpu1.committedOps 45689310 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 36015814 # Number of Instructions Simulated +system.cpu1.cpi 5.143512 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 5.143512 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.194420 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.194420 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 292255401 # number of integer regfile reads +system.cpu1.int_regfile_writes 53047565 # number of integer regfile writes +system.cpu1.fp_regfile_reads 3797 # number of floating regfile reads +system.cpu1.fp_regfile_writes 1766 # number of floating regfile writes +system.cpu1.misc_regfile_reads 133121160 # number of misc regfile reads +system.cpu1.misc_regfile_writes 545345 # number of misc regfile writes +system.cpu1.icache.tags.replacements 600500 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.750005 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 6745926 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 601012 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 11.224278 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 74974413000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.750005 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974121 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974121 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 8336018 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 8336018 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 7060189 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7060189 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7060189 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7060189 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7060189 # number of overall hits -system.cpu1.icache.overall_hits::total 7060189 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 661158 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 661158 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 661158 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 661158 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 661158 # number of overall misses -system.cpu1.icache.overall_misses::total 661158 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8979670253 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8979670253 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8979670253 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8979670253 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8979670253 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8979670253 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7721347 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7721347 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7721347 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7721347 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7721347 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7721347 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085627 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.085627 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085627 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.085627 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085627 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.085627 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13581.731225 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13581.731225 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13581.731225 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13581.731225 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13581.731225 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13581.731225 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 3157 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 541 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 208 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 7994182 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 7994182 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 6745926 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6745926 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6745926 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6745926 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 6745926 # number of overall hits +system.cpu1.icache.overall_hits::total 6745926 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 647211 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 647211 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 647211 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 647211 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 647211 # number of overall misses +system.cpu1.icache.overall_misses::total 647211 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8801556837 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8801556837 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8801556837 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8801556837 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8801556837 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8801556837 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7393137 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7393137 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7393137 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7393137 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7393137 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7393137 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.087542 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.087542 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.087542 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.087542 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.087542 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.087542 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13599.207734 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13599.207734 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13599.207734 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13599.207734 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13599.207734 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13599.207734 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 3107 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 341 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 199 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.177885 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 541 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.613065 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 341 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46487 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 46487 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 46487 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 46487 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 46487 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 46487 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 614671 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 614671 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 614671 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 614671 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 614671 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 614671 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7323309836 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7323309836 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7323309836 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7323309836 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7323309836 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7323309836 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3568000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3568000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3568000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3568000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079607 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079607 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079607 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.079607 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079607 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.079607 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11914.194481 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11914.194481 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11914.194481 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11914.194481 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11914.194481 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11914.194481 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46165 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 46165 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 46165 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 46165 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 46165 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 46165 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 601046 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 601046 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 601046 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 601046 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 601046 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 601046 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7178040035 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7178040035 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7178040035 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7178040035 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7178040035 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7178040035 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3605250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3605250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3605250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 3605250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081298 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.081298 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.081298 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.081298 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.081298 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.081298 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11942.580160 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11942.580160 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11942.580160 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11942.580160 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11942.580160 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11942.580160 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 363457 # number of replacements -system.cpu1.dcache.tags.tagsinuse 485.510277 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 13025047 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 363822 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.800603 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 70981354000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.510277 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948262 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.948262 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 365 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 60307713 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 60307713 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 8518372 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8518372 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4270609 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4270609 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 99866 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 99866 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97035 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 97035 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12788981 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12788981 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12788981 # number of overall hits -system.cpu1.dcache.overall_hits::total 12788981 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 402659 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 402659 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1566002 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1566002 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14224 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14224 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10931 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10931 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1968661 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1968661 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1968661 # number of overall misses -system.cpu1.dcache.overall_misses::total 1968661 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6122123976 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6122123976 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 79209493026 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 79209493026 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131211992 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 131211992 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58251087 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 58251087 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 85331617002 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 85331617002 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 85331617002 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 85331617002 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8921031 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8921031 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5836611 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5836611 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 114090 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 114090 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107966 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 107966 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14757642 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14757642 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14757642 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14757642 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045136 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045136 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.268307 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.268307 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124674 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124674 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101245 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101245 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.133399 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.133399 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.133399 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.133399 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15204.239756 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15204.239756 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 50580.710003 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 50580.710003 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9224.690101 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9224.690101 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5328.980606 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5328.980606 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 43345.003026 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 43345.003026 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 43345.003026 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 43345.003026 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 29359 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 20069 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3274 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 177 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.967318 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 113.384181 # average number of cycles each access was blocked +system.cpu1.dcache.tags.replacements 339082 # number of replacements +system.cpu1.dcache.tags.tagsinuse 482.965075 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 12423447 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 339594 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 36.583235 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 71024759250 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 482.965075 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.943291 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.943291 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 57544569 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 57544569 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 8247311 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8247311 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3935666 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3935666 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94453 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 94453 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 92037 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 92037 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12182977 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12182977 # 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number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1901363 # number of overall misses +system.cpu1.dcache.overall_misses::total 1901363 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6052529769 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6052529769 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 75305143416 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 75305143416 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 124772740 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 124772740 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 57202570 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 57202570 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 81357673185 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 81357673185 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 81357673185 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 81357673185 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8647347 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8647347 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5436993 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5436993 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 108095 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 108095 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102795 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 102795 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14084340 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14084340 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14084340 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14084340 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.046261 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.046261 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.276132 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.276132 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126204 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126204 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104655 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104655 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134998 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.134998 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134998 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.134998 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15129.962726 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15129.962726 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 50159.054900 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 50159.054900 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9146.220496 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9146.220496 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5317.212307 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5317.212307 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42789.132420 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 42789.132420 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42789.132420 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 42789.132420 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 27478 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 17677 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3226 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 175 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.517669 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 101.011429 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 327725 # number of writebacks -system.cpu1.dcache.writebacks::total 327725 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171279 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 171279 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1402802 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1402802 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1455 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1455 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1574081 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1574081 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1574081 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1574081 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231380 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 231380 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163200 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 163200 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12769 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12769 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10931 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10931 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 394580 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 394580 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 394580 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 394580 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2885564133 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2885564133 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7076211500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7076211500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89844256 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89844256 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36388913 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36388913 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9961775633 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9961775633 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9961775633 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9961775633 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169230997009 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169230997009 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25854670209 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25854670209 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195085667218 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195085667218 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025936 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025936 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027961 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027961 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111920 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111920 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101245 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101245 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026737 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026737 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026737 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026737 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12471.104387 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12471.104387 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43359.139093 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 43359.139093 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7036.123111 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7036.123111 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3328.964688 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3328.964688 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25246.529558 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25246.529558 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25246.529558 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25246.529558 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 304166 # number of writebacks +system.cpu1.dcache.writebacks::total 304166 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172051 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 172051 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1358464 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1358464 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1244 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1244 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1530515 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1530515 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1530515 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1530515 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227985 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 227985 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 142863 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 142863 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12398 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12398 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10758 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10758 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 370848 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 370848 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 370848 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 370848 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2835218608 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2835218608 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5632564954 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5632564954 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86730259 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86730259 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 35684430 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 35684430 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8467783562 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8467783562 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8467783562 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8467783562 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 62130810008 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 62130810008 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25850406364 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25850406364 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 87981216372 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 87981216372 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026365 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026365 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026276 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026276 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.114695 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.114695 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104655 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104655 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026331 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026331 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026331 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026331 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12435.987490 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12435.987490 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39426.338198 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39426.338198 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6995.504033 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6995.504033 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3317.013385 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3317.013385 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22833.569446 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22833.569446 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22833.569446 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22833.569446 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2701,18 +2239,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1519280505301 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1519280505301 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1519280505301 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1519280505301 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1737834287366 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1737834287366 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1737834287366 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1737834287366 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 42637 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 45161 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 50394 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 47884 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 2c40bbbf1..0d3018ad7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.526127 # Number of seconds simulated -sim_ticks 2526126762000 # Number of ticks simulated -final_tick 2526126762000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.526170 # Number of seconds simulated +sim_ticks 2526169857500 # Number of ticks simulated +final_tick 2526169857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60304 # Simulator instruction rate (inst/s) -host_op_rate 77594 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2525902204 # Simulator tick rate (ticks/s) -host_mem_usage 424400 # Number of bytes of host memory used -host_seconds 1000.09 # Real time elapsed on the host -sim_insts 60309150 # Number of instructions simulated -sim_ops 77600646 # Number of ops (including micro ops) simulated +host_inst_rate 58326 # Simulator instruction rate (inst/s) +host_op_rate 75048 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2443063970 # Simulator tick rate (ticks/s) +host_mem_usage 467448 # Number of bytes of host memory used +host_seconds 1034.02 # Real time elapsed on the host +sim_insts 60309637 # Number of instructions simulated +sim_ops 77601213 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093912 # Number of bytes read from this memory -system.physmem.bytes_read::total 129432344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 797632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9095320 # Number of bytes read from this memory +system.physmem.bytes_read::total 129433624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785024 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799624 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801096 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 43 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12467 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142128 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096848 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12463 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142150 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096868 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59141 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47320533 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1089 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813159 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47319725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1140 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3599943 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51237470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1497768 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1193951 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2691719 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1497768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47320533 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1089 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3600439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51237103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315748 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315748 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1193931 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2692256 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47319725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1140 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4793894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53929189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096848 # Number of read requests accepted -system.physmem.writeReqs 813136 # Number of write requests accepted -system.physmem.readBursts 15096848 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813136 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 963809856 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2388416 # Total number of bytes read from write queue -system.physmem.bytesWritten 6900096 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 129432344 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6799624 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 37319 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 705316 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4693 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943581 # Per bank write bursts -system.physmem.perBankRdBursts::1 943177 # Per bank write bursts -system.physmem.perBankRdBursts::2 939217 # Per bank write bursts -system.physmem.perBankRdBursts::3 939246 # Per bank write bursts -system.physmem.perBankRdBursts::4 943119 # Per bank write bursts -system.physmem.perBankRdBursts::5 943143 # Per bank write bursts -system.physmem.perBankRdBursts::6 939192 # Per bank write bursts -system.physmem.perBankRdBursts::7 938854 # Per bank write bursts -system.physmem.perBankRdBursts::8 943994 # Per bank write bursts -system.physmem.perBankRdBursts::9 943547 # Per bank write bursts -system.physmem.perBankRdBursts::10 939009 # Per bank write bursts -system.physmem.perBankRdBursts::11 937977 # Per bank write bursts -system.physmem.perBankRdBursts::12 943925 # Per bank write bursts -system.physmem.perBankRdBursts::13 943586 # Per bank write bursts -system.physmem.perBankRdBursts::14 939160 # Per bank write bursts -system.physmem.perBankRdBursts::15 938802 # Per bank write bursts -system.physmem.perBankWrBursts::0 6706 # Per bank write bursts -system.physmem.perBankWrBursts::1 6463 # Per bank write bursts -system.physmem.perBankWrBursts::2 6599 # Per bank write bursts -system.physmem.perBankWrBursts::3 6631 # Per bank write bursts -system.physmem.perBankWrBursts::4 6542 # Per bank write bursts -system.physmem.perBankWrBursts::5 6795 # Per bank write bursts -system.physmem.perBankWrBursts::6 6787 # Per bank write bursts -system.physmem.perBankWrBursts::7 6728 # Per bank write bursts -system.physmem.perBankWrBursts::8 7129 # Per bank write bursts -system.physmem.perBankWrBursts::9 6879 # Per bank write bursts -system.physmem.perBankWrBursts::10 6534 # Per bank write bursts -system.physmem.perBankWrBursts::11 6185 # Per bank write bursts -system.physmem.perBankWrBursts::12 7139 # Per bank write bursts -system.physmem.perBankWrBursts::13 6761 # Per bank write bursts -system.physmem.perBankWrBursts::14 7032 # Per bank write bursts -system.physmem.perBankWrBursts::15 6904 # Per bank write bursts +system.physmem.bw_total::cpu.inst 315748 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4794370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53929359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096868 # Number of read requests accepted +system.physmem.writeReqs 813159 # Number of write requests accepted +system.physmem.readBursts 15096868 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813159 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 960809152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5390400 # Total number of bytes read from write queue +system.physmem.bytesWritten 6824768 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129433624 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6801096 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 84225 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706499 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943297 # Per bank write bursts +system.physmem.perBankRdBursts::1 937033 # Per bank write bursts +system.physmem.perBankRdBursts::2 936962 # Per bank write bursts +system.physmem.perBankRdBursts::3 936535 # Per bank write bursts +system.physmem.perBankRdBursts::4 942693 # Per bank write bursts +system.physmem.perBankRdBursts::5 936569 # Per bank write bursts +system.physmem.perBankRdBursts::6 936319 # Per bank write bursts +system.physmem.perBankRdBursts::7 936043 # Per bank write bursts +system.physmem.perBankRdBursts::8 943596 # Per bank write bursts +system.physmem.perBankRdBursts::9 936992 # Per bank write bursts +system.physmem.perBankRdBursts::10 936414 # Per bank write bursts +system.physmem.perBankRdBursts::11 935912 # Per bank write bursts +system.physmem.perBankRdBursts::12 943556 # Per bank write bursts +system.physmem.perBankRdBursts::13 937007 # Per bank write bursts +system.physmem.perBankRdBursts::14 937039 # Per bank write bursts +system.physmem.perBankRdBursts::15 936676 # Per bank write bursts +system.physmem.perBankWrBursts::0 6606 # Per bank write bursts +system.physmem.perBankWrBursts::1 6375 # Per bank write bursts +system.physmem.perBankWrBursts::2 6521 # Per bank write bursts +system.physmem.perBankWrBursts::3 6552 # Per bank write bursts +system.physmem.perBankWrBursts::4 6461 # Per bank write bursts +system.physmem.perBankWrBursts::5 6711 # Per bank write bursts +system.physmem.perBankWrBursts::6 6720 # Per bank write bursts +system.physmem.perBankWrBursts::7 6668 # Per bank write bursts +system.physmem.perBankWrBursts::8 7045 # Per bank write bursts +system.physmem.perBankWrBursts::9 6826 # Per bank write bursts +system.physmem.perBankWrBursts::10 6497 # Per bank write bursts +system.physmem.perBankWrBursts::11 6136 # Per bank write bursts +system.physmem.perBankWrBursts::12 7072 # Per bank write bursts +system.physmem.perBankWrBursts::13 6672 # Per bank write bursts +system.physmem.perBankWrBursts::14 6956 # Per bank write bursts +system.physmem.perBankWrBursts::15 6819 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2526125654500 # Total gap between requests +system.physmem.totGap 2526168741500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 38 # Read request sizes (log2) system.physmem.readPktSize::3 14942208 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154602 # Read request sizes (log2) +system.physmem.readPktSize::6 154622 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59118 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1175583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1121241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1077080 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3628602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2607512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2594359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2599949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 53287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 57711 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 21124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20900 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20768 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 91 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59141 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1044851 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 985737 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 938636 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 947948 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 933228 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 933834 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2717841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2709185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3589675 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 37568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 33871 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 34960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 32201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 30053 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 21726 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 21191 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -144,619 +144,147 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 85983 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11289.547748 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1006.032615 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16787.302098 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23431 27.25% 27.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14045 16.33% 43.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2670 3.11% 46.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2200 2.56% 49.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1296 1.51% 50.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1149 1.34% 52.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 926 1.08% 53.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 910 1.06% 54.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 583 0.68% 54.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 573 0.67% 55.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 527 0.61% 56.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 540 0.63% 56.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 283 0.33% 57.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 315 0.37% 57.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 148 0.17% 57.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 512 0.60% 58.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 103 0.12% 58.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 143 0.17% 58.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 77 0.09% 58.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 250 0.29% 58.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 57 0.07% 59.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 507 0.59% 59.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 36 0.04% 59.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 193 0.22% 59.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 17 0.02% 59.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 103 0.12% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 71 0.08% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 17 0.02% 60.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 58 0.07% 60.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 16 0.02% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 468 0.54% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 10 0.01% 60.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 32 0.04% 60.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 249 0.29% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 8 0.01% 61.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 28 0.03% 61.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 7 0.01% 61.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 30 0.03% 61.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 8 0.01% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 18 0.02% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 6 0.01% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 116 0.13% 61.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 10 0.01% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 18 0.02% 61.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 4 0.00% 61.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 420 0.49% 61.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 24 0.03% 61.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 6 0.01% 61.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 25 0.03% 61.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 6 0.01% 61.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 21 0.02% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 6 0.01% 62.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 157 0.18% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 5 0.01% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 17 0.02% 62.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 9 0.01% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 20 0.02% 62.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 11 0.01% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 15 0.02% 62.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 13 0.02% 62.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 363 0.42% 62.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 9 0.01% 62.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 13 0.02% 62.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 7 0.01% 62.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 108 0.13% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 18 0.02% 62.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 14 0.02% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 12 0.01% 62.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 161 0.19% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 8 0.01% 63.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 15 0.02% 63.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 23 0.03% 63.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 6 0.01% 63.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 14 0.02% 63.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 4 0.00% 63.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 356 0.41% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 11 0.01% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 11 0.01% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 163 0.19% 63.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 2 0.00% 63.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 16 0.02% 63.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 2 0.00% 63.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 50 0.06% 63.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 6 0.01% 63.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 13 0.02% 63.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 4 0.00% 63.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 197 0.23% 64.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 3 0.00% 64.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 9 0.01% 64.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 7 0.01% 64.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 223 0.26% 64.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 4 0.00% 64.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 13 0.02% 64.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 5 0.01% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 140 0.16% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 2 0.00% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 8 0.01% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 2 0.00% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 88 0.10% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 2 0.00% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 3 0.00% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 158 0.18% 64.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 6 0.01% 64.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 14 0.02% 64.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 1 0.00% 64.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 345 0.40% 65.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 1 0.00% 65.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 5 0.01% 65.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 8 0.01% 65.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 13 0.02% 65.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 4 0.00% 65.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 18 0.02% 65.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 6 0.01% 65.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 141 0.16% 65.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 2 0.00% 65.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 6 0.01% 65.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 41 0.05% 65.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 2 0.00% 65.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 10 0.01% 65.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 399 0.46% 66.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 36 0.04% 66.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8583 2 0.00% 66.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 130 0.15% 66.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8903 2 0.00% 66.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 5 0.01% 66.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 1 0.00% 66.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 341 0.40% 66.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9351 3 0.00% 66.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 145 0.17% 66.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9543 1 0.00% 66.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9607 2 0.00% 66.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 78 0.09% 67.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9799 2 0.00% 67.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9863 3 0.00% 67.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 133 0.15% 67.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10055 2 0.00% 67.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 3 0.00% 67.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 212 0.25% 67.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10375 2 0.00% 67.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 150 0.17% 67.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10695 1 0.00% 67.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 41 0.05% 67.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10887 1 0.00% 67.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10951 2 0.00% 67.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 153 0.18% 67.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 4 0.00% 67.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 349 0.41% 68.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 8 0.01% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11655 3 0.00% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 141 0.16% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11911 3 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 94 0.11% 68.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12103 2 0.00% 68.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12167 4 0.00% 68.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 334 0.39% 68.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12359 1 0.00% 68.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 13 0.02% 68.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12679 3 0.00% 68.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12743 1 0.00% 68.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 141 0.16% 69.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 6 0.01% 69.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13127 1 0.00% 69.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 2 0.00% 69.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 399 0.46% 69.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13376-13383 1 0.00% 69.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13447 1 0.00% 69.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 94 0.11% 69.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13767 2 0.00% 69.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 2 0.00% 69.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13959 3 0.00% 69.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14023 1 0.00% 69.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 214 0.25% 69.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14151 2 0.00% 69.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 4 0.00% 69.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14279 1 0.00% 69.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 420 0.49% 70.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 5 0.01% 70.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14727 1 0.00% 70.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 22 0.03% 70.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 141 0.16% 70.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15175 1 0.00% 70.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 1 0.00% 70.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 335 0.39% 71.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15495 1 0.00% 71.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 80 0.09% 71.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15815 2 0.00% 71.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 5 0.01% 71.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15943 2 0.00% 71.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16007 2 0.00% 71.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16071 1 0.00% 71.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 143 0.17% 71.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16263 6 0.01% 71.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 673 0.78% 72.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16519 1 0.00% 72.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 144 0.17% 72.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 7 0.01% 72.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16967 2 0.00% 72.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 81 0.09% 72.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17287 2 0.00% 72.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 336 0.39% 72.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17543 2 0.00% 72.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 135 0.16% 72.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17735 1 0.00% 72.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17792-17799 4 0.00% 72.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 25 0.03% 72.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18048-18055 1 0.00% 72.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18112-18119 1 0.00% 72.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 6 0.01% 72.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 1 0.00% 72.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 2 0.00% 72.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 419 0.49% 73.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18560-18567 2 0.00% 73.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 214 0.25% 73.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18752-18759 1 0.00% 73.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 4 0.00% 73.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 97 0.11% 73.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19264-19271 2 0.00% 73.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 2 0.00% 73.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 391 0.45% 74.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19591 1 0.00% 74.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 10 0.01% 74.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19840-19847 3 0.00% 74.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19904-19911 1 0.00% 74.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 139 0.16% 74.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20032-20039 1 0.00% 74.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20160-20167 2 0.00% 74.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 13 0.02% 74.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 4 0.00% 74.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 331 0.38% 74.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20608-20615 1 0.00% 74.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20672-20679 1 0.00% 74.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 94 0.11% 75.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20800-20807 1 0.00% 75.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20864-20871 1 0.00% 75.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20928-20935 2 0.00% 75.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 142 0.17% 75.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21120-21127 2 0.00% 75.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 13 0.02% 75.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 2 0.00% 75.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 343 0.40% 75.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21632-21639 3 0.00% 75.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21696-21703 1 0.00% 75.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 150 0.17% 75.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 1 0.00% 75.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21952-21959 1 0.00% 75.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 38 0.04% 75.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22080-22087 1 0.00% 75.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22144-22151 3 0.00% 75.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 148 0.17% 76.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 2 0.00% 76.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22464-22471 1 0.00% 76.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 208 0.24% 76.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22656-22663 1 0.00% 76.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22720-22727 2 0.00% 76.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 129 0.15% 76.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 76 0.09% 76.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23104-23111 1 0.00% 76.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23168-23175 2 0.00% 76.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 148 0.17% 76.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23424-23431 1 0.00% 76.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23488-23495 1 0.00% 76.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 338 0.39% 77.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 10 0.01% 77.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23936-23943 2 0.00% 77.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 128 0.15% 77.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24128-24135 1 0.00% 77.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24256-24263 2 0.00% 77.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 34 0.04% 77.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24448-24455 4 0.00% 77.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24512-24519 1 0.00% 77.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 281 0.33% 77.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24640-24647 2 0.00% 77.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24704-24711 3 0.00% 77.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24768-24775 1 0.00% 77.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 36 0.04% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24960-24967 1 0.00% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 132 0.15% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25152-25159 1 0.00% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25216-25223 1 0.00% 77.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 9 0.01% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 2 0.00% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25536-25543 1 0.00% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 331 0.38% 78.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25792-25799 1 0.00% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 146 0.17% 78.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25920-25927 1 0.00% 78.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25984-25991 1 0.00% 78.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 78 0.09% 78.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26240-26247 2 0.00% 78.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26304-26311 1 0.00% 78.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 128 0.15% 78.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 6 0.01% 78.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 207 0.24% 78.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26688-26695 1 0.00% 78.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26752-26759 3 0.00% 78.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26816-26823 1 0.00% 78.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 146 0.17% 79.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26944-26951 3 0.00% 79.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27008-27015 1 0.00% 79.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 38 0.04% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27264-27271 1 0.00% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 151 0.18% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27463 1 0.00% 79.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27584-27591 2 0.00% 79.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 337 0.39% 79.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27712-27719 1 0.00% 79.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27840-27847 2 0.00% 79.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 13 0.02% 79.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27968-27975 1 0.00% 79.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 141 0.16% 79.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28224-28231 1 0.00% 79.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28288-28295 1 0.00% 79.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 97 0.11% 79.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 5 0.01% 79.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28608-28615 4 0.00% 79.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 328 0.38% 80.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28800-28807 1 0.00% 80.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28864-28871 1 0.00% 80.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 12 0.01% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29056-29063 2 0.00% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 141 0.16% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 7 0.01% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29575 3 0.00% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 399 0.46% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 90 0.10% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30144-30151 2 0.00% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 5 0.01% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30400-30407 1 0.00% 81.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 214 0.25% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30528-30535 1 0.00% 81.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 3 0.00% 81.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 415 0.48% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30848-30855 2 0.00% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 5 0.01% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31040-31047 1 0.00% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31111 1 0.00% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31168-31175 3 0.00% 81.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 21 0.02% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31367 2 0.00% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31424-31431 1 0.00% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 138 0.16% 82.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 3 0.00% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 338 0.39% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31872-31879 2 0.00% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31936-31943 1 0.00% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 78 0.09% 82.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32192-32199 1 0.00% 82.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 9 0.01% 82.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32384-32391 1 0.00% 82.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32448-32455 2 0.00% 82.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 145 0.17% 82.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32576-32583 1 0.00% 82.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32640-32647 1 0.00% 82.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 671 0.78% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32960-32967 1 0.00% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 141 0.16% 83.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 7 0.01% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33344-33351 1 0.00% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 4 0.00% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 85 0.10% 83.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33607 2 0.00% 83.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33671 1 0.00% 83.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33735 1 0.00% 83.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 348 0.40% 84.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 136 0.16% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 21 0.02% 84.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34432-34439 3 0.00% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34496-34503 2 0.00% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 8 0.01% 84.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34688-34695 2 0.00% 84.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 412 0.48% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 212 0.25% 85.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 5 0.01% 85.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35456-35463 3 0.00% 85.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 91 0.11% 85.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 392 0.46% 85.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35904-35911 1 0.00% 85.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35968-35975 2 0.00% 85.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 8 0.01% 85.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 140 0.16% 85.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36480-36487 4 0.00% 85.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36544-36551 1 0.00% 85.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 12 0.01% 85.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 327 0.38% 86.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36928-36935 1 0.00% 86.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 90 0.10% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37312-37319 1 0.00% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 141 0.16% 86.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37440-37447 1 0.00% 86.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37511 3 0.00% 86.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 10 0.01% 86.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37696-37703 1 0.00% 86.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37760-37767 1 0.00% 86.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 334 0.39% 86.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38080-38087 1 0.00% 86.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 149 0.17% 87.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38272-38279 1 0.00% 87.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 37 0.04% 87.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 2 0.00% 87.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 150 0.17% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38784-38791 1 0.00% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 205 0.24% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 127 0.15% 87.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 76 0.09% 87.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 2 0.00% 87.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39616-39623 1 0.00% 87.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 146 0.17% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 330 0.38% 88.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40000-40007 1 0.00% 88.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40064-40071 1 0.00% 88.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 7 0.01% 88.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40384-40391 1 0.00% 88.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 132 0.15% 88.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40576-40583 4 0.00% 88.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 37 0.04% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40896-40903 1 0.00% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 277 0.32% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41088-41095 1 0.00% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41152-41159 1 0.00% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 34 0.04% 88.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 128 0.15% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41600-41607 1 0.00% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 10 0.01% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41856-41863 1 0.00% 89.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41920-41927 1 0.00% 89.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 332 0.39% 89.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 142 0.17% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42432-42439 1 0.00% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 76 0.09% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42624-42631 2 0.00% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 131 0.15% 89.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42816-42823 1 0.00% 89.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42880-42887 2 0.00% 89.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 208 0.24% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 145 0.17% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43392-43399 1 0.00% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43456-43463 1 0.00% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 36 0.04% 90.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 2 0.00% 90.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 152 0.18% 90.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43840-43847 1 0.00% 90.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 340 0.40% 90.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44160-44167 1 0.00% 90.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 1 0.00% 90.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 8 0.01% 91.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44416-44423 2 0.00% 91.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 144 0.17% 91.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44608-44615 2 0.00% 91.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 94 0.11% 91.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 328 0.38% 91.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45191 3 0.00% 91.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 12 0.01% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45376-45383 1 0.00% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 141 0.16% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45632-45639 1 0.00% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 1 0.00% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45760-45767 1 0.00% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 11 0.01% 91.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45952-45959 1 0.00% 91.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 393 0.46% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 91 0.11% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46528-46535 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 4 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 211 0.25% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47040-47047 2 0.00% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 416 0.48% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47239 1 0.00% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 4 0.00% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47488-47495 2 0.00% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47552-47559 1 0.00% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 32 0.04% 93.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 1 0.00% 93.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47808-47815 2 0.00% 93.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 141 0.16% 93.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 335 0.39% 93.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48192-48199 1 0.00% 93.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 74 0.09% 93.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 4 0.00% 93.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 71 0.08% 93.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 140 0.16% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 4 0.00% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5017 5.83% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49280-49287 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49792-49799 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50304-50311 3 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50368-50375 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50432-50439 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50560-50567 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50695 4 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50880-50887 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51008-51015 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51136-51143 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51207 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51328-51335 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 85983 # Bytes accessed per row activation -system.physmem.totQLat 365185132750 # Total ticks spent queuing -system.physmem.totMemAccLat 457949856500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 75297645000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17467078750 # Total ticks spent accessing banks -system.physmem.avgQLat 24249.44 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1159.87 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 949853 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 1012.832967 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 998.129194 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 95.600820 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 4614 0.49% 0.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 3555 0.37% 0.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1868 0.20% 1.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1270 0.13% 1.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 998 0.11% 1.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 697 0.07% 1.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 628 0.07% 1.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 802 0.08% 1.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 935421 98.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 949853 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5541 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2709.372676 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 121858.968991 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 5537 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.04% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5541 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5541 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.245082 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.302826 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.619957 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3691 66.61% 66.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 16 0.29% 66.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 178 3.21% 70.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1008 18.19% 88.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 44 0.79% 89.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 25 0.45% 89.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 20 0.36% 89.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 16 0.29% 90.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 5 0.09% 90.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.04% 90.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.02% 90.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.02% 90.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.02% 90.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 2 0.04% 90.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 1 0.02% 90.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 143 2.58% 93.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 305 5.50% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 21 0.38% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 14 0.25% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 20 0.36% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 15 0.27% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 5 0.09% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 3 0.05% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 3 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5541 # Writes before turning the bus around for reads +system.physmem.totQLat 571195583500 # Total ticks spent queuing +system.physmem.totMemAccLat 674382869750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75063215000 # Total ticks spent in databus transfers +system.physmem.totBankLat 28124071250 # Total ticks spent accessing banks +system.physmem.avgQLat 38047.64 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1873.36 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30409.31 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.54 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44921.00 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.34 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.00 # Data bus utilization in percentage -system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads +system.physmem.busUtil 2.99 # Data bus utilization in percentage +system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.56 # Average write queue length when enqueuing -system.physmem.readRowHits 14988012 # Number of row buffer hits during reads -system.physmem.writeRowHits 93348 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.58 # Row buffer hit rate for writes -system.physmem.avgGap 158776.13 # Average gap between requests -system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 2.53 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.avgRdQLen 7.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.53 # Average write queue length when enqueuing +system.physmem.readRowHits 14041195 # Number of row buffer hits during reads +system.physmem.writeRowHits 91389 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.68 # Row buffer hit rate for writes +system.physmem.avgGap 158778.41 # Average gap between requests +system.physmem.pageHitRate 93.47 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.34 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -769,58 +297,58 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54878485 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149469 # Transaction distribution -system.membus.trans_dist::ReadResp 16149469 # Transaction distribution +system.membus.throughput 54878638 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149508 # Transaction distribution +system.membus.trans_dist::ReadResp 16149508 # Transaction distribution system.membus.trans_dist::WriteReq 763349 # Transaction distribution system.membus.trans_dist::WriteResp 763349 # Transaction distribution -system.membus.trans_dist::Writeback 59118 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4690 # Transaction distribution +system.membus.trans_dist::Writeback 59141 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4693 # Transaction distribution -system.membus.trans_dist::ReadExReq 131452 # Transaction distribution -system.membus.trans_dist::ReadExResp 131452 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution +system.membus.trans_dist::ReadExReq 131433 # Transaction distribution +system.membus.trans_dist::ReadExResp 131433 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885820 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272628 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885845 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272653 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34157044 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34157069 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694304 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092346 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16697056 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19095098 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138630010 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138630010 # Total data (bytes) +system.membus.tot_pkt_size::total 138632762 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138632762 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486866000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487078000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3686500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3653000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17361359500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17362845500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4731205438 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4737809043 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33737720957 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.membus.respLayer2.occupancy 37210156152 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48266825 # Throughput (bytes/s) +system.iobus.throughput 48266001 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16125556 # Transaction distribution system.iobus.trans_dist::ReadResp 16125556 # Transaction distribution system.iobus.trans_dist::WriteReq 8174 # Transaction distribution @@ -930,18 +458,18 @@ system.iobus.reqLayer25.occupancy 14942208000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374870000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40922322043 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) +system.iobus.respLayer1.occupancy 37245686848 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14743416 # Number of BP lookups -system.cpu.branchPred.condPredicted 11827380 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704687 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9504018 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7655579 # Number of BTB hits +system.cpu.branchPred.lookups 14755327 # Number of BP lookups +system.cpu.branchPred.condPredicted 11837490 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 706705 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9530563 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7665782 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.550973 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1397368 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72480 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.433674 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1400618 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72971 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -965,25 +493,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51180405 # DTB read hits -system.cpu.dtb.read_misses 65067 # DTB read misses -system.cpu.dtb.write_hits 11700451 # DTB write hits -system.cpu.dtb.write_misses 15748 # DTB write misses +system.cpu.dtb.read_hits 51187284 # DTB read hits +system.cpu.dtb.read_misses 65383 # DTB read misses +system.cpu.dtb.write_hits 11703682 # DTB write hits +system.cpu.dtb.write_misses 15916 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3477 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2401 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 399 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3484 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2464 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1377 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51245472 # DTB read accesses -system.cpu.dtb.write_accesses 11716199 # DTB write accesses +system.cpu.dtb.perms_faults 1363 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51252667 # DTB read accesses +system.cpu.dtb.write_accesses 11719598 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62880856 # DTB hits -system.cpu.dtb.misses 80815 # DTB misses -system.cpu.dtb.accesses 62961671 # DTB accesses +system.cpu.dtb.hits 62890966 # DTB hits +system.cpu.dtb.misses 81299 # DTB misses +system.cpu.dtb.accesses 62972265 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1005,8 +533,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 11521970 # ITB inst hits -system.cpu.itb.inst_misses 11115 # ITB inst misses +system.cpu.itb.inst_hits 11527099 # ITB inst hits +system.cpu.itb.inst_misses 11249 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -1015,114 +543,114 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2502 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2504 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2960 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2978 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11533085 # ITB inst accesses -system.cpu.itb.hits 11521970 # DTB hits -system.cpu.itb.misses 11115 # DTB misses -system.cpu.itb.accesses 11533085 # DTB accesses -system.cpu.numCycles 477047952 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11538348 # ITB inst accesses +system.cpu.itb.hits 11527099 # DTB hits +system.cpu.itb.misses 11249 # DTB misses +system.cpu.itb.accesses 11538348 # DTB accesses +system.cpu.numCycles 477119451 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29756603 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90277136 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14743416 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9052947 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20141800 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4650225 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 121200 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 98195863 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2631 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87675 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2688966 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11518528 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 709932 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5147 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 154198551 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.729959 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.081572 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29745347 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90343663 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14755327 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9066400 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20160515 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4659374 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 121718 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 98274067 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2638 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 88444 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2690508 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 430 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11523637 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 709778 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5230 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 154294046 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.730147 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.081756 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 134072201 86.95% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1305405 0.85% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1710070 1.11% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2294026 1.49% 90.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2104673 1.36% 91.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1102818 0.72% 92.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2555300 1.66% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 746086 0.48% 94.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8307972 5.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 134149007 86.94% 86.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1305162 0.85% 87.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1712027 1.11% 88.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2298089 1.49% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2109453 1.37% 91.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1103374 0.72% 92.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2555030 1.66% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 746204 0.48% 94.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8315700 5.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154198551 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030906 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.189241 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31769851 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 100064901 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18067338 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1262749 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3033712 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1957542 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172175 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107250920 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 570386 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3033712 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33504513 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38619180 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 55176666 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17578446 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6286034 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102244327 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 450 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 980082 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4063460 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 782 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106315700 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 473686161 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432563323 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10440 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78727135 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27588564 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1170552 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1076872 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12591466 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19711121 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13300191 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1936389 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2436828 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95079446 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983827 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122895781 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 165904 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18895197 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47144933 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501515 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154198551 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.796997 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.515893 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 154294046 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030926 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.189352 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31777956 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 100129696 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18080387 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1265250 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3040757 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1958128 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172070 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107328179 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 570705 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3040757 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33516419 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38693091 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 55142047 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17591419 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6310313 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102323009 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 472 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1000039 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4066050 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 733 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106393961 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 474042454 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432890289 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10421 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78727775 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27666185 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1171025 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1077190 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12642564 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19725934 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13308899 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1965192 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2472766 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95138203 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1987496 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122932074 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 165549 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18954995 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47273204 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 505173 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154294046 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.796739 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.515436 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 109876529 71.26% 71.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14361592 9.31% 80.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6875815 4.46% 85.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5666847 3.68% 88.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12323021 7.99% 96.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2802995 1.82% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1694666 1.10% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 469725 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127361 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 109928517 71.25% 71.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14405522 9.34% 80.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6874407 4.46% 85.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5677816 3.68% 88.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12311103 7.98% 96.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2805861 1.82% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1693952 1.10% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 468083 0.30% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128785 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154198551 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154294046 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61834 0.70% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61713 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available @@ -1150,437 +678,436 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8368136 94.62% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413820 4.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365366 94.65% 95.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 411034 4.65% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57946622 47.15% 47.17% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93414 0.08% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52506141 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12318913 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57971139 47.16% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93360 0.08% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 25 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52513425 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12323457 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122895781 # Type of FU issued -system.cpu.iq.rate 0.257617 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8843793 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071962 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409057037 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 115975062 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85458771 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23247 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12478 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10297 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131698673 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12383 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624051 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122932074 # Type of FU issued +system.cpu.iq.rate 0.257655 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8838117 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071894 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409219406 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116097301 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85490758 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23382 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10288 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131729199 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12474 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624027 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4056444 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6518 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30236 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1568197 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4071144 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6793 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30196 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1576838 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34108054 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 680529 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107946 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 680806 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3033712 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30168583 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 433803 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97285878 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 203457 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19711121 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13300191 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1411588 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113159 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3352 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30236 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 349021 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 270487 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619508 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120819447 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51867420 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2076334 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3040757 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30225758 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434257 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97346977 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205962 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19725934 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13308899 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1415361 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3429 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30196 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 351437 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 270055 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 621492 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120854906 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51874598 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2077168 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 222605 # number of nop insts executed -system.cpu.iew.exec_refs 64079545 # number of memory reference insts executed -system.cpu.iew.exec_branches 11817660 # Number of branches executed -system.cpu.iew.exec_stores 12212125 # Number of stores executed -system.cpu.iew.exec_rate 0.253265 # Inst execution rate -system.cpu.iew.wb_sent 119878750 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85469068 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47006672 # num instructions producing a value -system.cpu.iew.wb_consumers 87538881 # num instructions consuming a value +system.cpu.iew.exec_nop 221278 # number of nop insts executed +system.cpu.iew.exec_refs 64090111 # number of memory reference insts executed +system.cpu.iew.exec_branches 11821235 # Number of branches executed +system.cpu.iew.exec_stores 12215513 # Number of stores executed +system.cpu.iew.exec_rate 0.253301 # Inst execution rate +system.cpu.iew.wb_sent 119911072 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85501046 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47029089 # num instructions producing a value +system.cpu.iew.wb_consumers 87607932 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179162 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536980 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179203 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536813 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18642428 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482312 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 534972 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151164839 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.514346 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.491788 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18687715 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482323 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 537083 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151253289 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.514049 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.489960 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122735782 81.19% 81.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14630083 9.68% 90.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3890528 2.57% 93.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2132680 1.41% 94.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1607271 1.06% 95.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 973341 0.64% 96.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1599818 1.06% 97.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 715537 0.47% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2879799 1.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 122784132 81.18% 81.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14644365 9.68% 90.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3917692 2.59% 93.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2132798 1.41% 94.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1620432 1.07% 95.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 975760 0.65% 96.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1598249 1.06% 97.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 715459 0.47% 98.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2864402 1.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151164839 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60459531 # Number of instructions committed -system.cpu.commit.committedOps 77751027 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151253289 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60460018 # Number of instructions committed +system.cpu.commit.committedOps 77751594 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386671 # Number of memory references committed -system.cpu.commit.loads 15654677 # Number of loads committed -system.cpu.commit.membars 403573 # Number of memory barriers committed -system.cpu.commit.branches 10306328 # Number of branches committed +system.cpu.commit.refs 27386851 # Number of memory references committed +system.cpu.commit.loads 15654790 # Number of loads committed +system.cpu.commit.membars 403577 # Number of memory barriers committed +system.cpu.commit.branches 10306380 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69191102 # Number of committed integer instructions. -system.cpu.commit.function_calls 991248 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2879799 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69191623 # Number of committed integer instructions. +system.cpu.commit.function_calls 991253 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2864402 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242830080 # The number of ROB reads -system.cpu.rob.rob_writes 195907164 # The number of ROB writes -system.cpu.timesIdled 1776346 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322849401 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575122538 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60309150 # Number of Instructions Simulated -system.cpu.committedOps 77600646 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60309150 # Number of Instructions Simulated -system.cpu.cpi 7.910043 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.910043 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126422 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126422 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 548535745 # number of integer regfile reads -system.cpu.int_regfile_writes 87515632 # number of integer regfile writes -system.cpu.fp_regfile_reads 8349 # number of floating regfile reads -system.cpu.fp_regfile_writes 2926 # number of floating regfile writes -system.cpu.misc_regfile_reads 268179441 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173225 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58877700 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658609 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658608 # Transaction distribution +system.cpu.rob.rob_reads 242979782 # The number of ROB reads +system.cpu.rob.rob_writes 196005989 # The number of ROB writes +system.cpu.timesIdled 1777234 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322825405 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575137230 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60309637 # Number of Instructions Simulated +system.cpu.committedOps 77601213 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60309637 # Number of Instructions Simulated +system.cpu.cpi 7.911164 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.911164 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126404 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126404 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 548697999 # number of integer regfile reads +system.cpu.int_regfile_writes 87552825 # number of integer regfile writes +system.cpu.fp_regfile_reads 8408 # number of floating regfile reads +system.cpu.fp_regfile_writes 2932 # number of floating regfile writes +system.cpu.misc_regfile_reads 268236665 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173235 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58867266 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2659080 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2659079 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607534 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2957 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2969 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246101 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246101 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963183 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795840 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30059 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 127673 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7916755 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62784704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85494778 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 211580 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148531598 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148531598 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 200936 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128807668 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 607635 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2959 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2975 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246069 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246069 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961962 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796085 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30498 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129069 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7917614 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62744960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85505466 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214572 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148505990 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148505990 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 202724 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3129185667 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1475592252 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474638965 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2550083892 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2549207556 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19930988 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20255489 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74876053 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 75530794 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 981505 # number of replacements -system.cpu.icache.tags.tagsinuse 511.575357 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10456797 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 982017 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.648285 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6907075250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.575357 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999171 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999171 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 980897 # number of replacements +system.cpu.icache.tags.tagsinuse 511.570903 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10462766 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981409 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.660964 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6958078250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.570903 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999162 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999162 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 12500448 # Number of tag accesses -system.cpu.icache.tags.data_accesses 12500448 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 10456797 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10456797 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10456797 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10456797 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10456797 # number of overall hits -system.cpu.icache.overall_hits::total 10456797 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1061602 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1061602 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1061602 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1061602 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1061602 # number of overall misses -system.cpu.icache.overall_misses::total 1061602 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14273209676 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14273209676 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14273209676 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14273209676 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14273209676 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14273209676 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11518399 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11518399 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11518399 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11518399 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11518399 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11518399 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092166 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092166 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092166 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092166 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092166 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092166 # 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number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184391905866 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184398242865 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000813 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000197 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012587 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026754 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015975 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986473 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986473 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000195 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012590 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026850 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015999 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.984454 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984454 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.187500 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.187500 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541275 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541275 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000195 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012590 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223473 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092573 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000195 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012590 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223473 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092573 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 193750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60703.107276 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63024.674408 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61819.110803 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61405.960015 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61477.131933 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61342.279193 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61342.279193 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 193750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60703.107276 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61467.157893 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61412.672268 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 193750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60703.107276 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61467.157893 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61412.672268 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1701,168 +1228,168 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # 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Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 43094250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993228 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 101509393 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 101509393 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13753990 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13753990 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259407 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259407 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242755 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242755 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21013397 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21013397 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21013397 # number of overall hits -system.cpu.dcache.overall_hits::total 21013397 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 736321 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 736321 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2962815 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2962815 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13522 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13522 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3699136 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3699136 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3699136 # number of overall misses -system.cpu.dcache.overall_misses::total 3699136 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10001713308 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10001713308 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 140180267525 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 140180267525 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184727500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 184727500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 150181980833 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 150181980833 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 150181980833 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 150181980833 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14490311 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14490311 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222222 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222222 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256277 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256277 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24712533 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24712533 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24712533 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24712533 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050815 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050815 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289841 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289841 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052763 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052763 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149687 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149687 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149687 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149687 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13583.360121 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13583.360121 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47313.202993 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47313.202993 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13661.255731 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13661.255731 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40599.205012 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40599.205012 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40599.205012 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40599.205012 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30576 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 27091 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2628 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 288 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.634703 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 94.065972 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 101537487 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 101537487 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13760648 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13760648 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7259865 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7259865 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242998 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242998 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247594 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21020513 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21020513 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21020513 # number of overall hits +system.cpu.dcache.overall_hits::total 21020513 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 736359 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 736359 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2962417 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2962417 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13527 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13527 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 16 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 16 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3698776 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3698776 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3698776 # number of overall misses +system.cpu.dcache.overall_misses::total 3698776 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9982812336 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9982812336 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 139744433579 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 139744433579 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185287000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 185287000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 245503 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 245503 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 149727245915 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 149727245915 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 149727245915 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 149727245915 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14497007 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14497007 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222282 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222282 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256525 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256525 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247610 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247610 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24719289 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24719289 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24719289 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24719289 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050794 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050794 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289800 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289800 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052732 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052732 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000065 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000065 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149631 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149631 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149631 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149631 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13556.991000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13556.991000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.438444 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.438444 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13697.567827 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13697.567827 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15343.937500 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15343.937500 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40480.214513 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40480.214513 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40480.214513 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40480.214513 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 31777 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 23524 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2637 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 274 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.050436 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 85.854015 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607534 # number of writebacks -system.cpu.dcache.writebacks::total 607534 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350801 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 350801 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713841 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713841 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1334 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1334 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3064642 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3064642 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3064642 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3064642 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385520 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385520 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248974 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248974 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12188 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12188 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634494 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634494 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634494 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634494 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4971012627 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4971012627 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11323926285 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11323926285 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145258250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145258250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16294938912 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16294938912 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16294938912 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16294938912 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335926750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335926750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26847444003 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26847444003 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209183370753 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209183370753 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026605 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026605 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024356 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024356 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047558 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047558 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025675 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025675 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025675 # 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average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25681.785662 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25681.785662 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25681.785662 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607635 # number of writebacks +system.cpu.dcache.writebacks::total 607635 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350728 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 350728 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713476 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2713476 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1349 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1349 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3064204 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3064204 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3064204 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3064204 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385631 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385631 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248941 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248941 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12178 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12178 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634572 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634572 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634572 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634572 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4967633608 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4967633608 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11307381788 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11307381788 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145644250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145644250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 213497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 213497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16275015396 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16275015396 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16275015396 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16275015396 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182336207250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182336207250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26867769000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26867769000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209203976250 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209203976250 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026601 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026601 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024353 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047473 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047473 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000065 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000065 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025671 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025671 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025671 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025671 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.831616 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.831616 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45421.934466 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45421.934466 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11959.619806 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11959.619806 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13343.562500 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13343.562500 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25647.232144 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25647.232144 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25647.232144 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25647.232144 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1886,10 +1413,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499139103043 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1499139103043 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499139103043 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1499139103043 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1715151162848 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1715151162848 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1715151162848 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1715151162848 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index c90f786a8..8e01cba8d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,168 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403672 # Number of seconds simulated -sim_ticks 2403671650000 # Number of ticks simulated -final_tick 2403671650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403854 # Number of seconds simulated +sim_ticks 2403853586500 # Number of ticks simulated +final_tick 2403853586500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 179946 # Simulator instruction rate (inst/s) -host_op_rate 231118 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7169234406 # Simulator tick rate (ticks/s) -host_mem_usage 425424 # Number of bytes of host memory used -host_seconds 335.28 # Real time elapsed on the host -sim_insts 60331512 # Number of instructions simulated -sim_ops 77488235 # Number of ops (including micro ops) simulated +host_inst_rate 171159 # Simulator instruction rate (inst/s) +host_op_rate 219830 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6819657603 # Simulator tick rate (ticks/s) +host_mem_usage 469520 # Number of bytes of host memory used +host_seconds 352.49 # Real time elapsed on the host +sim_insts 60331708 # Number of instructions simulated +sim_ops 77487722 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 512456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7063576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 512776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7053720 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 64640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 678080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 63616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 681152 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 186240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1335136 # Number of bytes read from this memory -system.physmem.bytes_read::total 124660096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 512456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 64640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 186240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 763336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3743616 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1298488 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 159300 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1558028 # Number of bytes written to this memory -system.physmem.bytes_written::total 6759432 # Number of bytes written to this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 186368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1342304 # Number of bytes read from this memory +system.physmem.bytes_read::total 124659968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 512776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 63616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 186368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 762760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3743360 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1298364 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 159256 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1558196 # Number of bytes written to this memory +system.physmem.bytes_written::total 6759176 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14219 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110404 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14224 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110250 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1010 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10595 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 994 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10643 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2910 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20869 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512405 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58494 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 324622 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39825 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 389507 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812448 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47768202 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2912 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20981 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512403 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58490 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 324591 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39814 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 389549 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812444 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47764586 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 213197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2938661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2934338 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26892 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 282102 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26464 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 283358 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.dtb.walker 266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 77481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 555457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51862365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213197 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26892 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 77481 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317571 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1557457 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 540210 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 66274 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 648187 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2812128 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1557457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47768202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 77529 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 558397 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51858386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213314 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26464 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 77529 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317307 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1557233 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 540118 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 66250 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 648208 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2811809 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1557233 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47764586 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213197 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3478871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3474456 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 26892 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 348375 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 26464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 349609 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.dtb.walker 266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 77481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1203644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54674493 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13478771 # Number of read requests accepted -system.physmem.writeReqs 446331 # Number of write requests accepted -system.physmem.readBursts 13478771 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 446331 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 862641344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 2859200 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 109811808 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2805264 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 401653 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2355 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 837730 # Per bank write bursts -system.physmem.perBankRdBursts::1 837384 # Per bank write bursts -system.physmem.perBankRdBursts::2 837568 # Per bank write bursts -system.physmem.perBankRdBursts::3 837998 # Per bank write bursts -system.physmem.perBankRdBursts::4 839137 # Per bank write bursts -system.physmem.perBankRdBursts::5 839827 # Per bank write bursts -system.physmem.perBankRdBursts::6 839940 # Per bank write bursts -system.physmem.perBankRdBursts::7 841195 # Per bank write bursts -system.physmem.perBankRdBursts::8 842685 # Per bank write bursts -system.physmem.perBankRdBursts::9 845257 # Per bank write bursts -system.physmem.perBankRdBursts::10 845425 # Per bank write bursts -system.physmem.perBankRdBursts::11 845905 # Per bank write bursts -system.physmem.perBankRdBursts::12 847162 # Per bank write bursts -system.physmem.perBankRdBursts::13 848062 # Per bank write bursts -system.physmem.perBankRdBursts::14 846854 # Per bank write bursts -system.physmem.perBankRdBursts::15 846642 # Per bank write bursts -system.physmem.perBankWrBursts::0 2730 # Per bank write bursts -system.physmem.perBankWrBursts::1 2572 # Per bank write bursts -system.physmem.perBankWrBursts::2 2588 # Per bank write bursts -system.physmem.perBankWrBursts::3 3028 # Per bank write bursts -system.physmem.perBankWrBursts::4 3463 # Per bank write bursts -system.physmem.perBankWrBursts::5 3194 # Per bank write bursts -system.physmem.perBankWrBursts::6 2521 # Per bank write bursts -system.physmem.perBankWrBursts::7 2322 # Per bank write bursts -system.physmem.perBankWrBursts::8 2234 # Per bank write bursts -system.physmem.perBankWrBursts::9 2386 # Per bank write bursts -system.physmem.perBankWrBursts::10 2377 # Per bank write bursts -system.physmem.perBankWrBursts::11 2814 # Per bank write bursts -system.physmem.perBankWrBursts::12 3729 # Per bank write bursts -system.physmem.perBankWrBursts::13 3501 # Per bank write bursts -system.physmem.perBankWrBursts::14 2651 # Per bank write bursts -system.physmem.perBankWrBursts::15 2565 # Per bank write bursts +system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 77529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1206604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54670195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13446822 # Number of read requests accepted +system.physmem.writeReqs 446449 # Number of write requests accepted +system.physmem.readBursts 13446822 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 446449 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 860596480 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue +system.physmem.bytesWritten 2823168 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109564448 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2810956 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 402307 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2362 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 835680 # Per bank write bursts +system.physmem.perBankRdBursts::1 835344 # Per bank write bursts +system.physmem.perBankRdBursts::2 835508 # Per bank write bursts +system.physmem.perBankRdBursts::3 835965 # Per bank write bursts +system.physmem.perBankRdBursts::4 837088 # Per bank write bursts +system.physmem.perBankRdBursts::5 837779 # Per bank write bursts +system.physmem.perBankRdBursts::6 837907 # Per bank write bursts +system.physmem.perBankRdBursts::7 839147 # Per bank write bursts +system.physmem.perBankRdBursts::8 840641 # Per bank write bursts +system.physmem.perBankRdBursts::9 843268 # Per bank write bursts +system.physmem.perBankRdBursts::10 843373 # Per bank write bursts +system.physmem.perBankRdBursts::11 843869 # Per bank write bursts +system.physmem.perBankRdBursts::12 845852 # Per bank write bursts +system.physmem.perBankRdBursts::13 846016 # Per bank write bursts +system.physmem.perBankRdBursts::14 844806 # Per bank write bursts +system.physmem.perBankRdBursts::15 844577 # Per bank write bursts +system.physmem.perBankWrBursts::0 2668 # Per bank write bursts +system.physmem.perBankWrBursts::1 2526 # Per bank write bursts +system.physmem.perBankWrBursts::2 2530 # Per bank write bursts +system.physmem.perBankWrBursts::3 3005 # Per bank write bursts +system.physmem.perBankWrBursts::4 3419 # Per bank write bursts +system.physmem.perBankWrBursts::5 3167 # Per bank write bursts +system.physmem.perBankWrBursts::6 2515 # Per bank write bursts +system.physmem.perBankWrBursts::7 2303 # Per bank write bursts +system.physmem.perBankWrBursts::8 2186 # Per bank write bursts +system.physmem.perBankWrBursts::9 2396 # Per bank write bursts +system.physmem.perBankWrBursts::10 2346 # Per bank write bursts +system.physmem.perBankWrBursts::11 2792 # Per bank write bursts +system.physmem.perBankWrBursts::12 3710 # Per bank write bursts +system.physmem.perBankWrBursts::13 3446 # Per bank write bursts +system.physmem.perBankWrBursts::14 2600 # Per bank write bursts +system.physmem.perBankWrBursts::15 2503 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2402635561500 # Total gap between requests +system.physmem.totGap 2402817511500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 8 # Read request sizes (log2) -system.physmem.readPktSize::3 13443376 # Read request sizes (log2) +system.physmem.readPktSize::3 13411280 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 35387 # Read request sizes (log2) +system.physmem.readPktSize::6 35534 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 429332 # Write request sizes (log2) +system.physmem.writePktSize::2 429363 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 16999 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 985231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 962596 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 957159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3278666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2351782 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2351346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2368287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 47071 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 52789 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 17803 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 17814 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 17764 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 17625 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 17616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 17598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 23 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17086 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 867414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 844196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 838512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 839224 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 838671 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 838847 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2475363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2475187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3292199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 19694 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 19741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 19565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 19175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 19145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -178,369 +182,159 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48736 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 17758.945502 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 3164.892038 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 18326.287457 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 8690 17.83% 17.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 4827 9.90% 27.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 1035 2.12% 29.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 694 1.42% 31.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 398 0.82% 32.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 429 0.88% 32.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 259 0.53% 33.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 302 0.62% 34.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 176 0.36% 34.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 149 0.31% 34.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 171 0.35% 35.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 272 0.56% 35.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 78 0.16% 35.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 84 0.17% 36.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 41 0.08% 36.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 422 0.87% 36.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 26 0.05% 37.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 34 0.07% 37.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 22 0.05% 37.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 232 0.48% 37.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 28 0.06% 37.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 166 0.34% 38.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 13 0.03% 38.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 104 0.21% 38.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 12 0.02% 38.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 32 0.07% 38.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 7 0.01% 38.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 80 0.16% 38.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 11 0.02% 38.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 11 0.02% 38.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 7 0.01% 38.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 239 0.49% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 4 0.01% 39.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 11 0.02% 39.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 7 0.01% 39.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 71 0.15% 39.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 4 0.01% 39.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 5 0.01% 39.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 2 0.00% 39.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 72 0.15% 39.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 2 0.00% 39.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 3 0.01% 39.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 1 0.00% 39.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 3 0.01% 39.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 2 0.00% 39.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 6 0.01% 39.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 4 0.01% 39.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 360 0.74% 40.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 3 0.01% 40.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 3 0.01% 40.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 2 0.00% 40.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 69 0.14% 40.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 3 0.01% 40.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 6 0.01% 40.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 6 0.01% 40.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 67 0.14% 40.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 5 0.01% 40.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 8 0.02% 40.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 5 0.01% 40.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 67 0.14% 40.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 5 0.01% 40.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 9 0.02% 40.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 4 0.01% 40.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 338 0.69% 41.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 3 0.01% 41.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 7 0.01% 41.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 5 0.01% 41.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 70 0.14% 41.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 13 0.03% 41.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 5 0.01% 41.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 7 0.01% 41.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 72 0.15% 41.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 1 0.00% 41.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 5 0.01% 41.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 3 0.01% 41.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 64 0.13% 41.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 3 0.01% 41.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 4 0.01% 42.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 3 0.01% 42.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 280 0.57% 42.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 1 0.00% 42.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 2 0.00% 42.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 73 0.15% 42.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 4 0.01% 42.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 4 0.01% 42.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 1 0.00% 42.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 129 0.26% 43.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 2 0.00% 43.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 4 0.01% 43.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 176 0.36% 43.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 1 0.00% 43.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 10 0.02% 43.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 327 0.67% 44.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 5 0.01% 44.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 7 0.01% 44.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 1 0.00% 44.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 98 0.20% 44.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 1 0.00% 44.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 1 0.00% 44.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 2 0.00% 44.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 73 0.15% 44.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 4 0.01% 44.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 8 0.02% 44.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 2 0.00% 44.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 60 0.12% 44.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 5 0.01% 44.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 2 0.00% 44.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 3 0.01% 44.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 268 0.55% 45.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 1 0.00% 45.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 7 0.01% 45.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 66 0.14% 45.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 2 0.00% 45.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 1 0.00% 45.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 64 0.13% 45.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 42 0.09% 45.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 2 0.00% 45.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 515 1.06% 46.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 42 0.09% 46.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 66 0.14% 46.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 65 0.13% 46.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 267 0.55% 47.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 59 0.12% 47.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 69 0.14% 47.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 94 0.19% 47.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 322 0.66% 48.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 138 0.28% 48.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 128 0.26% 49.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 70 0.14% 49.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 279 0.57% 49.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 60 0.12% 50.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11655 1 0.00% 50.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 64 0.13% 50.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 65 0.13% 50.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 328 0.67% 50.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 63 0.13% 51.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12615 1 0.00% 51.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 64 0.13% 51.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 64 0.13% 51.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 357 0.73% 52.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 65 0.13% 52.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13959 1 0.00% 52.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 64 0.13% 52.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 1 0.00% 52.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 229 0.47% 52.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 64 0.13% 52.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 64 0.13% 53.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 190 0.39% 53.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 321 0.66% 54.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 65 0.13% 54.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 64 0.13% 54.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 672 1.38% 55.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 64 0.13% 55.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 64 0.13% 56.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 321 0.66% 56.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 189 0.39% 57.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 65 0.13% 57.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 64 0.13% 57.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 1 0.00% 57.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18368-18375 1 0.00% 57.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 229 0.47% 57.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 64 0.13% 57.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 63 0.13% 58.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19008-19015 1 0.00% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 1 0.00% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 357 0.73% 58.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 65 0.13% 58.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19904-19911 1 0.00% 58.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 65 0.13% 59.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 64 0.13% 59.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20288-20295 1 0.00% 59.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 1 0.00% 59.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 327 0.67% 59.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20608-20615 1 0.00% 59.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 64 0.13% 60.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 64 0.13% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 61 0.13% 60.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 274 0.56% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 69 0.14% 61.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 128 0.26% 61.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 137 0.28% 61.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22336-22343 1 0.00% 61.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 323 0.66% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 93 0.19% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22848-22855 1 0.00% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 68 0.14% 62.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 57 0.12% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 268 0.55% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 65 0.13% 63.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 65 0.13% 63.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 43 0.09% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 514 1.05% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24768-24775 1 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 42 0.09% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 66 0.14% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 64 0.13% 64.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25408-25415 1 0.00% 64.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 1 0.00% 64.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 264 0.54% 65.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25735 1 0.00% 65.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 57 0.12% 65.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 69 0.14% 65.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 95 0.19% 65.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 323 0.66% 66.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26752-26759 1 0.00% 66.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 137 0.28% 66.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27008-27015 1 0.00% 66.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 127 0.26% 67.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 68 0.14% 67.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 275 0.56% 67.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 61 0.13% 68.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 64 0.13% 68.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 65 0.13% 68.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 329 0.68% 68.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 65 0.13% 69.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 64 0.13% 69.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 64 0.13% 69.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 356 0.73% 70.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 65 0.13% 70.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 64 0.13% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 228 0.47% 70.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 64 0.13% 70.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 64 0.13% 71.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 189 0.39% 71.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 321 0.66% 72.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 63 0.13% 72.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32135 1 0.00% 72.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 64 0.13% 72.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 673 1.38% 73.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 64 0.13% 73.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 1 0.00% 73.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 64 0.13% 74.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 321 0.66% 74.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 189 0.39% 75.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 64 0.13% 75.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 65 0.13% 75.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 229 0.47% 75.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 64 0.13% 75.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 65 0.13% 76.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 356 0.73% 76.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 64 0.13% 76.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 64 0.13% 77.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 65 0.13% 77.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 329 0.68% 77.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 65 0.13% 78.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 64 0.13% 78.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 61 0.13% 78.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 276 0.57% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 68 0.14% 78.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 127 0.26% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 1 0.00% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 137 0.28% 79.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 322 0.66% 80.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 94 0.19% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 69 0.14% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 57 0.12% 80.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39808-39815 1 0.00% 80.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 264 0.54% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40128-40135 1 0.00% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 64 0.13% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 65 0.13% 81.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 42 0.09% 81.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 513 1.05% 82.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 43 0.09% 82.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 64 0.13% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 65 0.13% 82.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 266 0.55% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 57 0.12% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 68 0.14% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42695 1 0.00% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 93 0.19% 83.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 323 0.66% 84.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 137 0.28% 84.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 128 0.26% 85.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 69 0.14% 85.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 274 0.56% 85.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 61 0.13% 85.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 64 0.13% 86.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 64 0.13% 86.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44928-44935 1 0.00% 86.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 327 0.67% 86.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45191 1 0.00% 86.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45248-45255 1 0.00% 86.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 64 0.13% 87.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 64 0.13% 87.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45632-45639 1 0.00% 87.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 64 0.13% 87.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 356 0.73% 88.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46528-46535 1 0.00% 88.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 63 0.13% 88.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 64 0.13% 88.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 228 0.47% 88.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 64 0.13% 88.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 65 0.13% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 190 0.39% 89.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 322 0.66% 90.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 67 0.14% 90.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 64 0.13% 90.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 1 0.00% 90.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 1 0.00% 90.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 4701 9.65% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 48736 # Bytes accessed per row activation -system.physmem.totQLat 326317088000 # Total ticks spent queuing -system.physmem.totMemAccLat 407972525500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 67393855000 # Total ticks spent in databus transfers -system.physmem.totBankLat 14261582500 # Total ticks spent accessing banks -system.physmem.avgQLat 24209.71 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1058.08 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 95 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 844644 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 1019.942660 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1014.395909 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 58.300980 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1516 0.18% 0.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 1237 0.15% 0.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 570 0.07% 0.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 375 0.04% 0.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 256 0.03% 0.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 198 0.02% 0.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 155 0.02% 0.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 158 0.02% 0.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 840179 99.47% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 844644 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 1621 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 8295.373226 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 315033.644502 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 1620 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07 1 0.06% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 1621 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 1621 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.212832 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 24.563019 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.121341 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 1 0.06% 0.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 2 0.12% 0.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 1 0.06% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 1 0.06% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 1 0.06% 0.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 1 0.06% 0.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 1 0.06% 0.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12 2 0.12% 0.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 6 0.37% 0.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 488 30.10% 31.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 27 1.67% 32.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 60 3.70% 36.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 333 20.54% 57.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 10 0.62% 57.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.19% 57.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.12% 57.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 3 0.19% 58.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 2 0.12% 58.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 3 0.19% 58.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.31% 58.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.25% 58.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 5 0.31% 59.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 7 0.43% 59.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 3 0.19% 59.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 2 0.12% 60.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 8 0.49% 60.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 2 0.12% 60.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.06% 60.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 50 3.08% 63.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 4 0.25% 64.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 167 10.30% 74.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 328 20.23% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 16 0.99% 95.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 15 0.93% 96.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 23 1.42% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 17 1.05% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 13 0.80% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 2 0.12% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 2 0.12% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 1621 # Writes before turning the bus around for reads +system.physmem.totQLat 510864117000 # Total ticks spent queuing +system.physmem.totMemAccLat 601782495750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67234100000 # Total ticks spent in databus transfers +system.physmem.totBankLat 23684278750 # Total ticks spent accessing banks +system.physmem.avgQLat 37991.44 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1761.33 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30267.78 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 358.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.19 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 45.69 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44752.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 358.01 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.17 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 45.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.81 # Data bus utilization in percentage system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.37 # Average write queue length when enqueuing -system.physmem.readRowHits 13435330 # Number of row buffer hits during reads -system.physmem.writeRowHits 39380 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 88.14 # Row buffer hit rate for writes -system.physmem.avgGap 172539.89 # Average gap between requests -system.physmem.pageHitRate 99.64 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.87 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.avgRdQLen 8.42 # Average read queue length when enqueuing +system.physmem.avgWrQLen 5.41 # Average write queue length when enqueuing +system.physmem.readRowHits 12595156 # Number of row buffer hits during reads +system.physmem.writeRowHits 38053 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 86.21 # Row buffer hit rate for writes +system.physmem.avgGap 172948.29 # Average gap between requests +system.physmem.pageHitRate 93.64 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 2.74 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -553,322 +347,341 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55671828 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13814146 # Transaction distribution -system.membus.trans_dist::ReadResp 13814146 # Transaction distribution -system.membus.trans_dist::WriteReq 432166 # Transaction distribution -system.membus.trans_dist::WriteResp 432166 # Transaction distribution -system.membus.trans_dist::Writeback 16999 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2355 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2355 # Transaction distribution -system.membus.trans_dist::ReadExReq 27802 # Transaction distribution -system.membus.trans_dist::ReadExResp 27802 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 731808 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 214 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951163 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1683185 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26886752 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26886752 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28569937 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 735681 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 428 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5070064 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5806173 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107547008 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107547008 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113353181 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133816795 # Total data (bytes) +system.membus.throughput 55667457 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13781916 # Transaction distribution +system.membus.trans_dist::ReadResp 13781916 # Transaction distribution +system.membus.trans_dist::WriteReq 432200 # Transaction distribution +system.membus.trans_dist::WriteResp 432200 # Transaction distribution +system.membus.trans_dist::Writeback 17086 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2361 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2362 # Transaction distribution +system.membus.trans_dist::ReadExReq 27973 # Transaction distribution +system.membus.trans_dist::ReadExResp 27973 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 731598 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 210 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951620 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1683428 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26822560 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26822560 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28505988 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 735468 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 420 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5085164 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5821052 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107290240 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107290240 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113111292 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133816415 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 416936000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 416850000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 202000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 198000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14607946000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 14576843000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1594364889 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1595419615 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 30360976750 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.membus.respLayer2.occupancy 33523642000 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 63237 # number of replacements -system.l2c.tags.tagsinuse 50379.569066 # Cycle average of tags in use -system.l2c.tags.total_refs 1749643 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128631 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.602032 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375594870500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36839.610574 # Average occupied blocks per requestor +system.l2c.tags.replacements 63235 # number of replacements +system.l2c.tags.tagsinuse 50381.174231 # Cycle average of tags in use +system.l2c.tags.total_refs 1749008 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128627 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.597518 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375559570500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36838.397677 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5231.934240 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3832.971184 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5238.516596 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3833.196793 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993316 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 504.116293 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 687.425497 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 7.900489 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1683.581513 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1591.035818 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562128 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 493.229672 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 688.317801 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 8.879272 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.004789 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1684.639749 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1594.998425 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562109 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079833 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058486 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079933 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.058490 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007692 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010489 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000121 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.025689 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.024277 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768731 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 2 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65392 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2635 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6494 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55883 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000031 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997803 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17683980 # Number of tag accesses -system.l2c.tags.data_accesses 17683980 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 8701 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3143 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 467937 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 177040 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2608 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1169 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 128901 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 64374 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18792 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4308 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 282422 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 131846 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1291241 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597674 # number of Writeback hits -system.l2c.Writeback_hits::total 597674 # number of Writeback hits +system.l2c.tags.occ_percent::cpu1.inst 0.007526 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010503 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000135 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.025706 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.024338 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768756 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65386 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6490 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55882 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.997711 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17681539 # Number of tag accesses +system.l2c.tags.data_accesses 17681539 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 8692 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3137 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 468000 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 177035 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2622 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1183 # 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average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 62677.326183 # average ReadExReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61297.583631 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61580.949808 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61484.690182 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59571.534653 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63097.346862 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 68000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63649.226804 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62962.898924 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 62965.181460 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58128.521127 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61687.954375 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 66625 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 62767.771291 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61949.052146 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61833.263466 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59571.534653 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63097.346862 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 68000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63649.226804 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62962.898924 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 62965.181460 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58128.521127 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61687.954375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 66625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 62767.771291 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61949.052146 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61833.263466 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1021,52 +854,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58818769 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1020134 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1020133 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 432166 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 432166 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 265053 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1501 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1503 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80260 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80260 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831165 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2419053 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15627 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52402 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3318247 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26575552 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37346205 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21908 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 85644 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 64029309 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141280603 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 100404 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2176001251 # Layer occupancy (ticks) +system.toL2Bus.throughput 58805312 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1019677 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1019676 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 432200 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 432200 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 265274 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1507 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1511 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80476 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80476 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 830192 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2419562 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15560 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52654 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3317968 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26544384 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37373820 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21604 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 86116 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 64025924 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141258487 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 100872 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2176910263 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1872526171 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1870334166 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1845075146 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1845880168 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10168460 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10179455 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 31121231 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 31260469 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48762623 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13806510 # Transaction distribution -system.iobus.trans_dist::ReadResp 13806510 # Transaction distribution -system.iobus.trans_dist::WriteReq 2770 # Transaction distribution -system.iobus.trans_dist::WriteResp 2770 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11390 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3024 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48758934 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13774305 # Transaction distribution +system.iobus.trans_dist::ReadResp 13774305 # Transaction distribution +system.iobus.trans_dist::WriteReq 2774 # Transaction distribution +system.iobus.trans_dist::WriteResp 2774 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11404 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3022 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 254 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 252 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 716834 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 716614 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -1082,18 +915,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 731808 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26886752 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26886752 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27618560 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15354 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6048 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 731598 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26822560 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26822560 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27554158 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 508 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 504 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 713159 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 712940 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1109,18 +942,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 735681 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107547008 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107547008 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108282689 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 117209335 # Total data (bytes) -system.iobus.reqLayer0.occupancy 7953000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 735468 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107290240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107290240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108025708 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 117209339 # Total data (bytes) +system.iobus.reqLayer0.occupancy 7964000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1512000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1511000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 127000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 126000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1128,7 +961,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 358920000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 358810000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -1160,12 +993,12 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13443376000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13411280000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 729038000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 728824000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 36855449250 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.iobus.respLayer1.occupancy 33525822000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1189,25 +1022,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7998897 # DTB read hits +system.cpu0.dtb.read_hits 7997782 # DTB read hits system.cpu0.dtb.read_misses 6203 # DTB read misses -system.cpu0.dtb.write_hits 6598042 # DTB write hits -system.cpu0.dtb.write_misses 1992 # DTB write misses +system.cpu0.dtb.write_hits 6595987 # DTB write hits +system.cpu0.dtb.write_misses 1983 # DTB write misses system.cpu0.dtb.flush_tlb 556 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 678 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5672 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5673 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 123 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 209 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8005100 # DTB read accesses -system.cpu0.dtb.write_accesses 6600034 # DTB write accesses +system.cpu0.dtb.read_accesses 8003985 # DTB read accesses +system.cpu0.dtb.write_accesses 6597970 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14596939 # DTB hits -system.cpu0.dtb.misses 8195 # DTB misses -system.cpu0.dtb.accesses 14605134 # DTB accesses +system.cpu0.dtb.hits 14593769 # DTB hits +system.cpu0.dtb.misses 8186 # DTB misses +system.cpu0.dtb.accesses 14601955 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1229,15 +1062,15 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 32342389 # ITB inst hits -system.cpu0.itb.inst_misses 3452 # ITB inst misses +system.cpu0.itb.inst_hits 32336935 # ITB inst hits +system.cpu0.itb.inst_misses 3451 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 556 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 678 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID system.cpu0.itb.flush_entries 2628 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions @@ -1246,416 +1079,416 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # 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Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 494.923201 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.626935 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 9.052233 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.966647 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014896 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.017680 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999223 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 160 # 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number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4899198810 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015912 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070530 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009330 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015912 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070530 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009330 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015912 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070530 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009330 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11509.853664 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11901.806735 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11779.128803 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11509.853664 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11901.806735 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11779.128803 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11509.853664 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11901.806735 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11779.128803 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23779 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 23779 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 23779 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 23779 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 23779 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 23779 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 130939 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 284497 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 415436 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 130939 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 284497 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 415436 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 130939 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 284497 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 415436 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1504362250 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3384633315 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4888995565 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1504362250 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3384633315 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4888995565 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1504362250 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3384633315 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4888995565 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015977 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070265 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009318 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015977 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070265 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009318 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015977 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070265 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009318 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11489.031152 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11896.903359 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11768.348350 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11489.031152 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11896.903359 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11768.348350 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11489.031152 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11896.903359 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11768.348350 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 629840 # number of replacements +system.cpu0.dcache.tags.replacements 629883 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997118 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23225212 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 630352 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 36.844830 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 23225674 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 630395 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 36.843049 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.071711 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.097941 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.827465 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970843 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015816 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013335 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.048952 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.104316 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.843850 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970799 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015829 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013367 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 98826568 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 98826568 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6868032 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1817018 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4638626 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13323676 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5966375 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1312197 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2134420 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9412992 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131825 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 32972 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73365 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 238162 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 138288 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34722 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74382 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247392 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12834407 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 3129215 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6773046 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 22736668 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12834407 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 3129215 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6773046 # number of overall hits -system.cpu0.dcache.overall_hits::total 22736668 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 177045 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 63739 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 270648 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 511432 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 168130 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 28623 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 606733 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 803486 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6464 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1750 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3698 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11912 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 345175 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 92362 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 877381 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1314918 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 345175 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 92362 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 877381 # number of overall misses -system.cpu0.dcache.overall_misses::total 1314918 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 908043250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3905088066 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4813131316 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1020010237 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 23150589506 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 24170599743 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 23020750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 49421249 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 72441999 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 1928053487 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 27055677572 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 28983731059 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1928053487 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 27055677572 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 28983731059 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7045077 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1880757 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4909274 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13835108 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6134505 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1340820 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2741153 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10216478 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138289 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34722 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77063 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250074 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 138288 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34722 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74384 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247394 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13179582 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3221577 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7650427 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24051586 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13179582 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3221577 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7650427 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24051586 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025130 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033890 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.055130 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027407 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021347 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.221342 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.078646 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046743 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.050400 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.047987 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047634 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000027 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026190 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028670 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.114684 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.054671 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026190 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028670 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.114684 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.054671 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14246.273867 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14428.660348 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9411.087527 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35636.035251 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 38156.140355 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 30082.166638 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13154.714286 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13364.318280 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6081.430406 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20874.964672 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30836.862859 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 22042.234618 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20874.964672 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30836.862859 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 22042.234618 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7997 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3099 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 875 # 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number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34792 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74317 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247390 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13176345 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 3228773 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7647789 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24052907 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13176345 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 3228773 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7647789 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24052907 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025134 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033899 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.055023 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036930 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027390 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021352 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.221987 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.078780 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046753 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.050558 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.048174 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047720 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000054 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000016 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026184 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028675 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.114836 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.054706 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026184 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028675 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.114836 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.054706 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14247.871141 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14407.358418 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9395.764623 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35137.812348 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37790.547259 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 29809.294069 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13146.105742 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13340.088608 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6086.600402 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16125.250000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20723.829629 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30600.203178 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 21882.044193 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20723.829629 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30600.203178 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 21882.044193 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 7912 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2132 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 872 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 43 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.073394 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 49.581395 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597674 # number of writebacks -system.cpu0.dcache.writebacks::total 597674 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 139516 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 139516 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 553631 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 553631 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 397 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 397 # 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number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2479004099 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 960165763 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1859721243 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2819887006 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19520250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38036501 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57556751 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1740534513 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3558356592 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5298891105 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1740534513 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3558356592 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5298891105 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27401033000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28573458500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55974491500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1439106494 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13338859363 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14777965857 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28840139494 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41912317863 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70752457357 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033890 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026711 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014085 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021347 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019372 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007999 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050400 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.042835 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020198 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028670 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024082 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011500 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028670 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024082 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011500 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12243.190982 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12953.629541 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12721.257134 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33545.252524 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35021.679843 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34504.582515 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11154.428571 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11522.720691 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11395.119976 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18844.703590 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19314.331730 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19157.511696 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18844.703590 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19314.331730 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19157.511696 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597704 # number of writebacks +system.cpu0.dcache.writebacks::total 597704 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 139099 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 139099 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 554931 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 554931 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 402 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 402 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 694030 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 694030 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 694030 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 694030 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63884 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 130960 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 194844 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28702 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53249 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 81951 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1759 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3311 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5070 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 4 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 92586 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 184209 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 276795 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 92586 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 184209 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 276795 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 782254000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1693207098 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2475461098 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 948597510 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1850547743 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2799145253 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19606000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38066251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57672251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 56499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 56499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1730851510 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3543754841 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5274606351 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1730851510 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3543754841 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5274606351 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27378129500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28579482250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55957611750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1439295977 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13341687506 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14780983483 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28817425477 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41921169756 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70738595233 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033899 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026683 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014082 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021352 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019436 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008021 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050558 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.042958 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020268 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000016 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028675 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024087 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011508 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028675 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024087 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011508 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12244.912654 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12929.192868 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12704.836166 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33049.874922 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34752.722924 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34156.328208 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11146.105742 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11496.904561 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11375.197436 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14124.750000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18694.527358 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19237.685678 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19056.003002 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18694.527358 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19237.685678 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19056.003002 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1689,25 +1522,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2093956 # DTB read hits -system.cpu1.dtb.read_misses 2077 # DTB read misses -system.cpu1.dtb.write_hits 1416211 # DTB write hits +system.cpu1.dtb.read_hits 2097642 # DTB read hits +system.cpu1.dtb.read_misses 2089 # DTB read misses +system.cpu1.dtb.write_hits 1419704 # DTB write hits system.cpu1.dtb.write_misses 373 # DTB write misses system.cpu1.dtb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1760 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1767 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 36 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2096033 # DTB read accesses -system.cpu1.dtb.write_accesses 1416584 # DTB write accesses +system.cpu1.dtb.read_accesses 2099731 # DTB read accesses +system.cpu1.dtb.write_accesses 1420077 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3510167 # DTB hits -system.cpu1.dtb.misses 2450 # DTB misses -system.cpu1.dtb.accesses 3512617 # DTB accesses +system.cpu1.dtb.hits 3517346 # DTB hits +system.cpu1.dtb.misses 2462 # DTB misses +system.cpu1.dtb.accesses 3519808 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1729,8 +1562,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 8180990 # ITB inst hits -system.cpu1.itb.inst_misses 1185 # ITB inst misses +system.cpu1.itb.inst_hits 8195558 # ITB inst hits +system.cpu1.itb.inst_misses 1195 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1739,51 +1572,51 @@ system.cpu1.itb.flush_tlb 554 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 944 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 946 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8182175 # ITB inst accesses -system.cpu1.itb.hits 8180990 # DTB hits -system.cpu1.itb.misses 1185 # DTB misses -system.cpu1.itb.accesses 8182175 # DTB accesses -system.cpu1.numCycles 581419148 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8196753 # ITB inst accesses +system.cpu1.itb.hits 8195558 # DTB hits +system.cpu1.itb.misses 1195 # DTB misses +system.cpu1.itb.accesses 8196753 # DTB accesses +system.cpu1.numCycles 584703165 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7970398 # Number of instructions committed -system.cpu1.committedOps 10116193 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9089557 # Number of integer alu accesses +system.cpu1.committedInsts 7984738 # Number of instructions committed +system.cpu1.committedOps 10135701 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9107037 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 2019 # Number of float alu accesses -system.cpu1.num_func_calls 304010 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1112792 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9089557 # number of integer instructions +system.cpu1.num_func_calls 304651 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1115193 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9107037 # number of integer instructions system.cpu1.num_fp_insts 2019 # number of float instructions -system.cpu1.num_int_register_reads 52989642 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9881584 # number of times the integer registers were written +system.cpu1.num_int_register_reads 53092313 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9899825 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1441 # number of times the floating registers were read system.cpu1.num_fp_register_writes 580 # number of times the floating registers were written -system.cpu1.num_mem_refs 3676962 # number of memory refs -system.cpu1.num_load_insts 2186992 # Number of load instructions -system.cpu1.num_store_insts 1489970 # Number of store instructions -system.cpu1.num_idle_cycles 545339727.510646 # Number of idle cycles -system.cpu1.num_busy_cycles 36079420.489354 # Number of busy cycles -system.cpu1.not_idle_fraction 0.062054 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.937946 # Percentage of idle cycles -system.cpu1.Branches 1445114 # Number of branches fetched +system.cpu1.num_mem_refs 3684662 # number of memory refs +system.cpu1.num_load_insts 2190856 # Number of load instructions +system.cpu1.num_store_insts 1493806 # Number of store instructions +system.cpu1.num_idle_cycles 548865377.428164 # Number of idle cycles +system.cpu1.num_busy_cycles 35837787.571836 # Number of busy cycles +system.cpu1.not_idle_fraction 0.061292 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.938708 # Percentage of idle cycles +system.cpu1.Branches 1448177 # Number of branches fetched system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4780240 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3898194 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 223690 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3180058 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2524004 # Number of BTB hits +system.cpu2.branchPred.lookups 4782343 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3901882 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 223184 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3184465 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2528356 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 79.369747 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 414035 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21682 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 79.396571 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 413120 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21664 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1807,25 +1640,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10926394 # DTB read hits -system.cpu2.dtb.read_misses 23081 # DTB read misses -system.cpu2.dtb.write_hits 3349602 # DTB write hits -system.cpu2.dtb.write_misses 6536 # DTB write misses +system.cpu2.dtb.read_hits 10925413 # DTB read hits +system.cpu2.dtb.read_misses 23157 # DTB read misses +system.cpu2.dtb.write_hits 3347832 # DTB write hits +system.cpu2.dtb.write_misses 6500 # DTB write misses system.cpu2.dtb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 540 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 542 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2337 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 728 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 164 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2330 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 739 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10949475 # DTB read accesses -system.cpu2.dtb.write_accesses 3356138 # DTB write accesses +system.cpu2.dtb.perms_faults 476 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10948570 # DTB read accesses +system.cpu2.dtb.write_accesses 3354332 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14275996 # DTB hits -system.cpu2.dtb.misses 29617 # DTB misses -system.cpu2.dtb.accesses 14305613 # DTB accesses +system.cpu2.dtb.hits 14273245 # DTB hits +system.cpu2.dtb.misses 29657 # DTB misses +system.cpu2.dtb.accesses 14302902 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1847,294 +1680,294 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.inst_hits 4052754 # ITB inst hits -system.cpu2.itb.inst_misses 4681 # ITB inst misses +system.cpu2.itb.inst_hits 4050371 # ITB inst hits +system.cpu2.itb.inst_misses 4655 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 540 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 542 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1722 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1717 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 963 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 991 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4057435 # ITB inst accesses -system.cpu2.itb.hits 4052754 # DTB hits -system.cpu2.itb.misses 4681 # DTB misses -system.cpu2.itb.accesses 4057435 # DTB accesses -system.cpu2.numCycles 88329548 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4055026 # ITB inst accesses +system.cpu2.itb.hits 4050371 # DTB hits +system.cpu2.itb.misses 4655 # DTB misses +system.cpu2.itb.accesses 4055026 # DTB accesses +system.cpu2.numCycles 88306923 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9368286 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32480016 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4780240 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2938039 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6853051 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1759446 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 50956 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19165610 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 248 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 867 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 33412 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 724302 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 479 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4051341 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 290206 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2075 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37405927 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.043731 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.431289 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9346989 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32490356 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4782343 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2941476 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6854845 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1758076 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 51100 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19188137 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 264 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 924 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 33833 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 718254 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 435 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4048944 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 289644 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2020 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37402774 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.043825 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.431125 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30558019 81.69% 81.69% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 385772 1.03% 82.72% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 515915 1.38% 84.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 819609 2.19% 86.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 625256 1.67% 87.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 342326 0.92% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1044683 2.79% 91.67% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 230213 0.62% 92.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2884134 7.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30553136 81.69% 81.69% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 385541 1.03% 82.72% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 516309 1.38% 84.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 819811 2.19% 86.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 629209 1.68% 87.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 341976 0.91% 88.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1043472 2.79% 91.68% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 229749 0.61% 92.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2883571 7.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37405927 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.054118 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.367714 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9993670 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19739606 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6190224 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 324742 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1156786 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 609493 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53173 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36942390 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 178785 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1156786 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10542033 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6802518 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11433975 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5951508 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1518203 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34853467 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 104 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 325261 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 883658 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 140 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37388012 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 160878048 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 148313673 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 3357 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26544776 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10843235 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 285604 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 261905 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3322163 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6624625 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3901879 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 530898 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 772979 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32179363 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 501455 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34749523 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 55329 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7166724 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19100923 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 145150 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37405927 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.928984 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.590317 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37402774 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.054156 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.367925 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9974482 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19754417 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6192036 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 324676 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1156258 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 608942 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 52938 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36945008 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 178323 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1156258 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10522715 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6823267 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11427905 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5953488 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1518249 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34855169 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 93 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 324878 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 884563 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 125 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37394312 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 160859531 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 148302897 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 3365 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26531284 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10863027 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 285247 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 261616 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3319534 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6621271 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3899723 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 529692 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 779693 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32174765 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 504636 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34747602 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 55361 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7180763 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19089893 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 148627 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37402774 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.929011 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.590003 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24720555 66.09% 66.09% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3979487 10.64% 76.73% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2312001 6.18% 82.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1968335 5.26% 88.17% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2779247 7.43% 95.60% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 968566 2.59% 98.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 497905 1.33% 99.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 144867 0.39% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34964 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24715445 66.08% 66.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3980638 10.64% 76.72% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2310084 6.18% 82.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1974798 5.28% 88.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2777209 7.43% 95.60% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 968528 2.59% 98.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 496348 1.33% 99.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 144954 0.39% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34770 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37405927 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37402774 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19427 1.28% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1392100 91.45% 92.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 110700 7.27% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19778 1.30% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1391818 91.56% 92.86% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 108581 7.14% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 8337 0.02% 0.02% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19784762 56.94% 56.96% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 28044 0.08% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 4 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 4 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 384 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11409832 32.83% 89.88% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3518152 10.12% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 8338 0.02% 0.02% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19786480 56.94% 56.97% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 28071 0.08% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 5 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 5 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 384 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11408808 32.83% 89.88% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3515506 10.12% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34749523 # Type of FU issued -system.cpu2.iq.rate 0.393408 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1522228 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.043806 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108504523 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39852721 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28051848 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7496 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3959 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3344 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36259410 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 4004 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 206643 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34747602 # Type of FU issued +system.cpu2.iq.rate 0.393487 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1520177 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.043749 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108495492 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39865371 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28048299 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7541 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3951 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3361 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36255412 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 4029 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 205816 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1533647 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 2027 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9444 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 562515 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1533232 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1949 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9487 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 562230 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5286265 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 344866 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5287398 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 344554 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1156786 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5177746 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 87629 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32763326 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 61736 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6624625 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3901879 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 359192 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 29253 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2415 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9444 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 107780 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 89787 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 197567 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33835206 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11139307 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 914317 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1156258 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5195373 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 88422 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32761739 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 61550 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6621271 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3899723 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 362828 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 29785 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2577 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9487 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 107399 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 89296 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 196695 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33832847 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11137918 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 914755 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 82508 # number of nop insts executed -system.cpu2.iew.exec_refs 14623996 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3761047 # Number of branches executed -system.cpu2.iew.exec_stores 3484689 # Number of stores executed -system.cpu2.iew.exec_rate 0.383056 # Inst execution rate -system.cpu2.iew.wb_sent 33433924 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28055192 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16098734 # num instructions producing a value -system.cpu2.iew.wb_consumers 29085804 # num instructions consuming a value +system.cpu2.iew.exec_nop 82338 # number of nop insts executed +system.cpu2.iew.exec_refs 14620271 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3761250 # Number of branches executed +system.cpu2.iew.exec_stores 3482353 # Number of stores executed +system.cpu2.iew.exec_rate 0.383128 # Inst execution rate +system.cpu2.iew.wb_sent 33431998 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28051660 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16098716 # num instructions producing a value +system.cpu2.iew.wb_consumers 29087027 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.317620 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.553491 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.317661 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.553467 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7134883 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356305 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 171320 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 36248935 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.700393 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.738300 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7131660 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356009 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 171002 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 36246314 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.700075 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.737192 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27340525 75.42% 75.42% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4430140 12.22% 87.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1255420 3.46% 91.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 637620 1.76% 92.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 510981 1.41% 94.28% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 317875 0.88% 95.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 419132 1.16% 96.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 311355 0.86% 97.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1025887 2.83% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27334959 75.41% 75.41% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4433375 12.23% 87.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1255912 3.46% 91.11% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 639801 1.77% 92.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 511761 1.41% 94.29% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 317445 0.88% 95.16% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 418775 1.16% 96.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 310656 0.86% 97.18% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1023630 2.82% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 36248935 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20549284 # Number of instructions committed -system.cpu2.commit.committedOps 25388512 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 36246314 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20540563 # Number of instructions committed +system.cpu2.commit.committedOps 25375153 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8430342 # Number of memory references committed -system.cpu2.commit.loads 5090978 # Number of loads committed -system.cpu2.commit.membars 94231 # Number of memory barriers committed -system.cpu2.commit.branches 3241086 # Number of branches committed +system.cpu2.commit.refs 8425532 # Number of memory references committed +system.cpu2.commit.loads 5088039 # Number of loads committed +system.cpu2.commit.membars 94081 # Number of memory barriers committed +system.cpu2.commit.branches 3238597 # Number of branches committed system.cpu2.commit.fp_insts 3299 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22644563 # Number of committed integer instructions. -system.cpu2.commit.function_calls 295800 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 1025887 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 22633154 # Number of committed integer instructions. +system.cpu2.commit.function_calls 295425 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 1023630 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 67225559 # The number of ROB reads -system.cpu2.rob.rob_writes 66247729 # The number of ROB writes -system.cpu2.timesIdled 359329 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 50923621 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3554004914 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20493925 # Number of Instructions Simulated -system.cpu2.committedOps 25333153 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 20493925 # Number of Instructions Simulated -system.cpu2.cpi 4.310036 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.310036 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.232017 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.232017 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 157011420 # number of integer regfile reads -system.cpu2.int_regfile_writes 29864331 # number of integer regfile writes -system.cpu2.fp_regfile_reads 46835 # number of floating regfile reads -system.cpu2.fp_regfile_writes 45178 # number of floating regfile writes -system.cpu2.misc_regfile_reads 66864323 # number of misc regfile reads -system.cpu2.misc_regfile_writes 296992 # number of misc regfile writes +system.cpu2.rob.rob_reads 67208837 # The number of ROB reads +system.cpu2.rob.rob_writes 66213984 # The number of ROB writes +system.cpu2.timesIdled 359252 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 50904149 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3546216081 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20485207 # Number of Instructions Simulated +system.cpu2.committedOps 25319797 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 20485207 # Number of Instructions Simulated +system.cpu2.cpi 4.310765 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.310765 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.231977 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.231977 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 156999830 # number of integer regfile reads +system.cpu2.int_regfile_writes 29869338 # number of integer regfile writes +system.cpu2.fp_regfile_reads 46882 # number of floating regfile reads +system.cpu2.fp_regfile_writes 45194 # number of floating regfile writes +system.cpu2.misc_regfile_reads 67020139 # number of misc regfile reads +system.cpu2.misc_regfile_writes 296788 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2151,10 +1984,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1347826044250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1347826044250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1347826044250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1347826044250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1539425711000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1539425711000 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1539425711000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1539425711000 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 1944dbbec..ef9bf74a4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.550456 # Number of seconds simulated -sim_ticks 2550455693500 # Number of ticks simulated -final_tick 2550455693500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.550648 # Number of seconds simulated +sim_ticks 2550647964000 # Number of ticks simulated +final_tick 2550647964000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59744 # Simulator instruction rate (inst/s) -host_op_rate 76873 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2526372396 # Simulator tick rate (ticks/s) -host_mem_usage 427472 # Number of bytes of host memory used -host_seconds 1009.53 # Real time elapsed on the host -sim_insts 60313472 # Number of instructions simulated -sim_ops 77606209 # Number of ops (including micro ops) simulated +host_inst_rate 57676 # Simulator instruction rate (inst/s) +host_op_rate 74213 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2439007396 # Simulator tick rate (ticks/s) +host_mem_usage 470664 # Number of bytes of host memory used +host_seconds 1045.77 # Real time elapsed on the host +sim_insts 60315890 # Number of instructions simulated +sim_ops 77609880 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory @@ -26,142 +26,142 @@ system.realview.nvmem.bw_inst_read::total 25 # I system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 2176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 2048 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 504320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5079000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 295488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4015064 # Number of bytes read from this memory -system.physmem.bytes_read::total 131007536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 504320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 295488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799808 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3786368 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1520720 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1495380 # Number of bytes written to this memory -system.physmem.bytes_written::total 6802468 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 483008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5043284 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 315584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4051356 # Number of bytes read from this memory +system.physmem.bytes_read::total 131006576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 483008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 315584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785856 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1521376 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1494724 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801956 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 34 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 32 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7880 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 79395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4617 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 62741 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293498 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59162 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380180 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373845 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813187 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47485839 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 853 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7547 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 78836 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4931 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 63309 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293483 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59154 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380344 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373681 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813179 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47482259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 803 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 197737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1991409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 115857 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1574254 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51366325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 197737 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 115857 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313594 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484585 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 596254 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 586319 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2667158 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484585 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47485839 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 853 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 189367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1977256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 251 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 123727 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1588363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51362077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 189367 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 123727 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313094 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484272 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 596466 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 586017 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2666756 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47482259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 803 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 197737 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2587663 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 115857 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2160572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54033483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293498 # Number of read requests accepted -system.physmem.writeReqs 813187 # Number of write requests accepted -system.physmem.readBursts 15293498 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813187 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 978241024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 542848 # Total number of bytes read from write queue -system.physmem.bytesWritten 6911808 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131007536 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6802468 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 8482 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 705190 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4696 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955869 # Per bank write bursts -system.physmem.perBankRdBursts::1 955539 # Per bank write bursts -system.physmem.perBankRdBursts::2 954667 # Per bank write bursts -system.physmem.perBankRdBursts::3 954789 # Per bank write bursts -system.physmem.perBankRdBursts::4 955759 # Per bank write bursts -system.physmem.perBankRdBursts::5 955951 # Per bank write bursts -system.physmem.perBankRdBursts::6 954859 # Per bank write bursts -system.physmem.perBankRdBursts::7 954668 # Per bank write bursts -system.physmem.perBankRdBursts::8 956272 # Per bank write bursts -system.physmem.perBankRdBursts::9 955769 # Per bank write bursts -system.physmem.perBankRdBursts::10 954516 # Per bank write bursts -system.physmem.perBankRdBursts::11 954114 # Per bank write bursts -system.physmem.perBankRdBursts::12 956222 # Per bank write bursts -system.physmem.perBankRdBursts::13 955973 # Per bank write bursts -system.physmem.perBankRdBursts::14 955087 # Per bank write bursts -system.physmem.perBankRdBursts::15 954962 # Per bank write bursts -system.physmem.perBankWrBursts::0 6687 # Per bank write bursts -system.physmem.perBankWrBursts::1 6466 # Per bank write bursts -system.physmem.perBankWrBursts::2 6605 # Per bank write bursts -system.physmem.perBankWrBursts::3 6628 # Per bank write bursts -system.physmem.perBankWrBursts::4 6579 # Per bank write bursts -system.physmem.perBankWrBursts::5 6834 # Per bank write bursts -system.physmem.perBankWrBursts::6 6823 # Per bank write bursts -system.physmem.perBankWrBursts::7 6763 # Per bank write bursts -system.physmem.perBankWrBursts::8 7134 # Per bank write bursts -system.physmem.perBankWrBursts::9 6882 # Per bank write bursts -system.physmem.perBankWrBursts::10 6543 # Per bank write bursts -system.physmem.perBankWrBursts::11 6191 # Per bank write bursts -system.physmem.perBankWrBursts::12 7147 # Per bank write bursts -system.physmem.perBankWrBursts::13 6760 # Per bank write bursts -system.physmem.perBankWrBursts::14 7044 # Per bank write bursts -system.physmem.perBankWrBursts::15 6911 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 189367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2573722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 123727 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2174381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54028833 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293483 # Number of read requests accepted +system.physmem.writeReqs 813179 # Number of write requests accepted +system.physmem.readBursts 15293483 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813179 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 976671488 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2111424 # Total number of bytes read from write queue +system.physmem.bytesWritten 6834624 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131006576 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6801956 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 32991 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706366 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4694 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955809 # Per bank write bursts +system.physmem.perBankRdBursts::1 953120 # Per bank write bursts +system.physmem.perBankRdBursts::2 953063 # Per bank write bursts +system.physmem.perBankRdBursts::3 953290 # Per bank write bursts +system.physmem.perBankRdBursts::4 955524 # Per bank write bursts +system.physmem.perBankRdBursts::5 952811 # Per bank write bursts +system.physmem.perBankRdBursts::6 952747 # Per bank write bursts +system.physmem.perBankRdBursts::7 952554 # Per bank write bursts +system.physmem.perBankRdBursts::8 956154 # Per bank write bursts +system.physmem.perBankRdBursts::9 953015 # Per bank write bursts +system.physmem.perBankRdBursts::10 952848 # Per bank write bursts +system.physmem.perBankRdBursts::11 952579 # Per bank write bursts +system.physmem.perBankRdBursts::12 956184 # Per bank write bursts +system.physmem.perBankRdBursts::13 953741 # Per bank write bursts +system.physmem.perBankRdBursts::14 953594 # Per bank write bursts +system.physmem.perBankRdBursts::15 953459 # Per bank write bursts +system.physmem.perBankWrBursts::0 6616 # Per bank write bursts +system.physmem.perBankWrBursts::1 6407 # Per bank write bursts +system.physmem.perBankWrBursts::2 6542 # Per bank write bursts +system.physmem.perBankWrBursts::3 6564 # Per bank write bursts +system.physmem.perBankWrBursts::4 6491 # Per bank write bursts +system.physmem.perBankWrBursts::5 6761 # Per bank write bursts +system.physmem.perBankWrBursts::6 6753 # Per bank write bursts +system.physmem.perBankWrBursts::7 6706 # Per bank write bursts +system.physmem.perBankWrBursts::8 7029 # Per bank write bursts +system.physmem.perBankWrBursts::9 6806 # Per bank write bursts +system.physmem.perBankWrBursts::10 6476 # Per bank write bursts +system.physmem.perBankWrBursts::11 6118 # Per bank write bursts +system.physmem.perBankWrBursts::12 7056 # Per bank write bursts +system.physmem.perBankWrBursts::13 6677 # Per bank write bursts +system.physmem.perBankWrBursts::14 6959 # Per bank write bursts +system.physmem.perBankWrBursts::15 6830 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2550454486000 # Total gap between requests +system.physmem.totGap 2550646795500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 44 # Read request sizes (log2) system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154638 # Read request sizes (log2) +system.physmem.readPktSize::6 154623 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754025 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59162 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1173632 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1113468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1067801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3688063 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2661485 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2656312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2669345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 52900 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20336 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59154 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1055042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 994364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 947765 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 947544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 945397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 945218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2783572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2783267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3699218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 24042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 23218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 23233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 22770 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 22263 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 21886 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 21619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 50 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -173,717 +173,457 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86865 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11341.188281 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1014.168764 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16824.493217 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23628 27.20% 27.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14156 16.30% 43.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2700 3.11% 46.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2166 2.49% 49.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1318 1.52% 50.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1170 1.35% 51.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 896 1.03% 52.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 913 1.05% 54.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 566 0.65% 54.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 606 0.70% 55.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 521 0.60% 55.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 631 0.73% 56.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 271 0.31% 57.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 267 0.31% 57.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 154 0.18% 57.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 590 0.68% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 110 0.13% 58.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 147 0.17% 58.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 73 0.08% 58.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 151 0.17% 58.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 55 0.06% 58.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 532 0.61% 59.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 32 0.04% 59.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 226 0.26% 59.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 18 0.02% 59.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 114 0.13% 59.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 25 0.03% 59.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 112 0.13% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 26 0.03% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 51 0.06% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 19 0.02% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 424 0.49% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 10 0.01% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 29 0.03% 60.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 12 0.01% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 47 0.05% 60.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 15 0.02% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 23 0.03% 60.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 12 0.01% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 153 0.18% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 13 0.01% 60.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 25 0.03% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 8 0.01% 61.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 30 0.03% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 14 0.02% 61.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 22 0.03% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 8 0.01% 61.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 344 0.40% 61.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 8 0.01% 61.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 12 0.01% 61.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 9 0.01% 61.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 150 0.17% 61.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 12 0.01% 61.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 8 0.01% 61.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 14 0.02% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 136 0.16% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 11 0.01% 61.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 13 0.01% 61.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 10 0.01% 61.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 83 0.10% 62.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 12 0.01% 62.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 470 0.54% 62.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 7 0.01% 62.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 13 0.01% 62.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 83 0.10% 62.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 13 0.01% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 10 0.01% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 11 0.01% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 20 0.02% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 11 0.01% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 7 0.01% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 8 0.01% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 151 0.17% 63.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 7 0.01% 63.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 13 0.01% 63.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 10 0.01% 63.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 397 0.46% 63.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 3 0.00% 63.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 13 0.01% 63.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 7 0.01% 63.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 18 0.02% 63.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 13 0.01% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 9 0.01% 63.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 10 0.01% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 76 0.09% 63.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 6 0.01% 63.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 11 0.01% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 5 0.01% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 208 0.24% 63.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 5 0.01% 63.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 13 0.01% 63.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 7 0.01% 63.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 368 0.42% 64.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 6 0.01% 64.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 3 0.00% 64.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 4 0.00% 64.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 73 0.08% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 2 0.00% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 7 0.01% 64.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 5 0.01% 64.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 137 0.16% 64.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 10 0.01% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 24 0.03% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 2 0.00% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 60 0.07% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 5 0.01% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 5 0.01% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 7 0.01% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 270 0.31% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 5 0.01% 65.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 10 0.01% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 9 0.01% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 215 0.25% 65.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 8 0.01% 65.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 21 0.02% 65.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 7 0.01% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 8 0.01% 65.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 2 0.00% 65.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 2 0.00% 65.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 69 0.08% 65.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 4 0.00% 65.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 6 0.01% 65.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 602 0.69% 66.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8391 1 0.00% 66.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 67 0.08% 66.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 2 0.00% 66.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 203 0.23% 66.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 262 0.30% 66.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9287 1 0.00% 66.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 56 0.06% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 129 0.15% 67.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9799 1 0.00% 67.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 65 0.07% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10055 1 0.00% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 354 0.41% 67.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10375 1 0.00% 67.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 132 0.15% 67.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 66 0.08% 67.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 2 0.00% 67.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 377 0.43% 68.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 143 0.16% 68.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 1 0.00% 68.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 65 0.07% 68.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 444 0.51% 68.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 65 0.07% 69.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12679 1 0.00% 69.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 120 0.14% 69.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 129 0.15% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 321 0.37% 69.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 4 0.00% 69.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13703 1 0.00% 69.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 137 0.16% 69.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13959 1 0.00% 69.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 5 0.01% 69.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14151 1 0.00% 69.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 1 0.00% 69.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 386 0.44% 70.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 64 0.07% 70.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 71 0.08% 70.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 56 0.06% 70.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 1 0.00% 70.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 386 0.44% 70.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 121 0.14% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 5 0.01% 71.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 125 0.14% 71.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 641 0.74% 72.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16455 1 0.00% 72.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16519 1 0.00% 72.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 125 0.14% 72.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16839 1 0.00% 72.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 7 0.01% 72.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 120 0.14% 72.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17223 1 0.00% 72.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 386 0.44% 72.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 54 0.06% 72.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17735 2 0.00% 72.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17856-17863 1 0.00% 72.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 71 0.08% 72.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-17991 1 0.00% 72.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18112-18119 1 0.00% 72.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 65 0.07% 72.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18368-18375 1 0.00% 72.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 384 0.44% 73.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 5 0.01% 73.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 132 0.15% 73.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 6 0.01% 73.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 1 0.00% 73.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 322 0.37% 73.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 129 0.15% 74.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 120 0.14% 74.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 65 0.07% 74.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 442 0.51% 74.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20672-20679 1 0.00% 74.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 64 0.07% 74.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 1 0.00% 74.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21120-21127 1 0.00% 74.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 144 0.17% 75.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 377 0.43% 75.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 65 0.07% 75.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 131 0.15% 75.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 354 0.41% 76.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22656-22663 1 0.00% 76.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 66 0.08% 76.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22912-22919 1 0.00% 76.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 128 0.15% 76.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 55 0.06% 76.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 261 0.30% 76.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23616-23623 1 0.00% 76.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 203 0.23% 76.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 2 0.00% 76.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24256-24263 1 0.00% 76.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 67 0.08% 77.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24512-24519 1 0.00% 77.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 495 0.57% 77.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 66 0.08% 77.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 2 0.00% 77.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 204 0.23% 77.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 262 0.30% 78.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 56 0.06% 78.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 129 0.15% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 67 0.08% 78.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 355 0.41% 78.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26752-26759 1 0.00% 78.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 131 0.15% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26944-26951 1 0.00% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27072-27079 1 0.00% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 64 0.07% 79.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27328-27335 2 0.00% 79.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 3 0.00% 79.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27520-27527 1 0.00% 79.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 377 0.43% 79.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 143 0.16% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 65 0.07% 79.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 441 0.51% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 65 0.07% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 119 0.14% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 128 0.15% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29575 1 0.00% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 321 0.37% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 6 0.01% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 134 0.15% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 4 0.00% 81.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 385 0.44% 81.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 66 0.08% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 71 0.08% 81.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31296-31303 2 0.00% 81.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 54 0.06% 81.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 385 0.44% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 120 0.14% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 4 0.00% 82.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 124 0.14% 82.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 640 0.74% 83.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32896-32903 1 0.00% 83.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 124 0.14% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 4 0.00% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 121 0.14% 83.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33671 1 0.00% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33735 1 0.00% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 386 0.44% 84.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 54 0.06% 84.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34112-34119 1 0.00% 84.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 71 0.08% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 66 0.08% 84.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 384 0.44% 84.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35008-35015 1 0.00% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 4 0.00% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 134 0.15% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 5 0.01% 84.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35776-35783 1 0.00% 84.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 321 0.37% 85.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 128 0.15% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 120 0.14% 85.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 65 0.07% 85.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 441 0.51% 86.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 64 0.07% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 1 0.00% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 143 0.16% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37760-37767 1 0.00% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37824-37831 1 0.00% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 377 0.43% 86.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 1 0.00% 86.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38208-38215 1 0.00% 86.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 64 0.07% 86.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38464-38471 1 0.00% 86.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 130 0.15% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 355 0.41% 87.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 66 0.08% 87.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 128 0.15% 87.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39616-39623 1 0.00% 87.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 55 0.06% 87.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 261 0.30% 88.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40000-40007 1 0.00% 88.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 203 0.23% 88.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 1 0.00% 88.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 66 0.08% 88.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 496 0.57% 88.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 67 0.08% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41280-41287 1 0.00% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 2 0.00% 89.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 203 0.23% 89.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41920-41927 1 0.00% 89.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 260 0.30% 89.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 55 0.06% 89.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42304-42311 1 0.00% 89.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 128 0.15% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 67 0.08% 89.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42880-42887 1 0.00% 89.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 353 0.41% 90.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 131 0.15% 90.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 65 0.07% 90.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43840-43847 1 0.00% 90.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 379 0.44% 90.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 143 0.16% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44416-44423 2 0.00% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 67 0.08% 91.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 443 0.51% 91.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 67 0.08% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 122 0.14% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45632-45639 1 0.00% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 1 0.00% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45760-45767 1 0.00% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 130 0.15% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46016-46023 1 0.00% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 322 0.37% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 4 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 131 0.15% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 5 0.01% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-46983 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 384 0.44% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 64 0.07% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47552-47559 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 72 0.08% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 54 0.06% 93.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 385 0.44% 93.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 121 0.14% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48576-48583 1 0.00% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 5 0.01% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48832-48839 1 0.00% 93.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 123 0.14% 93.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 2 0.00% 93.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 1 0.00% 93.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5211 6.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49536-49543 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50112-50119 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50695 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51008-51015 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51463 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51648-51655 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51712-51719 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86865 # Bytes accessed per row activation -system.physmem.totQLat 369784547000 # Total ticks spent queuing -system.physmem.totMemAccLat 463560559500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76425080000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17350932500 # Total ticks spent accessing banks -system.physmem.avgQLat 24192.62 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1135.16 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 965273 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 1013.486813 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 999.850047 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 92.541667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 4202 0.44% 0.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 3517 0.36% 0.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1855 0.19% 0.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1291 0.13% 1.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 949 0.10% 1.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 717 0.07% 1.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 589 0.06% 1.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 765 0.08% 1.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 951388 98.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 965273 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5001 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 3051.486103 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 52637.524815 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 4974 99.46% 99.46% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.48% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::131072-196607 8 0.16% 99.64% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 6 0.12% 99.76% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::393216-458751 1 0.02% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::589824-655359 2 0.04% 99.82% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.84% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 7 0.14% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5001 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5001 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.353929 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.695200 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 9.701170 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 8 0.16% 0.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 2 0.04% 0.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 3 0.06% 0.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 1 0.02% 0.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 8 0.16% 0.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 1 0.02% 0.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 1 0.02% 0.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 3 0.06% 0.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 5 0.10% 0.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 2 0.04% 0.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 5 0.10% 0.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12 2 0.04% 0.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 1 0.02% 0.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14 1 0.02% 0.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 10 0.20% 1.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2816 56.31% 57.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 26 0.52% 57.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 135 2.70% 60.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 879 17.58% 78.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 49 0.98% 79.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 23 0.46% 79.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 15 0.30% 79.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 25 0.50% 80.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 14 0.28% 80.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 18 0.36% 81.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 7 0.14% 81.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 15 0.30% 81.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 16 0.32% 81.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 18 0.36% 82.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 15 0.30% 82.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 8 0.16% 82.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 16 0.32% 82.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 10 0.20% 83.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.02% 83.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 1 0.02% 83.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 3 0.06% 83.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 243 4.86% 88.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 480 9.60% 97.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 27 0.54% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 20 0.40% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 27 0.54% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 21 0.42% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 16 0.32% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5001 # Writes before turning the bus around for reads +system.physmem.totQLat 577566851750 # Total ticks spent queuing +system.physmem.totMemAccLat 682115428000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76302460000 # Total ticks spent in databus transfers +system.physmem.totBankLat 28246116250 # Total ticks spent accessing banks +system.physmem.avgQLat 37847.20 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1850.93 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30327.78 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 383.56 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44698.13 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 382.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.68 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.36 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.02 # Data bus utilization in percentage -system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.01 # Data bus utilization in percentage +system.physmem.busUtilRead 2.99 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 1.05 # Average write queue length when enqueuing -system.physmem.readRowHits 15213014 # Number of row buffer hits during reads -system.physmem.writeRowHits 93134 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.24 # Row buffer hit rate for writes -system.physmem.avgGap 158347.57 # Average gap between requests -system.physmem.pageHitRate 99.44 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 2.65 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 54973753 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346163 # Transaction distribution -system.membus.trans_dist::ReadResp 16346166 # Transaction distribution +system.physmem.avgRdQLen 6.73 # Average read queue length when enqueuing +system.physmem.avgWrQLen 15.38 # Average write queue length when enqueuing +system.physmem.readRowHits 14274135 # Number of row buffer hits during reads +system.physmem.writeRowHits 91331 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.54 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.51 # Row buffer hit rate for writes +system.physmem.avgGap 158359.74 # Average gap between requests +system.physmem.pageHitRate 93.48 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.60 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 54969038 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346130 # Transaction distribution +system.membus.trans_dist::ReadResp 16346133 # Transaction distribution system.membus.trans_dist::WriteReq 763365 # Transaction distribution system.membus.trans_dist::WriteResp 763365 # Transaction distribution -system.membus.trans_dist::Writeback 59162 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4696 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4696 # Transaction distribution -system.membus.trans_dist::ReadExReq 131412 # Transaction distribution -system.membus.trans_dist::ReadExResp 131412 # Transaction distribution +system.membus.trans_dist::Writeback 59154 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4693 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4694 # Transaction distribution +system.membus.trans_dist::ReadExReq 131434 # Transaction distribution +system.membus.trans_dist::ReadExResp 131434 # Transaction distribution system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution system.membus.trans_dist::StoreCondReq 3 # Transaction distribution system.membus.trans_dist::StoreCondResp 3 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383052 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383060 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885968 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885926 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272780 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550446 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390470 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34550412 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390486 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16699476 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19097594 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16698004 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19096138 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140208122 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140208122 # Total data (bytes) +system.membus.tot_pkt_size::total 140206666 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140206666 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487391000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487459000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3584500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3645000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17566049500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17565357500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4736056592 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4737629056 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34187486731 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.membus.respLayer2.occupancy 37816335199 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 64408 # number of replacements -system.l2c.tags.tagsinuse 51449.796153 # Cycle average of tags in use -system.l2c.tags.total_refs 1905827 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129798 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.683023 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2540137710500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36969.006628 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 22.725284 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4879.693838 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3326.753767 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.863300 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3332.963946 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2906.789020 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.564102 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000347 # Average percentage of cache occupancy +system.l2c.tags.replacements 64394 # number of replacements +system.l2c.tags.tagsinuse 51423.269942 # Cycle average of tags in use +system.l2c.tags.total_refs 1904392 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129782 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.673776 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2513283956500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36971.606132 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 22.825180 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000372 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4577.267389 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3052.603978 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.951997 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3614.635006 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3176.379887 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.564142 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000348 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074458 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.050762 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000181 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.050857 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044354 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.785062 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65368 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.069844 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.046579 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000121 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.055155 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.048468 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.784657 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 21 # 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average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.537692 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.686706 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62421.351588 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61492.320361 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 62008.251199 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64985.294118 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.332037 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.028816 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61909.037929 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61530.932970 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61740.166261 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64453.125000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60132.375676 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62379.214261 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62489.278752 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61744.106312 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 62013.232366 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64985.294118 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59382.099596 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61974.555949 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60166.599067 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61748.237856 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61701.909837 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64453.125000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60132.375676 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62379.214261 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62489.278752 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61744.106312 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 62013.232366 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59382.099596 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61974.555949 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60166.599067 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61748.237856 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61701.909837 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -1066,49 +814,49 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58427801 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2677013 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2677015 # Transaction distribution +system.toL2Bus.throughput 58424320 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2676714 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2676716 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763365 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763365 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 607832 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2952 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2962 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246108 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246108 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 608227 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2954 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2966 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246181 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246181 # Transaction distribution system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1968942 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5796822 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37990 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 150646 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7954400 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62968576 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85534266 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 56288 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 258652 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148817782 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148817782 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 199736 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4962135725 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967568 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5797861 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37552 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149979 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7952960 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62924224 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85579658 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 54820 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 255152 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148813854 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148813854 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 206020 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4963822946 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4435783766 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4432706696 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4484209498 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4484503287 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 23967895 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 23902881 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86426354 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86618127 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48423111 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322165 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322165 # Transaction distribution +system.iobus.throughput 48419467 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322169 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322169 # Transaction distribution system.iobus.trans_dist::WriteReq 8177 # Transaction distribution system.iobus.trans_dist::WriteResp 8177 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7932 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -1130,12 +878,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383052 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383060 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660684 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660692 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15864 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -1157,14 +905,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390470 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390486 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123500998 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123500998 # Total data (bytes) +system.iobus.tot_pkt_size::total 123501014 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123501014 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3971000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1210,19 +958,19 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374875000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374883000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41493951269 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu0.branchPred.lookups 7524637 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6008547 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 377377 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4829480 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3929632 # Number of BTB hits +system.iobus.respLayer1.occupancy 37825687801 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.cpu0.branchPred.lookups 7508483 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5992866 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 375676 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4822577 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3918936 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.367601 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 723615 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39097 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.262279 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 722501 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39246 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1246,25 +994,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25732063 # DTB read hits -system.cpu0.dtb.read_misses 40060 # DTB read misses -system.cpu0.dtb.write_hits 6173955 # DTB write hits -system.cpu0.dtb.write_misses 10391 # DTB write misses +system.cpu0.dtb.read_hits 25709068 # DTB read hits +system.cpu0.dtb.read_misses 39624 # DTB read misses +system.cpu0.dtb.write_hits 6152335 # DTB write hits +system.cpu0.dtb.write_misses 10221 # DTB write misses system.cpu0.dtb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5654 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1384 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 265 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 760 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5608 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1406 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 264 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 665 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25772123 # DTB read accesses -system.cpu0.dtb.write_accesses 6184346 # DTB write accesses +system.cpu0.dtb.perms_faults 646 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25748692 # DTB read accesses +system.cpu0.dtb.write_accesses 6162556 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31906018 # DTB hits -system.cpu0.dtb.misses 50451 # DTB misses -system.cpu0.dtb.accesses 31956469 # DTB accesses +system.cpu0.dtb.hits 31861403 # DTB hits +system.cpu0.dtb.misses 49845 # DTB misses +system.cpu0.dtb.accesses 31911248 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1286,664 +1034,664 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 5897367 # ITB inst hits -system.cpu0.itb.inst_misses 7084 # ITB inst misses +system.cpu0.itb.inst_hits 5876098 # ITB inst hits +system.cpu0.itb.inst_misses 7014 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2660 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 760 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2644 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1482 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1469 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5904451 # ITB inst accesses -system.cpu0.itb.hits 5897367 # DTB hits -system.cpu0.itb.misses 7084 # DTB misses -system.cpu0.itb.accesses 5904451 # DTB accesses -system.cpu0.numCycles 242280954 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5883112 # ITB inst accesses +system.cpu0.itb.hits 5876098 # DTB hits +system.cpu0.itb.misses 7014 # DTB misses +system.cpu0.itb.accesses 5883112 # DTB accesses +system.cpu0.numCycles 242192321 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15560897 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 45618983 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7524637 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4653247 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10311307 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2438027 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 82681 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 50295736 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 2004 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 47904 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1479659 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 328 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5895435 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 368728 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2960 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 79463748 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.723138 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.071375 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15567613 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 45445847 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7508483 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4641437 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10272972 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2435180 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 81106 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 50250706 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1544 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1986 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 48114 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1489776 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 378 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5874191 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 367063 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2900 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 79394723 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.721041 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.068559 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 69159455 87.03% 87.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 678650 0.85% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 874708 1.10% 88.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1176149 1.48% 90.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1117399 1.41% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 558232 0.70% 92.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1283192 1.61% 94.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 380865 0.48% 94.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4235098 5.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 69128739 87.07% 87.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 676261 0.85% 87.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 870795 1.10% 89.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1169302 1.47% 90.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1115285 1.40% 91.90% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 553948 0.70% 92.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1287197 1.62% 94.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 378519 0.48% 94.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4214677 5.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 79463748 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031057 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.188290 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16659746 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 51317609 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9233971 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 657554 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1592691 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1005769 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 91409 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 54704033 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 304298 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1592691 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17554490 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 20340792 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27693159 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8932278 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3348216 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 52126479 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 377 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 497478 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2175969 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 155 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 53794326 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 241736924 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 220533984 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5031 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 39400219 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14394106 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 593139 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 541531 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6973197 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10037020 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 7000202 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1050357 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1288163 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 48430994 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1028168 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 62176930 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 89712 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9957065 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24599714 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 276838 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 79463748 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.782457 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.501316 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 79394723 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031002 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.187644 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16658432 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 51288095 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9197431 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 656874 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1591763 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1006093 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 91406 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 54494283 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 303520 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1591763 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17551658 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 20345183 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27653568 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8896202 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3354292 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 51932303 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 196 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 500448 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2179621 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 261 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 53595851 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 240832893 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 219678051 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5082 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 39195467 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14400384 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 591696 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 540219 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6961736 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10014185 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6974197 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1050889 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1353332 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 48232956 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1025841 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 61971057 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 88766 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9957722 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24611703 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 275811 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 79394723 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.780544 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.499047 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 56925517 71.64% 71.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7350450 9.25% 80.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3522799 4.43% 85.32% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2913274 3.67% 88.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6168473 7.76% 96.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1495817 1.88% 98.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 789992 0.99% 99.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 231277 0.29% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 66149 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 56910995 71.68% 71.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7345017 9.25% 80.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3503110 4.41% 85.34% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2918035 3.68% 89.02% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6157997 7.76% 96.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1482939 1.87% 98.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 783446 0.99% 99.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 227116 0.29% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 66068 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 79463748 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 79394723 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 30568 0.69% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4194749 94.30% 94.98% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 223174 5.02% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 29670 0.67% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4193006 94.32% 94.99% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 222912 5.01% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 15922 0.03% 0.03% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29222200 47.00% 47.02% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47810 0.08% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1242 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26409099 42.47% 89.58% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6480639 10.42% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 15869 0.03% 0.03% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29065604 46.90% 46.93% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46869 0.08% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1239 0.00% 47.01% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.01% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 47.01% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.01% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26385475 42.58% 89.58% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6455974 10.42% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 62176930 # Type of FU issued -system.cpu0.iq.rate 0.256632 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4448493 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.071546 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208394864 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59425365 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43388237 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11204 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6101 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5139 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 66603600 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5901 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 313863 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 61971057 # Type of FU issued +system.cpu0.iq.rate 0.255875 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4445589 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.071737 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 207909567 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59225484 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43186225 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11292 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6130 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5133 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 66394829 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 5948 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 311727 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2132926 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3897 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15826 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 851086 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2130667 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3740 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15655 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 850179 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17067174 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 347980 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17067257 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 348827 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1592691 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15703960 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 239689 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 49567887 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 107700 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10037020 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 7000202 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 730031 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 54998 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4795 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15826 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 184371 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 145167 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 329538 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 61108768 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26079506 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1068162 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1591763 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15715155 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 239745 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 49373573 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 105603 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10014185 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6974197 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 727713 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 55741 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4727 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15655 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 183161 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 144870 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 328031 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 60906320 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26058550 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1064737 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 108725 # number of nop insts executed -system.cpu0.iew.exec_refs 32501673 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5985971 # Number of branches executed -system.cpu0.iew.exec_stores 6422167 # Number of stores executed -system.cpu0.iew.exec_rate 0.252223 # Inst execution rate -system.cpu0.iew.wb_sent 60615706 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43393376 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 23422073 # num instructions producing a value -system.cpu0.iew.wb_consumers 43067972 # num instructions consuming a value +system.cpu0.iew.exec_nop 114776 # number of nop insts executed +system.cpu0.iew.exec_refs 32455686 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5967734 # Number of branches executed +system.cpu0.iew.exec_stores 6397136 # Number of stores executed +system.cpu0.iew.exec_rate 0.251479 # Inst execution rate +system.cpu0.iew.wb_sent 60414213 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43191358 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 23287316 # num instructions producing a value +system.cpu0.iew.wb_consumers 42834885 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.179104 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.543840 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.178335 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.543653 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 9785974 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 751330 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 287324 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 77871057 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.504327 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.472133 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9785836 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 750030 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 285660 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 77802960 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.502286 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.465598 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 63445664 81.48% 81.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7408180 9.51% 90.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1965702 2.52% 93.51% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1101219 1.41% 94.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 850042 1.09% 96.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 579839 0.74% 96.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 741280 0.95% 97.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 350840 0.45% 98.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1428291 1.83% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 63388396 81.47% 81.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7400911 9.51% 90.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1988257 2.56% 93.54% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1098992 1.41% 94.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 865715 1.11% 96.07% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 575312 0.74% 96.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 733525 0.94% 97.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 350428 0.45% 98.20% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1401424 1.80% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 77871057 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 30068673 # Number of instructions committed -system.cpu0.commit.committedOps 39272492 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 77802960 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 29900744 # Number of instructions committed +system.cpu0.commit.committedOps 39079359 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14053210 # Number of memory references committed -system.cpu0.commit.loads 7904094 # Number of loads committed -system.cpu0.commit.membars 209520 # Number of memory barriers committed -system.cpu0.commit.branches 5180571 # Number of branches committed -system.cpu0.commit.fp_insts 5103 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 34976585 # Number of committed integer instructions. -system.cpu0.commit.function_calls 508087 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1428291 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14007536 # Number of memory references committed +system.cpu0.commit.loads 7883518 # Number of loads committed +system.cpu0.commit.membars 209346 # Number of memory barriers committed +system.cpu0.commit.branches 5162239 # Number of branches committed +system.cpu0.commit.fp_insts 5086 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 34792812 # Number of committed integer instructions. +system.cpu0.commit.function_calls 507721 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1401424 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 124525442 # The number of ROB reads -system.cpu0.rob.rob_writes 99752707 # The number of ROB writes -system.cpu0.timesIdled 907289 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 162817206 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2250738250 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 29995072 # Number of Instructions Simulated -system.cpu0.committedOps 39198891 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 29995072 # Number of Instructions Simulated -system.cpu0.cpi 8.077359 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.077359 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.123803 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.123803 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 277602258 # number of integer regfile reads -system.cpu0.int_regfile_writes 44085175 # number of integer regfile writes -system.cpu0.fp_regfile_reads 44877 # number of floating regfile reads -system.cpu0.fp_regfile_writes 42488 # number of floating regfile writes -system.cpu0.misc_regfile_reads 138395505 # number of misc regfile reads -system.cpu0.misc_regfile_writes 582325 # number of misc regfile writes -system.cpu0.icache.tags.replacements 984398 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.534546 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10515921 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 984910 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.677037 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7008829000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 316.868268 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 194.666278 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.618883 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.380208 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999091 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 124291086 # The number of ROB reads +system.cpu0.rob.rob_writes 99365166 # The number of ROB writes +system.cpu0.timesIdled 908697 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 162797598 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2248209209 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 29823122 # Number of Instructions Simulated +system.cpu0.committedOps 39001737 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 29823122 # Number of Instructions Simulated +system.cpu0.cpi 8.120958 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.120958 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.123138 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.123138 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 276680521 # number of integer regfile reads +system.cpu0.int_regfile_writes 43875243 # number of integer regfile writes +system.cpu0.fp_regfile_reads 44965 # number of floating regfile reads +system.cpu0.fp_regfile_writes 42348 # number of floating regfile writes +system.cpu0.misc_regfile_reads 137565982 # number of misc regfile reads +system.cpu0.misc_regfile_writes 581037 # number of misc regfile writes +system.cpu0.icache.tags.replacements 983714 # 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Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 163 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 12566693 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 12566693 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 5337223 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5178698 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10515921 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5337223 # 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average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11888.125825 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12001.990356 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12105.037502 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11888.125825 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12001.990356 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # 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Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 21529454 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 644356 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.412359 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 43687250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 256.274589 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 255.718633 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.500536 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.499450 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 190 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 101651746 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 101651746 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 7028815 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6747590 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13776405 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3755876 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3505333 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7261209 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116971 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 125973 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 242944 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 119744 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 127881 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247625 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10784691 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10252923 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21037614 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10784691 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10252923 # number of overall hits -system.cpu0.dcache.overall_hits::total 21037614 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 339393 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 409028 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 748421 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1648570 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1313214 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2961784 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7529 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5999 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13528 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 101648096 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 101648096 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 7014056 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6760706 # 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number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10761656 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10273998 # number of overall hits +system.cpu0.dcache.overall_hits::total 21035654 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 333491 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 414863 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 748354 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1635288 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1327358 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2962646 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7514 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6065 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13579 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 4 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1987963 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1722242 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3710205 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1987963 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1722242 # number of overall misses -system.cpu0.dcache.overall_misses::total 3710205 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5452544877 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 5973510192 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11426055069 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 85021863209 # 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number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 160917690891 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 90474408086 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 70443282805 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 160917690891 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7368208 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 7156618 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14524826 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5404446 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 4818547 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10222993 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124500 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 131972 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 256472 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 119750 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 127885 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247635 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12772654 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11975165 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24747819 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12772654 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11975165 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24747819 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.046062 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057154 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051527 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.305040 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.272533 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289718 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060474 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045457 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052746 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 6 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1968779 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1742221 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3711000 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1968779 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1742221 # number of overall misses +system.cpu0.dcache.overall_misses::total 3711000 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5348440293 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6102853229 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11451293522 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 83999211786 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 64837852526 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 148837064312 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 107360498 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 81153996 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 188514494 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 90501 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 78000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 168501 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 89347652079 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 70940705755 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 160288357834 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 256633 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 119397 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 128251 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247648 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12730435 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 12016219 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24746654 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12730435 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 12016219 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24746654 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.045388 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057816 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.051528 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.303794 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.274211 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.289787 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060534 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045772 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052912 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000050 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000031 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000040 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.155642 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.143818 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149920 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.155642 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.143818 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149920 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16065.578480 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14604.159598 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15266.881968 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 51573.098630 # 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average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13380.708326 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13882.796524 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15083.500000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45511.112675 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 40902.081592 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 43371.644125 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45511.112675 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 40902.081592 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 43371.644125 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 36158 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 27990 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3441 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 289 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.507992 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 96.851211 # average number of cycles each access was blocked +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14041.750000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45382.265901 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 40718.545899 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 43192.766864 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45382.265901 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 40718.545899 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 43192.766864 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 37128 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 22269 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3473 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 273 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.690469 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 81.571429 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 607832 # number of writebacks -system.cpu0.dcache.writebacks::total 607832 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 151038 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 211492 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 362530 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1512262 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1200569 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2712831 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 756 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 622 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1378 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1663300 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1412061 # 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number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16804462881 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91527132501 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90809770250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336902751 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13691854278 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13083150967 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26775005245 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 141500 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 141500 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 322616 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 312498 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 635114 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 322616 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 312498 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 635114 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2596085748 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2657791594 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5253877342 # 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number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13068639684 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26779127531 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 155750 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 155750 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105218986779 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103892921217 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209111907996 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025563 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027602 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026568 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025221 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023377 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024352 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.054402 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040743 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047374 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105257486597 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103859896434 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209117383031 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025475 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027721 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026585 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025161 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023465 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.054371 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041108 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047523 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000050 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000031 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025419 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025902 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025653 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025419 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025902 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025653 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13933.898543 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13286.722972 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13602.612056 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47179.018143 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45492.118665 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46415.738360 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12622.287317 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11506.045192 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12128.292757 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000047 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025342 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026006 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025665 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025342 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026006 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025665 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13869.609399 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13361.510975 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13607.837878 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47002.959406 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45387.965893 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46266.328011 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12590.421099 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11563.338351 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12131.703509 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13083.166667 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27891.681728 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24982.400005 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26470.223994 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27891.681728 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24982.400005 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26470.223994 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12041.583333 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27779.380328 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25002.202612 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26412.913077 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27779.380328 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25002.202612 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26412.913077 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1958,15 +1706,15 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7303181 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5881126 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 346154 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4653929 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3750959 # Number of BTB hits +system.cpu1.branchPred.lookups 7323132 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5902490 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 346200 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4511574 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3765481 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 80.597684 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 679679 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34597 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 83.462690 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 676459 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34463 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1990,25 +1738,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25488049 # DTB read hits -system.cpu1.dtb.read_misses 36227 # DTB read misses -system.cpu1.dtb.write_hits 5538132 # DTB write hits -system.cpu1.dtb.write_misses 8320 # DTB write misses -system.cpu1.dtb.flush_tlb 512 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 25506602 # DTB read hits +system.cpu1.dtb.read_misses 36488 # DTB read misses +system.cpu1.dtb.write_hits 5558527 # DTB write hits +system.cpu1.dtb.write_misses 8439 # DTB write misses +system.cpu1.dtb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5495 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1338 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 228 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 679 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 5463 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2276 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 232 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 677 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25524276 # DTB read accesses -system.cpu1.dtb.write_accesses 5546452 # DTB write accesses +system.cpu1.dtb.perms_faults 679 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25543090 # DTB read accesses +system.cpu1.dtb.write_accesses 5566966 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31026181 # DTB hits -system.cpu1.dtb.misses 44547 # DTB misses -system.cpu1.dtb.accesses 31070728 # DTB accesses +system.cpu1.dtb.hits 31065129 # DTB hits +system.cpu1.dtb.misses 44927 # DTB misses +system.cpu1.dtb.accesses 31110056 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -2030,294 +1778,294 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 5688452 # ITB inst hits -system.cpu1.itb.inst_misses 7006 # ITB inst misses +system.cpu1.itb.inst_hits 5703436 # ITB inst hits +system.cpu1.itb.inst_misses 7020 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 512 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2704 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 679 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2688 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1448 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1487 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5695458 # ITB inst accesses -system.cpu1.itb.hits 5688452 # DTB hits -system.cpu1.itb.misses 7006 # DTB misses -system.cpu1.itb.accesses 5695458 # DTB accesses -system.cpu1.numCycles 236990378 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5710456 # ITB inst accesses +system.cpu1.itb.hits 5703436 # DTB hits +system.cpu1.itb.misses 7020 # DTB misses +system.cpu1.itb.accesses 5710456 # DTB accesses +system.cpu1.numCycles 237056909 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14445279 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 45031495 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7303181 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4430638 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9912685 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2288075 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 85272 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 49385810 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1038 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1883 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 43903 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1235955 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5686448 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 352687 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3068 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 76688585 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.724367 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.076407 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14419718 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 45234990 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7323132 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4441940 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9947853 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2287798 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 84999 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 49482147 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1272 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1896 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 44871 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1235484 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 189 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5701379 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 352457 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3064 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76794959 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.726229 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.078871 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66784675 87.09% 87.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 633491 0.83% 87.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 843387 1.10% 89.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1127901 1.47% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 993338 1.30% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 549443 0.72% 92.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1277588 1.67% 94.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 369483 0.48% 94.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4109279 5.36% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66855647 87.06% 87.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 632615 0.82% 87.88% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 843009 1.10% 88.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1133482 1.48% 90.45% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1002056 1.30% 91.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 554704 0.72% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1272745 1.66% 94.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 372184 0.48% 94.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4128517 5.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 76688585 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030816 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.190014 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15549027 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 50133952 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 8864377 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 645129 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1493916 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 964413 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 85194 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 52934695 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 283965 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1493916 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16391230 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19303163 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 27652687 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8622958 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3222506 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 50466149 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 174 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 593171 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 1994496 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 690 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 52886950 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 233487672 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 213429055 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5328 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 39332432 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13554518 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 579559 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 536966 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6477487 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9753455 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6333018 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 895982 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1122035 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 46958561 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 957421 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60864798 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 86364 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9232524 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 23424717 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 226140 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 76688585 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.793662 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.504660 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76794959 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030892 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.190819 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15530724 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 50222847 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 8895356 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 650267 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1493551 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 963840 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 85500 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 53154493 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 286161 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1493551 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16374919 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19306160 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 27715779 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8656578 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3245827 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 50687701 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 339 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 605911 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2002092 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 648 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53113804 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 234485879 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 214384735 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5365 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 39540919 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13572884 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 579809 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 536931 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6499660 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9772559 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6360216 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 888468 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1099515 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47171321 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 962588 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 61070577 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 91971 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9248404 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 23463374 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 229936 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76794959 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.795242 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.505673 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 54509370 71.08% 71.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 7300848 9.52% 80.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3460717 4.51% 85.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2863086 3.73% 88.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6124123 7.99% 96.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1373475 1.79% 98.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 772006 1.01% 99.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 222325 0.29% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 62635 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 54534134 71.01% 71.01% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 7328500 9.54% 80.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3483988 4.54% 85.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2874889 3.74% 88.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6131286 7.98% 96.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1377966 1.79% 98.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 776904 1.01% 99.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 225300 0.29% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 61992 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 76688585 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76794959 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 28981 0.66% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 4 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4176523 94.96% 95.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 192832 4.38% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29712 0.67% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 3 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4180230 94.88% 95.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 195658 4.44% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 12596 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28808168 47.33% 47.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45770 0.08% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 867 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26145062 42.96% 90.38% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 5852305 9.62% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 12649 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28971083 47.44% 47.46% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46630 0.08% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 875 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26162080 42.84% 90.38% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 5877234 9.62% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60864798 # Type of FU issued -system.cpu1.iq.rate 0.256824 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4398340 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.072264 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 202935847 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 57156855 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 42177968 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11410 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6319 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5146 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65244557 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5985 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 312441 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 61070577 # Type of FU issued +system.cpu1.iq.rate 0.257620 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4405603 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.072140 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 203466895 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 57390461 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 42382296 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11528 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6422 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5160 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65457468 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6063 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 311906 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2001655 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2943 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15220 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 749307 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 1999074 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3048 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 15122 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 750838 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 17042804 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 332523 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 17042744 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 332080 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1493916 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14868856 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 223350 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48029034 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 96518 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9753455 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6333018 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 681732 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 49156 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 5134 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15220 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 168778 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 134493 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 303271 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59837987 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25827716 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1026811 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1493551 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14864582 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 222698 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48241525 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 96453 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9772559 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6360216 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 687199 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 48610 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4313 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 15122 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 168053 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 134565 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 302618 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 60042253 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25845364 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1028324 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 113052 # number of nop insts executed -system.cpu1.iew.exec_refs 31629861 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5852394 # Number of branches executed -system.cpu1.iew.exec_stores 5802145 # Number of stores executed -system.cpu1.iew.exec_rate 0.252491 # Inst execution rate -system.cpu1.iew.wb_sent 59370669 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 42183114 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23501476 # num instructions producing a value -system.cpu1.iew.wb_consumers 42733790 # num instructions consuming a value +system.cpu1.iew.exec_nop 107616 # number of nop insts executed +system.cpu1.iew.exec_refs 31671376 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5872062 # Number of branches executed +system.cpu1.iew.exec_stores 5826012 # Number of stores executed +system.cpu1.iew.exec_rate 0.253282 # Inst execution rate +system.cpu1.iew.wb_sent 59578158 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 42387456 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23643387 # num instructions producing a value +system.cpu1.iew.wb_consumers 43005248 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.177995 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.549951 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.178807 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.549779 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9169088 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 731281 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 262316 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 75194669 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.511793 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.483255 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9166908 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 732652 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 262014 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 75301408 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.513681 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.486972 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60941986 81.05% 81.05% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 7448338 9.91% 90.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1921902 2.56% 93.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1064941 1.42% 94.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 820613 1.09% 96.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 497482 0.66% 96.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 699016 0.93% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 369953 0.49% 98.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1430438 1.90% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60995111 81.00% 81.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 7470337 9.92% 90.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1928698 2.56% 93.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1074141 1.43% 94.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 820415 1.09% 96.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 494186 0.66% 96.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 699344 0.93% 97.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 371316 0.49% 98.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1447860 1.92% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 75194669 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 30395180 # Number of instructions committed -system.cpu1.commit.committedOps 38484098 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 75301408 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 30565527 # Number of instructions committed +system.cpu1.commit.committedOps 38680902 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13335511 # Number of memory references committed -system.cpu1.commit.loads 7751800 # Number of loads committed -system.cpu1.commit.membars 194141 # Number of memory barriers committed -system.cpu1.commit.branches 5126394 # Number of branches committed -system.cpu1.commit.fp_insts 5109 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 34219487 # Number of committed integer instructions. -system.cpu1.commit.function_calls 483277 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1430438 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13382863 # Number of memory references committed +system.cpu1.commit.loads 7773485 # Number of loads committed +system.cpu1.commit.membars 194338 # Number of memory barriers committed +system.cpu1.commit.branches 5145142 # Number of branches committed +system.cpu1.commit.fp_insts 5126 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 34406663 # Number of committed integer instructions. +system.cpu1.commit.function_calls 483721 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1447860 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 120543738 # The number of ROB reads -system.cpu1.rob.rob_writes 96843723 # The number of ROB writes -system.cpu1.timesIdled 866392 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 160301793 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2319061347 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 30318400 # Number of Instructions Simulated -system.cpu1.committedOps 38407318 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 30318400 # Number of Instructions Simulated -system.cpu1.cpi 7.816718 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.816718 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.127931 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.127931 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 271568545 # number of integer regfile reads -system.cpu1.int_regfile_writes 43555908 # number of integer regfile writes -system.cpu1.fp_regfile_reads 45194 # number of floating regfile reads -system.cpu1.fp_regfile_writes 42320 # number of floating regfile writes -system.cpu1.misc_regfile_reads 132647791 # number of misc regfile reads -system.cpu1.misc_regfile_writes 591619 # number of misc regfile writes +system.cpu1.rob.rob_reads 120827478 # The number of ROB reads +system.cpu1.rob.rob_writes 97232532 # The number of ROB writes +system.cpu1.timesIdled 865086 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 160261950 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2316983227 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 30492768 # Number of Instructions Simulated +system.cpu1.committedOps 38608143 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 30492768 # Number of Instructions Simulated +system.cpu1.cpi 7.774201 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.774201 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.128631 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.128631 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 272500909 # number of integer regfile reads +system.cpu1.int_regfile_writes 43779735 # number of integer regfile writes +system.cpu1.fp_regfile_reads 45015 # number of floating regfile reads +system.cpu1.fp_regfile_writes 42294 # number of floating regfile writes +system.cpu1.misc_regfile_reads 133085319 # number of misc regfile reads +system.cpu1.misc_regfile_writes 592959 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2334,17 +2082,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518507680269 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1518507680269 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518507680269 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1518507680269 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736889440801 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1736889440801 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736889440801 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1736889440801 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83057 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83061 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 31d2c1779..094868576 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,147 +1,147 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.629750 # Number of seconds simulated -sim_ticks 2629749511500 # Number of ticks simulated -final_tick 2629749511500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.629695 # Number of seconds simulated +sim_ticks 2629694709500 # Number of ticks simulated +final_tick 2629694709500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 406352 # Simulator instruction rate (inst/s) -host_op_rate 517075 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17746353667 # Simulator tick rate (ticks/s) -host_mem_usage 422316 # Number of bytes of host memory used -host_seconds 148.19 # Real time elapsed on the host -sim_insts 60215342 # Number of instructions simulated -sim_ops 76622873 # Number of ops (including micro ops) simulated +host_inst_rate 422902 # Simulator instruction rate (inst/s) +host_op_rate 538135 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18468797106 # Simulator tick rate (ticks/s) +host_mem_usage 466428 # Number of bytes of host memory used +host_seconds 142.39 # Real time elapsed on the host +sim_insts 60215255 # Number of instructions simulated +sim_ops 76622777 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 298760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4637400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 291720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4684888 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 405700 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4423316 # Number of bytes read from this memory -system.physmem.bytes_read::total 134021624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 298760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 405700 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704460 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3690048 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1524460 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1491820 # Number of bytes written to this memory -system.physmem.bytes_written::total 6706328 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 412356 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4375828 # Number of bytes read from this memory +system.physmem.bytes_read::total 134021240 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 291720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 412356 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704076 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3689664 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1522876 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1493404 # Number of bytes written to this memory +system.physmem.bytes_written::total 6705944 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10880 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 72495 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10770 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73237 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6355 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 69149 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690914 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57657 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 381115 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 372955 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811727 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47250225 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6459 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 68407 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690908 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57651 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380719 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373351 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811721 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47251210 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 113608 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1763438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 110933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1781533 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 154273 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1682029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50963646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 113608 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 154273 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267881 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1403194 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 579698 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 567286 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2550177 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1403194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47250225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 156808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1664006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50964562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 110933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 156808 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267741 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1403077 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 579108 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 567900 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2550085 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1403077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47251210 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 113608 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2343136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 110933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2360641 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 154273 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2249315 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53513824 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690914 # Number of read requests accepted -system.physmem.writeReqs 811727 # Number of write requests accepted -system.physmem.readBursts 15690914 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811727 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1004216640 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1856 # Total number of bytes read from write queue -system.physmem.bytesWritten 6837504 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134021624 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6706328 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 704891 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4516 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 980392 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 156808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2231906 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53514647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690908 # Number of read requests accepted +system.physmem.writeReqs 811721 # Number of write requests accepted +system.physmem.readBursts 15690908 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811721 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1004216192 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1920 # Total number of bytes read from write queue +system.physmem.bytesWritten 6737024 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134021240 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6705944 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 30 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706455 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4517 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 980391 # Per bank write bursts system.physmem.perBankRdBursts::1 980206 # Per bank write bursts -system.physmem.perBankRdBursts::2 980222 # Per bank write bursts +system.physmem.perBankRdBursts::2 980218 # Per bank write bursts system.physmem.perBankRdBursts::3 980431 # Per bank write bursts system.physmem.perBankRdBursts::4 986950 # Per bank write bursts system.physmem.perBankRdBursts::5 980708 # Per bank write bursts system.physmem.perBankRdBursts::6 980610 # Per bank write bursts -system.physmem.perBankRdBursts::7 980424 # Per bank write bursts +system.physmem.perBankRdBursts::7 980421 # Per bank write bursts system.physmem.perBankRdBursts::8 980615 # Per bank write bursts system.physmem.perBankRdBursts::9 980431 # Per bank write bursts system.physmem.perBankRdBursts::10 979815 # Per bank write bursts system.physmem.perBankRdBursts::11 979558 # Per bank write bursts -system.physmem.perBankRdBursts::12 980153 # Per bank write bursts +system.physmem.perBankRdBursts::12 980154 # Per bank write bursts system.physmem.perBankRdBursts::13 980093 # Per bank write bursts system.physmem.perBankRdBursts::14 980167 # Per bank write bursts system.physmem.perBankRdBursts::15 980110 # Per bank write bursts -system.physmem.perBankWrBursts::0 6736 # Per bank write bursts -system.physmem.perBankWrBursts::1 6598 # Per bank write bursts -system.physmem.perBankWrBursts::2 6606 # Per bank write bursts -system.physmem.perBankWrBursts::3 6671 # Per bank write bursts -system.physmem.perBankWrBursts::4 6749 # Per bank write bursts -system.physmem.perBankWrBursts::5 7050 # Per bank write bursts -system.physmem.perBankWrBursts::6 7030 # Per bank write bursts -system.physmem.perBankWrBursts::7 6882 # Per bank write bursts -system.physmem.perBankWrBursts::8 6998 # Per bank write bursts -system.physmem.perBankWrBursts::9 6828 # Per bank write bursts -system.physmem.perBankWrBursts::10 6323 # Per bank write bursts -system.physmem.perBankWrBursts::11 6124 # Per bank write bursts -system.physmem.perBankWrBursts::12 6612 # Per bank write bursts -system.physmem.perBankWrBursts::13 6392 # Per bank write bursts -system.physmem.perBankWrBursts::14 6620 # Per bank write bursts -system.physmem.perBankWrBursts::15 6617 # Per bank write bursts +system.physmem.perBankWrBursts::0 6645 # Per bank write bursts +system.physmem.perBankWrBursts::1 6506 # Per bank write bursts +system.physmem.perBankWrBursts::2 6513 # Per bank write bursts +system.physmem.perBankWrBursts::3 6561 # Per bank write bursts +system.physmem.perBankWrBursts::4 6643 # Per bank write bursts +system.physmem.perBankWrBursts::5 6949 # Per bank write bursts +system.physmem.perBankWrBursts::6 6933 # Per bank write bursts +system.physmem.perBankWrBursts::7 6786 # Per bank write bursts +system.physmem.perBankWrBursts::8 6904 # Per bank write bursts +system.physmem.perBankWrBursts::9 6725 # Per bank write bursts +system.physmem.perBankWrBursts::10 6221 # Per bank write bursts +system.physmem.perBankWrBursts::11 6029 # Per bank write bursts +system.physmem.perBankWrBursts::12 6513 # Per bank write bursts +system.physmem.perBankWrBursts::13 6297 # Per bank write bursts +system.physmem.perBankWrBursts::14 6516 # Per bank write bursts +system.physmem.perBankWrBursts::15 6525 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2629745080000 # Total gap between requests +system.physmem.totGap 2629690290000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6718 # Read request sizes (log2) system.physmem.readPktSize::3 15532032 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152164 # Read request sizes (log2) +system.physmem.readPktSize::6 152158 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754070 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57657 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1279103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1122938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1123139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3790711 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2702315 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2701600 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2718927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 52097 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 57127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20508 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20484 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 49 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57651 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1128915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 971082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 971066 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 973046 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 971647 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 972454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2865167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2865325 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3808659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 25323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 23577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 23920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 23318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 22983 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 22230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 22150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -157,372 +157,172 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90358 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11189.419509 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1031.170467 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16748.902235 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23468 25.97% 25.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14751 16.33% 42.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2914 3.22% 45.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2094 2.32% 47.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1353 1.50% 49.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1190 1.32% 50.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 937 1.04% 51.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1064 1.18% 52.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 629 0.70% 53.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 518 0.57% 54.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 534 0.59% 54.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 581 0.64% 55.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 314 0.35% 55.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 296 0.33% 56.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 233 0.26% 56.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 596 0.66% 56.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 187 0.21% 57.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 143 0.16% 57.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 114 0.13% 57.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 279 0.31% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 129 0.14% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2228 2.47% 60.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 121 0.13% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 211 0.23% 60.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 45 0.05% 60.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 43 0.05% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 36 0.04% 60.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 110 0.12% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 48 0.05% 61.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 23 0.03% 61.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 25 0.03% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 356 0.39% 61.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 15 0.02% 61.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 22 0.02% 61.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 30 0.03% 61.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 81 0.09% 61.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 12 0.01% 61.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 26 0.03% 61.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 20 0.02% 61.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 86 0.10% 61.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 19 0.02% 61.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 10 0.01% 61.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 26 0.03% 61.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 61 0.07% 61.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 6 0.01% 61.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 22 0.02% 61.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 332 0.37% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 20 0.02% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 10 0.01% 62.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 9 0.01% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 157 0.17% 62.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 5 0.01% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 12 0.01% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 18 0.02% 62.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 140 0.15% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 11 0.01% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 18 0.02% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 30 0.03% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 133 0.15% 62.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 19 0.02% 63.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 8 0.01% 63.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 8 0.01% 63.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 364 0.40% 63.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 3 0.00% 63.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 3 0.00% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 18 0.02% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 73 0.08% 63.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 2 0.00% 63.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 14 0.02% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 3 0.00% 63.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 77 0.09% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 17 0.02% 63.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 5 0.01% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 3 0.00% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 26 0.03% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 5 0.01% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 8 0.01% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 15 0.02% 63.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 270 0.30% 64.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 5 0.01% 64.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 15 0.02% 64.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 3 0.00% 64.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 73 0.08% 64.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 165 0.18% 64.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 59 0.07% 64.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 1 0.00% 64.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 245 0.27% 64.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 129 0.14% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 1 0.00% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 396 0.44% 65.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 186 0.21% 65.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 2 0.00% 65.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 68 0.08% 65.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 1 0.00% 65.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 2 0.00% 65.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 266 0.29% 65.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 68 0.08% 65.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 129 0.14% 66.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 66 0.07% 66.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 514 0.57% 66.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 66 0.07% 66.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 130 0.14% 66.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 68 0.08% 66.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 264 0.29% 67.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 2 0.00% 67.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 69 0.08% 67.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 190 0.21% 67.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10055 1 0.00% 67.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 395 0.44% 67.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 130 0.14% 68.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 245 0.27% 68.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 65 0.07% 68.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 270 0.30% 68.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 6 0.01% 68.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11591 1 0.00% 68.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 73 0.08% 68.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11840-11847 1 0.00% 68.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 68 0.08% 68.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 342 0.38% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 2 0.00% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 127 0.14% 69.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12679 1 0.00% 69.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 128 0.14% 69.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 133 0.15% 69.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 321 0.36% 70.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 57 0.06% 70.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 77 0.09% 70.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 70 0.08% 70.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 324 0.36% 70.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14407 1 0.00% 70.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 72 0.08% 70.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 127 0.14% 70.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 141 0.16% 71.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 387 0.43% 71.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 73 0.08% 71.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 1 0.00% 71.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 65 0.07% 71.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 651 0.72% 72.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 66 0.07% 72.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 2 0.00% 72.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16967 1 0.00% 72.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 72 0.08% 72.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 389 0.43% 72.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 142 0.16% 73.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 126 0.14% 73.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 70 0.08% 73.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 1 0.00% 73.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 321 0.36% 73.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 69 0.08% 73.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 77 0.09% 73.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 59 0.07% 73.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 322 0.36% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19648-19655 1 0.00% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 131 0.14% 74.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 131 0.14% 74.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 129 0.14% 74.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 344 0.38% 75.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 69 0.08% 75.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 72 0.08% 75.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 6 0.01% 75.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21440-21447 1 0.00% 75.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 266 0.29% 75.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 64 0.07% 75.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 246 0.27% 75.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 133 0.15% 76.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 396 0.44% 76.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 186 0.21% 76.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 68 0.08% 76.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23424-23431 1 0.00% 76.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 265 0.29% 77.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 68 0.08% 77.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 130 0.14% 77.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 65 0.07% 77.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24384-24391 1 0.00% 77.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 512 0.57% 77.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 66 0.07% 77.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 129 0.14% 78.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 67 0.07% 78.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 1 0.00% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 264 0.29% 78.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25792-25799 1 0.00% 78.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 69 0.08% 78.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 185 0.20% 78.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 394 0.44% 79.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 130 0.14% 79.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26944-26951 1 0.00% 79.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 246 0.27% 79.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 65 0.07% 79.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 267 0.30% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27840-27847 2 0.00% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 4 0.00% 80.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 73 0.08% 80.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 69 0.08% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 1 0.00% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 339 0.38% 80.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 128 0.14% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 130 0.14% 80.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 133 0.15% 80.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 322 0.36% 81.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29760-29767 1 0.00% 81.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 1 0.00% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 57 0.06% 81.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 76 0.08% 81.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30279 2 0.00% 81.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 68 0.08% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 322 0.36% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 72 0.08% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 126 0.14% 82.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 141 0.16% 82.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 1 0.00% 82.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 387 0.43% 82.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 71 0.08% 82.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32192-32199 1 0.00% 82.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 1 0.00% 82.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 66 0.07% 82.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 652 0.72% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 71 0.08% 83.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 3 0.00% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33344-33351 1 0.00% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 71 0.08% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 386 0.43% 84.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 141 0.16% 84.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 126 0.14% 84.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 72 0.08% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 320 0.35% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 68 0.08% 84.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 76 0.08% 85.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 57 0.06% 85.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35648-35655 1 0.00% 85.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 321 0.36% 85.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 132 0.15% 85.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 129 0.14% 85.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 128 0.14% 85.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 338 0.37% 86.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 69 0.08% 86.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 72 0.08% 86.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 4 0.00% 86.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37696-37703 2 0.00% 86.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 269 0.30% 86.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 65 0.07% 86.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 246 0.27% 87.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 129 0.14% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 394 0.44% 87.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 185 0.20% 87.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 67 0.07% 87.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39744-39751 1 0.00% 87.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 264 0.29% 88.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40064-40071 1 0.00% 88.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 67 0.07% 88.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 129 0.14% 88.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 65 0.07% 88.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 512 0.57% 89.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41152-41159 1 0.00% 89.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 65 0.07% 89.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 129 0.14% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 68 0.08% 89.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 264 0.29% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42112-42119 1 0.00% 89.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 68 0.08% 89.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 186 0.21% 89.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 395 0.44% 90.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 132 0.15% 90.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 246 0.27% 90.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 64 0.07% 90.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 266 0.29% 91.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 6 0.01% 91.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 71 0.08% 91.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 69 0.08% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 340 0.38% 91.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 129 0.14% 91.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 130 0.14% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 131 0.14% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 320 0.35% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 58 0.06% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 74 0.08% 92.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 70 0.08% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 320 0.35% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 72 0.08% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 128 0.14% 93.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 142 0.16% 93.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 388 0.43% 93.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48192-48199 1 0.00% 93.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 73 0.08% 93.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 2 0.00% 93.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 66 0.07% 94.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 2 0.00% 94.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5356 5.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90358 # Bytes accessed per row activation -system.physmem.totQLat 377355345750 # Total ticks spent queuing -system.physmem.totMemAccLat 474591583250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78454425000 # Total ticks spent in databus transfers -system.physmem.totBankLat 18781812500 # Total ticks spent accessing banks -system.physmem.avgQLat 24049.33 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1196.99 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 346 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 990183 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 1014.719065 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1002.794597 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 86.877825 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3622 0.37% 0.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 3291 0.33% 0.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1715 0.17% 0.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1178 0.12% 0.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 920 0.09% 1.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 703 0.07% 1.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 532 0.05% 1.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 420 0.04% 1.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 977802 98.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 990183 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4537 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 3458.425832 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 54557.622307 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 4511 99.43% 99.43% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::131072-196607 8 0.18% 99.60% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 4 0.09% 99.69% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::393216-458751 2 0.04% 99.74% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::589824-655359 3 0.07% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.82% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.13% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4537 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4537 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.201675 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 21.361663 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 9.873768 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 5 0.11% 0.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 7 0.15% 0.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 5 0.11% 0.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 2 0.04% 0.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 2 0.04% 0.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 4 0.09% 0.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 6 0.13% 0.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 3 0.07% 0.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 3 0.07% 0.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 3 0.07% 0.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 3 0.07% 0.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12 2 0.04% 0.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 4 0.09% 1.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14 7 0.15% 1.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 17 0.37% 1.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1491 32.86% 34.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 339 7.47% 41.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 208 4.58% 46.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1050 23.14% 69.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 16 0.35% 70.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 12 0.26% 70.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 20 0.44% 70.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 24 0.53% 71.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 18 0.40% 71.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 14 0.31% 71.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 18 0.40% 72.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 18 0.40% 72.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 19 0.42% 73.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 13 0.29% 73.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 11 0.24% 73.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 12 0.26% 73.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 11 0.24% 74.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 3 0.07% 74.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 2 0.04% 74.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 1 0.02% 74.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 1015 22.37% 96.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 76 1.68% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 13 0.29% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 42 0.93% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 1 0.02% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 5 0.11% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 5 0.11% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 5 0.11% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4537 # Writes before turning the bus around for reads +system.physmem.totQLat 592300556750 # Total ticks spent queuing +system.physmem.totMemAccLat 700300341750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78454390000 # Total ticks spent in databus transfers +system.physmem.totBankLat 29545395000 # Total ticks spent accessing banks +system.physmem.avgQLat 37748.08 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1882.97 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30246.32 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.87 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44631.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.56 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.96 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.00 # Data bus utilization in percentage system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 1.22 # Average write queue length when enqueuing -system.physmem.readRowHits 15616397 # Number of row buffer hits during reads -system.physmem.writeRowHits 90966 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.15 # Row buffer hit rate for writes -system.physmem.avgGap 159352.98 # Average gap between requests -system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 2.38 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.avgRdQLen 7.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.89 # Average write queue length when enqueuing +system.physmem.readRowHits 14676487 # Number of row buffer hits during reads +system.physmem.writeRowHits 89750 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.54 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.26 # Row buffer hit rate for writes +system.physmem.avgGap 159349.78 # Average gap between requests +system.physmem.pageHitRate 93.48 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.16 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -535,259 +335,259 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54425810 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743683 # Transaction distribution -system.membus.trans_dist::ReadResp 16743683 # Transaction distribution +system.membus.throughput 54426652 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743677 # Transaction distribution +system.membus.trans_dist::ReadResp 16743677 # Transaction distribution system.membus.trans_dist::WriteReq 763441 # Transaction distribution system.membus.trans_dist::WriteResp 763441 # Transaction distribution -system.membus.trans_dist::Writeback 57657 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution +system.membus.trans_dist::Writeback 57651 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution system.membus.trans_dist::ReadExReq 131342 # Transaction distribution system.membus.trans_dist::ReadExResp 131342 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383092 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892593 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4279557 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892577 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279541 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35343621 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 35343605 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390550 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16471696 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18869990 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16470928 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18869222 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143126246 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143126246 # Total data (bytes) +system.membus.tot_pkt_size::total 143125478 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143125478 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1225748500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1225762000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3758000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3755500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 18171669500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 18171181500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4990674222 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4987933108 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 35076241500 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.membus.respLayer2.occupancy 38819144750 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 62047 # number of replacements -system.l2c.tags.tagsinuse 51602.841569 # Cycle average of tags in use -system.l2c.tags.total_refs 1699505 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127430 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.336773 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2574813583500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38208.002352 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000703 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2774.091625 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3066.452073 # Average occupied blocks per requestor +system.l2c.tags.replacements 62041 # number of replacements +system.l2c.tags.tagsinuse 51600.507824 # Cycle average of tags in use +system.l2c.tags.total_refs 1699332 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127423 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.336148 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2574803290500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38204.625202 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000702 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2677.995545 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3048.557344 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4246.643785 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3307.650843 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.583008 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 4342.999627 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3326.329216 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.582956 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.042329 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.046790 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.040863 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.046517 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.064799 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.050471 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.787397 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2131 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6484 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56716 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17278266 # Number of tag accesses -system.l2c.tags.data_accesses 17278266 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 9823 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3607 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 411412 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 183126 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 10084 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3595 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 433138 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 187347 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1242132 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596464 # number of Writeback hits -system.l2c.Writeback_hits::total 596464 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits +system.l2c.tags.occ_percent::cpu1.inst 0.066269 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.050756 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.787361 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65382 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2132 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6447 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56751 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.997650 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17277037 # Number of tag accesses +system.l2c.tags.data_accesses 17277037 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 9996 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3617 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 411271 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 183421 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 9883 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3502 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 433200 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 187065 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1241955 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596489 # number of Writeback hits +system.l2c.Writeback_hits::total 596489 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57116 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16703971375 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 351469750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 91091698124 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 856250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 92298367251 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183742391375 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000553 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009976 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027589 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014653 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026149 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016484 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.990141 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991941 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991062 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.551679 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.522590 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.537244 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000553 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009976 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.236165 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014653 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.219771 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.101830 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000553 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009976 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.236165 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014653 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.219771 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.101830 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58979.783733 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61746.463599 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57804.054054 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62301.018447 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58607.881035 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63532.131980 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 60649.001057 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58025.807203 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63091.280111 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60274.092045 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 58539.598819 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58191.904329 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 58369.524553 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.677048 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.346861 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57369.202308 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57588.717582 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 57475.158179 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58979.783733 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58771.769629 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57804.054054 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57716.052382 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58607.881035 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58567.783210 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58678.128322 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58025.807203 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57988.084297 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57853.998478 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58979.783733 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58771.769629 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57804.054054 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57716.052382 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58607.881035 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58567.783210 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58678.128322 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58025.807203 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57988.084297 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57853.998478 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -939,39 +739,39 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52791444 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2472019 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2472019 # Transaction distribution +system.toL2Bus.throughput 52790847 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2471761 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471761 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763441 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763441 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596464 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2906 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2906 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247513 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247513 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725197 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753946 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20259 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50584 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7549986 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54755680 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83794182 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28816 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138658310 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138658310 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 169964 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4808748000 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 596489 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2909 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2909 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 247515 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247515 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725013 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5754007 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20046 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50514 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7549580 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54750240 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83796742 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28484 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79520 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138654986 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138654986 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 168824 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4808734000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3865724000 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3865148750 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4421241528 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4420266392 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 13055000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 12925000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30676250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30634250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48159266 # Throughput (bytes/s) +system.iobus.throughput 48160270 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16715394 # Transaction distribution system.iobus.trans_dist::ReadResp 16715394 # Transaction distribution system.iobus.trans_dist::WriteReq 8184 # Transaction distribution @@ -1081,8 +881,8 @@ system.iobus.reqLayer25.occupancy 15532032000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374908000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42583156500 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) +system.iobus.respLayer1.occupancy 38823243250 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1106,25 +906,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7421730 # DTB read hits -system.cpu0.dtb.read_misses 6821 # DTB read misses -system.cpu0.dtb.write_hits 5623030 # DTB write hits -system.cpu0.dtb.write_misses 1843 # DTB write misses +system.cpu0.dtb.read_hits 7344844 # DTB read hits +system.cpu0.dtb.read_misses 6860 # DTB read misses +system.cpu0.dtb.write_hits 5551128 # DTB write hits +system.cpu0.dtb.write_misses 1832 # DTB write misses system.cpu0.dtb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 666 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 699 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6415 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 6351 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 147 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 137 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 218 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7428551 # DTB read accesses -system.cpu0.dtb.write_accesses 5624873 # DTB write accesses +system.cpu0.dtb.perms_faults 220 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7351704 # DTB read accesses +system.cpu0.dtb.write_accesses 5552960 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13044760 # DTB hits -system.cpu0.dtb.misses 8664 # DTB misses -system.cpu0.dtb.accesses 13053424 # DTB accesses +system.cpu0.dtb.hits 12895972 # DTB hits +system.cpu0.dtb.misses 8692 # DTB misses +system.cpu0.dtb.accesses 12904664 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1146,125 +946,125 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 30640130 # ITB inst hits -system.cpu0.itb.inst_misses 3559 # ITB inst misses +system.cpu0.itb.inst_hits 30211154 # ITB inst hits +system.cpu0.itb.inst_misses 3603 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 666 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 699 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2782 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2758 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30643689 # ITB inst accesses -system.cpu0.itb.hits 30640130 # DTB hits -system.cpu0.itb.misses 3559 # DTB misses -system.cpu0.itb.accesses 30643689 # DTB accesses -system.cpu0.numCycles 2628262208 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30214757 # ITB inst accesses +system.cpu0.itb.hits 30211154 # DTB hits +system.cpu0.itb.misses 3603 # DTB misses +system.cpu0.itb.accesses 30214757 # DTB accesses +system.cpu0.numCycles 2627736532 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 30017324 # Number of instructions committed -system.cpu0.committedOps 38175915 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34451316 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4807 # Number of float alu accesses -system.cpu0.num_func_calls 1059150 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3975405 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34451316 # number of integer instructions -system.cpu0.num_fp_insts 4807 # number of float instructions -system.cpu0.num_int_register_reads 199768149 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37153826 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 123415 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 247773 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 124360 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 123412 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247772 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11819956 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11974343 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 23794299 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11819956 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11974343 # 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average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46321.101784 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45365.375240 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45847.801149 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13491.895053 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14202.546917 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13835.283703 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27774.509942 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26985.635712 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 27378.900097 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27774.509942 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26985.635712 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 27378.900097 # average overall miss latency +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048462 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044947 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046712 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026433 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025657 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.026038 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026433 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025657 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.026038 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14905.117884 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14797.370862 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14850.668041 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46164.416338 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44523.628952 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45349.932582 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13441.956882 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14311.913781 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13858.670295 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27675.186671 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26684.852262 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 27178.305139 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27675.186671 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26684.852262 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 27178.305139 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1444,77 +1244,77 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 596464 # number of writebacks -system.cpu0.dcache.writebacks::total 596464 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182444 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 186677 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 369121 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126405 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 124014 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 250419 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5984 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5595 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11579 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 308849 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 310691 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 619540 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 308849 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 310691 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 619540 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2356704250 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2383886500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4740590750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5575941129 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5352926355 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10928867484 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68762500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68225750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136988250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7932645379 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7736812855 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15669458234 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7932645379 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7736812855 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15669458234 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91432491750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90647732000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182080223750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13248714489 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12991485999 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26240200488 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104681206239 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103639217999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208320424238 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027219 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027189 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027204 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024703 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024276 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.writebacks::writebacks 596489 # number of writebacks +system.cpu0.dcache.writebacks::total 596489 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182595 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 186544 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 369139 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126114 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 124310 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 250424 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6030 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5544 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11574 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 308709 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 310854 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 619563 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 308709 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 310854 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619563 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2355168000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2386207250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4741375250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5543852798 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5262622685 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10806475483 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68990000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68208750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137198750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7899020798 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7648829935 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15547850733 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7899020798 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7648829935 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15547850733 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 90318421750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 91762441000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182080862750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13218125626 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13022508499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26240634125 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 103536547376 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 104784949499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208321496875 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027528 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026897 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027205 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024995 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023998 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024490 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048119 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.045335 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046732 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026129 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025946 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.026037 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026129 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025946 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026037 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12917.411644 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12770.113619 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12842.918040 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44111.713374 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43163.887585 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43642.325399 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11491.059492 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12194.057194 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11830.749633 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25684.542864 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24901.953565 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25292.084827 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25684.542864 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24901.953565 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25292.084827 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048462 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044947 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046712 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026433 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025657 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.026038 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026433 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025657 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026038 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12898.315945 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12791.659072 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12844.417008 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43959.059248 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42334.668852 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43152.714927 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11441.127695 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12303.165584 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11854.047866 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25587.270854 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24605.859777 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25094.866435 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25587.270854 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24605.859777 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25094.866435 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1548,25 +1348,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7578931 # DTB read hits -system.cpu1.dtb.read_misses 7259 # DTB read misses -system.cpu1.dtb.write_hits 5610002 # DTB write hits -system.cpu1.dtb.write_misses 1852 # DTB write misses +system.cpu1.dtb.read_hits 7655819 # DTB read hits +system.cpu1.dtb.read_misses 7243 # DTB read misses +system.cpu1.dtb.write_hits 5681899 # DTB write hits +system.cpu1.dtb.write_misses 1828 # DTB write misses system.cpu1.dtb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 773 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 740 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6696 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 6711 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 139 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 234 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7586190 # DTB read accesses -system.cpu1.dtb.write_accesses 5611854 # DTB write accesses +system.cpu1.dtb.perms_faults 232 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7663062 # DTB read accesses +system.cpu1.dtb.write_accesses 5683727 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13188933 # DTB hits -system.cpu1.dtb.misses 9111 # DTB misses -system.cpu1.dtb.accesses 13198044 # DTB accesses +system.cpu1.dtb.hits 13337718 # DTB hits +system.cpu1.dtb.misses 9071 # DTB misses +system.cpu1.dtb.accesses 13346789 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1588,50 +1388,50 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 30869347 # ITB inst hits -system.cpu1.itb.inst_misses 3806 # ITB inst misses +system.cpu1.itb.inst_hits 31298229 # ITB inst hits +system.cpu1.itb.inst_misses 3696 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 773 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 740 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2929 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2898 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 30873153 # ITB inst accesses -system.cpu1.itb.hits 30869347 # DTB hits -system.cpu1.itb.misses 3806 # DTB misses -system.cpu1.itb.accesses 30873153 # DTB accesses -system.cpu1.numCycles 2631236815 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 31301925 # ITB inst accesses +system.cpu1.itb.hits 31298229 # DTB hits +system.cpu1.itb.misses 3696 # DTB misses +system.cpu1.itb.accesses 31301925 # DTB accesses +system.cpu1.numCycles 2631652887 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30198018 # Number of instructions committed -system.cpu1.committedOps 38446958 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34771949 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5462 # Number of float alu accesses -system.cpu1.num_func_calls 1081332 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3974549 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34771949 # number of integer instructions -system.cpu1.num_fp_insts 5462 # number of float instructions -system.cpu1.num_int_register_reads 201690852 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37382680 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3860 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1604 # number of times the floating registers were written -system.cpu1.num_mem_refs 13782650 # number of memory refs -system.cpu1.num_load_insts 7920272 # Number of load instructions -system.cpu1.num_store_insts 5862378 # Number of store instructions -system.cpu1.num_idle_cycles 2292306354.384825 # Number of idle cycles -system.cpu1.num_busy_cycles 338930460.615175 # Number of busy cycles -system.cpu1.not_idle_fraction 0.128810 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.871190 # Percentage of idle cycles -system.cpu1.Branches 5177848 # Number of branches fetched +system.cpu1.committedInsts 30590318 # Number of instructions committed +system.cpu1.committedOps 38894351 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 35148183 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5686 # Number of float alu accesses +system.cpu1.num_func_calls 1095318 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4014750 # number of instructions that are conditional controls +system.cpu1.num_int_insts 35148183 # number of integer instructions +system.cpu1.num_fp_insts 5686 # number of float instructions +system.cpu1.num_int_register_reads 203876321 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37823170 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4205 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1482 # number of times the floating registers were written +system.cpu1.num_mem_refs 13931138 # number of memory refs +system.cpu1.num_load_insts 7996929 # Number of load instructions +system.cpu1.num_store_insts 5934209 # Number of store instructions +system.cpu1.num_idle_cycles 2293790821.520695 # Number of idle cycles +system.cpu1.num_busy_cycles 337862065.479305 # Number of busy cycles +system.cpu1.not_idle_fraction 0.128384 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.871616 # Percentage of idle cycles +system.cpu1.Branches 5235663 # Number of branches fetched system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements @@ -1650,10 +1450,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557250761500 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1557250761500 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557250761500 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1557250761500 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1783080197250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1783080197250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1783080197250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1783080197250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 467207c9e..6ae80aee8 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.133933 # Number of seconds simulated -sim_ticks 5133933067000 # Number of ticks simulated -final_tick 5133933067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.137972 # Number of seconds simulated +sim_ticks 5137971999000 # Number of ticks simulated +final_tick 5137971999000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 186687 # Simulator instruction rate (inst/s) -host_op_rate 369023 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2350538489 # Simulator tick rate (ticks/s) -host_mem_usage 736008 # Number of bytes of host memory used -host_seconds 2184.15 # Real time elapsed on the host -sim_insts 407751929 # Number of instructions simulated -sim_ops 806002693 # Number of ops (including micro ops) simulated +host_inst_rate 151274 # Simulator instruction rate (inst/s) +host_op_rate 299020 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1905679647 # Simulator tick rate (ticks/s) +host_mem_usage 770140 # Number of bytes of host memory used +host_seconds 2696.14 # Real time elapsed on the host +sim_insts 407854776 # Number of instructions simulated +sim_ops 806198141 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 2437184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1029376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10746496 # Number of bytes read from this memory -system.physmem.bytes_read::total 14217280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1029376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1029376 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9492672 # Number of bytes written to this memory -system.physmem.bytes_written::total 9492672 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38081 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16084 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 167914 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222145 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 148323 # Number of write requests responded to by this memory -system.physmem.num_writes::total 148323 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 474721 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 200504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2093229 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2769276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 200504 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 200504 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1849006 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1849006 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1849006 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 474721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 760 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 200504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2093229 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4618282 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222145 # Number of read requests accepted -system.physmem.writeReqs 148323 # Number of write requests accepted -system.physmem.readBursts 222145 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 148323 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 14211648 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue -system.physmem.bytesWritten 9492416 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 14217280 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9492672 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::pc.south_bridge.ide 2477120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1034624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10750336 # Number of bytes read from this memory +system.physmem.bytes_read::total 14265472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1034624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1034624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9529024 # Number of bytes written to this memory +system.physmem.bytes_written::total 9529024 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38705 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 49 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16166 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 167974 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222898 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 148891 # Number of write requests responded to by this memory +system.physmem.num_writes::total 148891 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 482120 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 201368 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2092331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2776479 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 201368 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 201368 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1854627 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1854627 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1854627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 482120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 201368 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2092331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4631107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222898 # Number of read requests accepted +system.physmem.writeReqs 148891 # Number of write requests accepted +system.physmem.readBursts 222898 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 148891 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14252672 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 12800 # Total number of bytes read from write queue +system.physmem.bytesWritten 9527360 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14265472 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9529024 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 200 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1715 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 14970 # Per bank write bursts -system.physmem.perBankRdBursts::1 13960 # Per bank write bursts -system.physmem.perBankRdBursts::2 14769 # Per bank write bursts -system.physmem.perBankRdBursts::3 13764 # Per bank write bursts -system.physmem.perBankRdBursts::4 13644 # Per bank write bursts -system.physmem.perBankRdBursts::5 13392 # Per bank write bursts -system.physmem.perBankRdBursts::6 13407 # Per bank write bursts -system.physmem.perBankRdBursts::7 13589 # Per bank write bursts -system.physmem.perBankRdBursts::8 13408 # Per bank write bursts -system.physmem.perBankRdBursts::9 13258 # Per bank write bursts -system.physmem.perBankRdBursts::10 13821 # Per bank write bursts -system.physmem.perBankRdBursts::11 13878 # Per bank write bursts -system.physmem.perBankRdBursts::12 14332 # Per bank write bursts -system.physmem.perBankRdBursts::13 14527 # Per bank write bursts -system.physmem.perBankRdBursts::14 13749 # Per bank write bursts -system.physmem.perBankRdBursts::15 13589 # Per bank write bursts -system.physmem.perBankWrBursts::0 10370 # Per bank write bursts -system.physmem.perBankWrBursts::1 9405 # Per bank write bursts -system.physmem.perBankWrBursts::2 9871 # Per bank write bursts -system.physmem.perBankWrBursts::3 9165 # Per bank write bursts -system.physmem.perBankWrBursts::4 9017 # Per bank write bursts -system.physmem.perBankWrBursts::5 8953 # Per bank write bursts -system.physmem.perBankWrBursts::6 8740 # Per bank write bursts -system.physmem.perBankWrBursts::7 8992 # Per bank write bursts -system.physmem.perBankWrBursts::8 8721 # Per bank write bursts -system.physmem.perBankWrBursts::9 8568 # Per bank write bursts -system.physmem.perBankWrBursts::10 9309 # Per bank write bursts -system.physmem.perBankWrBursts::11 9216 # Per bank write bursts -system.physmem.perBankWrBursts::12 9686 # Per bank write bursts -system.physmem.perBankWrBursts::13 9800 # Per bank write bursts -system.physmem.perBankWrBursts::14 9415 # Per bank write bursts -system.physmem.perBankWrBursts::15 9091 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 1701 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 14548 # Per bank write bursts +system.physmem.perBankRdBursts::1 13887 # Per bank write bursts +system.physmem.perBankRdBursts::2 14162 # Per bank write bursts +system.physmem.perBankRdBursts::3 13520 # Per bank write bursts +system.physmem.perBankRdBursts::4 14300 # Per bank write bursts +system.physmem.perBankRdBursts::5 13581 # Per bank write bursts +system.physmem.perBankRdBursts::6 13426 # Per bank write bursts +system.physmem.perBankRdBursts::7 13413 # Per bank write bursts +system.physmem.perBankRdBursts::8 13607 # Per bank write bursts +system.physmem.perBankRdBursts::9 13662 # Per bank write bursts +system.physmem.perBankRdBursts::10 13602 # Per bank write bursts +system.physmem.perBankRdBursts::11 13631 # Per bank write bursts +system.physmem.perBankRdBursts::12 14336 # Per bank write bursts +system.physmem.perBankRdBursts::13 14588 # Per bank write bursts +system.physmem.perBankRdBursts::14 14340 # Per bank write bursts +system.physmem.perBankRdBursts::15 14095 # Per bank write bursts +system.physmem.perBankWrBursts::0 9881 # Per bank write bursts +system.physmem.perBankWrBursts::1 9301 # Per bank write bursts +system.physmem.perBankWrBursts::2 9417 # Per bank write bursts +system.physmem.perBankWrBursts::3 9104 # Per bank write bursts +system.physmem.perBankWrBursts::4 9702 # Per bank write bursts +system.physmem.perBankWrBursts::5 8858 # Per bank write bursts +system.physmem.perBankWrBursts::6 8862 # Per bank write bursts +system.physmem.perBankWrBursts::7 8906 # Per bank write bursts +system.physmem.perBankWrBursts::8 8978 # Per bank write bursts +system.physmem.perBankWrBursts::9 9056 # Per bank write bursts +system.physmem.perBankWrBursts::10 9081 # Per bank write bursts +system.physmem.perBankWrBursts::11 9102 # Per bank write bursts +system.physmem.perBankWrBursts::12 9605 # Per bank write bursts +system.physmem.perBankWrBursts::13 9854 # Per bank write bursts +system.physmem.perBankWrBursts::14 9646 # Per bank write bursts +system.physmem.perBankWrBursts::15 9512 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 5133933013500 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 5137971883500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 222145 # Read request sizes (log2) +system.physmem.readPktSize::6 222898 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 148323 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 174666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6950 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2066 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1506 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1430 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 864 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 755 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 678 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 656 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 606 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 571 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 555 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148891 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 173419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13832 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 4649 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2839 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3447 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2968 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1096 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 836 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 757 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 696 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -141,369 +141,239 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 6022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 6256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 7022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 7020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 7083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 7644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 7121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 7236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 68754 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 344.735608 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 150.882581 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1084.800437 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 30893 44.93% 44.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 10573 15.38% 60.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 6859 9.98% 70.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 4406 6.41% 76.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 2663 3.87% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 2166 3.15% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1652 2.40% 86.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 1226 1.78% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 1018 1.48% 89.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 978 1.42% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 656 0.95% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 637 0.93% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 446 0.65% 93.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 438 0.64% 93.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 344 0.50% 94.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 542 0.79% 95.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 252 0.37% 95.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 218 0.32% 95.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 163 0.24% 96.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 136 0.20% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 158 0.23% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 420 0.61% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 150 0.22% 97.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 127 0.18% 97.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 107 0.16% 97.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 87 0.13% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 59 0.09% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 64 0.09% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 17 0.02% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 43 0.06% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 19 0.03% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 31 0.05% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 40 0.06% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 10 0.01% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 13 0.02% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 16 0.02% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 31 0.05% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 10 0.01% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 6 0.01% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 13 0.02% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 31 0.05% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 12 0.02% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 4 0.01% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 6 0.01% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 27 0.04% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 9 0.01% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 12 0.02% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 6 0.01% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 28 0.04% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 7 0.01% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 25 0.04% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 3 0.00% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 5 0.01% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 5 0.01% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 26 0.04% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 10 0.01% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 5 0.01% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 9 0.01% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 28 0.04% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 4 0.01% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 15 0.02% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 3 0.00% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 27 0.04% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 3 0.00% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 2 0.00% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 2 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 23 0.03% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 3 0.00% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 5 0.01% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 25 0.04% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 4 0.01% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 22 0.03% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.00% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 3 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 4 0.01% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 26 0.04% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 2 0.00% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 22 0.03% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 4 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 3 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 24 0.03% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 4 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 24 0.03% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 3 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 24 0.03% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 3 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 4 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 23 0.03% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 4 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 75 0.11% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 3 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 2 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 5 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 5 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 3 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 9 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 11 0.02% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7491 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 3 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 4 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 3 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 5 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 3 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 15 0.02% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8515 5 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8643 2 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 2 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 4 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 4 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 4 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9923 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9987 3 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 3 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11139 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11203 2 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11267 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11395 3 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 3 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11715 2 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11907 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12163 2 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12227 2 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 3 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12931 2 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 2 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 2 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 3 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13891 6 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 5 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 4 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 2 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 25 0.04% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 6 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 8 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 4 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 3 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 8 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 3 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 14 0.02% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 2 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 4 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 5 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 3 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 4 0.01% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 2 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 10 0.01% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 9 0.01% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 42 0.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 68754 # Bytes accessed per row activation -system.physmem.totQLat 5103462500 # Total ticks spent queuing -system.physmem.totMemAccLat 9310522500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1110285000 # Total ticks spent in databus transfers -system.physmem.totBankLat 3096775000 # Total ticks spent accessing banks -system.physmem.avgQLat 22982.67 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13945.86 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 49868 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 381.994064 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 221.175651 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 374.202346 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15813 31.71% 31.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11064 22.19% 53.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5080 10.19% 64.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2824 5.66% 69.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1980 3.97% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1284 2.57% 76.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 922 1.85% 78.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 716 1.44% 79.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10185 20.42% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 49868 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 8142 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.350037 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 531.765782 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 8141 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 8142 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 8142 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.283591 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.627324 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.611364 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 6056 74.38% 74.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 1276 15.67% 90.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 101 1.24% 91.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 41 0.50% 91.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 52 0.64% 92.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 70 0.86% 93.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 65 0.80% 94.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 71 0.87% 94.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 51 0.63% 95.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 44 0.54% 96.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 56 0.69% 96.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 33 0.41% 97.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 34 0.42% 97.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 29 0.36% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 35 0.43% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 23 0.28% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 19 0.23% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 12 0.15% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 12 0.15% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 9 0.11% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 6 0.07% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 7 0.09% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 2 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 13 0.16% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-65 13 0.16% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::66-67 1 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::70-71 1 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-73 4 0.05% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::74-75 3 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-77 2 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-81 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 8142 # Writes before turning the bus around for reads +system.physmem.totQLat 5275412250 # Total ticks spent queuing +system.physmem.totMemAccLat 9510468500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1113490000 # Total ticks spent in databus transfers +system.physmem.totBankLat 3121566250 # Total ticks spent accessing banks +system.physmem.avgQLat 23688.64 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14017.04 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41928.53 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 42705.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.77 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.78 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 8.57 # Average write queue length when enqueuing -system.physmem.readRowHits 193293 # Number of row buffer hits during reads -system.physmem.writeRowHits 108329 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.04 # Row buffer hit rate for writes -system.physmem.avgGap 13857966.18 # Average gap between requests -system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.02 # Average write queue length when enqueuing +system.physmem.readRowHits 186969 # Number of row buffer hits during reads +system.physmem.writeRowHits 110725 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.96 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.37 # Row buffer hit rate for writes +system.physmem.avgGap 13819590.91 # Average gap between requests +system.physmem.pageHitRate 80.11 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 0.14 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 5095991 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 662317 # Transaction distribution -system.membus.trans_dist::ReadResp 662311 # Transaction distribution -system.membus.trans_dist::WriteReq 13762 # Transaction distribution -system.membus.trans_dist::WriteResp 13762 # Transaction distribution -system.membus.trans_dist::Writeback 148323 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2201 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1734 # Transaction distribution -system.membus.trans_dist::ReadExReq 179351 # Transaction distribution -system.membus.trans_dist::ReadExResp 179346 # Transaction distribution -system.membus.trans_dist::MessageReq 1642 # Transaction distribution -system.membus.trans_dist::MessageResp 1642 # Transaction distribution -system.membus.trans_dist::BadAddressError 6 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3284 # Packet count per connected master and slave (bytes) +system.membus.throughput 5100645 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 662331 # Transaction distribution +system.membus.trans_dist::ReadResp 662323 # Transaction distribution +system.membus.trans_dist::WriteReq 13764 # Transaction distribution +system.membus.trans_dist::WriteResp 13764 # Transaction distribution +system.membus.trans_dist::Writeback 148891 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2168 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1718 # Transaction distribution +system.membus.trans_dist::ReadExReq 179464 # Transaction distribution +system.membus.trans_dist::ReadExResp 179461 # Transaction distribution +system.membus.trans_dist::MessageReq 1643 # Transaction distribution +system.membus.trans_dist::MessageResp 1643 # Transaction distribution +system.membus.trans_dist::BadAddressError 8 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471038 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 474374 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1720496 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132379 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 132379 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1856159 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775076 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475146 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721276 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 133006 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 133006 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1857568 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241802 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18286080 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20078023 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5423872 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5423872 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25508463 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25508463 # Total data (bytes) -system.membus.snoop_data_through_bus 654016 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 250556000 # Layer occupancy (ticks) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550149 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18330624 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20122575 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5463872 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5463872 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25593019 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25593019 # Total data (bytes) +system.membus.snoop_data_through_bus 613952 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 250521000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583258500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583253500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3284000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1605908499 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1611616249 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1642000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3150989153 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3152435901 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 429464748 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 429736248 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47576 # number of replacements -system.iocache.tags.tagsinuse 0.103980 # Cycle average of tags in use +system.iocache.tags.replacements 47579 # number of replacements +system.iocache.tags.tagsinuse 0.116331 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47592 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992951939000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103980 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006499 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006499 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4992993838000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116331 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007271 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007271 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428679 # Number of tag accesses -system.iocache.tags.data_accesses 428679 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses -system.iocache.ReadReq_misses::total 911 # number of ReadReq misses +system.iocache.tags.tag_accesses 428697 # Number of tag accesses +system.iocache.tags.data_accesses 428697 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 913 # number of ReadReq misses +system.iocache.ReadReq_misses::total 913 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses -system.iocache.demand_misses::total 47631 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses -system.iocache.overall_misses::total 47631 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151022435 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 151022435 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11480088301 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11480088301 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 11631110736 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11631110736 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 11631110736 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11631110736 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47633 # number of demand (read+write) misses +system.iocache.demand_misses::total 47633 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47633 # number of overall misses +system.iocache.overall_misses::total 47633 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149265435 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 149265435 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11474717915 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11474717915 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 11623983350 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11623983350 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 11623983350 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11623983350 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 913 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 913 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47633 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47633 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47633 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47633 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -512,40 +382,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165776.547750 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 165776.547750 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 245721.068086 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 245721.068086 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 244192.033256 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 244192.033256 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 244192.033256 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 244192.033256 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 172788 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 163488.975904 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 163488.975904 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 245606.119756 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 245606.119756 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 244032.148930 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 244032.148930 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 244032.148930 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 244032.148930 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 177888 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10383 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 14382 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 16.641433 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.368794 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46667 # number of writebacks -system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 46668 # number of writebacks +system.iocache.writebacks::total 46668 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 913 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 913 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 103624935 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 103624935 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9049102305 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9049102305 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9152727240 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9152727240 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9152727240 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9152727240 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47633 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47633 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47633 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47633 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 101762935 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 101762935 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9043225919 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9043225919 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9144988854 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9144988854 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9144988854 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9144988854 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -554,14 +424,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113748.556531 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 113748.556531 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 193687.977419 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 193687.977419 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 192159.040121 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 192159.040121 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 192159.040121 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 192159.040121 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111459.950712 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 111459.950712 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 193562.198609 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 193562.198609 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 191988.513300 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 191988.513300 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 191988.513300 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 191988.513300 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -575,13 +445,13 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 638147 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 225559 # Transaction distribution -system.iobus.trans_dist::ReadResp 225559 # Transaction distribution +system.iobus.throughput 637649 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 225561 # Transaction distribution +system.iobus.trans_dist::ReadResp 225561 # Transaction distribution system.iobus.trans_dist::WriteReq 57591 # Transaction distribution system.iobus.trans_dist::WriteResp 57591 # Transaction distribution -system.iobus.trans_dist::MessageReq 1642 # Transaction distribution -system.iobus.trans_dist::MessageResp 1642 # Transaction distribution +system.iobus.trans_dist::MessageReq 1643 # Transaction distribution +system.iobus.trans_dist::MessageResp 1643 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) @@ -601,11 +471,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 471038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95262 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95262 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3284 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 569584 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95266 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95266 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 569590 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) @@ -625,13 +495,13 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::total 241802 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027832 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027832 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3276202 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3276202 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3916600 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3276222 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3276222 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3918904 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -667,155 +537,155 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424364988 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 425268102 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 460167000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 53080252 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 53403752 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1642000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 85602749 # Number of BP lookups -system.cpu.branchPred.condPredicted 85602749 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 882967 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79146839 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77528417 # Number of BTB hits +system.cpu.branchPred.lookups 85606951 # Number of BP lookups +system.cpu.branchPred.condPredicted 85606951 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 878900 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79252981 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77536604 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.955165 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1444593 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 180696 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.834306 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1442152 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 179942 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 453810576 # number of cpu cycles simulated +system.cpu.numCycles 453123649 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25587128 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 422793434 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85602749 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 78973010 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 162653475 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3995125 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 108453 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 71359520 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 43835 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87857 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 286 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8489508 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 384110 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2391 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 262908725 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.175877 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.411274 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25513299 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 422793316 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85606951 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 78978756 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162666775 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3977899 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 109317 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 70887668 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 43514 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 89257 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 186 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8479758 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 384207 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2414 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 262364646 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.182537 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.411732 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 100670178 38.29% 38.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1530444 0.58% 38.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71820335 27.32% 66.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 896426 0.34% 66.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1566584 0.60% 67.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2396730 0.91% 68.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1019321 0.39% 68.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1330214 0.51% 68.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81678493 31.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 100112047 38.16% 38.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1537808 0.59% 38.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71834602 27.38% 66.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 894624 0.34% 66.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1560586 0.59% 67.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2393199 0.91% 67.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1018516 0.39% 68.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1331320 0.51% 68.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81681944 31.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 262908725 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.188631 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.931652 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29469022 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 68533895 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158500921 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3336716 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3068171 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 832628882 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1005 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3068171 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32166033 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 43333689 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12473461 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158788115 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13079256 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 829706187 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21464 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6056720 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5143219 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 991368832 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1800529447 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1106981108 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 114 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 963921381 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27447449 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 454679 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 459073 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 29562257 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 16738170 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9831898 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1099509 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 931888 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 824922108 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1185282 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 820965230 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 150616 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19266581 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29327510 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 130776 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 262908725 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.122625 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.401229 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 262364646 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.188926 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.933064 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29407134 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 68048451 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158512522 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3341909 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3054630 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 832669874 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 887 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3054630 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32105381 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 42832622 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12466754 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158806940 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13098319 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 829768905 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20738 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6073581 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5148249 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 991466417 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1800660067 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1107048961 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 106 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964157062 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27309353 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 454429 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 460129 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 29597584 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 16731616 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9822119 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1090956 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 912656 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 824999655 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1185445 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 821065367 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 147374 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19153823 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29264539 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 130709 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 262364646 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.129482 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.399412 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 76541753 29.11% 29.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15760378 5.99% 35.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10546081 4.01% 39.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7369618 2.80% 41.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75729447 28.80% 70.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3748882 1.43% 72.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72293205 27.50% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 772480 0.29% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 146881 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 75980319 28.96% 28.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15750588 6.00% 34.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10556494 4.02% 38.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7365908 2.81% 41.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75746368 28.87% 70.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3736962 1.42% 72.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72307682 27.56% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 774907 0.30% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 145418 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 262908725 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 262364646 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 349560 33.18% 33.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 241 0.02% 33.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 1967 0.19% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 548780 52.08% 85.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 153094 14.53% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 352804 33.38% 33.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 241 0.02% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 895 0.08% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 548620 51.91% 85.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 154313 14.60% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 307236 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 793474466 96.65% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 149866 0.02% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 124488 0.02% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 307554 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 793584898 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150109 0.02% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 124066 0.02% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued @@ -842,297 +712,297 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17682042 2.15% 98.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9227132 1.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17676623 2.15% 98.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9222117 1.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 820965230 # Type of FU issued -system.cpu.iq.rate 1.809048 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1053642 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001283 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1906151693 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 845384400 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 817050943 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 198 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 821711543 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 93 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1694469 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 821065367 # Type of FU issued +system.cpu.iq.rate 1.812012 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1056873 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001287 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1905808819 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 845349453 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 817155578 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 173 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 180 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 48 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 821814606 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 80 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1693534 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2748093 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 19141 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11819 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1409863 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2731831 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17734 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12108 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1395931 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1931395 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 11998 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932011 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12232 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3068171 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 31463417 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2151711 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 826107390 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 248376 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 16738170 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9831898 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 690155 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1620159 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12279 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11819 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 498534 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 508074 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1006608 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819554351 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17378079 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1410878 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3054630 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30960729 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2157350 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 826185100 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 241589 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 16731616 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9822119 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 690497 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1620390 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12858 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12108 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 495281 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 506440 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1001721 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819661058 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17373288 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1404308 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26421028 # number of memory reference insts executed -system.cpu.iew.exec_branches 83090233 # Number of branches executed -system.cpu.iew.exec_stores 9042949 # Number of stores executed -system.cpu.iew.exec_rate 1.805939 # Inst execution rate -system.cpu.iew.wb_sent 819150966 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 817050997 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638575855 # num instructions producing a value -system.cpu.iew.wb_consumers 1043882621 # num instructions consuming a value +system.cpu.iew.exec_refs 26412112 # number of memory reference insts executed +system.cpu.iew.exec_branches 83101028 # Number of branches executed +system.cpu.iew.exec_stores 9038824 # Number of stores executed +system.cpu.iew.exec_rate 1.808913 # Inst execution rate +system.cpu.iew.wb_sent 819257147 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 817155626 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638657480 # num instructions producing a value +system.cpu.iew.wb_consumers 1044041746 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.800423 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611731 # average fanout of values written-back +system.cpu.iew.wb_rate 1.803383 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611716 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19994665 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1054506 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 892807 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 259840554 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.101913 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.863847 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 19877862 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1054736 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 888910 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 259310016 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.109013 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.863250 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 88304488 33.98% 33.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11858711 4.56% 38.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3833949 1.48% 40.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74748511 28.77% 68.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2384583 0.92% 69.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1475819 0.57% 70.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 859128 0.33% 70.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70844564 27.26% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5530801 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87730314 33.83% 33.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11862694 4.57% 38.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3835821 1.48% 39.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74768182 28.83% 68.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2381229 0.92% 69.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1479438 0.57% 70.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 861979 0.33% 70.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70857593 27.33% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5532766 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 259840554 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407751929 # Number of instructions committed -system.cpu.commit.committedOps 806002693 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 259310016 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407854776 # Number of instructions committed +system.cpu.commit.committedOps 806198141 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22412111 # Number of memory references committed -system.cpu.commit.loads 13990076 # Number of loads committed -system.cpu.commit.membars 474663 # Number of memory barriers committed -system.cpu.commit.branches 82157264 # Number of branches committed +system.cpu.commit.refs 22425972 # Number of memory references committed +system.cpu.commit.loads 13999784 # Number of loads committed +system.cpu.commit.membars 474669 # Number of memory barriers committed +system.cpu.commit.branches 82177261 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 734852381 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155163 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5530801 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 735033306 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155486 # Number of function calls committed. +system.cpu.commit.bw_lim_events 5532766 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1080228878 # The number of ROB reads -system.cpu.rob.rob_writes 1655077473 # The number of ROB writes -system.cpu.timesIdled 1260592 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 190901851 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9814061063 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407751929 # Number of Instructions Simulated -system.cpu.committedOps 806002693 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407751929 # Number of Instructions Simulated -system.cpu.cpi 1.112958 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.112958 # CPI: Total CPI of All Threads -system.cpu.ipc 0.898507 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.898507 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1088763208 # number of integer regfile reads -system.cpu.int_regfile_writes 653821136 # number of integer regfile writes -system.cpu.fp_regfile_reads 54 # number of floating regfile reads -system.cpu.cc_regfile_reads 415622850 # number of cc regfile reads -system.cpu.cc_regfile_writes 321492626 # number of cc regfile writes -system.cpu.misc_regfile_reads 264082516 # number of misc regfile reads -system.cpu.misc_regfile_writes 402300 # number of misc regfile writes -system.cpu.toL2Bus.throughput 53661983 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3016761 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3016231 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13762 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13762 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1581663 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2241 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2241 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 334732 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 288041 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916491 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6123200 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19443 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 154439 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8213573 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61324288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207594695 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 616960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5463872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 274999815 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 274973191 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 523840 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4039348922 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 1079774887 # The number of ROB reads +system.cpu.rob.rob_writes 1655221365 # The number of ROB writes +system.cpu.timesIdled 1257777 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 190759003 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9822826051 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407854776 # Number of Instructions Simulated +system.cpu.committedOps 806198141 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407854776 # Number of Instructions Simulated +system.cpu.cpi 1.110993 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.110993 # CPI: Total CPI of All Threads +system.cpu.ipc 0.900096 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.900096 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1088904390 # number of integer regfile reads +system.cpu.int_regfile_writes 653903158 # number of integer regfile writes +system.cpu.fp_regfile_reads 48 # number of floating regfile reads +system.cpu.cc_regfile_reads 415697548 # number of cc regfile reads +system.cpu.cc_regfile_writes 321557341 # number of cc regfile writes +system.cpu.misc_regfile_reads 264102486 # number of misc regfile reads +system.cpu.misc_regfile_writes 402568 # number of misc regfile writes +system.cpu.toL2Bus.throughput 53587278 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3014875 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3014340 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1579042 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 336648 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 289942 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1911181 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6131826 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18757 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 150026 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8211790 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61153920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207959183 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 582080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5191488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 274886671 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 274861071 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 468864 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4035423910 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 624000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 600000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1440815600 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1436807344 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3139539816 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3142634309 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 14707994 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 14495745 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 103656142 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 103414152 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 957724 # number of replacements -system.cpu.icache.tags.tagsinuse 509.254964 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7477774 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 958236 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.803687 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147611306250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.254964 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994639 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994639 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 955079 # number of replacements +system.cpu.icache.tags.tagsinuse 509.954947 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7470392 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 955591 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.817562 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147668859250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.954947 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996006 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996006 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 196 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9447804 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9447804 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7477774 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7477774 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7477774 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7477774 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7477774 # number of overall hits -system.cpu.icache.overall_hits::total 7477774 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1011731 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1011731 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1011731 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1011731 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1011731 # number of overall misses -system.cpu.icache.overall_misses::total 1011731 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14180716030 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14180716030 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14180716030 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14180716030 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14180716030 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14180716030 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8489505 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8489505 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8489505 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8489505 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8489505 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8489505 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119174 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.119174 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.119174 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.119174 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.119174 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.119174 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14016.290921 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14016.290921 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14016.290921 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14016.290921 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14016.290921 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14016.290921 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5333 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 9435405 # Number of tag accesses +system.cpu.icache.tags.data_accesses 9435405 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7470392 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7470392 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7470392 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7470392 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7470392 # number of overall hits +system.cpu.icache.overall_hits::total 7470392 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1009362 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1009362 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1009362 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1009362 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1009362 # number of overall misses +system.cpu.icache.overall_misses::total 1009362 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14063763284 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14063763284 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14063763284 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14063763284 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14063763284 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14063763284 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8479754 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8479754 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8479754 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8479754 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8479754 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8479754 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119032 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.119032 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.119032 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.119032 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.119032 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.119032 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13933.319546 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13933.319546 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13933.319546 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13933.319546 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13933.319546 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13933.319546 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4512 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 185 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 173 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.827027 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 26.080925 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53432 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 53432 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 53432 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 53432 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 53432 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 53432 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958299 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 958299 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 958299 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 958299 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 958299 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 958299 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11693776143 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11693776143 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11693776143 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11693776143 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11693776143 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11693776143 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112880 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112880 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112880 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.112880 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112880 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.112880 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12202.638365 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12202.638365 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12202.638365 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12202.638365 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12202.638365 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12202.638365 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53711 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 53711 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 53711 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 53711 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 53711 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 53711 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 955651 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 955651 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 955651 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 955651 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 955651 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 955651 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11613116903 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11613116903 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11613116903 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11613116903 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11613116903 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11613116903 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112698 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112698 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112698 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.112698 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112698 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.112698 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12152.048083 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12152.048083 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12152.048083 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12152.048083 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12152.048083 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12152.048083 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 8926 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.004704 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 20407 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 8940 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.282662 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5105549292500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.004704 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375294 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.375294 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.replacements 8788 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 5.050842 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 20362 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 8802 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.313338 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5105053160000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 5.050842 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.315678 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.315678 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 70243 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 70243 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20415 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 20415 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.tag_accesses 69716 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 69716 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20363 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 20363 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 20417 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 20417 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 20417 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 20417 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9803 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 9803 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9803 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 9803 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9803 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 9803 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 109186247 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 109186247 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 109186247 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 109186247 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 109186247 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 109186247 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30218 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 30218 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 20365 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 20365 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 20365 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 20365 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9662 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 9662 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9662 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 9662 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9662 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 9662 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 109674498 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 109674498 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 109674498 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 109674498 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 109674498 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 109674498 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30025 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 30025 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30220 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 30220 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30220 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 30220 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.324409 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.324409 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.324388 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.324388 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.324388 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.324388 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11138.044170 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11138.044170 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11138.044170 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11138.044170 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11138.044170 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11138.044170 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30027 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 30027 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30027 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 30027 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.321799 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.321799 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.321777 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.321777 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.321777 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.321777 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11351.117574 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11351.117574 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11351.117574 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11351.117574 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11351.117574 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11351.117574 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1141,85 +1011,85 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1993 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1993 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9803 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9803 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9803 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 9803 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9803 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 9803 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 89573259 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 89573259 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 89573259 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 89573259 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 89573259 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 89573259 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.324409 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.324409 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.324388 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.324388 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.324388 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.324388 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9137.331327 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9137.331327 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9137.331327 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9137.331327 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9137.331327 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9137.331327 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1311 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1311 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9662 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9662 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9662 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 9662 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9662 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 9662 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 90345008 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 90345008 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 90345008 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 90345008 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 90345008 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 90345008 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.321799 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.321799 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.321777 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.321777 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.321777 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.321777 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9350.549369 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9350.549369 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9350.549369 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9350.549369 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9350.549369 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9350.549369 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 68011 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 14.842846 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 91726 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 68027 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.348376 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 4994240386000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.842846 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.927678 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.927678 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 67950 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 13.831671 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 92323 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 67966 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.358370 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5101646178000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.831671 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.864479 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.864479 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 390650 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 390650 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 91726 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 91726 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 91726 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 91726 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 91726 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 91726 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 69066 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 69066 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 69066 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 69066 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 69066 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 69066 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 860977213 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 860977213 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 860977213 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 860977213 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 860977213 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 860977213 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 160792 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 160792 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 160792 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 160792 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 160792 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 160792 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429536 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429536 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429536 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429536 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429536 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429536 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12466.006617 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12466.006617 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12466.006617 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12466.006617 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12466.006617 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12466.006617 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 391373 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 391373 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92323 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 92323 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92323 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 92323 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92323 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 92323 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68909 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 68909 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68909 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 68909 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68909 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 68909 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 862549215 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 862549215 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 862549215 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 862549215 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 862549215 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 862549215 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 161232 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 161232 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 161232 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 161232 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 161232 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 161232 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.427390 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.427390 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.427390 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.427390 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.427390 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.427390 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12517.221481 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12517.221481 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12517.221481 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12517.221481 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12517.221481 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12517.221481 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1228,153 +1098,153 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 21216 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 21216 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 69066 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 69066 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 69066 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 69066 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 69066 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 69066 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 722730929 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 722730929 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 722730929 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 722730929 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 722730929 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 722730929 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429536 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429536 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429536 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429536 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429536 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429536 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10464.351910 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10464.351910 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10464.351910 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 16529 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 16529 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68909 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68909 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68909 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 68909 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68909 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 68909 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 724629911 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 724629911 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 724629911 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 724629911 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 724629911 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 724629911 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.427390 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.427390 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.427390 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.427390 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.427390 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.427390 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10515.751368 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10515.751368 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10515.751368 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10515.751368 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10515.751368 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10515.751368 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1656829 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997280 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18997986 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1657341 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.462931 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 39724250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997280 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1659840 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996448 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18992605 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1660352 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.438903 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 40084250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996448 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 87846935 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 87846935 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 10898836 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10898836 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8096443 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8096443 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 18995279 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18995279 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18995279 # number of overall hits -system.cpu.dcache.overall_hits::total 18995279 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2236048 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2236048 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316058 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316058 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2552106 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2552106 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2552106 # number of overall misses -system.cpu.dcache.overall_misses::total 2552106 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33041447208 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33041447208 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12234670517 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12234670517 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45276117725 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45276117725 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45276117725 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45276117725 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13134884 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13134884 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8412501 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8412501 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21547385 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21547385 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21547385 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21547385 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170237 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.170237 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037570 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037570 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118442 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118442 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118442 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118442 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14776.716425 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14776.716425 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38710.206725 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38710.206725 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17740.688563 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17740.688563 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17740.688563 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17740.688563 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 395761 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 87845319 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 87845319 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 10889826 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10889826 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8100117 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8100117 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 18989943 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18989943 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18989943 # number of overall hits +system.cpu.dcache.overall_hits::total 18989943 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2239768 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2239768 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316527 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316527 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2556295 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2556295 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2556295 # number of overall misses +system.cpu.dcache.overall_misses::total 2556295 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32903838390 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32903838390 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11976667737 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11976667737 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 44880506127 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 44880506127 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 44880506127 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 44880506127 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13129594 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13129594 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8416644 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8416644 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21546238 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21546238 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21546238 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21546238 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170589 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.170589 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118642 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118642 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118642 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118642 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14690.735107 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14690.735107 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37837.744448 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37837.744448 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17556.857142 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17556.857142 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17556.857142 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17556.857142 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 388578 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42262 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42350 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.364465 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.175396 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1558454 # number of writebacks -system.cpu.dcache.writebacks::total 1558454 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 866560 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 866560 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25905 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 25905 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 892465 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 892465 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 892465 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 892465 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369488 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29152333179 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29152333179 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29152333179 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29152333179 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97363398000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97363398000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2536146500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2536146500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99899544500 # 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average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13005.980852 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39085.580621 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39085.580621 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17565.445285 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17565.445285 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17565.445285 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17565.445285 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1561202 # number of writebacks +system.cpu.dcache.writebacks::total 1561202 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 869210 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 869210 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60745.633604 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61370.923592 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 102223 # number of writebacks +system.cpu.l2cache.writebacks::total 102223 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 49 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16166 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35906 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 52125 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1443 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1443 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133016 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133016 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 49 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16166 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 168922 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 185141 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 49 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16166 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 168922 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 185141 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3552250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 319250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1040184259 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2389977554 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3434033313 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15330925 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15330925 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7506177359 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7506177359 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3552250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 319250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1040184259 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9896154913 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10940210672 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3552250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 319250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1040184259 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9896154913 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10940210672 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89250256000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89250256000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370696500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370696500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91620952500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91620952500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000759 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000514 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016918 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026212 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021739 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.820819 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.820819 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.458806 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.458806 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000759 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000514 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016918 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101774 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.068885 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000759 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000514 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016918 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101774 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.068885 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72494.897959 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79812.500000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64343.947730 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66562.066340 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65880.735022 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10624.341649 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10624.341649 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56430.635104 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56430.635104 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72494.897959 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79812.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64343.947730 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58584.168510 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59091.236798 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72494.897959 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79812.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64343.947730 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58584.168510 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59091.236798 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index 269726e62..cc51e20ce 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.304497 # Nu sim_ticks 5304496750000 # Number of ticks simulated final_tick 5304496750000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125034 # Simulator instruction rate (inst/s) -host_op_rate 239740 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6206530470 # Simulator tick rate (ticks/s) -host_mem_usage 832476 # Number of bytes of host memory used -host_seconds 854.66 # Real time elapsed on the host +host_inst_rate 156851 # Simulator instruction rate (inst/s) +host_op_rate 300747 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7785889362 # Simulator tick rate (ticks/s) +host_mem_usage 816820 # Number of bytes of host memory used +host_seconds 681.30 # Real time elapsed on the host sim_insts 106862058 # Number of instructions simulated sim_ops 204897478 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -199,6 +199,38 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.totQLat 0 # Total ticks spent queuing system.physmem.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 0 # Total ticks spent in databus transfers diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index c3991f43e..b144561d0 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,161 +1,161 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.137456 # Number of seconds simulated -sim_ticks 5137456264000 # Number of ticks simulated -final_tick 5137456264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.139775 # Number of seconds simulated +sim_ticks 5139775442500 # Number of ticks simulated +final_tick 5139775442500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 293296 # Simulator instruction rate (inst/s) -host_op_rate 582999 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6174974039 # Simulator tick rate (ticks/s) -host_mem_usage 983548 # Number of bytes of host memory used -host_seconds 831.98 # Real time elapsed on the host -sim_insts 244016231 # Number of instructions simulated -sim_ops 485043652 # Number of ops (including micro ops) simulated +host_inst_rate 241106 # Simulator instruction rate (inst/s) +host_op_rate 479260 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5080243819 # Simulator tick rate (ticks/s) +host_mem_usage 990760 # Number of bytes of host memory used +host_seconds 1011.72 # Real time elapsed on the host +sim_insts 243931071 # Number of instructions simulated +sim_ops 484875903 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 2422400 # Number of bytes read from this memory +system.physmem.bytes_read::pc.south_bridge.ide 2452480 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 383808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5693376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 137536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1729152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 2176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 439552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5834944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 98048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1717440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1664 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 448384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2947264 # Number of bytes read from this memory -system.physmem.bytes_read::total 13764480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 383808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 137536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 448384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 969728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9086592 # Number of bytes written to this memory -system.physmem.bytes_written::total 9086592 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 37850 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu2.inst 432064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2820032 # Number of bytes read from this memory +system.physmem.bytes_read::total 13796608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 439552 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 98048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 432064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 969664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9118784 # Number of bytes written to this memory +system.physmem.bytes_written::total 9118784 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38320 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 5997 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 88959 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2149 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 27018 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 34 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6868 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 91171 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1532 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 26835 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 26 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 7006 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 46051 # Number of read requests responded to by this memory -system.physmem.num_reads::total 215070 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 141978 # Number of write requests responded to by this memory -system.physmem.num_writes::total 141978 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 471517 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu2.inst 6751 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 44063 # Number of read requests responded to by this memory +system.physmem.num_reads::total 215572 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 142481 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142481 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 477157 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 74708 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1108209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26771 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 336577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 85520 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1135253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 19076 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 334147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 324 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 87277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 573682 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2679240 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 74708 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26771 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 87277 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 188756 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1768695 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1768695 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1768695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 471517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 84063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 548668 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2684282 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 85520 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 19076 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 84063 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 188659 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1774160 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1774160 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1774160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 477157 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 74708 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1108209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 26771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 336577 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 85520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1135253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 19076 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 334147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 324 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 87277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 573682 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4447935 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 102292 # Number of read requests accepted -system.physmem.writeReqs 78374 # Number of write requests accepted -system.physmem.readBursts 102292 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 78374 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6544384 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2304 # Total number of bytes read from write queue -system.physmem.bytesWritten 5015936 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6546688 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5015936 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 36 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu2.inst 84063 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 548668 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4458442 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 98736 # Number of read requests accepted +system.physmem.writeReqs 74818 # Number of write requests accepted +system.physmem.readBursts 98736 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 74818 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6312704 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6400 # Total number of bytes read from write queue +system.physmem.bytesWritten 4788352 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6319104 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4788352 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 100 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 862 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6805 # Per bank write bursts -system.physmem.perBankRdBursts::1 7244 # Per bank write bursts -system.physmem.perBankRdBursts::2 6375 # Per bank write bursts -system.physmem.perBankRdBursts::3 6857 # Per bank write bursts -system.physmem.perBankRdBursts::4 6927 # Per bank write bursts -system.physmem.perBankRdBursts::5 6780 # Per bank write bursts -system.physmem.perBankRdBursts::6 5925 # Per bank write bursts -system.physmem.perBankRdBursts::7 6310 # Per bank write bursts -system.physmem.perBankRdBursts::8 5868 # Per bank write bursts -system.physmem.perBankRdBursts::9 5795 # Per bank write bursts -system.physmem.perBankRdBursts::10 5783 # Per bank write bursts -system.physmem.perBankRdBursts::11 6231 # Per bank write bursts -system.physmem.perBankRdBursts::12 6160 # Per bank write bursts -system.physmem.perBankRdBursts::13 6316 # Per bank write bursts -system.physmem.perBankRdBursts::14 6211 # Per bank write bursts -system.physmem.perBankRdBursts::15 6669 # Per bank write bursts -system.physmem.perBankWrBursts::0 5462 # Per bank write bursts -system.physmem.perBankWrBursts::1 5811 # Per bank write bursts -system.physmem.perBankWrBursts::2 4880 # Per bank write bursts -system.physmem.perBankWrBursts::3 5445 # Per bank write bursts -system.physmem.perBankWrBursts::4 5542 # Per bank write bursts -system.physmem.perBankWrBursts::5 5461 # Per bank write bursts -system.physmem.perBankWrBursts::6 4520 # Per bank write bursts -system.physmem.perBankWrBursts::7 4685 # Per bank write bursts -system.physmem.perBankWrBursts::8 4152 # Per bank write bursts -system.physmem.perBankWrBursts::9 4422 # Per bank write bursts -system.physmem.perBankWrBursts::10 4208 # Per bank write bursts -system.physmem.perBankWrBursts::11 4507 # Per bank write bursts -system.physmem.perBankWrBursts::12 4889 # Per bank write bursts -system.physmem.perBankWrBursts::13 4664 # Per bank write bursts -system.physmem.perBankWrBursts::14 4834 # Per bank write bursts -system.physmem.perBankWrBursts::15 4892 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 734 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6153 # Per bank write bursts +system.physmem.perBankRdBursts::1 6286 # Per bank write bursts +system.physmem.perBankRdBursts::2 6219 # Per bank write bursts +system.physmem.perBankRdBursts::3 6279 # Per bank write bursts +system.physmem.perBankRdBursts::4 6331 # Per bank write bursts +system.physmem.perBankRdBursts::5 6377 # Per bank write bursts +system.physmem.perBankRdBursts::6 5798 # Per bank write bursts +system.physmem.perBankRdBursts::7 6202 # Per bank write bursts +system.physmem.perBankRdBursts::8 5707 # Per bank write bursts +system.physmem.perBankRdBursts::9 6391 # Per bank write bursts +system.physmem.perBankRdBursts::10 5673 # Per bank write bursts +system.physmem.perBankRdBursts::11 6223 # Per bank write bursts +system.physmem.perBankRdBursts::12 6101 # Per bank write bursts +system.physmem.perBankRdBursts::13 6086 # Per bank write bursts +system.physmem.perBankRdBursts::14 6643 # Per bank write bursts +system.physmem.perBankRdBursts::15 6167 # Per bank write bursts +system.physmem.perBankWrBursts::0 4924 # Per bank write bursts +system.physmem.perBankWrBursts::1 4781 # Per bank write bursts +system.physmem.perBankWrBursts::2 4796 # Per bank write bursts +system.physmem.perBankWrBursts::3 4885 # Per bank write bursts +system.physmem.perBankWrBursts::4 4841 # Per bank write bursts +system.physmem.perBankWrBursts::5 4959 # Per bank write bursts +system.physmem.perBankWrBursts::6 4374 # Per bank write bursts +system.physmem.perBankWrBursts::7 4731 # Per bank write bursts +system.physmem.perBankWrBursts::8 4283 # Per bank write bursts +system.physmem.perBankWrBursts::9 4855 # Per bank write bursts +system.physmem.perBankWrBursts::10 4375 # Per bank write bursts +system.physmem.perBankWrBursts::11 4455 # Per bank write bursts +system.physmem.perBankWrBursts::12 4488 # Per bank write bursts +system.physmem.perBankWrBursts::13 4484 # Per bank write bursts +system.physmem.perBankWrBursts::14 5021 # Per bank write bursts +system.physmem.perBankWrBursts::15 4566 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 5136272146500 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times write queue was full causing retry +system.physmem.totGap 5135962999500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 102292 # Read request sizes (log2) +system.physmem.readPktSize::6 98736 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 78374 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 79930 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1482 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 828 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 776 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 356 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 307 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 303 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 17 # What read queue length does an incoming req see +system.physmem.writePktSize::6 74818 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 76556 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1291 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1756 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1005 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 756 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 662 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 432 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -165,556 +165,474 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 11 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37207 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 310.623700 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.064630 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1005.971949 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 16908 45.44% 45.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 5765 15.49% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3845 10.33% 71.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2398 6.45% 77.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1477 3.97% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1206 3.24% 84.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 882 2.37% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 634 1.70% 89.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 564 1.52% 90.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 479 1.29% 91.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 331 0.89% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 285 0.77% 93.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 209 0.56% 94.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 204 0.55% 94.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 197 0.53% 95.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 303 0.81% 95.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 153 0.41% 96.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 117 0.31% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 75 0.20% 96.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 61 0.16% 97.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 106 0.28% 97.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 199 0.53% 97.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 97 0.26% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 87 0.23% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 45 0.12% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 43 0.12% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 26 0.07% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 28 0.08% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 16 0.04% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 12 0.03% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 10 0.03% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 10 0.03% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 17 0.05% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 7 0.02% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 10 0.03% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 3 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 3 0.01% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 7 0.02% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 3 0.01% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 7 0.02% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 9 0.02% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 4 0.01% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 6 0.02% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 6 0.02% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 2 0.01% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 2 0.01% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 13 0.03% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 4 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.01% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 3 0.01% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 4 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 4 0.01% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 2 0.01% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 7 0.02% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 2 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 3 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 2 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 24 0.06% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 2 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 10 0.03% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 4 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 25 0.07% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 2 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 3 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 2 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 2 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 23 0.06% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 2 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 5 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 6 0.02% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 2 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 2 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 3 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 4 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 2 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8643 2 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9411 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10179 2 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11139 2 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11267 2 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 2 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11715 2 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12739 2 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13891 2 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 2 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 4 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 2 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 3 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 2 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 3 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 5 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 8 0.02% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15683 1 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 2 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 2 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 3 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 11 0.03% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 14 0.04% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 22 0.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37207 # Bytes accessed per row activation -system.physmem.totQLat 2596442750 # Total ticks spent queuing -system.physmem.totMemAccLat 4566061500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 511280000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1458338750 # Total ticks spent accessing banks -system.physmem.avgQLat 25391.59 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14261.64 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3885 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 22863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 371.369637 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 216.870030 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 366.414967 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7224 31.60% 31.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 5292 23.15% 54.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 2324 10.16% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1423 6.22% 71.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 882 3.86% 74.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 607 2.65% 77.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 442 1.93% 79.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 389 1.70% 81.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4280 18.72% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 22863 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4109 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.004867 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 117.614100 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 4100 99.78% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 6 0.15% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2815 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6656-6911 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4109 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4109 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.208323 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.187975 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.583219 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-1 44 1.07% 1.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2-3 6 0.15% 1.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-5 4 0.10% 1.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6-7 4 0.10% 1.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-9 2 0.05% 1.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14-15 4 0.10% 1.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2755 67.05% 68.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 853 20.76% 89.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 55 1.34% 90.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 41 1.00% 91.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 36 0.88% 92.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 45 1.10% 93.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 25 0.61% 94.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 36 0.88% 95.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 20 0.49% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 26 0.63% 96.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 28 0.68% 96.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 10 0.24% 97.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 24 0.58% 97.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 13 0.32% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 21 0.51% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 18 0.44% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 6 0.15% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 4 0.10% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 10 0.24% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 1 0.02% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 2 0.05% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 1 0.02% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 4 0.10% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-65 9 0.22% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-69 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-77 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4109 # Writes before turning the bus around for reads +system.physmem.totQLat 2553947750 # Total ticks spent queuing +system.physmem.totMemAccLat 4444375250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 493180000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1397247500 # Total ticks spent accessing banks +system.physmem.avgQLat 25892.65 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14165.70 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44653.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.27 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.27 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.98 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 45058.35 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.23 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.93 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.23 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.11 # Average write queue length when enqueuing -system.physmem.readRowHits 86197 # Number of row buffer hits during reads -system.physmem.writeRowHits 57226 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.30 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.02 # Row buffer hit rate for writes -system.physmem.avgGap 28429655.53 # Average gap between requests -system.physmem.pageHitRate 79.40 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.13 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 6440814 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 424797 # Transaction distribution -system.membus.trans_dist::ReadResp 424797 # Transaction distribution -system.membus.trans_dist::WriteReq 7056 # Transaction distribution -system.membus.trans_dist::WriteResp 7056 # Transaction distribution -system.membus.trans_dist::Writeback 78374 # Transaction distribution -system.membus.trans_dist::UpgradeReq 877 # Transaction distribution -system.membus.trans_dist::UpgradeResp 877 # Transaction distribution -system.membus.trans_dist::ReadExReq 80570 # Transaction distribution -system.membus.trans_dist::ReadExResp 80570 # Transaction distribution -system.membus.trans_dist::MessageReq 957 # Transaction distribution -system.membus.trans_dist::MessageResp 957 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1914 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 1914 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497710 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 221000 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1030868 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 68894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 68894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1101676 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3828 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 3828 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 160435 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995417 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8741760 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 9897612 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2820864 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2820864 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 12722304 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 32756791 # Total data (bytes) -system.membus.snoop_data_through_bus 332608 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 164980499 # Layer occupancy (ticks) +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.06 # Average write queue length when enqueuing +system.physmem.readRowHits 80976 # Number of row buffer hits during reads +system.physmem.writeRowHits 55952 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.10 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.78 # Row buffer hit rate for writes +system.physmem.avgGap 29592881.75 # Average gap between requests +system.physmem.pageHitRate 78.94 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.12 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6444852 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 422305 # Transaction distribution +system.membus.trans_dist::ReadResp 422303 # Transaction distribution +system.membus.trans_dist::WriteReq 6370 # Transaction distribution +system.membus.trans_dist::WriteResp 6370 # Transaction distribution +system.membus.trans_dist::Writeback 74818 # Transaction distribution +system.membus.trans_dist::UpgradeReq 747 # Transaction distribution +system.membus.trans_dist::UpgradeResp 747 # Transaction distribution +system.membus.trans_dist::ReadExReq 78043 # Transaction distribution +system.membus.trans_dist::ReadExResp 78043 # Transaction distribution +system.membus.trans_dist::MessageReq 885 # Transaction distribution +system.membus.trans_dist::MessageResp 885 # Transaction distribution +system.membus.trans_dist::BadAddressError 2 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1770 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 1770 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 309432 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497538 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 212160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1019134 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 66106 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 66106 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1087010 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3540 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 3540 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 158682 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995073 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8391680 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 9545435 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2715776 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2715776 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 12264751 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 32837413 # Total data (bytes) +system.membus.snoop_data_through_bus 287680 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 162853500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 315323500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 315156500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1914000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1770000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 859913497 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 821391499 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 957000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 885000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1658568572 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1625485201 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 223775499 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 213559749 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 103968 # number of replacements -system.l2c.tags.tagsinuse 64819.095791 # Cycle average of tags in use -system.l2c.tags.total_refs 3669692 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168243 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.811855 # Average number of references to valid blocks. +system.l2c.tags.replacements 104632 # number of replacements +system.l2c.tags.tagsinuse 64756.494280 # Cycle average of tags in use +system.l2c.tags.total_refs 3664896 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168700 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.724339 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51211.809516 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121912 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1304.363790 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4492.907273 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 251.742289 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1518.622796 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.780510 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.958868 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1352.233300 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4674.555536 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.781430 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51511.220399 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131167 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1228.361726 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4265.224240 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 282.161159 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1465.784470 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 10.322385 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.042344 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1365.490726 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4627.755664 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.785999 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.019903 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.068556 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003841 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.023172 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000180 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.020633 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.071328 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989061 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64275 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3733 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7385 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52859 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.980759 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 33713228 # Number of tag accesses -system.l2c.tags.data_accesses 33713228 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 21716 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 11486 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 326601 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 505560 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 10498 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5651 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 148959 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 223967 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 55385 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 11312 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 366888 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 576803 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2264826 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.018743 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.065082 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.004305 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.022366 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000158 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.020836 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.070614 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.988106 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64068 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2732 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7219 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53790 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.977600 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 33688290 # Number of tag accesses +system.l2c.tags.data_accesses 33688290 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 22061 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 11615 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 344470 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 519863 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 10165 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5243 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 139799 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 221175 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 54188 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 10719 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 354261 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 566062 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2259621 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1544272 # number of Writeback hits -system.l2c.Writeback_hits::total 1544272 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 123 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 38 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 95 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 256 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 65648 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 35064 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 65209 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 165921 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 21716 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 11488 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 326601 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 571208 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 10498 # 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Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000219024509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.107425 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006714 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006714 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428661 # Number of tag accesses -system.iocache.tags.data_accesses 428661 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses -system.iocache.ReadReq_misses::total 909 # number of ReadReq misses +system.iocache.tags.tag_accesses 428643 # Number of tag accesses +system.iocache.tags.data_accesses 428643 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses +system.iocache.ReadReq_misses::total 907 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47629 # number of demand (read+write) misses -system.iocache.demand_misses::total 47629 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47629 # number of overall misses -system.iocache.overall_misses::total 47629 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 135882017 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 135882017 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 5955673280 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5955673280 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 6091555297 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 6091555297 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 6091555297 # number of overall miss cycles -system.iocache.overall_miss_latency::total 6091555297 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47627 # number of demand (read+write) misses +system.iocache.demand_misses::total 47627 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47627 # number of overall misses +system.iocache.overall_misses::total 47627 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 128792785 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 128792785 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 5668191006 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5668191006 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 5796983791 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5796983791 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 5796983791 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5796983791 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47629 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47629 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47627 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47627 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -904,60 +822,60 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 149485.167217 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 149485.167217 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 127475.883562 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 127475.883562 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 127895.930987 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 127895.930987 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 127895.930987 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 127895.930987 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 91729 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 141998.660419 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 141998.660419 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 121322.581464 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 121322.581464 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 121716.332983 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 121716.332983 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 121716.332983 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 121716.332983 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 88529 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5124 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7334 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 17.901835 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.071039 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 754 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 754 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 24064 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 24064 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 24818 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 24818 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 24818 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 24818 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96648017 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 96648017 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4703544282 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4703544282 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4800192299 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4800192299 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4800192299 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4800192299 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.829483 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.829483 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.515068 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.515068 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.521069 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.521069 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.521069 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.521069 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 128180.393899 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 128180.393899 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 195459.785655 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 195459.785655 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 193415.758683 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 193415.758683 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 193415.758683 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 193415.758683 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 744 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 744 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 22928 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 22928 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 23672 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 23672 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 23672 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 23672 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90079785 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 90079785 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4474936508 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4474936508 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4565016293 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4565016293 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4565016293 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4565016293 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.820287 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.820287 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.490753 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.490753 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.497029 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.497029 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.497029 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.497029 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 121074.979839 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 121074.979839 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 195173.434578 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 195173.434578 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 192844.554453 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 192844.554453 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 192844.554453 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 192844.554453 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -967,474 +885,476 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 52370833 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1836862 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1836332 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 7056 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 7056 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 922959 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 811 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 811 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 181042 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 156978 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1050040 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3684115 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 38115 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 140219 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4912489 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 33600320 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 122621708 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 135720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 527336 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 156885084 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 268925359 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 127504 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5157428290 # Layer occupancy (ticks) +system.toL2Bus.throughput 52329028 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1794981 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1794440 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 6370 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 6370 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 902417 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 716 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 716 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 170908 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 147982 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1004724 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3613728 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 35279 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 136436 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4790167 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 32150080 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119808027 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 127712 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 515032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 152600851 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 268845429 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 114024 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5038805323 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1008000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 931500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2365130940 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2262930320 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4803653283 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4696428413 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 21171206 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 19332464 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 74417261 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 72173756 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1276721 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 150736 # Transaction distribution -system.iobus.trans_dist::ReadResp 150736 # Transaction distribution -system.iobus.trans_dist::WriteReq 30161 # Transaction distribution -system.iobus.trans_dist::WriteResp 30161 # Transaction distribution -system.iobus.trans_dist::MessageReq 957 # Transaction distribution -system.iobus.trans_dist::MessageResp 957 # Transaction distribution +system.iobus.throughput 1276348 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 149977 # Transaction distribution +system.iobus.trans_dist::ReadResp 149977 # Transaction distribution +system.iobus.trans_dist::WriteReq 28411 # Transaction distribution +system.iobus.trans_dist::WriteResp 28411 # Transaction distribution +system.iobus.trans_dist::MessageReq 885 # Transaction distribution +system.iobus.trans_dist::MessageResp 885 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5986 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5752 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1160 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 46 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 582 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 50 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287076 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 580 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287032 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 332 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 15082 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 13448 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 312158 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 49636 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 49636 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1914 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1914 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 363708 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 309432 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 47344 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 47344 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1770 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1770 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 358546 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3380 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3245 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 23 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 291 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 25 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 12 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143538 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143516 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 664 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7541 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 6724 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4128 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 160435 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1576592 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1576592 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3828 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3828 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1740855 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6559098 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2255722 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 158682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1503808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1503808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3540 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3540 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1666030 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 6560144 # Total data (bytes) +system.iobus.reqLayer0.occupancy 2116890 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4948000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4753000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 383000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 39000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 42000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 143539000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 143517000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 458000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 264000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11248000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10048000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 218954798 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 209101042 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 306061000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 303949000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 29747501 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 28759251 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 957000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 885000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 1152461068 # number of cpu cycles simulated +system.cpu0.numCycles 1144797664 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 71542662 # Number of instructions committed -system.cpu0.committedOps 145644721 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 133686522 # Number of integer alu accesses +system.cpu0.committedInsts 72999922 # Number of instructions committed +system.cpu0.committedOps 148305710 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 136279674 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 963574 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14130614 # number of instructions that are conditional controls -system.cpu0.num_int_insts 133686522 # number of integer instructions +system.cpu0.num_func_calls 1016299 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14345558 # number of instructions that are conditional controls +system.cpu0.num_int_insts 136279674 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 245609809 # number of times the integer registers were read -system.cpu0.num_int_register_writes 114802156 # number of times the integer registers were written +system.cpu0.num_int_register_reads 250792350 # number of times the integer registers were read +system.cpu0.num_int_register_writes 116890419 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 83145706 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55494396 # number of times the CC registers were written -system.cpu0.num_mem_refs 13834339 # number of memory refs -system.cpu0.num_load_insts 10142209 # Number of load instructions -system.cpu0.num_store_insts 3692130 # Number of store instructions -system.cpu0.num_idle_cycles 1095316733.110107 # Number of idle cycles -system.cpu0.num_busy_cycles 57144334.889893 # Number of busy cycles -system.cpu0.not_idle_fraction 0.049585 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.950415 # Percentage of idle cycles -system.cpu0.Branches 15442715 # Number of branches fetched +system.cpu0.num_cc_register_reads 84577193 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 56435831 # number of times the CC registers were written +system.cpu0.num_mem_refs 14370687 # number of memory refs +system.cpu0.num_load_insts 10454117 # Number of load instructions +system.cpu0.num_store_insts 3916570 # Number of store instructions +system.cpu0.num_idle_cycles 1087719763.352511 # Number of idle cycles +system.cpu0.num_busy_cycles 57077900.647489 # Number of busy cycles +system.cpu0.not_idle_fraction 0.049859 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.950141 # Percentage of idle cycles +system.cpu0.Branches 15728655 # Number of branches fetched system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 857108 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.816977 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 128607019 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 857620 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 149.958046 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 147466681500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 303.791229 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 134.865519 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 72.160229 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.593342 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.263409 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.140938 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997689 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 853193 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.838528 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 129757026 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 853705 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 151.992815 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 147468978000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 295.878537 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 138.959383 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 76.000608 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.577888 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.271405 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.148439 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997732 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 130343050 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 130343050 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 87032678 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 38704601 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2869740 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 128607019 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 87032678 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 38704601 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2869740 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 128607019 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 87032678 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 38704601 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2869740 # number of overall hits -system.cpu0.icache.overall_hits::total 128607019 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 332599 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 151109 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 394689 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 878397 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 332599 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 151109 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 394689 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 878397 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 332599 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 151109 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 394689 # number of overall misses -system.cpu0.icache.overall_misses::total 878397 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2111983250 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5690259841 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7802243091 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2111983250 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5690259841 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7802243091 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2111983250 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5690259841 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7802243091 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 87365277 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 38855710 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3264429 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 129485416 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 87365277 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 38855710 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3264429 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 129485416 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 87365277 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 38855710 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3264429 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 129485416 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003807 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.003889 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.120906 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006784 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003807 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.003889 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.120906 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006784 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003807 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.003889 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.120906 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006784 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13976.555003 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14417.072280 # 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mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.061741 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034718 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032833 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018787 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065561 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.085550 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.045076 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065561 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.085550 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.045076 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12235.570561 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14451.969857 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13834.111707 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35393.937975 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33072.611607 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33933.852768 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16966.312778 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17133.287139 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17084.249636 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16966.312778 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17133.287139 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17084.249636 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1545523 # number of writebacks +system.cpu0.dcache.writebacks::total 1545523 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 357871 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 357871 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 17395 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 17395 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 375266 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 375266 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 375266 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 375266 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 225063 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 578353 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 803416 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 58088 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 90563 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 148651 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 283151 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 668916 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 952067 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 283151 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 668916 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 952067 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2737161496 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8309689554 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11046851050 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1998659220 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2996226317 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4994885537 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4735820716 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11305915871 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16041736587 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4735820716 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11305915871 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16041736587 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30467694000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33225580500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63693274500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 404660000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 790542000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1195202000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30872354000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34016122500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64888476500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.087612 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.119442 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.060636 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036160 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031444 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017698 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.067816 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.086622 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.043977 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.067816 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086622 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.043977 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12161.756913 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14367.850697 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13749.851945 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34407.437336 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33084.441958 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33601.425735 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16725.424653 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16901.846975 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16849.377814 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16725.424653 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16901.846975 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16849.377814 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1445,307 +1365,307 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606011326 # number of cpu cycles simulated +system.cpu1.numCycles 2608015730 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35164948 # Number of instructions committed -system.cpu1.committedOps 68413270 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 63529188 # Number of integer alu accesses +system.cpu1.committedInsts 34716890 # Number of instructions committed +system.cpu1.committedOps 67541836 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 62669042 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 457891 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6471423 # number of instructions that are conditional controls -system.cpu1.num_int_insts 63529188 # number of integer instructions +system.cpu1.num_func_calls 430919 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6413966 # number of instructions that are conditional controls +system.cpu1.num_int_insts 62669042 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 117257194 # number of times the integer registers were read -system.cpu1.num_int_register_writes 54850904 # number of times the integer registers were written +system.cpu1.num_int_register_reads 115548964 # number of times the integer registers were read +system.cpu1.num_int_register_writes 54160900 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36014934 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26882843 # number of times the CC registers were written -system.cpu1.num_mem_refs 4560424 # number of memory refs -system.cpu1.num_load_insts 2872895 # Number of load instructions -system.cpu1.num_store_insts 1687529 # Number of store instructions -system.cpu1.num_idle_cycles 2475874291.383945 # Number of idle cycles -system.cpu1.num_busy_cycles 130137034.616055 # Number of busy cycles -system.cpu1.not_idle_fraction 0.049937 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.950063 # Percentage of idle cycles -system.cpu1.Branches 7096172 # Number of branches fetched +system.cpu1.num_cc_register_reads 35562537 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26614034 # number of times the CC registers were written +system.cpu1.num_mem_refs 4364452 # number of memory refs +system.cpu1.num_load_insts 2756893 # Number of load instructions +system.cpu1.num_store_insts 1607559 # Number of store instructions +system.cpu1.num_idle_cycles 2483429860.768801 # Number of idle cycles +system.cpu1.num_busy_cycles 124585869.231199 # Number of busy cycles +system.cpu1.not_idle_fraction 0.047770 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.952230 # Percentage of idle cycles +system.cpu1.Branches 7003911 # Number of branches fetched system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 29049356 # Number of BP lookups -system.cpu2.branchPred.condPredicted 29049356 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 330189 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26516680 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25920061 # Number of BTB hits +system.cpu2.branchPred.lookups 28782114 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28782114 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 316524 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26348266 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25752004 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.750024 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 553809 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 66194 # Number of incorrect RAS predictions. -system.cpu2.numCycles 157465018 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.736997 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 537542 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 63717 # Number of incorrect RAS predictions. +system.cpu2.numCycles 155552038 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10014190 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 143120520 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 29049356 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26473870 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 54776048 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1540394 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 78659 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 25463388 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 3574 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 6100 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 25165 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 454 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3264432 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 152504 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2125 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 91560833 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.080398 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.405930 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9686701 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 141772190 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28782114 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26289546 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 54340809 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1470890 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 70055 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 24627328 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 4722 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 7901 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 23768 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 376 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3150040 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 144648 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2015 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 89899907 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 3.110146 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.408280 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 36927513 40.33% 40.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 611138 0.67% 41.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23812381 26.01% 67.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 328703 0.36% 67.36% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 619714 0.68% 68.04% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 832275 0.91% 68.95% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 355282 0.39% 69.34% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 540716 0.59% 69.93% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27533111 30.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 35694732 39.70% 39.70% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 594255 0.66% 40.37% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23712499 26.38% 66.74% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 314699 0.35% 67.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 599600 0.67% 67.76% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 812421 0.90% 68.66% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 338881 0.38% 69.04% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 517837 0.58% 69.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27314983 30.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 91560833 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.184481 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.908904 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 11521398 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 24357574 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 32837645 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1316376 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1196608 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 281192085 # Number of instructions handled by decode +system.cpu2.fetch.rateDist::total 89899907 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.185032 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.911413 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 11154829 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 23540580 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 30801007 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1287318 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1141583 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 278785410 # Number of instructions handled by decode system.cpu2.decode.SquashedInsts 11 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1196608 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 12539536 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 14626708 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4503596 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 32964525 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5398696 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 280154725 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 7234 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2491982 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 2219031 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 334708153 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 610319016 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 374834819 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 56 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 324049688 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10658465 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 153621 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 154561 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 11685330 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6409686 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3556417 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 350066 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 288206 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 278401976 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 420214 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 276663998 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 65469 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7519016 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11586940 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 57670 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 91560833 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.021641 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.405034 # Number of insts issued each cycle +system.cpu2.rename.SquashCycles 1141583 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 12143079 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 13933433 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4524497 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 30930733 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5252059 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 277791777 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 7238 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2464468 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 2117220 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 331976691 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 604531856 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 371338716 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 38 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 321781805 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10194886 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 148461 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 149473 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 11392573 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6171654 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3395563 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 345995 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 292325 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 276091246 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 414813 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 274477250 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 60541 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7173454 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11041443 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 56132 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 89899907 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 3.053143 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.400877 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 27548029 30.09% 30.09% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6302445 6.88% 36.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 4040687 4.41% 41.38% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2809709 3.07% 44.45% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 25166051 27.49% 71.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1389542 1.52% 73.46% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23947180 26.15% 99.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 301462 0.33% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 55728 0.06% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 26563563 29.55% 29.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6130901 6.82% 36.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3934206 4.38% 40.74% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2710119 3.01% 43.76% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 25036419 27.85% 71.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1342117 1.49% 73.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23840310 26.52% 99.62% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 288717 0.32% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 53555 0.06% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 91560833 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 89899907 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 136321 35.17% 35.17% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 124 0.03% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 194124 50.09% 85.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 56993 14.71% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 122290 33.50% 33.50% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 245 0.07% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 189949 52.03% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 52573 14.40% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 81905 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 266468718 96.31% 96.34% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 56660 0.02% 96.37% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 48242 0.02% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.38% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6674536 2.41% 98.79% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3333937 1.21% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 80536 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 264658650 96.42% 96.45% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 54855 0.02% 96.47% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 48402 0.02% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6455691 2.35% 98.84% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3179116 1.16% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 276663998 # Type of FU issued -system.cpu2.iq.rate 1.756987 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 387562 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001401 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 645385259 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 286345237 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 275267423 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 94 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 106 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 22 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 276969613 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 42 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 657734 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 274477250 # Type of FU issued +system.cpu2.iq.rate 1.764537 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 365057 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001330 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 639321511 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 283683445 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 273115126 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 61 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 18 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 274761742 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 29 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 634301 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1052819 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6947 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4672 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 529632 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1002623 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6718 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4440 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 510444 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 656268 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 10631 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 656391 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 10280 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1196608 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9811775 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 820688 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 278822190 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 75669 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6409704 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3556417 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 239796 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 634227 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 4101 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4672 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 184871 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 190702 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 375573 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 276137017 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6556879 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 526981 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1141583 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 9227965 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 815382 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 276506059 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 71664 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6171654 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3395563 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 234992 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 633068 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 3849 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4440 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 176570 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 182317 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 358887 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 273973436 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6342946 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 503814 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9821909 # number of memory reference insts executed -system.cpu2.iew.exec_branches 28090459 # Number of branches executed -system.cpu2.iew.exec_stores 3265030 # Number of stores executed -system.cpu2.iew.exec_rate 1.753640 # Inst execution rate -system.cpu2.iew.wb_sent 275979435 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 275267445 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 214496489 # num instructions producing a value -system.cpu2.iew.wb_consumers 350700107 # num instructions consuming a value +system.cpu2.iew.exec_refs 9455734 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27867681 # Number of branches executed +system.cpu2.iew.exec_stores 3112788 # Number of stores executed +system.cpu2.iew.exec_rate 1.761298 # Inst execution rate +system.cpu2.iew.wb_sent 273823666 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 273115144 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 212986974 # num instructions producing a value +system.cpu2.iew.wb_consumers 348231532 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.748118 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.611624 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.755780 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.611625 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7834345 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 362544 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 332977 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 90364225 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 2.998816 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.871519 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7474898 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 358681 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 318992 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 88758324 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 3.031021 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.870805 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 32381210 35.83% 35.83% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4545159 5.03% 40.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1281676 1.42% 42.28% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24783522 27.43% 69.71% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 890698 0.99% 70.69% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 597656 0.66% 71.36% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 358639 0.40% 71.75% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23381642 25.87% 97.63% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2144023 2.37% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 31301057 35.27% 35.27% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4393147 4.95% 40.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1229186 1.38% 41.60% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24655081 27.78% 69.38% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 868070 0.98% 70.36% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 585819 0.66% 71.02% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 347474 0.39% 71.41% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23302544 26.25% 97.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2075946 2.34% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 90364225 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 137308621 # Number of instructions committed -system.cpu2.commit.committedOps 270985661 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 88758324 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 136214259 # Number of instructions committed +system.cpu2.commit.committedOps 269028357 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8383670 # Number of memory references committed -system.cpu2.commit.loads 5356885 # Number of loads committed -system.cpu2.commit.membars 165489 # Number of memory barriers committed -system.cpu2.commit.branches 27738642 # Number of branches committed +system.cpu2.commit.refs 8054150 # Number of memory references committed +system.cpu2.commit.loads 5169031 # Number of loads committed +system.cpu2.commit.membars 165004 # Number of memory barriers committed +system.cpu2.commit.branches 27530478 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 247503684 # Number of committed integer instructions. -system.cpu2.commit.function_calls 442390 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 2144023 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 245624895 # Number of committed integer instructions. +system.cpu2.commit.function_calls 430032 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 2075946 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 367011505 # The number of ROB reads -system.cpu2.rob.rob_writes 558841004 # The number of ROB writes -system.cpu2.timesIdled 481956 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65904185 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4905068069 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 137308621 # Number of Instructions Simulated -system.cpu2.committedOps 270985661 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 137308621 # Number of Instructions Simulated -system.cpu2.cpi 1.146796 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.146796 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.871994 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.871994 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 367544012 # number of integer regfile reads -system.cpu2.int_regfile_writes 220503659 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72990 # number of floating regfile reads -system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes -system.cpu2.cc_regfile_reads 140406201 # number of cc regfile reads -system.cpu2.cc_regfile_writes 108013944 # number of cc regfile writes -system.cpu2.misc_regfile_reads 89640596 # number of misc regfile reads -system.cpu2.misc_regfile_writes 136839 # number of misc regfile writes +system.cpu2.rob.rob_reads 363157720 # The number of ROB reads +system.cpu2.rob.rob_writes 554152180 # The number of ROB writes +system.cpu2.timesIdled 477715 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 65652131 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4906975665 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 136214259 # Number of Instructions Simulated +system.cpu2.committedOps 269028357 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 136214259 # Number of Instructions Simulated +system.cpu2.cpi 1.141966 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.141966 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.875683 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.875683 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 364409735 # number of integer regfile reads +system.cpu2.int_regfile_writes 218808578 # number of integer regfile writes +system.cpu2.fp_regfile_reads 73042 # number of floating regfile reads +system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes +system.cpu2.cc_regfile_reads 139320542 # number of cc regfile reads +system.cpu2.cc_regfile_writes 107246688 # number of cc regfile writes +system.cpu2.misc_regfile_reads 88724841 # number of misc regfile reads +system.cpu2.misc_regfile_writes 132896 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 8c91cbc4e..7e42f0dae 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,56 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026912 # Number of seconds simulated -sim_ticks 26911921000 # Number of ticks simulated -final_tick 26911921000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026923 # Number of seconds simulated +sim_ticks 26922512500 # Number of ticks simulated +final_tick 26922512500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 176190 # Simulator instruction rate (inst/s) -host_op_rate 177456 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52341651 # Simulator tick rate (ticks/s) -host_mem_usage 402844 # Number of bytes of host memory used -host_seconds 514.16 # Real time elapsed on the host +host_inst_rate 143955 # Simulator instruction rate (inst/s) +host_op_rate 144989 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42782119 # Simulator tick rate (ticks/s) +host_mem_usage 446112 # Number of bytes of host memory used +host_seconds 629.29 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 45504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947776 # Number of bytes read from this memory -system.physmem.bytes_read::total 993280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45504 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 711 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14809 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15520 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1690849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35217701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36908551 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1690849 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1690849 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1690849 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35217701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 36908551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15520 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory +system.physmem.bytes_read::total 992896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15514 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1680675 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35199092 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36879767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1680675 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1680675 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1680675 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35199092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 36879767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15514 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 15520 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 15514 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 993280 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 992896 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 993280 # Total read bytes from the system interface side +system.physmem.bytesReadSys 992896 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 989 # Per bank write bursts +system.physmem.perBankRdBursts::0 988 # Per bank write bursts system.physmem.perBankRdBursts::1 886 # Per bank write bursts system.physmem.perBankRdBursts::2 942 # Per bank write bursts -system.physmem.perBankRdBursts::3 1029 # Per bank write bursts -system.physmem.perBankRdBursts::4 1049 # Per bank write bursts +system.physmem.perBankRdBursts::3 1028 # Per bank write bursts +system.physmem.perBankRdBursts::4 1050 # Per bank write bursts system.physmem.perBankRdBursts::5 1105 # Per bank write bursts -system.physmem.perBankRdBursts::6 1079 # Per bank write bursts -system.physmem.perBankRdBursts::7 1079 # Per bank write bursts +system.physmem.perBankRdBursts::6 1078 # Per bank write bursts +system.physmem.perBankRdBursts::7 1078 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts -system.physmem.perBankRdBursts::9 959 # Per bank write bursts +system.physmem.perBankRdBursts::9 956 # Per bank write bursts system.physmem.perBankRdBursts::10 938 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts system.physmem.perBankRdBursts::12 904 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26911727500 # Total gap between requests +system.physmem.totGap 26922312500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15520 # Read request sizes (log2) +system.physmem.readPktSize::6 15514 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 11175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4158 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10767 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -154,167 +154,104 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 622 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1591.562701 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 476.433802 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2197.906875 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 160 25.72% 25.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 68 10.93% 36.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 41 6.59% 43.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 21 3.38% 46.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 13 2.09% 48.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 6 0.96% 49.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 27 4.34% 54.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 12 1.93% 55.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 5 0.80% 56.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 10 1.61% 58.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 3 0.48% 58.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 4 0.64% 59.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 5 0.80% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 8 1.29% 61.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 3 0.48% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 3 0.48% 62.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 6 0.96% 63.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 2 0.32% 63.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.32% 64.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.48% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.32% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 4 0.64% 65.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 6 0.96% 66.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 19 3.05% 69.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 6 0.96% 70.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 6 0.96% 71.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 3 0.48% 72.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 3 0.48% 72.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 1 0.16% 72.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 6 0.96% 73.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.32% 73.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 6 0.96% 74.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.32% 75.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.16% 75.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 3 0.48% 75.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.16% 76.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 2 0.32% 76.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.16% 76.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 5 0.80% 77.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 4 0.64% 77.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 2 0.32% 78.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 3 0.48% 78.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 4 0.64% 79.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 2 0.32% 79.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 2 0.32% 80.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 2 0.32% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 3 0.48% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.16% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 2 0.32% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.16% 81.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 3 0.48% 81.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 3 0.48% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 2 0.32% 82.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.16% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 1 0.16% 83.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.16% 83.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 3 0.48% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 2 0.32% 84.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.16% 84.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 3 0.48% 84.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 4 0.64% 85.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 4 0.64% 86.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.16% 86.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 3 0.48% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 2 0.32% 86.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 2 0.32% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.16% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 2 0.32% 87.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.16% 87.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 2 0.32% 88.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 5 0.80% 89.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 3 0.48% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 4 0.64% 90.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 2 0.32% 90.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 6 0.96% 91.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 3 0.48% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 1 0.16% 92.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 1 0.16% 92.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 1 0.16% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.16% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 3 0.48% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 1 0.16% 93.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.32% 93.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 1 0.16% 93.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 2 0.32% 94.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 3 0.48% 94.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.16% 94.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 2 0.32% 95.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.16% 95.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 3 0.48% 95.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.16% 95.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.16% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.16% 96.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.16% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.16% 96.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.32% 96.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.16% 96.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.16% 97.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.16% 97.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 1 0.16% 97.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.16% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.16% 97.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.32% 98.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 12 1.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 622 # Bytes accessed per row activation -system.physmem.totQLat 103005000 # Total ticks spent queuing -system.physmem.totMemAccLat 356453750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77600000 # Total ticks spent in databus transfers -system.physmem.totBankLat 175848750 # Total ticks spent accessing banks -system.physmem.avgQLat 6636.92 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 11330.46 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 880 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 935.927273 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 827.602742 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 262.440032 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 41 4.66% 4.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 26 2.95% 7.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13 1.48% 9.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 0.45% 9.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5 0.57% 10.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 0.23% 10.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 0.23% 10.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.11% 10.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 786 89.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 880 # Bytes accessed per row activation +system.physmem.totQLat 108095000 # Total ticks spent queuing +system.physmem.totMemAccLat 369557500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77570000 # Total ticks spent in databus transfers +system.physmem.totBankLat 183892500 # Total ticks spent accessing banks +system.physmem.avgQLat 6967.58 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11853.33 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 22967.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23820.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 36.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.91 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 36.88 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.29 # Data bus utilization in percentage system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14898 # Number of row buffer hits during reads +system.physmem.readRowHits 14141 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.99 # Row buffer hit rate for reads +system.physmem.readRowHitRate 91.15 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1734003.06 # Average gap between requests -system.physmem.pageHitRate 95.99 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.99 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 36908551 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 982 # Transaction distribution -system.membus.trans_dist::ReadResp 982 # Transaction distribution +system.physmem.avgGap 1735355.97 # Average gap between requests +system.physmem.pageHitRate 91.15 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.09 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 36879767 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 976 # Transaction distribution +system.membus.trans_dist::ReadResp 976 # Transaction distribution system.membus.trans_dist::UpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 1 # Transaction distribution system.membus.trans_dist::ReadExReq 14538 # Transaction distribution system.membus.trans_dist::ReadExResp 14538 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31042 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31042 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 993280 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 993280 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 993280 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31030 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31030 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992896 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 992896 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 992896 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 19254500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 19225500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 145212249 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 144897999 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 26683530 # Number of BP lookups -system.cpu.branchPred.condPredicted 22001633 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 843091 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11366562 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11283436 # Number of BTB hits +system.cpu.branchPred.lookups 26688187 # Number of BP lookups +system.cpu.branchPred.condPredicted 22005801 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 842567 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11378681 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11285656 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.268679 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 69998 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 165 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.182462 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 69960 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 176 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -400,133 +337,133 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53823843 # number of cpu cycles simulated +system.cpu.numCycles 53845026 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14173676 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127895760 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26683530 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11353434 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24037387 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4765940 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11314746 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 14173388 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127901014 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26688187 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11355616 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24038968 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4766662 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11320590 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13845039 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 329540 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53432137 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.410093 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.214797 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 13845523 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 330018 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53440501 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.409803 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.214653 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29433098 55.09% 55.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3389468 6.34% 61.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2029496 3.80% 65.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1553729 2.91% 68.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1668795 3.12% 71.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2919650 5.46% 76.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1509735 2.83% 79.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1090422 2.04% 81.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9837744 18.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29439765 55.09% 55.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3390250 6.34% 61.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2029247 3.80% 65.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1554755 2.91% 68.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1667292 3.12% 71.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2920236 5.46% 76.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1512043 2.83% 79.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1089860 2.04% 81.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9837053 18.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53432137 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.495757 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.376192 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16937041 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9161066 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22405812 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1030640 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3897578 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4444113 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8703 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126077551 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42669 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3897578 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18718868 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3591285 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 186478 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21552610 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5485318 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123153621 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 426233 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4596906 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1480 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143604331 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536493258 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 499981919 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 760 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 53440501 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.495648 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.375354 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16937222 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9166719 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22408314 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1029433 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3898813 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4444354 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8681 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126084070 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42675 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3898813 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18718559 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3593311 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 188330 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21554671 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5486817 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123168222 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 424808 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4599857 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1460 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143625263 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536555031 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 500037832 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 718 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36190145 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4605 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4603 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12541075 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29476574 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5520683 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2151148 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1293650 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118168195 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8471 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105168426 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 79356 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26740210 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65568590 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 253 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53432137 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.968262 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.908954 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 36211077 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4609 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4607 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12545622 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29481569 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5520172 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2131780 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1278964 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118183319 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8477 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105169429 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 79348 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26754797 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65616265 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 259 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53440501 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.967972 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.909350 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15374181 28.77% 28.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11650585 21.80% 50.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8250698 15.44% 66.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6826591 12.78% 78.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4953996 9.27% 88.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2948586 5.52% 93.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2456814 4.60% 98.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 528614 0.99% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 442072 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15384800 28.79% 28.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11651642 21.80% 50.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8259769 15.46% 66.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6813523 12.75% 78.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4933870 9.23% 88.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2968386 5.55% 93.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2461371 4.61% 98.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 525076 0.98% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 442064 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53432137 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53440501 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45737 6.91% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 340297 51.45% 58.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 275411 41.64% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 46222 6.98% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 26 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 339934 51.34% 58.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 275932 41.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74430007 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74431142 70.77% 70.77% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 10980 0.01% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued @@ -549,90 +486,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 130 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 132 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 172 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25613380 24.35% 95.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5113753 4.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25611933 24.35% 95.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5115067 4.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105168426 # Type of FU issued -system.cpu.iq.rate 1.953938 # Inst issue rate -system.cpu.iq.fu_busy_cnt 661472 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006290 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264509133 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144921601 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102693545 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 684 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 985 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 281 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105829562 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 336 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 441614 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105169429 # Type of FU issued +system.cpu.iq.rate 1.953187 # Inst issue rate +system.cpu.iq.fu_busy_cnt 662114 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006296 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 264520145 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144951370 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102696867 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 676 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 925 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 287 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105831206 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 337 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 441415 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6902608 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6756 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6465 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 775839 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6907603 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6432 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6446 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 775328 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31615 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 31602 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3897578 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 958412 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 126923 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118189357 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 310100 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29476574 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5520683 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4583 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 65855 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6705 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6465 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 447219 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 445977 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 893196 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104191790 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25292626 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 976636 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3898813 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 959371 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 127029 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118204490 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 309594 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29481569 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5520172 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4589 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 66074 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6711 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6446 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 446623 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 445838 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 892461 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104194994 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25292197 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 974435 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12691 # number of nop insts executed -system.cpu.iew.exec_refs 30349836 # number of memory reference insts executed -system.cpu.iew.exec_branches 21326689 # Number of branches executed -system.cpu.iew.exec_stores 5057210 # Number of stores executed -system.cpu.iew.exec_rate 1.935792 # Inst execution rate -system.cpu.iew.wb_sent 102971901 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102693826 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62250392 # num instructions producing a value -system.cpu.iew.wb_consumers 104309215 # num instructions consuming a value +system.cpu.iew.exec_nop 12694 # number of nop insts executed +system.cpu.iew.exec_refs 30350924 # number of memory reference insts executed +system.cpu.iew.exec_branches 21328461 # Number of branches executed +system.cpu.iew.exec_stores 5058727 # Number of stores executed +system.cpu.iew.exec_rate 1.935090 # Inst execution rate +system.cpu.iew.wb_sent 102975092 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102697154 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62242577 # num instructions producing a value +system.cpu.iew.wb_consumers 104291686 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.907962 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596787 # average fanout of values written-back +system.cpu.iew.wb_rate 1.907273 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596812 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26939334 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 26954537 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 834485 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49534559 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.842208 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.540547 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 833969 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49541688 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.841943 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.539958 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20043988 40.46% 40.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13146531 26.54% 67.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4167490 8.41% 75.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3431351 6.93% 82.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1535298 3.10% 85.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 726633 1.47% 86.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 954931 1.93% 88.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 253243 0.51% 89.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5275094 10.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20036957 40.44% 40.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13159597 26.56% 67.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4169965 8.42% 75.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3431804 6.93% 82.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1536139 3.10% 85.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 734203 1.48% 86.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 944467 1.91% 88.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 252800 0.51% 89.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5275756 10.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49534559 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 49541688 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -643,239 +580,237 @@ system.cpu.commit.branches 18732304 # Nu system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5275094 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5275756 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162446025 # The number of ROB reads -system.cpu.rob.rob_writes 240301749 # The number of ROB writes -system.cpu.timesIdled 46102 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 391706 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 162467695 # The number of ROB reads +system.cpu.rob.rob_writes 240333520 # The number of ROB writes +system.cpu.timesIdled 46195 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 404525 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated -system.cpu.cpi 0.594149 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.594149 # CPI: Total CPI of All Threads -system.cpu.ipc 1.683079 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.683079 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495606364 # number of integer regfile reads -system.cpu.int_regfile_writes 120553547 # number of integer regfile writes -system.cpu.fp_regfile_reads 143 # number of floating regfile reads -system.cpu.fp_regfile_writes 349 # number of floating regfile writes -system.cpu.misc_regfile_reads 29209842 # number of misc regfile reads +system.cpu.cpi 0.594383 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.594383 # CPI: Total CPI of All Threads +system.cpu.ipc 1.682417 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.682417 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495621667 # number of integer regfile reads +system.cpu.int_regfile_writes 120557380 # number of integer regfile writes +system.cpu.fp_regfile_reads 149 # number of floating regfile reads +system.cpu.fp_regfile_writes 361 # number of floating regfile writes +system.cpu.misc_regfile_reads 29211256 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4497544713 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 904632 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904632 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 942884 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43696 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1476 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838066 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2839542 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 47168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120990272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 121037440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 121037440 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 1888491000 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 4495994050 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 904654 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904654 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 942932 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 43718 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 43718 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1467 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838210 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2839677 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120996480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 121043392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 121043392 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 1888584500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1225749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1216499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1424096491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1423941741 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 632.652083 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13844045 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 737 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18784.321574 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 632.458088 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13844537 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 733 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18887.499318 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 632.652083 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.308912 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.308912 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 734 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 632.458088 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.308817 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.308817 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 730 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 676 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.358398 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27690815 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27690815 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13844045 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13844045 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13844045 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13844045 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13844045 # number of overall hits -system.cpu.icache.overall_hits::total 13844045 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 993 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 993 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 993 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 993 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 993 # number of overall misses -system.cpu.icache.overall_misses::total 993 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 66969998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 66969998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 66969998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 66969998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 66969998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 66969998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13845038 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13845038 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13845038 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13845038 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13845038 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13845038 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000072 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000072 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000072 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000072 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000072 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000072 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67442.092649 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67442.092649 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67442.092649 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67442.092649 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67442.092649 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67442.092649 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 594 # number of cycles access was blocked +system.cpu.icache.tags.occ_task_id_percent::1024 0.356445 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 27691778 # Number of tag accesses +system.cpu.icache.tags.data_accesses 27691778 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 13844537 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13844537 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13844537 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13844537 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13844537 # number of overall hits +system.cpu.icache.overall_hits::total 13844537 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 985 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 985 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 985 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 985 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 985 # number of overall misses +system.cpu.icache.overall_misses::total 985 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 65965748 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 65965748 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 65965748 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 65965748 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 65965748 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 65965748 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13845522 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13845522 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13845522 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13845522 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13845522 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13845522 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66970.302538 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66970.302538 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66970.302538 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66970.302538 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66970.302538 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66970.302538 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 596 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 49.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 254 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 254 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 254 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 254 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 254 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 739 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 739 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 739 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 739 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17269250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58105250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 707 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14807 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15514 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 707 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14807 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15514 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41129750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17372750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58502500 # 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number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000300 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001086 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332708 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332708 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016366 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016366 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57434.599156 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63724.169742 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59170.315682 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 793837000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 793837000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41129750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 811209750 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332540 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964529 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016359 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964529 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016359 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58175.035361 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64582.713755 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59941.086066 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53689.193837 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53689.193837 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57434.599156 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53872.830711 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54036.001933 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57434.599156 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53872.830711 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54036.001933 # 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number of replacements -system.cpu.dcache.tags.tagsinuse 3671.741279 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28144387 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 947589 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.701049 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 8006035000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3671.741279 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.896421 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.896421 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 943542 # number of replacements +system.cpu.dcache.tags.tagsinuse 3671.682953 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28143982 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 947638 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.699086 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 8008531250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3671.682953 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.896407 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.896407 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 445 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3140 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 464 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3129 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 59988391 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 59988391 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23603738 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23603738 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4532850 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4532850 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3905 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3905 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 59988388 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 59988388 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23603660 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23603660 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4532519 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4532519 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3912 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3912 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28136588 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28136588 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28136588 # number of overall hits -system.cpu.dcache.overall_hits::total 28136588 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1173883 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1173883 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 202131 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 202131 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 28136179 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28136179 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28136179 # number of overall hits +system.cpu.dcache.overall_hits::total 28136179 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1173928 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1173928 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 202462 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 202462 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1376014 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1376014 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1376014 # number of overall misses -system.cpu.dcache.overall_misses::total 1376014 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13893935229 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13893935229 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8459874583 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8459874583 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1376390 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1376390 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1376390 # number of overall misses +system.cpu.dcache.overall_misses::total 1376390 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13893768230 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13893768230 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8571552365 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8571552365 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 251500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22353809812 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22353809812 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22353809812 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22353809812 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24777621 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24777621 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 22465320595 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22465320595 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22465320595 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22465320595 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24777588 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24777588 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3912 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3912 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29512602 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29512602 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29512602 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29512602 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047377 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047377 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042689 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.042689 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001789 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001789 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046625 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046625 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046625 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046625 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.877365 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.877365 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41853.424675 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41853.424675 # average WriteReq miss latency +system.cpu.dcache.demand_accesses::cpu.data 29512569 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29512569 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29512569 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29512569 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047379 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047379 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042759 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.042759 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001786 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001786 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046637 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046637 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046637 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046637 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.281406 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.281406 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42336.598300 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42336.598300 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16245.336030 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16245.336030 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16245.336030 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16245.336030 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 154233 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16321.915006 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16321.915006 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16321.915006 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16321.915006 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 154484 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23951 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23933 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.439522 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.454853 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942884 # number of writebacks -system.cpu.dcache.writebacks::total 942884 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269973 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 269973 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158450 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158450 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 942932 # number of writebacks +system.cpu.dcache.writebacks::total 942932 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269988 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 269988 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158763 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158763 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 428423 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 428423 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 428423 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 428423 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903910 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903910 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43681 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43681 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947591 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947591 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947591 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947591 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994274260 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994274260 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1319346668 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1319346668 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11313620928 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11313620928 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11313620928 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11313620928 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036481 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036481 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009225 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009225 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032108 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032108 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032108 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032108 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.713899 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.713899 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30204.131499 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30204.131499 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11939.350340 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11939.350340 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11939.350340 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11939.350340 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 428751 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 428751 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 428751 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 428751 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903940 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903940 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43699 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43699 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947639 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947639 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947639 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947639 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994791010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994791010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1332397702 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1332397702 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11327188712 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11327188712 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11327188712 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11327188712 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036482 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036482 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009229 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009229 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032110 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032110 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032110 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032110 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.918612 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.918612 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30490.347651 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30490.347651 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11953.063046 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11953.063046 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11953.063046 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11953.063046 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 167e49074..1b324ac26 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065614 # Number of seconds simulated -sim_ticks 65613727000 # Number of ticks simulated -final_tick 65613727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065578 # Number of seconds simulated +sim_ticks 65578127500 # Number of ticks simulated +final_tick 65578127500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111661 # Simulator instruction rate (inst/s) -host_op_rate 196618 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46373693 # Simulator tick rate (ticks/s) -host_mem_usage 390932 # Number of bytes of host memory used -host_seconds 1414.89 # Real time elapsed on the host +host_inst_rate 88175 # Simulator instruction rate (inst/s) +host_op_rate 155262 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36599742 # Simulator tick rate (ticks/s) +host_mem_usage 427692 # Number of bytes of host memory used +host_seconds 1791.76 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1883136 # Number of bytes read from this memory -system.physmem.bytes_read::total 1946752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 63616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 63616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10688 # Number of bytes written to this memory -system.physmem.bytes_written::total 10688 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 994 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29424 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30418 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 167 # Number of write requests responded to by this memory -system.physmem.num_writes::total 167 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 969553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28700336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29669889 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 969553 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 969553 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 162893 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 162893 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 162893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 969553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28700336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29832782 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30419 # Number of read requests accepted -system.physmem.writeReqs 167 # Number of write requests accepted -system.physmem.readBursts 30419 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 167 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1943936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2880 # Total number of bytes read from write queue -system.physmem.bytesWritten 9856 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1946816 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10688 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 45 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 63744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1882880 # Number of bytes read from this memory +system.physmem.bytes_read::total 1946624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 63744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 63744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10368 # Number of bytes written to this memory +system.physmem.bytes_written::total 10368 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 996 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29420 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30416 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 162 # Number of write requests responded to by this memory +system.physmem.num_writes::total 162 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 972031 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28712012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29684044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 972031 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 972031 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 158101 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 158101 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 158101 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 972031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28712012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29842145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30418 # Number of read requests accepted +system.physmem.writeReqs 162 # Number of write requests accepted +system.physmem.readBursts 30418 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 162 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1942912 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3840 # Total number of bytes read from write queue +system.physmem.bytesWritten 8384 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1946752 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10368 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 60 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1928 # Per bank write bursts -system.physmem.perBankRdBursts::1 2077 # Per bank write bursts -system.physmem.perBankRdBursts::2 2029 # Per bank write bursts -system.physmem.perBankRdBursts::3 1927 # Per bank write bursts +system.physmem.perBankRdBursts::0 1927 # Per bank write bursts +system.physmem.perBankRdBursts::1 2065 # Per bank write bursts +system.physmem.perBankRdBursts::2 2026 # Per bank write bursts +system.physmem.perBankRdBursts::3 1928 # Per bank write bursts system.physmem.perBankRdBursts::4 2026 # Per bank write bursts -system.physmem.perBankRdBursts::5 1899 # Per bank write bursts -system.physmem.perBankRdBursts::6 1963 # Per bank write bursts +system.physmem.perBankRdBursts::5 1900 # Per bank write bursts +system.physmem.perBankRdBursts::6 1961 # Per bank write bursts system.physmem.perBankRdBursts::7 1862 # Per bank write bursts -system.physmem.perBankRdBursts::8 1939 # Per bank write bursts +system.physmem.perBankRdBursts::8 1940 # Per bank write bursts system.physmem.perBankRdBursts::9 1933 # Per bank write bursts system.physmem.perBankRdBursts::10 1805 # Per bank write bursts -system.physmem.perBankRdBursts::11 1795 # Per bank write bursts +system.physmem.perBankRdBursts::11 1796 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts system.physmem.perBankRdBursts::13 1800 # Per bank write bursts -system.physmem.perBankRdBursts::14 1821 # Per bank write bursts -system.physmem.perBankRdBursts::15 1778 # Per bank write bursts -system.physmem.perBankWrBursts::0 15 # Per bank write bursts -system.physmem.perBankWrBursts::1 95 # Per bank write bursts -system.physmem.perBankWrBursts::2 7 # Per bank write bursts -system.physmem.perBankWrBursts::3 11 # Per bank write bursts -system.physmem.perBankWrBursts::4 6 # Per bank write bursts +system.physmem.perBankRdBursts::14 1818 # Per bank write bursts +system.physmem.perBankRdBursts::15 1779 # Per bank write bursts +system.physmem.perBankWrBursts::0 10 # Per bank write bursts +system.physmem.perBankWrBursts::1 71 # Per bank write bursts +system.physmem.perBankWrBursts::2 3 # Per bank write bursts +system.physmem.perBankWrBursts::3 17 # Per bank write bursts +system.physmem.perBankWrBursts::4 12 # Per bank write bursts system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 12 # Per bank write bursts +system.physmem.perBankWrBursts::6 10 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts system.physmem.perBankWrBursts::9 5 # Per bank write bursts @@ -82,26 +82,26 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 65613689500 # Total gap between requests +system.physmem.totGap 65578111000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30419 # Read request sizes (log2) +system.physmem.readPktSize::6 30418 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 167 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29918 # What read queue length does an incoming req see +system.physmem.writePktSize::6 162 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29902 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 362 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -129,280 +129,243 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1275 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1527.767843 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 562.023414 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1657.823974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 326 25.57% 25.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 105 8.24% 33.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 43 3.37% 37.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 28 2.20% 39.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 22 1.73% 41.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 22 1.73% 42.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 19 1.49% 44.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 15 1.18% 45.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 17 1.33% 46.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 13 1.02% 47.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 46 3.61% 51.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 12 0.94% 52.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 8 0.63% 53.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 7 0.55% 53.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 12 0.94% 54.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 11 0.86% 55.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 8 0.63% 56.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 16 1.25% 57.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 7 0.55% 57.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 9 0.71% 58.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 9 0.71% 59.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 7 0.55% 59.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 11 0.86% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 6 0.47% 61.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 14 1.10% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 4 0.31% 62.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 9 0.71% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 6 0.47% 63.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 3 0.24% 63.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 12 0.94% 64.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 12 0.94% 65.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 8 0.63% 66.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 32 2.51% 68.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 7 0.55% 69.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 7 0.55% 70.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 5 0.39% 70.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 6 0.47% 70.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 10 0.78% 71.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 5 0.39% 72.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 7 0.55% 72.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 3 0.24% 72.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 9 0.71% 73.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 7 0.55% 74.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 6 0.47% 74.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 5 0.39% 74.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 11 0.86% 75.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 9 0.71% 76.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 7 0.55% 77.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136 5 0.39% 77.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 5 0.39% 77.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 8 0.63% 78.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 11 0.86% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 9 0.71% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 10 0.78% 80.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 12 0.94% 81.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 15 1.18% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648 10 0.78% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712 14 1.10% 84.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776 9 0.71% 85.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840 8 0.63% 86.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904 8 0.63% 86.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968 15 1.18% 88.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032 13 1.02% 89.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 11 0.86% 89.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 21 1.65% 91.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 10 0.78% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288 6 0.47% 92.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 7 0.55% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416 4 0.31% 93.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480 5 0.39% 94.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544 4 0.31% 94.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608 4 0.31% 94.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672 6 0.47% 95.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736 7 0.55% 95.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 5 0.39% 96.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864 6 0.47% 96.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928 5 0.39% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 6 0.47% 97.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 5 0.39% 97.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 6 0.47% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184 4 0.31% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248 2 0.16% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312 2 0.16% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376 2 0.16% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440 2 0.16% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568 1 0.08% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696 1 0.08% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952 1 0.08% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016 1 0.08% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080 1 0.08% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208 1 0.08% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592 1 0.08% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656 3 0.24% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1275 # Bytes accessed per row activation -system.physmem.totQLat 92483500 # Total ticks spent queuing -system.physmem.totMemAccLat 678771000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 151870000 # Total ticks spent in databus transfers -system.physmem.totBankLat 434417500 # Total ticks spent accessing banks -system.physmem.avgQLat 3044.82 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14302.28 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::22 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1672 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 934.162679 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 823.717230 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 264.349754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 77 4.61% 4.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 54 3.23% 7.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 19 1.14% 8.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 10 0.60% 9.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 11 0.66% 10.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 5 0.30% 10.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 0.36% 10.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4 0.24% 11.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1486 88.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1672 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 4327.142857 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 47.742498 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 11404.448466 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6 85.71% 85.71% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 14.29% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.714286 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.459831 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.545621 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3 42.86% 42.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3 42.86% 85.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 14.29% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7 # Writes before turning the bus around for reads +system.physmem.totQLat 98355750 # Total ticks spent queuing +system.physmem.totMemAccLat 704267000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 151790000 # Total ticks spent in databus transfers +system.physmem.totBankLat 454121250 # Total ticks spent accessing banks +system.physmem.avgQLat 3239.86 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14958.87 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 22347.11 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23198.73 # Average memory access latency per DRAM burst system.physmem.avgRdBW 29.63 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 29.67 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBW 0.13 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 29.69 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.16 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.96 # Average write queue length when enqueuing -system.physmem.readRowHits 29156 # Number of row buffer hits during reads -system.physmem.writeRowHits 97 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.99 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.08 # Row buffer hit rate for writes -system.physmem.avgGap 2145219.69 # Average gap between requests -system.physmem.pageHitRate 95.78 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.92 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 29832782 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1416 # Transaction distribution -system.membus.trans_dist::ReadResp 1415 # Transaction distribution -system.membus.trans_dist::Writeback 167 # Transaction distribution +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 15.72 # Average write queue length when enqueuing +system.physmem.readRowHits 27690 # Number of row buffer hits during reads +system.physmem.writeRowHits 93 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.21 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.41 # Row buffer hit rate for writes +system.physmem.avgGap 2144477.14 # Average gap between requests +system.physmem.pageHitRate 91.03 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.03 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 29841169 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1415 # Transaction distribution +system.membus.trans_dist::ReadResp 1412 # Transaction distribution +system.membus.trans_dist::Writeback 162 # Transaction distribution system.membus.trans_dist::ReadExReq 29003 # Transaction distribution system.membus.trans_dist::ReadExResp 29003 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61004 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61004 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61004 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1957440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1957440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 1957440 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1957440 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60995 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60995 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 60995 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1956928 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1956928 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1956928 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1956928 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 34950500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 34882000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 284209000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 284250750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 33859770 # Number of BP lookups -system.cpu.branchPred.condPredicted 33859770 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 774913 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19306649 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19202709 # Number of BTB hits +system.cpu.branchPred.lookups 33848859 # Number of BP lookups +system.cpu.branchPred.condPredicted 33848859 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 773675 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19289255 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19197917 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.461636 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5016745 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5399 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.526482 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5013789 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5382 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 131227460 # number of cpu cycles simulated +system.cpu.numCycles 131156258 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 26135230 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 182265293 # Number of instructions fetch has processed -system.cpu.fetch.Branches 33859770 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24219454 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 55459629 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5354571 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 44982751 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 314 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 26124618 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 182201449 # Number of instructions fetch has processed +system.cpu.fetch.Branches 33848859 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24211706 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 55441130 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5339784 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 44953696 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 286 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 25575393 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 166244 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 131122211 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.450609 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.313707 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 25565447 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 166050 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 131050652 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.451103 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.313857 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 78139546 59.59% 59.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1960111 1.49% 61.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2942175 2.24% 63.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3833696 2.92% 66.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7767416 5.92% 72.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4757872 3.63% 75.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2665225 2.03% 77.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1316047 1.00% 78.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 27740123 21.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 78085477 59.58% 59.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1960121 1.50% 61.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2941365 2.24% 63.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3832581 2.92% 66.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7765611 5.93% 72.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4754905 3.63% 75.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2663892 2.03% 77.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1315906 1.00% 78.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 27730794 21.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 131122211 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258024 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.388926 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36831320 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37195756 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 43906245 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8644656 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4544234 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 318852911 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 4544234 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42322552 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9742718 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7418 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 46754999 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27750290 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 315016174 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 215 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26317 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25895473 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 317188133 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 836523485 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 515056961 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 484 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131050652 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258080 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.389194 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36811004 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37176024 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 43889002 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8643749 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4530873 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 318736109 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 4530873 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42298555 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9762867 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7405 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 46737142 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27713810 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 314904511 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 214 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26056 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25855633 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 317074927 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 836235433 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 514870937 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 492 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37975386 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 483 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 481 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62628696 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 101555761 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 34778058 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 39627069 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5861390 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 311484166 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1638 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 300275524 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 89306 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32714418 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 46115217 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1193 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 131122211 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.290043 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.698539 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 37862180 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 484 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 482 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 62586078 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 101522320 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 34765778 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 39602927 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5818030 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 311370743 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1646 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 300208382 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 88815 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32598997 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 45935189 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1201 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131050652 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.290781 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.700647 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24369701 18.59% 18.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23163237 17.67% 36.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25526976 19.47% 55.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25864200 19.73% 75.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18882898 14.40% 89.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8250397 6.29% 96.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3948647 3.01% 99.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 938964 0.72% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 177191 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24364795 18.59% 18.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23214690 17.71% 36.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25426307 19.40% 55.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25814267 19.70% 75.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18862103 14.39% 89.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8277108 6.32% 96.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3959654 3.02% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 947423 0.72% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 184305 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 131122211 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131050652 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 31436 1.53% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 31474 1.53% 1.53% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available @@ -431,118 +394,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1917677 93.05% 94.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 111849 5.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1916835 93.04% 94.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 111878 5.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 31277 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 169841029 56.56% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11216 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 331 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 34 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97301451 32.40% 88.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33090186 11.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 169792966 56.56% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11226 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 332 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97287204 32.41% 88.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33085346 11.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 300275524 # Type of FU issued -system.cpu.iq.rate 2.288206 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2060962 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006864 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 733823004 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344232038 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 298020704 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 523 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 719 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 302304968 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 241 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54149706 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 300208382 # Type of FU issued +system.cpu.iq.rate 2.288937 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2060187 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006863 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 733615929 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344003056 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 297961989 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 489 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 706 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 149 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 302237064 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 228 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 54184589 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10776376 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 31265 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33344 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3338306 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10742935 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 32064 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33208 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3326026 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 3224 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8563 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 8575 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4544234 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2798212 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 162335 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 311485804 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 196342 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 101555761 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 34778058 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 4530873 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2837927 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 162034 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 311372389 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 196090 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 101522320 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 34765778 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 470 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2616 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73755 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33344 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 393170 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 428306 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 821476 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 298872684 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 96891554 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1402840 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 2524 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73590 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33208 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 392510 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 427924 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 820434 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 298810960 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 96874788 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1397422 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 129817497 # number of memory reference insts executed -system.cpu.iew.exec_branches 30820824 # Number of branches executed -system.cpu.iew.exec_stores 32925943 # Number of stores executed -system.cpu.iew.exec_rate 2.277516 # Inst execution rate -system.cpu.iew.wb_sent 298390596 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 298020860 # cumulative count of insts written-back -system.cpu.iew.wb_producers 218260006 # num instructions producing a value -system.cpu.iew.wb_consumers 296755223 # num instructions consuming a value +system.cpu.iew.exec_refs 129797042 # number of memory reference insts executed +system.cpu.iew.exec_branches 30816203 # Number of branches executed +system.cpu.iew.exec_stores 32922254 # Number of stores executed +system.cpu.iew.exec_rate 2.278282 # Inst execution rate +system.cpu.iew.wb_sent 298329085 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 297962138 # cumulative count of insts written-back +system.cpu.iew.wb_producers 218205948 # num instructions producing a value +system.cpu.iew.wb_consumers 296684532 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.271025 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.735488 # average fanout of values written-back +system.cpu.iew.wb_rate 2.271810 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.735481 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 33306189 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 33192838 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 774954 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 126577977 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.197795 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.970921 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 773712 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126519779 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.198806 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.971927 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58251121 46.02% 46.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19170530 15.15% 61.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11719383 9.26% 70.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9409192 7.43% 77.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1839491 1.45% 79.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2078967 1.64% 80.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1287907 1.02% 81.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 695737 0.55% 82.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22125649 17.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58265880 46.05% 46.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19155859 15.14% 61.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11581370 9.15% 70.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9445264 7.47% 77.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1880302 1.49% 79.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2071430 1.64% 80.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1302334 1.03% 81.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 693009 0.55% 82.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22124331 17.49% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 126577977 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126519779 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -553,100 +516,100 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. system.cpu.commit.function_calls 4237596 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22125649 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22124331 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 415950981 # The number of ROB reads -system.cpu.rob.rob_writes 627545399 # The number of ROB writes -system.cpu.timesIdled 13719 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 105249 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 415780750 # The number of ROB reads +system.cpu.rob.rob_writes 627305222 # The number of ROB writes +system.cpu.timesIdled 13712 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 105606 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.830614 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.830614 # CPI: Total CPI of All Threads -system.cpu.ipc 1.203929 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.203929 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 483744129 # number of integer regfile reads -system.cpu.int_regfile_writes 234595251 # number of integer regfile writes -system.cpu.fp_regfile_reads 141 # number of floating regfile reads -system.cpu.fp_regfile_writes 77 # number of floating regfile writes -system.cpu.cc_regfile_reads 107058970 # number of cc regfile reads -system.cpu.cc_regfile_writes 64002830 # number of cc regfile writes -system.cpu.misc_regfile_reads 191827908 # number of misc regfile reads +system.cpu.cpi 0.830163 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.830163 # CPI: Total CPI of All Threads +system.cpu.ipc 1.204583 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.204583 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 483659759 # number of integer regfile reads +system.cpu.int_regfile_writes 234542237 # number of integer regfile writes +system.cpu.fp_regfile_reads 137 # number of floating regfile reads +system.cpu.fp_regfile_writes 71 # number of floating regfile writes +system.cpu.cc_regfile_reads 107049810 # number of cc regfile reads +system.cpu.cc_regfile_writes 63997871 # number of cc regfile writes +system.cpu.misc_regfile_reads 191792946 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4042576518 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1995299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1995298 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2066887 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82323 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2022 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6220108 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6222130 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265183808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 265248512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 265248512 # Total data (bytes) +system.cpu.toL2Bus.throughput 4044284064 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1995295 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1995292 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2066395 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 82322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82322 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2024 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219602 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6221626 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265151808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 265216576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 265216576 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4139141500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 4138401000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1689999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1688749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3122002000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3121628749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 57 # number of replacements -system.cpu.icache.tags.tagsinuse 819.642194 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25574088 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1011 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25295.833828 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 55 # number of replacements +system.cpu.icache.tags.tagsinuse 821.703802 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25564150 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1012 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25261.017787 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 819.642194 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.400216 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.400216 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 954 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 821.703802 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.401223 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.401223 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 957 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 867 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.465820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51151797 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51151797 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25574088 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25574088 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25574088 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25574088 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25574088 # number of overall hits -system.cpu.icache.overall_hits::total 25574088 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1305 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1305 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1305 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1305 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1305 # number of overall misses -system.cpu.icache.overall_misses::total 1305 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 88661748 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 88661748 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 88661748 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 88661748 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 88661748 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 88661748 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25575393 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25575393 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25575393 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25575393 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25575393 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25575393 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 870 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.467285 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 51131906 # Number of tag accesses +system.cpu.icache.tags.data_accesses 51131906 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25564150 # 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Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 573 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3367 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 150351466 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 150351466 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 40071930 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40071930 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31341693 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31341693 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71413623 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71413623 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71413623 # 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number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74137428 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74137428 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74137428 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74137428 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061496 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.061496 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 74085889 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74085889 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74085889 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74085889 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061585 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.061585 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.003119 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036740 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036740 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036740 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036740 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11958.131613 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11958.131613 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28347.010453 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28347.010453 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12548.143405 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12548.143405 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12548.143405 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12548.143405 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32707 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.036773 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036773 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036773 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036773 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11958.570307 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11958.570307 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28575.157035 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28575.157035 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12556.583112 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12556.583112 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12556.583112 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12556.583112 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32689 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9497 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9492 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.443930 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.443847 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066887 # number of writebacks -system.cpu.dcache.writebacks::total 2066887 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631351 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 631351 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15843 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15843 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 647194 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 647194 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 647194 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 647194 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994395 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994395 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 2066395 # number of writebacks +system.cpu.dcache.writebacks::total 2066395 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631958 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 631958 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15832 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15832 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 647790 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 647790 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 647790 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 647790 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994389 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994389 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82216 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 82216 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076611 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076611 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076611 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076611 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21996462750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21996462750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2491650748 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2491650748 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24488113498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24488113498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24488113498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24488113498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046710 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046710 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076605 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076605 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076605 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076605 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21997400000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21997400000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2514181749 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2514181749 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24511581749 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24511581749 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24511581749 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24511581749 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046766 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046766 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002615 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002615 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028010 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028010 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028010 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028010 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11029.140541 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11029.140541 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30306.153887 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30306.153887 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11792.345075 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11792.345075 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11792.345075 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11792.345075 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028030 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028030 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028030 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028030 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11029.643665 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11029.643665 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30580.200314 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30580.200314 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11803.680406 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11803.680406 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11803.680406 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11803.680406 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 4ea8f08d5..50a810bbd 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202697 # Number of seconds simulated -sim_ticks 202696649500 # Number of ticks simulated -final_tick 202696649500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202387 # Number of seconds simulated +sim_ticks 202386636500 # Number of ticks simulated +final_tick 202386636500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 142513 # Simulator instruction rate (inst/s) -host_op_rate 160675 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57175030 # Simulator tick rate (ticks/s) -host_mem_usage 274024 # Number of bytes of host memory used -host_seconds 3545.20 # Real time elapsed on the host +host_inst_rate 118405 # Simulator instruction rate (inst/s) +host_op_rate 133495 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47430504 # Simulator tick rate (ticks/s) +host_mem_usage 317288 # Number of bytes of host memory used +host_seconds 4267.01 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 215936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9269696 # Number of bytes read from this memory -system.physmem.bytes_read::total 9485632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 215936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 215936 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6249792 # Number of bytes written to this memory -system.physmem.bytes_written::total 6249792 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3374 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144839 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148213 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97653 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97653 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1065316 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 45731866 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 46797182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1065316 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1065316 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30833228 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30833228 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30833228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1065316 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 45731866 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77630410 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148213 # Number of read requests accepted -system.physmem.writeReqs 97653 # Number of write requests accepted -system.physmem.readBursts 148213 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97653 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9481152 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4480 # Total number of bytes read from write queue -system.physmem.bytesWritten 6249152 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9485632 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6249792 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 70 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 215296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9261568 # Number of bytes read from this memory +system.physmem.bytes_read::total 9476864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 215296 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 215296 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6245824 # Number of bytes written to this memory +system.physmem.bytes_written::total 6245824 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3364 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144712 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148076 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97591 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97591 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1063786 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45761757 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 46825542 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1063786 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1063786 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30860852 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30860852 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30860852 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1063786 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45761757 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 77686394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148077 # Number of read requests accepted +system.physmem.writeReqs 97591 # Number of write requests accepted +system.physmem.readBursts 148077 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97591 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9467712 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue +system.physmem.bytesWritten 6243712 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9476928 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6245824 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 7 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9594 # Per bank write bursts -system.physmem.perBankRdBursts::1 9237 # Per bank write bursts -system.physmem.perBankRdBursts::2 9258 # Per bank write bursts -system.physmem.perBankRdBursts::3 8983 # Per bank write bursts -system.physmem.perBankRdBursts::4 9776 # Per bank write bursts -system.physmem.perBankRdBursts::5 9641 # Per bank write bursts -system.physmem.perBankRdBursts::6 9120 # Per bank write bursts -system.physmem.perBankRdBursts::7 8318 # Per bank write bursts -system.physmem.perBankRdBursts::8 8799 # Per bank write bursts -system.physmem.perBankRdBursts::9 8914 # Per bank write bursts -system.physmem.perBankRdBursts::10 8952 # Per bank write bursts -system.physmem.perBankRdBursts::11 9727 # Per bank write bursts -system.physmem.perBankRdBursts::12 9657 # Per bank write bursts -system.physmem.perBankRdBursts::13 9778 # Per bank write bursts -system.physmem.perBankRdBursts::14 8939 # Per bank write bursts -system.physmem.perBankRdBursts::15 9450 # Per bank write bursts -system.physmem.perBankWrBursts::0 6271 # Per bank write bursts -system.physmem.perBankWrBursts::1 6158 # Per bank write bursts -system.physmem.perBankWrBursts::2 6091 # Per bank write bursts -system.physmem.perBankWrBursts::3 5883 # Per bank write bursts -system.physmem.perBankWrBursts::4 6254 # Per bank write bursts -system.physmem.perBankWrBursts::5 6272 # Per bank write bursts -system.physmem.perBankWrBursts::6 6041 # Per bank write bursts -system.physmem.perBankWrBursts::7 5553 # Per bank write bursts -system.physmem.perBankWrBursts::8 5808 # Per bank write bursts -system.physmem.perBankWrBursts::9 5908 # Per bank write bursts -system.physmem.perBankWrBursts::10 5990 # Per bank write bursts -system.physmem.perBankWrBursts::11 6516 # Per bank write bursts -system.physmem.perBankWrBursts::12 6373 # Per bank write bursts -system.physmem.perBankWrBursts::13 6333 # Per bank write bursts -system.physmem.perBankWrBursts::14 6051 # Per bank write bursts -system.physmem.perBankWrBursts::15 6141 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 9 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9595 # Per bank write bursts +system.physmem.perBankRdBursts::1 9241 # Per bank write bursts +system.physmem.perBankRdBursts::2 9230 # Per bank write bursts +system.physmem.perBankRdBursts::3 8948 # Per bank write bursts +system.physmem.perBankRdBursts::4 9774 # Per bank write bursts +system.physmem.perBankRdBursts::5 9652 # Per bank write bursts +system.physmem.perBankRdBursts::6 9107 # Per bank write bursts +system.physmem.perBankRdBursts::7 8317 # Per bank write bursts +system.physmem.perBankRdBursts::8 8793 # Per bank write bursts +system.physmem.perBankRdBursts::9 8911 # Per bank write bursts +system.physmem.perBankRdBursts::10 8931 # Per bank write bursts +system.physmem.perBankRdBursts::11 9713 # Per bank write bursts +system.physmem.perBankRdBursts::12 9649 # Per bank write bursts +system.physmem.perBankRdBursts::13 9746 # Per bank write bursts +system.physmem.perBankRdBursts::14 8931 # Per bank write bursts +system.physmem.perBankRdBursts::15 9395 # Per bank write bursts +system.physmem.perBankWrBursts::0 6267 # Per bank write bursts +system.physmem.perBankWrBursts::1 6152 # Per bank write bursts +system.physmem.perBankWrBursts::2 6088 # Per bank write bursts +system.physmem.perBankWrBursts::3 5869 # Per bank write bursts +system.physmem.perBankWrBursts::4 6257 # Per bank write bursts +system.physmem.perBankWrBursts::5 6287 # Per bank write bursts +system.physmem.perBankWrBursts::6 6043 # Per bank write bursts +system.physmem.perBankWrBursts::7 5545 # Per bank write bursts +system.physmem.perBankWrBursts::8 5805 # Per bank write bursts +system.physmem.perBankWrBursts::9 5895 # Per bank write bursts +system.physmem.perBankWrBursts::10 5984 # Per bank write bursts +system.physmem.perBankWrBursts::11 6504 # Per bank write bursts +system.physmem.perBankWrBursts::12 6370 # Per bank write bursts +system.physmem.perBankWrBursts::13 6330 # Per bank write bursts +system.physmem.perBankWrBursts::14 6044 # Per bank write bursts +system.physmem.perBankWrBursts::15 6118 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 202696525000 # Total gap between requests +system.physmem.totGap 202386616500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 148213 # Read request sizes (log2) +system.physmem.readPktSize::6 148077 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97653 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97591 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138091 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 494 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -129,177 +129,177 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69151 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 227.469277 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 137.950297 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.311281 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 32073 46.38% 46.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 12750 18.44% 64.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 5391 7.80% 72.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 3340 4.83% 77.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2388 3.45% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 2364 3.42% 84.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 3443 4.98% 89.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1961 2.84% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 807 1.17% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 577 0.83% 94.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 471 0.68% 94.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 358 0.52% 95.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 272 0.39% 95.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 260 0.38% 96.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 188 0.27% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 160 0.23% 96.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 170 0.25% 96.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 142 0.21% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 124 0.18% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 152 0.22% 97.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 134 0.19% 97.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 815 1.18% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 105 0.15% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 136 0.20% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 73 0.11% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 89 0.13% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 48 0.07% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 64 0.09% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 20 0.03% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 34 0.05% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 22 0.03% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 21 0.03% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 9 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 15 0.02% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 7 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 10 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 5 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 4 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 7 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 7 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 10 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 8 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 7 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 6 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 4 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 4 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 2 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 4 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136 2 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 3 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 4 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 5 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 2 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 1 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 4 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 4 0.01% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648 3 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712 2 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776 4 0.01% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904 1 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968 1 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032 2 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 2 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 1 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 2 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 1 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416 4 0.01% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480 1 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544 3 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672 3 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 4 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864 4 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928 6 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 8 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 4 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 4 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69151 # Bytes accessed per row activation -system.physmem.totQLat 1733842500 # Total ticks spent queuing -system.physmem.totMemAccLat 4938805000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 740715000 # Total ticks spent in databus transfers -system.physmem.totBankLat 2464247500 # Total ticks spent accessing banks -system.physmem.avgQLat 11703.84 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 16634.25 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 39628 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 257.573029 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 159.018208 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 287.256707 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15558 39.26% 39.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11171 28.19% 67.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4346 10.97% 78.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2186 5.52% 83.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1365 3.44% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 780 1.97% 89.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 563 1.42% 90.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 515 1.30% 92.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3144 7.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39628 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5484 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.971554 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 384.653172 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5482 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5484 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5484 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.789570 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.450739 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 4.762634 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 3346 61.01% 61.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 1810 33.01% 94.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 182 3.32% 97.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 11 0.20% 97.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 3 0.05% 97.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 4 0.07% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 3 0.05% 97.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 1 0.02% 97.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 3 0.05% 97.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 1 0.02% 97.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.02% 97.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 12 0.22% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 29 0.53% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 19 0.35% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 8 0.15% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 7 0.13% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 7 0.13% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 8 0.15% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 9 0.16% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 6 0.11% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 4 0.07% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 3 0.05% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-65 2 0.04% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::66-67 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-73 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-77 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::90-91 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5484 # Writes before turning the bus around for reads +system.physmem.totQLat 1351646500 # Total ticks spent queuing +system.physmem.totMemAccLat 4559189000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 739665000 # Total ticks spent in databus transfers +system.physmem.totBankLat 2467877500 # Total ticks spent accessing banks +system.physmem.avgQLat 9136.88 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16682.40 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33338.09 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30819.28 # Average memory access latency per DRAM burst system.physmem.avgRdBW 46.78 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 30.83 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 46.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 30.83 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBW 30.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 46.83 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 30.86 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 8.92 # Average write queue length when enqueuing -system.physmem.readRowHits 118670 # Number of row buffer hits during reads -system.physmem.writeRowHits 57965 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.11 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.36 # Row buffer hit rate for writes -system.physmem.avgGap 824418.69 # Average gap between requests -system.physmem.pageHitRate 71.86 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.58 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 77630410 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46935 # Transaction distribution -system.membus.trans_dist::ReadResp 46935 # Transaction distribution -system.membus.trans_dist::Writeback 97653 # Transaction distribution -system.membus.trans_dist::UpgradeReq 7 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 101278 # Transaction distribution -system.membus.trans_dist::ReadExResp 101278 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394093 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 394093 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15735424 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15735424 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15735424 # Total data (bytes) +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 20.36 # Average write queue length when enqueuing +system.physmem.readRowHits 116029 # Number of row buffer hits during reads +system.physmem.writeRowHits 64903 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.51 # Row buffer hit rate for writes +system.physmem.avgGap 823821.65 # Average gap between requests +system.physmem.pageHitRate 73.69 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.51 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 77686394 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46784 # Transaction distribution +system.membus.trans_dist::ReadResp 46783 # Transaction distribution +system.membus.trans_dist::Writeback 97591 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9 # Transaction distribution +system.membus.trans_dist::UpgradeResp 9 # Transaction distribution +system.membus.trans_dist::ReadExReq 101293 # Transaction distribution +system.membus.trans_dist::ReadExResp 101293 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 393762 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15722688 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15722688 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15722688 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1083458000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1083423500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1398218993 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1396187241 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 182767812 # Number of BP lookups -system.cpu.branchPred.condPredicted 143090812 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7262422 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93142512 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87193307 # Number of BTB hits +system.cpu.branchPred.lookups 182802497 # Number of BP lookups +system.cpu.branchPred.condPredicted 143128799 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7265604 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 92710665 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87222146 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.612793 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12680291 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 116092 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.079949 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12678300 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 116271 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -385,134 +385,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 405393300 # number of cpu cycles simulated +system.cpu.numCycles 404773274 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119358761 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761461935 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182767812 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99873598 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170116443 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35667741 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 77537943 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 427 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 119371431 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761670050 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182802497 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99900446 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170159805 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35695191 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 77489066 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 40 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 409 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114511433 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2436940 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 394614975 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.164245 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.986660 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 114520254 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2435167 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 394646362 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.164609 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.986746 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 224511182 56.89% 56.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14185619 3.59% 60.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22882928 5.80% 66.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22735959 5.76% 72.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20902964 5.30% 77.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11599090 2.94% 80.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13052635 3.31% 83.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11995684 3.04% 86.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52748914 13.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 224499175 56.89% 56.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14180048 3.59% 60.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22900330 5.80% 66.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22746018 5.76% 72.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20904181 5.30% 77.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11597078 2.94% 80.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13062660 3.31% 83.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11996924 3.04% 86.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52759948 13.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 394614975 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.450841 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.878329 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129045860 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 73029235 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158776788 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6235766 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27527326 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26113836 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76704 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825433505 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 295928 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27527326 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135634392 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10115343 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 47882338 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158241210 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15214366 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800503248 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1357 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3055222 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8963577 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 323 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954180101 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3518022066 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3236814887 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 394646362 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.451617 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.881720 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129065441 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 72977589 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158843318 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6208520 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27551494 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26113840 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76933 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825615862 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 295408 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27551494 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135663599 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10124037 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 47858907 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158270703 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15177622 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800676203 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1362 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3041401 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8927839 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 380 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954380743 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3518821037 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3237543722 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 408 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 287927810 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2293035 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2293033 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41823481 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170244853 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73468690 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28584671 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15947575 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 754970143 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775446 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665247715 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1368678 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187299729 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479807189 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797814 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 394614975 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.685815 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.734907 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 288128452 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2293069 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2293066 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41767697 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170285712 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73492930 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28608200 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15804502 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 755130380 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775454 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665331830 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1375167 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187454297 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 480174835 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797822 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 394646362 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.685894 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.735410 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 139112608 35.25% 35.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69963718 17.73% 52.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71480339 18.11% 71.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53412881 13.54% 84.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31169155 7.90% 92.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15993671 4.05% 96.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8759011 2.22% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2903101 0.74% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1820491 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 139160941 35.26% 35.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69972049 17.73% 52.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71433490 18.10% 71.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53381143 13.53% 84.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31203736 7.91% 92.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16006372 4.06% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8742132 2.22% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2922216 0.74% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1824283 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 394614975 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 394646362 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 480625 5.03% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6529255 68.28% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2553152 26.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 481604 5.01% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6543314 68.07% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2587932 26.92% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447743251 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383309 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447808389 67.31% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383403 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued @@ -540,84 +540,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153363071 23.05% 90.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63757987 9.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153377795 23.05% 90.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63762146 9.58% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665247715 # Type of FU issued -system.cpu.iq.rate 1.640993 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9563032 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014375 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1736041890 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 946851577 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 645982069 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 225 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 304 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 665331830 # Type of FU issued +system.cpu.iq.rate 1.643715 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9612850 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014448 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1736297816 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 947166381 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 646062448 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 674810634 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 674944567 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8546846 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 8567764 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44215298 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 41270 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810207 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16608213 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44256157 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 42344 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810357 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16632453 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19520 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8279 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19504 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8568 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27527326 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5271033 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 384981 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760303523 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1119045 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170244853 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73468690 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286904 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 219731 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11453 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810207 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4335544 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4001823 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8337367 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655831134 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150081839 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9416581 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27551494 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5275843 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 386509 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760464256 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1125230 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170285712 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73492930 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286912 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 220350 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11309 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810357 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4338774 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4002387 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8341161 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655913475 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150097155 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9418355 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1557934 # number of nop insts executed -system.cpu.iew.exec_refs 212547196 # number of memory reference insts executed -system.cpu.iew.exec_branches 138487054 # Number of branches executed -system.cpu.iew.exec_stores 62465357 # Number of stores executed -system.cpu.iew.exec_rate 1.617765 # Inst execution rate -system.cpu.iew.wb_sent 650951989 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 645982085 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374676308 # num instructions producing a value -system.cpu.iew.wb_consumers 646230138 # num instructions consuming a value +system.cpu.iew.exec_nop 1558422 # number of nop insts executed +system.cpu.iew.exec_refs 212571042 # number of memory reference insts executed +system.cpu.iew.exec_branches 138499517 # Number of branches executed +system.cpu.iew.exec_stores 62473887 # Number of stores executed +system.cpu.iew.exec_rate 1.620447 # Inst execution rate +system.cpu.iew.wb_sent 651035258 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 646062464 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374747617 # num instructions producing a value +system.cpu.iew.wb_consumers 646369396 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.593470 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579788 # average fanout of values written-back +system.cpu.iew.wb_rate 1.596109 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579773 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189364408 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189524475 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7188399 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 367087649 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.555400 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.230509 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7191502 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 367094868 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.555370 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.229648 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 159393543 43.42% 43.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98511772 26.84% 70.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33830447 9.22% 79.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18783252 5.12% 84.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16176645 4.41% 89.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7442765 2.03% 91.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6952611 1.89% 92.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3163238 0.86% 93.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22833376 6.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 159372239 43.41% 43.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98509322 26.83% 70.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33822268 9.21% 79.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18793314 5.12% 84.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16194287 4.41% 88.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7448885 2.03% 91.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7004810 1.91% 92.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3214010 0.88% 93.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22735733 6.19% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 367087649 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 367094868 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -628,239 +628,243 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22833376 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22735733 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1104579710 # The number of ROB reads -system.cpu.rob.rob_writes 1548313166 # The number of ROB writes -system.cpu.timesIdled 328667 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10778325 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1104844639 # The number of ROB reads +system.cpu.rob.rob_writes 1548657613 # The number of ROB writes +system.cpu.timesIdled 329536 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10126912 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.802381 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.802381 # CPI: Total CPI of All Threads -system.cpu.ipc 1.246290 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.246290 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3058357965 # number of integer regfile reads -system.cpu.int_regfile_writes 751931601 # number of integer regfile writes +system.cpu.cpi 0.801154 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.801154 # CPI: Total CPI of All Threads +system.cpu.ipc 1.248199 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.248199 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3058738251 # number of integer regfile reads +system.cpu.int_regfile_writes 752038270 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 237823379 # number of misc regfile reads +system.cpu.misc_regfile_reads 237846973 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.throughput 733902057 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 864632 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 864632 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1110906 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 71 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 71 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 348829 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 348829 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33629 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504262 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3537891 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1073600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147680832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148754432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148754432 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 5056 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2273126497 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 735012008 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 864661 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 864660 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1110883 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 79 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 79 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 348779 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 348779 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33728 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504101 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3537829 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1076352 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147674432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148750784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148750784 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 5824 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2273084998 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 25848480 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 25918735 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1823961981 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1823048732 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 14927 # number of replacements -system.cpu.icache.tags.tagsinuse 1097.546967 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 114490465 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16785 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6820.998808 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 14973 # number of replacements +system.cpu.icache.tags.tagsinuse 1095.994633 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 114499162 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16828 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6804.086166 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1097.546967 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.535912 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.535912 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 229039718 # Number of tag accesses -system.cpu.icache.tags.data_accesses 229039718 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 114490465 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114490465 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114490465 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114490465 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114490465 # number of overall hits -system.cpu.icache.overall_hits::total 114490465 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 20967 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 20967 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 20967 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 20967 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 20967 # number of overall misses -system.cpu.icache.overall_misses::total 20967 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 566965977 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 566965977 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 566965977 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 566965977 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 566965977 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 566965977 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114511432 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114511432 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114511432 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114511432 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114511432 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114511432 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000183 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000183 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000183 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000183 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000183 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000183 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27040.872657 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27040.872657 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27040.872657 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27040.872657 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27040.872657 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27040.872657 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1029 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1095.994633 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.535154 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.535154 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1855 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 79 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 300 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.905762 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 229057415 # Number of tag accesses +system.cpu.icache.tags.data_accesses 229057415 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 114499162 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114499162 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114499162 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114499162 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114499162 # number of overall hits +system.cpu.icache.overall_hits::total 114499162 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21091 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21091 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21091 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21091 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21091 # number of overall misses +system.cpu.icache.overall_misses::total 21091 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 555853234 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 555853234 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 555853234 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 555853234 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 555853234 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 555853234 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114520253 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114520253 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114520253 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114520253 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114520253 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114520253 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26354.996634 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 26354.996634 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 26354.996634 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 26354.996634 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 26354.996634 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 26354.996634 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 663 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 85.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 60.272727 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4113 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4113 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4113 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4113 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4113 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4113 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16854 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16854 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16854 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16854 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16854 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16854 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 413760769 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 413760769 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 413760769 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 413760769 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 413760769 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 413760769 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000147 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000147 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000147 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000147 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000147 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000147 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24549.707429 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24549.707429 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24549.707429 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24549.707429 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24549.707429 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24549.707429 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4181 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4181 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4181 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4181 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4181 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4181 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16910 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16910 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16910 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16910 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16910 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16910 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 402050014 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 402050014 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 402050014 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 402050014 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 402050014 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 402050014 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23775.873093 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23775.873093 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23775.873093 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23775.873093 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23775.873093 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23775.873093 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 115464 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27088.798678 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1780777 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 146712 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.137910 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 102535173000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23012.092696 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 360.882153 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3715.823828 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.702273 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011013 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.113398 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.826685 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31248 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2200 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7669 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21308 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953613 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 19090479 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 19090479 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 13395 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 804194 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 817589 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1110906 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1110906 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 66 # 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number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 80008 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6013621251 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6013621251 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 207676000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8834690751 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9042366751 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 207676000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8834690751 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9042366751 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200071 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051217 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054112 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.101266 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.101266 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290425 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290425 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200071 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120944 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.122041 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200071 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120944 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.122041 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61716.493314 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64973.156913 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64738.917151 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61860.441370 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61860.441370 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65125.074096 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63585.445433 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63620.493891 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65125.074096 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63585.445433 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63620.493891 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59367.990710 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59367.990710 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61716.493314 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61049.738109 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61064.889795 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61716.493314 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61049.738109 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61064.889795 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1192511 # number of replacements -system.cpu.dcache.tags.tagsinuse 4057.506365 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 190177939 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1196607 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 158.930993 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1192434 # number of replacements +system.cpu.dcache.tags.tagsinuse 4057.447359 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 190168921 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1196530 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 158.933684 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4256684250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4057.506365 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.990602 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.990602 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4057.447359 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.990588 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.990588 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2352 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1686 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2348 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1681 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 391455847 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 391455847 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 136212044 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136212044 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50988351 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50988351 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488804 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488804 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 391443552 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 391443552 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 136203085 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136203085 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50988219 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50988219 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488837 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488837 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187200395 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187200395 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187200395 # number of overall hits -system.cpu.dcache.overall_hits::total 187200395 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1700889 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1700889 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3250955 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3250955 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 36 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 36 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4951844 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4951844 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4951844 # number of overall misses -system.cpu.dcache.overall_misses::total 4951844 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29691567711 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29691567711 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 72513714730 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 72513714730 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 595500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 595500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102205282441 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102205282441 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102205282441 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102205282441 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137912933 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137912933 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 187191304 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187191304 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187191304 # number of overall hits +system.cpu.dcache.overall_hits::total 187191304 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1703703 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1703703 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3251087 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3251087 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 39 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 39 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 4954790 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4954790 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4954790 # number of overall misses +system.cpu.dcache.overall_misses::total 4954790 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29263316713 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29263316713 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 70545580472 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 70545580472 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 635500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 635500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 99808897185 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 99808897185 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 99808897185 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 99808897185 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137906788 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137906788 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488840 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488840 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488876 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488876 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192152239 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192152239 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192152239 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192152239 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012333 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012333 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059937 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059937 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025770 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025770 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025770 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025770 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17456.499343 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17456.499343 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22305.357881 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 22305.357881 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16541.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16541.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20639.842944 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20639.842944 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20639.842944 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20639.842944 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17574 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 52604 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1663 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.567649 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 79.582451 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 192146094 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192146094 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192146094 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192146094 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012354 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012354 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059940 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059940 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000026 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000026 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025787 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025787 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025787 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025787 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17176.301687 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17176.301687 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21699.074947 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21699.074947 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16294.871795 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16294.871795 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20143.920769 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20143.920769 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20143.920769 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20143.920769 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 17635 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 54424 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1686 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 666 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.459668 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 81.717718 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1110906 # number of writebacks -system.cpu.dcache.writebacks::total 1110906 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 852565 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 852565 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902601 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2902601 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 36 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 36 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3755166 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3755166 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3755166 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3755166 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848324 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848324 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348354 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348354 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196678 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196678 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196678 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196678 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12420423026 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12420423026 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10423297989 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10423297989 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22843721015 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22843721015 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22843721015 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22843721015 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1110883 # number of writebacks +system.cpu.dcache.writebacks::total 1110883 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 855409 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 855409 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902772 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2902772 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 39 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 39 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3758181 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3758181 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3758181 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3758181 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848294 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848294 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348315 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348315 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196609 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196609 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196609 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196609 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12295329526 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12295329526 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10170217738 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10170217738 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22465547264 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22465547264 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22465547264 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22465547264 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006151 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006151 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006422 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006422 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14641.131249 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14641.131249 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29921.568258 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29921.568258 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19089.279668 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19089.279668 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19089.279668 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19089.279668 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14494.184240 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14494.184240 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29198.334088 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29198.334088 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18774.342550 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18774.342550 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18774.342550 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18774.342550 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 7553b7709..a5895db0e 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.459119 # Number of seconds simulated -sim_ticks 459118646000 # Number of ticks simulated -final_tick 459118646000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.458346 # Number of seconds simulated +sim_ticks 458345683000 # Number of ticks simulated +final_tick 458345683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66655 # Simulator instruction rate (inst/s) -host_op_rate 123253 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37009979 # Simulator tick rate (ticks/s) -host_mem_usage 397004 # Number of bytes of host memory used -host_seconds 12405.27 # Real time elapsed on the host +host_inst_rate 77949 # Simulator instruction rate (inst/s) +host_op_rate 144137 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43207948 # Simulator tick rate (ticks/s) +host_mem_usage 382980 # Number of bytes of host memory used +host_seconds 10607.90 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 202048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24472064 # Number of bytes read from this memory -system.physmem.bytes_read::total 24674112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202048 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18787264 # Number of bytes written to this memory -system.physmem.bytes_written::total 18787264 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3157 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382376 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385533 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293551 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293551 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 440078 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53302266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53742344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 440078 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440078 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 40920281 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 40920281 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 40920281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 440078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53302266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 94662625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385533 # Number of read requests accepted -system.physmem.writeReqs 293551 # Number of write requests accepted -system.physmem.readBursts 385533 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 293551 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24663104 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11008 # Total number of bytes read from write queue -system.physmem.bytesWritten 18787008 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24674112 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18787264 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 172 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 201344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24476224 # Number of bytes read from this memory +system.physmem.bytes_read::total 24677568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 201344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 201344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18790080 # Number of bytes written to this memory +system.physmem.bytes_written::total 18790080 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3146 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382441 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385587 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293595 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293595 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 439284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53401232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53840516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 439284 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 439284 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 40995434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 40995434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 40995434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 439284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53401232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 94835949 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385587 # Number of read requests accepted +system.physmem.writeReqs 293595 # Number of write requests accepted +system.physmem.readBursts 385587 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 293595 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24655680 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21888 # Total number of bytes read from write queue +system.physmem.bytesWritten 18787904 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24677568 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18790080 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 342 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 134286 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24058 # Per bank write bursts -system.physmem.perBankRdBursts::1 26419 # Per bank write bursts -system.physmem.perBankRdBursts::2 24669 # Per bank write bursts -system.physmem.perBankRdBursts::3 24489 # Per bank write bursts -system.physmem.perBankRdBursts::4 23234 # Per bank write bursts -system.physmem.perBankRdBursts::5 23657 # Per bank write bursts -system.physmem.perBankRdBursts::6 24395 # Per bank write bursts -system.physmem.perBankRdBursts::7 24194 # Per bank write bursts -system.physmem.perBankRdBursts::8 23609 # Per bank write bursts -system.physmem.perBankRdBursts::9 23827 # Per bank write bursts -system.physmem.perBankRdBursts::10 24795 # Per bank write bursts -system.physmem.perBankRdBursts::11 24049 # Per bank write bursts -system.physmem.perBankRdBursts::12 23230 # Per bank write bursts -system.physmem.perBankRdBursts::13 22964 # Per bank write bursts -system.physmem.perBankRdBursts::14 23781 # Per bank write bursts -system.physmem.perBankRdBursts::15 23991 # Per bank write bursts -system.physmem.perBankWrBursts::0 18530 # Per bank write bursts -system.physmem.perBankWrBursts::1 19817 # Per bank write bursts -system.physmem.perBankWrBursts::2 18937 # Per bank write bursts -system.physmem.perBankWrBursts::3 18901 # Per bank write bursts -system.physmem.perBankWrBursts::4 18031 # Per bank write bursts -system.physmem.perBankWrBursts::5 18405 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 137451 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 23999 # Per bank write bursts +system.physmem.perBankRdBursts::1 26321 # Per bank write bursts +system.physmem.perBankRdBursts::2 24635 # Per bank write bursts +system.physmem.perBankRdBursts::3 24488 # Per bank write bursts +system.physmem.perBankRdBursts::4 23208 # Per bank write bursts +system.physmem.perBankRdBursts::5 23662 # Per bank write bursts +system.physmem.perBankRdBursts::6 24431 # Per bank write bursts +system.physmem.perBankRdBursts::7 24245 # Per bank write bursts +system.physmem.perBankRdBursts::8 23683 # Per bank write bursts +system.physmem.perBankRdBursts::9 23822 # Per bank write bursts +system.physmem.perBankRdBursts::10 24823 # Per bank write bursts +system.physmem.perBankRdBursts::11 24044 # Per bank write bursts +system.physmem.perBankRdBursts::12 23228 # Per bank write bursts +system.physmem.perBankRdBursts::13 22920 # Per bank write bursts +system.physmem.perBankRdBursts::14 23793 # Per bank write bursts +system.physmem.perBankRdBursts::15 23943 # Per bank write bursts +system.physmem.perBankWrBursts::0 18539 # Per bank write bursts +system.physmem.perBankWrBursts::1 19811 # Per bank write bursts +system.physmem.perBankWrBursts::2 18919 # Per bank write bursts +system.physmem.perBankWrBursts::3 18907 # Per bank write bursts +system.physmem.perBankWrBursts::4 18016 # Per bank write bursts +system.physmem.perBankWrBursts::5 18404 # Per bank write bursts system.physmem.perBankWrBursts::6 18977 # Per bank write bursts -system.physmem.perBankWrBursts::7 18937 # Per bank write bursts -system.physmem.perBankWrBursts::8 18537 # Per bank write bursts -system.physmem.perBankWrBursts::9 18113 # Per bank write bursts -system.physmem.perBankWrBursts::10 18820 # Per bank write bursts -system.physmem.perBankWrBursts::11 17706 # Per bank write bursts +system.physmem.perBankWrBursts::7 18938 # Per bank write bursts +system.physmem.perBankWrBursts::8 18573 # Per bank write bursts +system.physmem.perBankWrBursts::9 18106 # Per bank write bursts +system.physmem.perBankWrBursts::10 18839 # Per bank write bursts +system.physmem.perBankWrBursts::11 17716 # Per bank write bursts system.physmem.perBankWrBursts::12 17343 # Per bank write bursts -system.physmem.perBankWrBursts::13 16958 # Per bank write bursts -system.physmem.perBankWrBursts::14 17714 # Per bank write bursts -system.physmem.perBankWrBursts::15 17821 # Per bank write bursts +system.physmem.perBankWrBursts::13 16932 # Per bank write bursts +system.physmem.perBankWrBursts::14 17725 # Per bank write bursts +system.physmem.perBankWrBursts::15 17816 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 459118532000 # Total gap between requests +system.physmem.totGap 458345657000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 385533 # Read request sizes (log2) +system.physmem.readPktSize::6 385587 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 293551 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380740 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293595 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 380584 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 291 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -129,327 +129,303 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 13202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 13291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 13315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 13330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 13327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 13318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 13375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 13367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 13375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 13396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 13419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 13353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 13357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 13368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 13341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 13319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 13314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 13315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 13324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 13309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 13490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 13282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147556 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 294.463932 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 155.686360 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 443.719039 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 63845 43.27% 43.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 27907 18.91% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 12368 8.38% 70.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 7167 4.86% 75.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 4813 3.26% 78.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3571 2.42% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 2697 1.83% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2226 1.51% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 1892 1.28% 85.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 1575 1.07% 86.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1962 1.33% 88.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1193 0.81% 88.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 1191 0.81% 89.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 1073 0.73% 90.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 940 0.64% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 929 0.63% 91.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 1014 0.69% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1122 0.76% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 1123 0.76% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 892 0.60% 94.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 768 0.52% 95.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 5249 3.56% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 304 0.21% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 220 0.15% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 176 0.12% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 127 0.09% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 88 0.06% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 94 0.06% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 86 0.06% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 56 0.04% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 55 0.04% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 48 0.03% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 43 0.03% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 26 0.02% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 35 0.02% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 32 0.02% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 24 0.02% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 27 0.02% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 18 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 18 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 24 0.02% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 20 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 23 0.02% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 17 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 18 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 20 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 16 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 19 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136 14 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 17 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 12 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 19 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 5 0.00% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 18 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 12 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 8 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648 14 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712 10 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776 15 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840 9 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904 9 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968 11 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032 10 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 12 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 14 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 20 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288 31 0.02% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416 10 0.01% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480 3 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544 5 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608 2 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672 6 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736 6 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 2 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864 4 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928 2 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 4 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 3 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 3 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184 4 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312 6 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440 5 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504 3 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568 3 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632 2 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696 4 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760 6 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824 2 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888 9 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952 3 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016 11 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080 4 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208 3 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336 3 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147556 # Bytes accessed per row activation -system.physmem.totQLat 3828283250 # Total ticks spent queuing -system.physmem.totMemAccLat 12084928250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1926805000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6329840000 # Total ticks spent accessing banks -system.physmem.avgQLat 9934.28 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 16425.74 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 16668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 16965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 16912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 16903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 21550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 22491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 16827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 96485 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 354.073856 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 206.339683 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 360.153261 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 30862 31.99% 31.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 25245 26.16% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9104 9.44% 67.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4981 5.16% 72.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3508 3.64% 76.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2549 2.64% 79.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1904 1.97% 81.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1721 1.78% 82.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16611 17.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 96485 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 16638 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.153564 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 214.001392 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 16625 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 16638 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 16638 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.644008 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.412925 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.984420 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 15809 95.02% 95.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 568 3.41% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 13 0.08% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 7 0.04% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 5 0.03% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 61 0.37% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 106 0.64% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 27 0.16% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 20 0.12% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.04% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 16638 # Writes before turning the bus around for reads +system.physmem.totQLat 2817376000 # Total ticks spent queuing +system.physmem.totMemAccLat 11128592250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1926225000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6384991250 # Total ticks spent accessing banks +system.physmem.avgQLat 7313.21 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16573.85 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31360.02 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 53.72 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 40.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 53.74 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 40.92 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28887.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 53.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 40.99 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 53.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 41.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.74 # Data bus utilization in percentage system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.64 # Average write queue length when enqueuing -system.physmem.readRowHits 326971 # Number of row buffer hits during reads -system.physmem.writeRowHits 204381 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.85 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 69.62 # Row buffer hit rate for writes -system.physmem.avgGap 676085.04 # Average gap between requests -system.physmem.pageHitRate 78.27 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 5.79 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 94662625 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 178699 # Transaction distribution -system.membus.trans_dist::ReadResp 178699 # Transaction distribution -system.membus.trans_dist::Writeback 293551 # Transaction distribution -system.membus.trans_dist::UpgradeReq 134286 # Transaction distribution -system.membus.trans_dist::UpgradeResp 134286 # Transaction distribution -system.membus.trans_dist::ReadExReq 206834 # Transaction distribution -system.membus.trans_dist::ReadExResp 206834 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1333189 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1333189 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1333189 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43461376 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43461376 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43461376 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43461376 # Total data (bytes) +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.28 # Average write queue length when enqueuing +system.physmem.readRowHits 317177 # Number of row buffer hits during reads +system.physmem.writeRowHits 216322 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.33 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.68 # Row buffer hit rate for writes +system.physmem.avgGap 674849.54 # Average gap between requests +system.physmem.pageHitRate 78.59 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 5.94 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 94835949 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 178789 # Transaction distribution +system.membus.trans_dist::ReadResp 178789 # Transaction distribution +system.membus.trans_dist::Writeback 293595 # Transaction distribution +system.membus.trans_dist::UpgradeReq 137451 # Transaction distribution +system.membus.trans_dist::UpgradeResp 137451 # Transaction distribution +system.membus.trans_dist::ReadExReq 206798 # Transaction distribution +system.membus.trans_dist::ReadExResp 206798 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1339671 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1339671 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1339671 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43467648 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43467648 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43467648 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43467648 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3389612000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3393086500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3899599974 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3901807065 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 205593718 # Number of BP lookups -system.cpu.branchPred.condPredicted 205593718 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9903647 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 117157105 # Number of BTB lookups -system.cpu.branchPred.BTBHits 114691543 # Number of BTB hits +system.cpu.branchPred.lookups 205603387 # Number of BP lookups +system.cpu.branchPred.condPredicted 205603387 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9902113 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 117080162 # Number of BTB lookups +system.cpu.branchPred.BTBHits 114702381 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.895508 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25059747 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1804675 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.969100 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25060949 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1802781 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 918398587 # number of cpu cycles simulated +system.cpu.numCycles 916852867 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 167393029 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1131661435 # Number of instructions fetch has processed -system.cpu.fetch.Branches 205593718 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 139751290 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 352253008 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 71076779 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 305103735 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 48807 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 255424 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 162015300 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2531137 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 885975121 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.376486 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.323818 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 167425421 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1131697501 # Number of instructions fetch has processed +system.cpu.fetch.Branches 205603387 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 139763330 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 352285469 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 71105811 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 304521969 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 48109 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 252946 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 162022121 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2522560 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 885484431 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.378017 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.324314 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 537792455 60.70% 60.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23395629 2.64% 63.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25258320 2.85% 66.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27887801 3.15% 69.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 17745441 2.00% 71.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 22910084 2.59% 73.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 29420868 3.32% 77.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 26641357 3.01% 80.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174923166 19.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 537271116 60.68% 60.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23397088 2.64% 63.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25262126 2.85% 66.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27864383 3.15% 69.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 17763945 2.01% 71.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 22926561 2.59% 73.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 29429676 3.32% 77.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 26640012 3.01% 80.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174929524 19.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 885975121 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.223861 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.232212 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 222542151 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 260234378 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 295346908 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 46930608 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 60921076 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2071264981 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 885484431 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.224249 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.234328 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 222585266 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 259638923 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 295357907 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 46951879 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 60950456 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2071410922 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 60921076 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 256051169 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 115707666 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 18212 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 306637897 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 146639101 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2035099231 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19841 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 24966361 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 106369922 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2138037437 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5150524594 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3273371991 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 41733 # Number of floating rename lookups +system.cpu.rename.SquashCycles 60950456 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 256114538 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 114960463 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17780 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 306643544 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 146797650 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2035254884 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19108 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 24985336 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 106570240 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2138126742 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5150804980 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3273565222 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40421 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 523996583 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1255 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1189 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 346554163 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 495859665 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194411587 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 195293101 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 54696349 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1975355646 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13955 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1772015968 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 483793 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 441457587 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 735091170 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13403 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 885975121 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.000074 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.882925 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 524085888 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1238 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1169 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 346813798 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 495843290 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 194454992 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 195400842 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 54863800 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1975546158 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 13200 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1772179882 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 484148 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 441719386 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 735183548 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 12648 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 885484431 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.001368 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.882860 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 269258289 30.39% 30.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151881714 17.14% 47.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 137407528 15.51% 63.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131753954 14.87% 77.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91677002 10.35% 88.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 55986071 6.32% 94.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34414851 3.88% 98.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11835829 1.34% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1759883 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 268514596 30.32% 30.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 152316057 17.20% 47.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 137257157 15.50% 63.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131678995 14.87% 77.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91673992 10.35% 88.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 56016548 6.33% 94.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34412328 3.89% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11858214 1.34% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1756544 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 885975121 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 885484431 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4932504 32.46% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7653540 50.37% 82.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2609071 17.17% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4914226 32.32% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7684512 50.55% 82.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2604414 17.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2623104 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1165669250 65.78% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 353281 0.02% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880805 0.22% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 50 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2627261 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1165804408 65.78% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 352994 0.02% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880826 0.22% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 67 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued @@ -475,84 +451,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 429265174 24.22% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170224304 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 429279214 24.22% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170235112 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1772015968 # Type of FU issued -system.cpu.iq.rate 1.929463 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15195115 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008575 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4445670799 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2417030484 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1744778187 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15166 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 51932 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3516 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1784580890 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7089 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 172585161 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1772179882 # Type of FU issued +system.cpu.iq.rate 1.932895 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15203152 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008579 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4445517936 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2417485915 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1744947174 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 13559 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 50440 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3261 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1784749273 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 6500 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 172700004 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 111758592 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 386790 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 327293 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45251401 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 111742246 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 386565 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 329489 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45294806 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 14735 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 596 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 14850 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 595 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 60921076 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 68026001 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7165661 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1975369601 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 781836 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 495860749 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 194411587 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3446 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4462926 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 83952 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 327293 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5902213 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4423139 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10325352 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1752891418 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 424133385 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19124550 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 60950456 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 66921774 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7152270 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1975559358 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 792714 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 495844403 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 194454992 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3102 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4466928 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 83631 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 329489 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5907148 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4425214 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10332362 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1753055321 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 424140880 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19124561 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590919865 # number of memory reference insts executed -system.cpu.iew.exec_branches 167459905 # Number of branches executed -system.cpu.iew.exec_stores 166786480 # Number of stores executed -system.cpu.iew.exec_rate 1.908639 # Inst execution rate -system.cpu.iew.wb_sent 1749637243 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1744781703 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1324895228 # num instructions producing a value -system.cpu.iew.wb_consumers 1945542332 # num instructions consuming a value +system.cpu.iew.exec_refs 590933103 # number of memory reference insts executed +system.cpu.iew.exec_branches 167483673 # Number of branches executed +system.cpu.iew.exec_stores 166792223 # Number of stores executed +system.cpu.iew.exec_rate 1.912036 # Inst execution rate +system.cpu.iew.wb_sent 1749807321 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1744950435 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1324909698 # num instructions producing a value +system.cpu.iew.wb_consumers 1945755632 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.899809 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.680990 # average fanout of values written-back +system.cpu.iew.wb_rate 1.903196 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.680923 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 446410033 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 446599399 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9933076 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 825054045 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.853198 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.435700 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9930890 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 824533975 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.854367 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.435928 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 333030107 40.36% 40.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193187610 23.42% 63.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 63292581 7.67% 71.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92556987 11.22% 82.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24936073 3.02% 85.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27503514 3.33% 89.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9360719 1.13% 90.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11372840 1.38% 91.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69813614 8.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 332362619 40.31% 40.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193345604 23.45% 63.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 63386723 7.69% 71.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92493757 11.22% 82.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24926721 3.02% 85.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27481357 3.33% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9323499 1.13% 90.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11375843 1.38% 91.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69837852 8.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 825054045 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 824533975 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -563,245 +539,245 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions. system.cpu.commit.function_calls 17673145 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69813614 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69837852 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2730639165 # The number of ROB reads -system.cpu.rob.rob_writes 4011880242 # The number of ROB writes -system.cpu.timesIdled 3355901 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32423466 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2730284223 # The number of ROB reads +system.cpu.rob.rob_writes 4012285085 # The number of ROB writes +system.cpu.timesIdled 3361589 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 31368436 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.110683 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.110683 # CPI: Total CPI of All Threads -system.cpu.ipc 0.900347 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.900347 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2716194969 # number of integer regfile reads -system.cpu.int_regfile_writes 1420370160 # number of integer regfile writes -system.cpu.fp_regfile_reads 3538 # number of floating regfile reads -system.cpu.fp_regfile_writes 76 # number of floating regfile writes -system.cpu.cc_regfile_reads 597194910 # number of cc regfile reads -system.cpu.cc_regfile_writes 405402169 # number of cc regfile writes -system.cpu.misc_regfile_reads 964642327 # number of misc regfile reads +system.cpu.cpi 1.108814 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.108814 # CPI: Total CPI of All Threads +system.cpu.ipc 0.901865 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.901865 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2716343034 # number of integer regfile reads +system.cpu.int_regfile_writes 1420512883 # number of integer regfile writes +system.cpu.fp_regfile_reads 3304 # number of floating regfile reads +system.cpu.fp_regfile_writes 92 # number of floating regfile writes +system.cpu.cc_regfile_reads 597249207 # number of cc regfile reads +system.cpu.cc_regfile_writes 405429285 # number of cc regfile writes +system.cpu.misc_regfile_reads 964722506 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 698022201 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1904986 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1904985 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2330749 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 135709 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 135709 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771688 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771688 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 149463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7670245 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7819708 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 436992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311346432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 311783424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 311783424 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 8691584 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4905579957 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 699635153 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1908088 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1908087 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2330726 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 138856 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 138856 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771730 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771730 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152619 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7676496 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7829115 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 437120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311344320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 311781440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 311781440 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 8893312 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4908984370 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 214416742 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 219136241 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3952860716 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3952027365 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 5299 # number of replacements -system.cpu.icache.tags.tagsinuse 1035.961197 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 161868793 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6888 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23500.115128 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5320 # number of replacements +system.cpu.icache.tags.tagsinuse 1037.745275 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 161872406 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6896 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 23473.376740 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1035.961197 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.505840 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.505840 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1589 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1037.745275 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506712 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506712 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1576 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 245 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1238 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.775879 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 324173234 # Number of tag accesses -system.cpu.icache.tags.data_accesses 324173234 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 161870665 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161870665 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161870665 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161870665 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161870665 # number of overall hits -system.cpu.icache.overall_hits::total 161870665 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 144635 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 144635 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 144635 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 144635 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 144635 # number of overall misses -system.cpu.icache.overall_misses::total 144635 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 939845985 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 939845985 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 939845985 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 939845985 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 939845985 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 939845985 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162015300 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162015300 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162015300 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162015300 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162015300 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162015300 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000893 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000893 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000893 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000893 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000893 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000893 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6498.053618 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6498.053618 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6498.053618 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6498.053618 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6498.053618 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6498.053618 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 251 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 238 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1228 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 324190030 # Number of tag accesses +system.cpu.icache.tags.data_accesses 324190030 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 161874355 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161874355 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161874355 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161874355 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161874355 # number of overall hits +system.cpu.icache.overall_hits::total 161874355 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 147766 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 147766 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 147766 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 147766 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 147766 # number of overall misses +system.cpu.icache.overall_misses::total 147766 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 941588486 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 941588486 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 941588486 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 941588486 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 941588486 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 941588486 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162022121 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162022121 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162022121 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162022121 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162022121 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162022121 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000912 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000912 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000912 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000912 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000912 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000912 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6372.159265 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6372.159265 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6372.159265 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6372.159265 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6372.159265 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6372.159265 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 953 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 41.833333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 119.125000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2000 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2000 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2000 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2000 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2000 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2000 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 142635 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 142635 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 142635 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 142635 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 142635 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 142635 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 558603007 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 558603007 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 558603007 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 558603007 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 558603007 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 558603007 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000880 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000880 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000880 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000880 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000880 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000880 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3916.310912 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3916.310912 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3916.310912 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 3916.310912 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3916.310912 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 3916.310912 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1977 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1977 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1977 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1977 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1977 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1977 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 145789 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 145789 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 145789 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 145789 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 145789 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 145789 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 560897259 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 560897259 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 560897259 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 560897259 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 560897259 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 560897259 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000900 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000900 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000900 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000900 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000900 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000900 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3847.322219 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3847.322219 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3847.322219 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 3847.322219 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3847.322219 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 3847.322219 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 352851 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29668.075307 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3697142 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 385214 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.597631 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 199249645000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21122.585790 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 223.642071 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8321.847447 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.644610 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006825 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.253963 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.905398 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32363 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 239 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11704 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20343 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987640 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41217237 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41217237 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 3670 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1586809 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1590479 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2330749 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2330749 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1446 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1446 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 564831 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 564831 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3670 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2151640 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2155310 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3670 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2151640 # number of overall hits -system.cpu.l2cache.overall_hits::total 2155310 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3159 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 175542 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 178701 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 134263 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 134263 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206857 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206857 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3159 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 382399 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 385558 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3159 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 382399 # number of overall misses -system.cpu.l2cache.overall_misses::total 385558 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 240297250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13188147460 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13428444710 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6534219 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 6534219 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15150269977 # 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mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150931 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151764 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62497.457896 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59770.380573 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59818.381649 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.021306 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.021306 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58129.310618 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58129.310618 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62497.457896 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58882.958553 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58912.456827 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62497.457896 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58882.958553 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58912.456827 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2529943 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.243531 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 396026298 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2534039 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 156.282637 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1794365000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.243531 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998106 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998106 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2529933 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.224261 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 395924693 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2534029 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 156.243158 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1796857250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.224261 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998102 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998102 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 730 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3318 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 753 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3301 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 801176347 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 801176347 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 247278807 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 247278807 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148236045 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148236045 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 395514852 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 395514852 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 395514852 # number of overall hits -system.cpu.dcache.overall_hits::total 395514852 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2882145 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2882145 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 924157 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 924157 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3806302 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3806302 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3806302 # number of overall misses -system.cpu.dcache.overall_misses::total 3806302 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58050756258 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58050756258 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26834846719 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26834846719 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 84885602977 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 84885602977 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 84885602977 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 84885602977 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250160952 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250160952 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 800965525 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 800965525 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 247184750 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 247184750 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148232864 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148232864 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 395417614 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 395417614 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 395417614 # number of overall hits +system.cpu.dcache.overall_hits::total 395417614 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2870796 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2870796 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 927338 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 927338 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3798134 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3798134 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3798134 # number of overall misses +system.cpu.dcache.overall_misses::total 3798134 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57044971459 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57044971459 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26405527365 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26405527365 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83450498824 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83450498824 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83450498824 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83450498824 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250055546 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250055546 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 399321154 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 399321154 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 399321154 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 399321154 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011521 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011521 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006196 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006196 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009532 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009532 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009532 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009532 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20141.511360 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20141.511360 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29037.108109 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29037.108109 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22301.331575 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22301.331575 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22301.331575 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22301.331575 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7238 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 399215748 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 399215748 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 399215748 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 399215748 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011481 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011481 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006217 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006217 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009514 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009514 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009514 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009514 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19870.785475 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19870.785475 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28474.544734 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28474.544734 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21971.446722 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21971.446722 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21971.446722 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21971.446722 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6569 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 664 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 666 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.900602 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.863363 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330749 # number of writebacks -system.cpu.dcache.writebacks::total 2330749 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1119535 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1119535 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17020 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 17020 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1136555 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1136555 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1136555 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1136555 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762610 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762610 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 907137 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 907137 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2669747 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2669747 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2669747 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2669747 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30854243503 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30854243503 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24711423781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 24711423781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55565667284 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 55565667284 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55565667284 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 55565667284 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007046 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007046 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006082 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006082 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006686 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006686 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006686 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006686 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.861259 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17504.861259 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27241.115489 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27241.115489 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20813.083518 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20813.083518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20813.083518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20813.083518 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2330726 # number of writebacks +system.cpu.dcache.writebacks::total 2330726 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1108238 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1108238 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17013 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 17013 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1125251 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1125251 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1125251 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1125251 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762558 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762558 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 54680532135 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54680532135 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 54680532135 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007049 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007049 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006103 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006103 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006695 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006695 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006695 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006695 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17247.590859 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17247.590859 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26672.510241 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26672.510241 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20457.510536 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20457.510536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20457.510536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20457.510536 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index eb5995295..4b6099b52 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.139926 # Nu sim_ticks 139926186500 # Number of ticks simulated final_tick 139926186500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 138827 # Simulator instruction rate (inst/s) -host_op_rate 138827 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48726388 # Simulator tick rate (ticks/s) -host_mem_usage 236592 # Number of bytes of host memory used -host_seconds 2871.67 # Real time elapsed on the host +host_inst_rate 124689 # Simulator instruction rate (inst/s) +host_op_rate 124689 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43764124 # Simulator tick rate (ticks/s) +host_mem_usage 271420 # Number of bytes of host memory used +host_seconds 3197.28 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1820 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4589 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -154,79 +154,60 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1198 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 387.899833 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 185.568922 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 772.018563 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 419 34.97% 34.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 201 16.78% 51.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 128 10.68% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 91 7.60% 70.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 61 5.09% 75.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 40 3.34% 78.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 30 2.50% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 22 1.84% 82.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 25 2.09% 84.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 18 1.50% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 20 1.67% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 8 0.67% 88.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 17 1.42% 90.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 10 0.83% 90.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 8 0.67% 91.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 6 0.50% 92.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 10 0.83% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 7 0.58% 93.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 7 0.58% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 1 0.08% 94.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 4 0.33% 94.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 4 0.33% 94.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 2 0.17% 95.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 5 0.42% 95.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 5 0.42% 95.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 4 0.33% 96.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.08% 96.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.17% 96.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 1 0.08% 96.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 2 0.17% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 1 0.08% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.17% 96.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.08% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.17% 97.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.08% 97.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 4 0.33% 97.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 2 0.17% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.08% 98.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 2 0.17% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.08% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.08% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.08% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 2 0.17% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.08% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.08% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.08% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.08% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.08% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 1 0.08% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 1 0.08% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 1 0.08% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.08% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.08% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 1 0.08% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 2 0.17% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1198 # Bytes accessed per row activation -system.physmem.totQLat 59880500 # Total ticks spent queuing -system.physmem.totMemAccLat 197624250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 558 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 480.917563 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 280.270360 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.877438 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 147 26.34% 26.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 107 19.18% 45.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 50 8.96% 54.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28 5.02% 59.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15 2.69% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 15 2.69% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 1.25% 66.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5 0.90% 67.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 184 32.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 558 # Bytes accessed per row activation +system.physmem.totQLat 59527000 # Total ticks spent queuing +system.physmem.totMemAccLat 199924500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 36640000 # Total ticks spent in databus transfers -system.physmem.totBankLat 101103750 # Total ticks spent accessing banks -system.physmem.avgQLat 8171.47 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13796.91 # Average bank access latency per DRAM burst +system.physmem.totBankLat 103757500 # Total ticks spent accessing banks +system.physmem.avgQLat 8123.23 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14159.05 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26968.37 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27282.27 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.35 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.35 # Average system read bandwidth in MiByte/s @@ -235,15 +216,15 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6130 # Number of row buffer hits during reads +system.physmem.readRowHits 5962 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.65 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 19094720.66 # Average gap between requests -system.physmem.pageHitRate 83.65 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.42 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.pageHitRate 81.36 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.43 # Percentage of time for which DRAM has all the banks in precharge state system.membus.throughput 3351710 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4183 # Transaction distribution system.membus.trans_dist::ReadResp 4183 # Transaction distribution @@ -257,7 +238,7 @@ system.membus.data_through_bus 468992 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 8743500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 68145750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 68133000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 53489673 # Number of BP lookups @@ -273,22 +254,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754637 # DTB read hits +system.cpu.dtb.read_hits 94754639 # DTB read hits system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754658 # DTB read accesses -system.cpu.dtb.write_hits 73521124 # DTB write hits +system.cpu.dtb.read_accesses 94754660 # DTB read accesses +system.cpu.dtb.write_hits 73521131 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73521159 # DTB write accesses -system.cpu.dtb.data_hits 168275761 # DTB hits +system.cpu.dtb.write_accesses 73521166 # DTB write accesses +system.cpu.dtb.data_hits 168275770 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275817 # DTB accesses -system.cpu.itb.fetch_hits 48611324 # ITB hits +system.cpu.dtb.data_accesses 168275826 # DTB accesses +system.cpu.itb.fetch_hits 48611322 # ITB hits system.cpu.itb.fetch_misses 44520 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 48655844 # ITB accesses +system.cpu.itb.fetch_accesses 48655842 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -307,13 +288,13 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 24259168 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280386579 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 280386572 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 439722438 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119631950 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 439722431 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119631955 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 219828431 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100484574 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.floatRegFileAccesses 219828436 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100484576 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 168485322 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken). @@ -324,12 +305,12 @@ system.cpu.execution_unit.executions 205475782 # Nu system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 279400617 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 279400810 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7206 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13545708 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 266306666 # Number of cycles cpu stages are processed. -system.cpu.activity 95.159695 # Percentage of cycles cpu is active +system.cpu.timesIdled 7266 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13545705 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 266306669 # Number of cycles cpu stages are processed. +system.cpu.activity 95.159696 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -350,27 +331,27 @@ system.cpu.ipc_total 1.424553 # IP system.cpu.stage0.idleCycles 78104700 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 201747674 # Number of cycles 1+ instructions are processed. system.cpu.stage0.utilization 72.090750 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 107200641 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 172651733 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.693860 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 107200637 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 172651737 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.693862 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.idleCycles 102637143 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 177215231 # Number of cycles 1+ instructions are processed. system.cpu.stage2.utilization 63.324541 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 181107759 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98744615 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.284537 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 90384394 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189467980 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.702831 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 181107747 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98744627 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 35.284541 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 90384400 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189467974 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.702829 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 1975 # number of replacements -system.cpu.icache.tags.tagsinuse 1830.939408 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 48606790 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1830.934233 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 48606787 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12453.699718 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 12453.698950 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1830.939408 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894013 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894013 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1830.934233 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894011 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894011 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id @@ -378,44 +359,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 322 system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1366 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 97226551 # Number of tag accesses -system.cpu.icache.tags.data_accesses 97226551 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 48606790 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 48606790 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 48606790 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 48606790 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 48606790 # number of overall hits -system.cpu.icache.overall_hits::total 48606790 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4534 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4534 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4534 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4534 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4534 # number of overall misses -system.cpu.icache.overall_misses::total 4534 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 280061250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 280061250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 280061250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 280061250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 280061250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 280061250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 48611324 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 48611324 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 48611324 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 48611324 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 48611324 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 48611324 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 97226547 # Number of tag accesses +system.cpu.icache.tags.data_accesses 97226547 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 48606787 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 48606787 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 48606787 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 48606787 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 48606787 # number of overall hits +system.cpu.icache.overall_hits::total 48606787 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4535 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4535 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4535 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4535 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4535 # number of overall misses +system.cpu.icache.overall_misses::total 4535 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 279787250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 279787250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 279787250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 279787250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 279787250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 279787250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 48611322 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 48611322 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 48611322 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 48611322 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 48611322 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 48611322 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61769.133216 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61769.133216 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61769.133216 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61769.133216 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61769.133216 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61769.133216 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61695.093716 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61695.093716 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61695.093716 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61695.093716 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61695.093716 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61695.093716 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 330 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -424,36 +405,36 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 110 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 631 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 631 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 631 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 631 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 631 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 631 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 632 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 632 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 632 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 632 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 632 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 632 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 244179750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 244179750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 244179750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 244179750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 244179750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 244179750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243875500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 243875500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243875500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 243875500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243875500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 243875500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62562.067640 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62562.067640 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62562.067640 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 62562.067640 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62562.067640 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 62562.067640 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62484.114783 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62484.114783 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62484.114783 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62484.114783 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62484.114783 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62484.114783 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.throughput 3981070 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution @@ -471,21 +452,21 @@ system.cpu.toL2Bus.data_through_bus 557056 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6459750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6445500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6671999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6649999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3906.845611 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3906.832917 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 370.534640 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.739390 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 627.571581 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 370.533355 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.730052 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 627.569510 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088768 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088767 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.119227 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 4717 # Occupied blocks per task id @@ -520,17 +501,17 @@ system.cpu.l2cache.demand_misses::total 7328 # nu system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7328 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234790750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 62080250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 296871000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 227075250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 227075250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 234790750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 289155500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 523946250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 234790750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 289155500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 523946250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234486500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61133000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 295619500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 230289500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 230289500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 234486500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 291422500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 525909000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 234486500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 291422500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 525909000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses) @@ -555,17 +536,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909745 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69899.002679 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75340.109223 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70970.834329 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72201.987281 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72201.987281 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69899.002679 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72853.489544 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71499.215338 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69899.002679 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72853.489544 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71499.215338 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69808.425127 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74190.533981 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70671.647143 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73224.006359 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73224.006359 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69808.425127 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73424.666163 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71767.057860 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69808.425127 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73424.666163 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71767.057860 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -585,17 +566,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 192686250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 51812250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 244498500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 188269250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 188269250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192686250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 240081500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 432767750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192686250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 240081500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 432767750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 192420000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 50867000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 243287000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 191492500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 191492500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192420000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 242359500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 434779500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192420000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 242359500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 434779500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses @@ -607,27 +588,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57364.170884 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62878.944175 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58450.513985 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59863.036566 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59863.036566 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57364.170884 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60489.166037 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59056.734443 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57364.170884 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60489.166037 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59056.734443 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57284.906222 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61731.796117 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58160.889314 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60887.917329 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60887.917329 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57284.906222 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61063.114135 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59331.263646 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57284.906222 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61063.114135 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59331.263646 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3284.890275 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168254255 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3284.879976 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168254239 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40523.664499 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40523.660645 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3284.890275 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.801975 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.801975 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3284.879976 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.801973 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.801973 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id @@ -639,28 +620,28 @@ system.cpu.dcache.tags.tag_accesses 336554588 # Nu system.cpu.dcache.tags.data_accesses 336554588 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501074 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501074 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168254255 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168254255 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168254255 # number of overall hits -system.cpu.dcache.overall_hits::total 168254255 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501058 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501058 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168254239 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168254239 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168254239 # number of overall hits +system.cpu.dcache.overall_hits::total 168254239 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1308 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1308 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19655 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19655 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 20963 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20963 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 20963 # number of overall misses -system.cpu.dcache.overall_misses::total 20963 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88453749 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88453749 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1129220750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1129220750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1217674499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1217674499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1217674499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1217674499 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 19671 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19671 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 20979 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20979 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 20979 # number of overall misses +system.cpu.dcache.overall_misses::total 20979 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 87087749 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 87087749 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1166784250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1166784250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1253871999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1253871999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1253871999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1253871999 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -671,25 +652,25 @@ system.cpu.dcache.overall_accesses::cpu.data 168275218 system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000014 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000267 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000267 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000268 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000125 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000125 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000125 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67625.190367 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67625.190367 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57452.085983 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57452.085983 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58086.843438 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58086.843438 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 58086.843438 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 58086.843438 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33688 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66580.847859 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66580.847859 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59314.943318 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59314.943318 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59767.958387 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59767.958387 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59767.958387 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59767.958387 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33117 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 584 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 591 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.684932 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.035533 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -697,12 +678,12 @@ system.cpu.dcache.writebacks::writebacks 649 # nu system.cpu.dcache.writebacks::total 649 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16453 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16453 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16811 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16811 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16811 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16811 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16469 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16469 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16827 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16827 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16827 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16827 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses @@ -711,14 +692,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 64535001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 64535001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 230815000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 230815000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 295350001 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 295350001 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 295350001 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 295350001 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63587751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 63587751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 234030250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 234030250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 297618001 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 297618001 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 297618001 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 297618001 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -727,14 +708,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67931.580000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67931.580000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72084.634603 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72084.634603 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71134.393304 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71134.393304 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71134.393304 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71134.393304 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66934.474737 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66934.474737 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73088.772642 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73088.772642 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71680.636079 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71680.636079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71680.636079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71680.636079 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 39e558e65..8d6cbc006 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.077516 # Number of seconds simulated -sim_ticks 77516381000 # Number of ticks simulated -final_tick 77516381000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.077418 # Number of seconds simulated +sim_ticks 77417500000 # Number of ticks simulated +final_tick 77417500000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 222910 # Simulator instruction rate (inst/s) -host_op_rate 222910 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46007212 # Simulator tick rate (ticks/s) -host_mem_usage 236600 # Number of bytes of host memory used -host_seconds 1684.87 # Real time elapsed on the host +host_inst_rate 187521 # Simulator instruction rate (inst/s) +host_op_rate 187521 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38653802 # Simulator tick rate (ticks/s) +host_mem_usage 273448 # Number of bytes of host memory used +host_seconds 2002.84 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 221184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255424 # Number of bytes read from this memory -system.physmem.bytes_read::total 476608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221184 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3991 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7447 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2853384 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3295097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6148481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2853384 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2853384 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2853384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3295097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6148481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7447 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 220992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255488 # Number of bytes read from this memory +system.physmem.bytes_read::total 476480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220992 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3453 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3992 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7445 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2854548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3300132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6154681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2854548 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2854548 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2854548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3300132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6154681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7445 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7447 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7445 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 476608 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 476480 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 476608 # Total read bytes from the system interface side +system.physmem.bytesReadSys 476480 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 524 # Per bank write bursts -system.physmem.perBankRdBursts::1 653 # Per bank write bursts +system.physmem.perBankRdBursts::1 654 # Per bank write bursts system.physmem.perBankRdBursts::2 449 # Per bank write bursts system.physmem.perBankRdBursts::3 600 # Per bank write bursts system.physmem.perBankRdBursts::4 447 # Per bank write bursts system.physmem.perBankRdBursts::5 455 # Per bank write bursts -system.physmem.perBankRdBursts::6 515 # Per bank write bursts +system.physmem.perBankRdBursts::6 518 # Per bank write bursts system.physmem.perBankRdBursts::7 524 # Per bank write bursts -system.physmem.perBankRdBursts::8 439 # Per bank write bursts -system.physmem.perBankRdBursts::9 407 # Per bank write bursts -system.physmem.perBankRdBursts::10 340 # Per bank write bursts +system.physmem.perBankRdBursts::8 436 # Per bank write bursts +system.physmem.perBankRdBursts::9 405 # Per bank write bursts +system.physmem.perBankRdBursts::10 339 # Per bank write bursts system.physmem.perBankRdBursts::11 306 # Per bank write bursts system.physmem.perBankRdBursts::12 414 # Per bank write bursts -system.physmem.perBankRdBursts::13 542 # Per bank write bursts -system.physmem.perBankRdBursts::14 453 # Per bank write bursts +system.physmem.perBankRdBursts::13 541 # Per bank write bursts +system.physmem.perBankRdBursts::14 454 # Per bank write bursts system.physmem.perBankRdBursts::15 379 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 77516291500 # Total gap between requests +system.physmem.totGap 77417410500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7447 # Read request sizes (log2) +system.physmem.readPktSize::6 7445 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4394 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2044 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2023 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 735 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -154,72 +154,60 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1164 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 404.618557 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.969320 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 801.678722 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 417 35.82% 35.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 184 15.81% 51.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 111 9.54% 61.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 97 8.33% 69.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 49 4.21% 73.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 38 3.26% 76.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 28 2.41% 79.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 28 2.41% 81.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 22 1.89% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 22 1.89% 85.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 9 0.77% 86.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 13 1.12% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 15 1.29% 88.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 15 1.29% 90.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 6 0.52% 90.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 7 0.60% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 16 1.37% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 3 0.26% 92.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 5 0.43% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.17% 93.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.26% 93.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 11 0.95% 94.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 0.34% 94.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 6 0.52% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.26% 95.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 4 0.34% 96.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 3 0.26% 96.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 3 0.26% 96.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.26% 96.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 3 0.26% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.17% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 5 0.43% 97.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.09% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.09% 97.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 2 0.17% 98.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.09% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.09% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.09% 98.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 2 0.17% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 2 0.17% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.09% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 1 0.09% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.09% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.17% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 1 0.09% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.09% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.09% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 1 0.09% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.09% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.09% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.09% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.09% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 3 0.26% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1164 # Bytes accessed per row activation -system.physmem.totQLat 59914250 # Total ticks spent queuing -system.physmem.totMemAccLat 199861750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37235000 # Total ticks spent in databus transfers -system.physmem.totBankLat 102712500 # Total ticks spent accessing banks -system.physmem.avgQLat 8045.42 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13792.47 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 457.157393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 257.861215 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.549348 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 187 29.73% 29.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 122 19.40% 49.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53 8.43% 57.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24 3.82% 61.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18 2.86% 64.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 15 2.38% 66.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 1.11% 67.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 0.48% 68.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 200 31.80% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 629 # Bytes accessed per row activation +system.physmem.totQLat 62316500 # Total ticks spent queuing +system.physmem.totMemAccLat 205595250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37225000 # Total ticks spent in databus transfers +system.physmem.totBankLat 106053750 # Total ticks spent accessing banks +system.physmem.avgQLat 8370.25 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14244.96 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26837.89 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27615.21 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.15 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.15 # Average system read bandwidth in MiByte/s @@ -228,60 +216,60 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6283 # Number of row buffer hits during reads +system.physmem.readRowHits 6071 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.37 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.54 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10409062.91 # Average gap between requests -system.physmem.pageHitRate 84.37 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.56 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 6148481 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4317 # Transaction distribution -system.membus.trans_dist::ReadResp 4317 # Transaction distribution -system.membus.trans_dist::ReadExReq 3130 # Transaction distribution -system.membus.trans_dist::ReadExResp 3130 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14894 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 476608 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 476608 # Total data (bytes) +system.physmem.avgGap 10398577.64 # Average gap between requests +system.physmem.pageHitRate 81.54 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.52 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6154681 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4313 # Transaction distribution +system.membus.trans_dist::ReadResp 4313 # Transaction distribution +system.membus.trans_dist::ReadExReq 3132 # Transaction distribution +system.membus.trans_dist::ReadExResp 3132 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14890 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14890 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476480 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 476480 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 476480 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 9290500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9329500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69562000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 69519750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 50307155 # Number of BP lookups -system.cpu.branchPred.condPredicted 29267262 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1212205 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26317352 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23268236 # Number of BTB hits +system.cpu.branchPred.lookups 50246060 # Number of BP lookups +system.cpu.branchPred.condPredicted 29233966 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1199560 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 25853120 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23225371 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.414047 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9019862 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1049 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.835853 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9012456 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1102 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 101828804 # DTB read hits -system.cpu.dtb.read_misses 77910 # DTB read misses -system.cpu.dtb.read_acv 48604 # DTB read access violations -system.cpu.dtb.read_accesses 101906714 # DTB read accesses -system.cpu.dtb.write_hits 78465960 # DTB write hits -system.cpu.dtb.write_misses 1494 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 78467454 # DTB write accesses -system.cpu.dtb.data_hits 180294764 # DTB hits -system.cpu.dtb.data_misses 79404 # DTB misses -system.cpu.dtb.data_acv 48608 # DTB access violations -system.cpu.dtb.data_accesses 180374168 # DTB accesses -system.cpu.itb.fetch_hits 50297233 # ITB hits -system.cpu.itb.fetch_misses 369 # ITB misses +system.cpu.dtb.read_hits 101798719 # DTB read hits +system.cpu.dtb.read_misses 78049 # DTB read misses +system.cpu.dtb.read_acv 48607 # DTB read access violations +system.cpu.dtb.read_accesses 101876768 # DTB read accesses +system.cpu.dtb.write_hits 78433341 # DTB write hits +system.cpu.dtb.write_misses 1499 # DTB write misses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_accesses 78434840 # DTB write accesses +system.cpu.dtb.data_hits 180232060 # DTB hits +system.cpu.dtb.data_misses 79548 # DTB misses +system.cpu.dtb.data_acv 48609 # DTB access violations +system.cpu.dtb.data_accesses 180311608 # DTB accesses +system.cpu.itb.fetch_hits 50221171 # ITB hits +system.cpu.itb.fetch_misses 373 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 50297602 # ITB accesses +system.cpu.itb.fetch_accesses 50221544 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -295,105 +283,105 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 155032764 # number of cpu cycles simulated +system.cpu.numCycles 154835002 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 51194259 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 449183474 # Number of instructions fetch has processed -system.cpu.fetch.Branches 50307155 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32288098 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 78871433 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6172161 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19742008 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 181 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 10560 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 51111974 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 448661331 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50246060 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32237827 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 78769244 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6113875 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19767092 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 184 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 10735 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 50297233 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 412894 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 154739151 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.902843 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.324835 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 50221171 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 406319 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 154534598 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.903307 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.325117 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75867718 49.03% 49.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4287409 2.77% 51.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6889018 4.45% 56.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5374428 3.47% 59.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11763624 7.60% 67.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7816659 5.05% 72.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5616009 3.63% 76.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1833388 1.18% 77.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35290898 22.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75765354 49.03% 49.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4278797 2.77% 51.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6878880 4.45% 56.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5365294 3.47% 59.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11742013 7.60% 67.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7808130 5.05% 72.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5610858 3.63% 76.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1827134 1.18% 77.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35258138 22.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154739151 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324494 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.897345 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 56553436 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15088868 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74238964 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3941383 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4916500 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9487386 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4275 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 445247195 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12161 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4916500 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 59699528 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4890372 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 419538 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 75126102 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9687111 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 440708166 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 170 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18989 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8005915 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 287519835 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 579387338 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 414037453 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 165349884 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 154534598 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324514 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.897674 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 56469798 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15107857 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74141890 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3943911 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4871142 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9469846 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4291 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 444777840 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12202 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4871142 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 59608441 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4896661 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 418311 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 75037002 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9703041 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 440308504 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 162 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18256 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8013879 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 287257669 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 578877349 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 413693152 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 165184196 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27987506 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 36934 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 290 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27862892 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104720393 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80633883 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8938676 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6410471 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 408405086 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 279 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 401961016 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 974295 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32695397 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15321612 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154739151 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.597668 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.996651 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27725340 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 36879 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 302 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27905569 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104673865 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80579462 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8919028 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6395315 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 408114726 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 290 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 401714158 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 971094 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32406044 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15222181 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154534598 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.599510 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.995704 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28425455 18.37% 18.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 25900888 16.74% 35.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25580333 16.53% 51.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24228882 15.66% 67.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21279905 13.75% 81.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15505585 10.02% 91.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8490760 5.49% 96.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3998033 2.58% 99.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1329310 0.86% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28287072 18.30% 18.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25862273 16.74% 35.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25616970 16.58% 51.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24199972 15.66% 67.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21258651 13.76% 81.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15520360 10.04% 91.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8472156 5.48% 96.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3988463 2.58% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1328681 0.86% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154739151 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154534598 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 33873 0.29% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 33844 0.29% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 57850 0.49% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 5381 0.05% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 5383 0.05% 0.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1948507 16.46% 17.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1748153 14.77% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 57389 0.49% 0.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 4757 0.04% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 5293 0.04% 0.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1937864 16.39% 17.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1755771 14.85% 32.09% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.09% # attempts to use FU when none available @@ -415,118 +403,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.09% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5077908 42.90% 74.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2960216 25.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5068587 42.87% 74.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2960872 25.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 155836212 38.77% 38.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126206 0.53% 39.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32826139 8.17% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7503461 1.87% 49.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2792900 0.69% 50.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16557877 4.12% 54.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1579224 0.39% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103415841 25.73% 80.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79289575 19.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 155710180 38.76% 38.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126250 0.53% 39.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32800446 8.17% 47.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7495713 1.87% 49.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2793863 0.70% 50.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16555604 4.12% 54.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1576822 0.39% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103379318 25.73% 80.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79242381 19.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 401961016 # Type of FU issued -system.cpu.iq.rate 2.592749 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11837271 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029449 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 634505774 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 260497209 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 234812479 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 336966975 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 180652533 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 161419314 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 241576222 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172188484 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 15052407 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 401714158 # Type of FU issued +system.cpu.iq.rate 2.594466 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11824377 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029435 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 633974130 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 260128925 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 234699525 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 336784255 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 180440959 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 161353653 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 241409796 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172095158 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 15058802 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9965906 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 111384 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 48996 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7113154 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9919378 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 112340 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 48844 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7058733 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260897 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3921 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260875 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3830 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4916500 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2514816 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 370985 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 433209224 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 130318 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104720393 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80633883 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 279 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 90 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 76 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 48996 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 956631 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 408580 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1365211 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 398393230 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101955347 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3567786 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4871142 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2518143 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 371002 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 432897365 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 126094 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104673865 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80579462 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 290 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 87 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 80 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 48844 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 943634 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 406077 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1349711 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 398212292 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101925424 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3501866 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24803859 # number of nop insts executed -system.cpu.iew.exec_refs 180422830 # number of memory reference insts executed -system.cpu.iew.exec_branches 46575028 # Number of branches executed -system.cpu.iew.exec_stores 78467483 # Number of stores executed -system.cpu.iew.exec_rate 2.569736 # Inst execution rate -system.cpu.iew.wb_sent 396861814 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 396231793 # cumulative count of insts written-back -system.cpu.iew.wb_producers 193564452 # num instructions producing a value -system.cpu.iew.wb_consumers 271143010 # num instructions consuming a value +system.cpu.iew.exec_nop 24782349 # number of nop insts executed +system.cpu.iew.exec_refs 180360292 # number of memory reference insts executed +system.cpu.iew.exec_branches 46546611 # Number of branches executed +system.cpu.iew.exec_stores 78434868 # Number of stores executed +system.cpu.iew.exec_rate 2.571849 # Inst execution rate +system.cpu.iew.wb_sent 396683492 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396053178 # cumulative count of insts written-back +system.cpu.iew.wb_producers 193508627 # num instructions producing a value +system.cpu.iew.wb_consumers 271030051 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.555794 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.713883 # average fanout of values written-back +system.cpu.iew.wb_rate 2.557905 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.713975 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34575269 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34263124 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1208013 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149822651 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.660910 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.995203 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1195351 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149663456 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.663740 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.995900 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 55444795 37.01% 37.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22572345 15.07% 52.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13039783 8.70% 60.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11474023 7.66% 68.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8200661 5.47% 73.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5438800 3.63% 77.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5171862 3.45% 80.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3280269 2.19% 83.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 25200113 16.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 55327244 36.97% 36.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22535122 15.06% 52.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13022576 8.70% 60.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11475094 7.67% 68.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8197799 5.48% 73.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5452875 3.64% 77.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5172237 3.46% 80.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3274038 2.19% 83.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 25206471 16.84% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149822651 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149663456 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -537,228 +525,228 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 25200113 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 25206471 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 557859413 # The number of ROB reads -system.cpu.rob.rob_writes 871404727 # The number of ROB writes -system.cpu.timesIdled 3579 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 293613 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 557381715 # The number of ROB reads +system.cpu.rob.rob_writes 870735186 # The number of ROB writes +system.cpu.timesIdled 3600 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 300404 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.412788 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.412788 # CPI: Total CPI of All Threads -system.cpu.ipc 2.422551 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.422551 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 398219851 # number of integer regfile reads -system.cpu.int_regfile_writes 170183531 # number of integer regfile writes -system.cpu.fp_regfile_reads 156589680 # number of floating regfile reads -system.cpu.fp_regfile_writes 104065109 # number of floating regfile writes +system.cpu.cpi 0.412261 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.412261 # CPI: Total CPI of All Threads +system.cpu.ipc 2.425645 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.425645 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 398046268 # number of integer regfile reads +system.cpu.int_regfile_writes 170097469 # number of integer regfile writes +system.cpu.fp_regfile_reads 156518592 # number of floating regfile reads +system.cpu.fp_regfile_writes 104028166 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 7356381 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 5061 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5061 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 659 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3190 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8138 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9023 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17161 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 570240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 570240 # Total data (bytes) +system.cpu.toL2Bus.throughput 7364950 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 5055 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5055 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 661 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3193 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3193 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8124 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9033 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17157 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 259968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 570176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 570176 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 5114000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 5115500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6775000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6740250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6675000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6663250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2141 # number of replacements -system.cpu.icache.tags.tagsinuse 1831.580097 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 50291612 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4069 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12359.698206 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2135 # number of replacements +system.cpu.icache.tags.tagsinuse 1832.551439 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 50215552 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4062 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12362.272772 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1831.580097 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894326 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894326 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 336 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1334 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 100598535 # Number of tag accesses -system.cpu.icache.tags.data_accesses 100598535 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 50291612 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 50291612 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 50291612 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 50291612 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 50291612 # number of overall hits -system.cpu.icache.overall_hits::total 50291612 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5621 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5621 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5621 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5621 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5621 # number of overall misses -system.cpu.icache.overall_misses::total 5621 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 330634250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 330634250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 330634250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 330634250 # 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number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 332785750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50221171 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50221171 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50221171 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50221171 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50221171 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50221171 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000112 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000112 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000112 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000112 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59225.084535 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59225.084535 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59225.084535 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59225.084535 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 251 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 148.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 83.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4069 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4069 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249126500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 249126500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249126500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 249126500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249126500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 249126500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1557 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1557 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1557 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1557 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1557 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1557 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4062 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4062 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4062 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4062 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4062 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4062 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250275250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 250275250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250275250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 250275250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250275250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 250275250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61225.485377 # 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Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86473896 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86473896 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500850 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500850 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 159974746 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 159974746 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 159974746 # number of overall hits +system.cpu.dcache.overall_hits::total 159974746 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1803 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1803 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19879 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19879 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21682 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21682 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21682 # number of overall misses +system.cpu.dcache.overall_misses::total 21682 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 116178750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 116178750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1100405079 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1100405079 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1216583829 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1216583829 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1216583829 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1216583829 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86475699 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86475699 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 160032782 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 160032782 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 160032782 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 160032782 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 159996428 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 159996428 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 159996428 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 159996428 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000270 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000270 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000135 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000135 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000135 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000135 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63957.586786 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63957.586786 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54710.187283 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54710.187283 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55473.643831 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55473.643831 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55473.643831 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55473.643831 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 40366 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000136 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000136 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000136 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000136 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64436.356073 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64436.356073 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55355.152623 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55355.152623 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56110.314039 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56110.314039 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56110.314039 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56110.314039 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 40445 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 653 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 670 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 61.816233 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 60.365672 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 659 # number of writebacks -system.cpu.dcache.writebacks::total 659 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 794 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 794 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16657 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16657 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17451 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17451 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17451 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17451 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 992 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 992 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3190 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3190 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4182 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4182 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4182 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4182 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 68767000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 68767000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 229720000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 229720000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298487000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 298487000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298487000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 298487000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 661 # number of writebacks +system.cpu.dcache.writebacks::total 661 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 810 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 810 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16686 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16686 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17496 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17496 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17496 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17496 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 993 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 993 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3193 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3193 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4186 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4186 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4186 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4186 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 69211250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 69211250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 233753500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 233753500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 302964750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 302964750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 302964750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 302964750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -924,14 +912,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69321.572581 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69321.572581 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72012.539185 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72012.539185 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71374.222860 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71374.222860 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71374.222860 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71374.222860 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69699.144008 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69699.144008 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73208.111494 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73208.111494 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72375.716675 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72375.716675 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72375.716675 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72375.716675 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 634fe5f9a..648c5ea6f 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068504 # Number of seconds simulated -sim_ticks 68503867000 # Number of ticks simulated -final_tick 68503867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068245 # Number of seconds simulated +sim_ticks 68245472000 # Number of ticks simulated +final_tick 68245472000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147835 # Simulator instruction rate (inst/s) -host_op_rate 189000 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37091215 # Simulator tick rate (ticks/s) -host_mem_usage 278164 # Number of bytes of host memory used -host_seconds 1846.90 # Real time elapsed on the host +host_inst_rate 123424 # Simulator instruction rate (inst/s) +host_op_rate 157791 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30849723 # Simulator tick rate (ticks/s) +host_mem_usage 321440 # Number of bytes of host memory used +host_seconds 2212.19 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 193984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272256 # Number of bytes read from this memory -system.physmem.bytes_read::total 466240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 193984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 193984 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3031 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4254 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7285 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2831723 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3974316 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6806039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2831723 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2831723 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2831723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3974316 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6806039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7286 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 193792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272576 # Number of bytes read from this memory +system.physmem.bytes_read::total 466368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 193792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 193792 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3028 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4259 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7287 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2839632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3994053 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6833684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2839632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2839632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2839632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3994053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6833684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7288 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7286 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7288 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 466304 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 466432 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 466304 # Total read bytes from the system interface side +system.physmem.bytesReadSys 466432 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 606 # Per bank write bursts -system.physmem.perBankRdBursts::1 800 # Per bank write bursts +system.physmem.perBankRdBursts::1 802 # Per bank write bursts system.physmem.perBankRdBursts::2 608 # Per bank write bursts system.physmem.perBankRdBursts::3 526 # Per bank write bursts -system.physmem.perBankRdBursts::4 443 # Per bank write bursts -system.physmem.perBankRdBursts::5 354 # Per bank write bursts -system.physmem.perBankRdBursts::6 164 # Per bank write bursts -system.physmem.perBankRdBursts::7 219 # Per bank write bursts -system.physmem.perBankRdBursts::8 207 # Per bank write bursts -system.physmem.perBankRdBursts::9 291 # Per bank write bursts -system.physmem.perBankRdBursts::10 322 # Per bank write bursts -system.physmem.perBankRdBursts::11 415 # Per bank write bursts -system.physmem.perBankRdBursts::12 529 # Per bank write bursts +system.physmem.perBankRdBursts::4 441 # Per bank write bursts +system.physmem.perBankRdBursts::5 356 # Per bank write bursts +system.physmem.perBankRdBursts::6 162 # Per bank write bursts +system.physmem.perBankRdBursts::7 220 # Per bank write bursts +system.physmem.perBankRdBursts::8 205 # Per bank write bursts +system.physmem.perBankRdBursts::9 290 # Per bank write bursts +system.physmem.perBankRdBursts::10 324 # Per bank write bursts +system.physmem.perBankRdBursts::11 417 # Per bank write bursts +system.physmem.perBankRdBursts::12 531 # Per bank write bursts system.physmem.perBankRdBursts::13 687 # Per bank write bursts system.physmem.perBankRdBursts::14 611 # Per bank write bursts -system.physmem.perBankRdBursts::15 504 # Per bank write bursts +system.physmem.perBankRdBursts::15 502 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 68503846500 # Total gap between requests +system.physmem.totGap 68245446000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7286 # Read request sizes (log2) +system.physmem.readPktSize::6 7288 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 66 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4342 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 590 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -154,124 +154,102 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1286 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 361.604977 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 163.647663 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 753.981601 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 537 41.76% 41.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 220 17.11% 58.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 131 10.19% 69.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 77 5.99% 75.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 39 3.03% 78.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 38 2.95% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 26 2.02% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 31 2.41% 85.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 17 1.32% 86.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 23 1.79% 88.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 6 0.47% 89.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 16 1.24% 90.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 3 0.23% 90.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 8 0.62% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 7 0.54% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 7 0.54% 92.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 5 0.39% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 8 0.62% 93.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 5 0.39% 93.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 6 0.47% 94.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 1 0.08% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 4 0.31% 94.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 0.31% 94.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 6 0.47% 95.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.23% 95.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 3 0.23% 95.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 3 0.23% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 4 0.31% 96.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 2 0.16% 96.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.23% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.16% 96.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 4 0.31% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 2 0.16% 97.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.08% 97.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.16% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.08% 97.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.08% 97.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.08% 97.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.08% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.08% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 2 0.16% 98.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.08% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 2 0.16% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.08% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.08% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.08% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 2 0.16% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.08% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 1 0.08% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.08% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.08% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 3 0.23% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 1 0.08% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.08% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.08% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.08% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 2 0.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1286 # Bytes accessed per row activation -system.physmem.totQLat 62980000 # Total ticks spent queuing -system.physmem.totMemAccLat 198080000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36430000 # Total ticks spent in databus transfers -system.physmem.totBankLat 98670000 # Total ticks spent accessing banks -system.physmem.avgQLat 8643.97 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13542.41 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 580 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 479.779310 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 274.986956 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 421.744260 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 159 27.41% 27.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 117 20.17% 47.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 45 7.76% 55.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23 3.97% 59.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14 2.41% 61.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13 2.24% 63.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 1.03% 65.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 0.34% 65.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 201 34.66% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 580 # Bytes accessed per row activation +system.physmem.totQLat 57907000 # Total ticks spent queuing +system.physmem.totMemAccLat 195684500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36440000 # Total ticks spent in databus transfers +system.physmem.totBankLat 101337500 # Total ticks spent accessing banks +system.physmem.avgQLat 7945.53 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13904.71 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27186.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26850.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.83 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.81 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.83 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6000 # Number of row buffer hits during reads +system.physmem.readRowHits 5839 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.35 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.12 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9402120.02 # Average gap between requests -system.physmem.pageHitRate 82.35 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.05 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 6806039 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4462 # Transaction distribution -system.membus.trans_dist::ReadResp 4461 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 2824 # Transaction distribution -system.membus.trans_dist::ReadExResp 2824 # Transaction distribution +system.physmem.avgGap 9364084.25 # Average gap between requests +system.physmem.pageHitRate 80.12 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.16 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6833684 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4468 # Transaction distribution +system.membus.trans_dist::ReadResp 4467 # Transaction distribution +system.membus.trans_dist::ReadExReq 2820 # Transaction distribution +system.membus.trans_dist::ReadExResp 2820 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14575 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 14575 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466240 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 466240 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 466240 # Total data (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 466368 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 466368 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8931500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8915000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 67747998 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 67732500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 35407535 # Number of BP lookups -system.cpu.branchPred.condPredicted 21210003 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1658535 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19582924 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16814113 # Number of BTB hits +system.cpu.branchPred.lookups 35342667 # Number of BP lookups +system.cpu.branchPred.condPredicted 21189046 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1621967 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18355176 # Number of BTB lookups +system.cpu.branchPred.BTBHits 16729462 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 85.861095 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6780652 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 8453 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 91.143021 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6774978 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 8404 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -357,100 +335,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 137007735 # number of cpu cycles simulated +system.cpu.numCycles 136490945 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 38995510 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 317974758 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35407535 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23594765 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70934448 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6878177 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21511393 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 109 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1738 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37596145 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 512137 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136651264 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.983546 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454335 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 38825213 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 317051968 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35342667 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23504440 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70679896 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6716000 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21545367 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 106 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1322 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37451719 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 502899 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136134435 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.985255 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454681 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66349844 48.55% 48.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6791529 4.97% 53.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5702360 4.17% 57.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6103499 4.47% 62.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4918940 3.60% 65.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4085838 2.99% 68.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3180821 2.33% 71.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4138782 3.03% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35379651 25.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66077496 48.54% 48.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6747770 4.96% 53.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5691244 4.18% 57.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6070617 4.46% 62.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4899295 3.60% 65.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4080163 3.00% 68.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3177720 2.33% 71.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4131471 3.03% 74.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35258659 25.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136651264 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258435 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.320853 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45513422 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16662187 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66798256 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2538078 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5139321 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7340905 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69056 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401756741 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 208904 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5139321 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 51060721 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1905439 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 332675 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63727748 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14485360 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 394162913 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 18 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1657895 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10187119 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 22377 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 432668253 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2737675688 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1575239963 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 200387111 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 136134435 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258938 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.322879 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45319095 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16701200 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66547822 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2552537 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5013781 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7320658 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69067 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 400437341 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 211449 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5013781 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50843684 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1928767 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 335631 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63516277 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14496295 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 392925979 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 32 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1658279 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10203172 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 22306 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 431444746 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2730832248 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1570013245 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 200164445 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 48102060 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11946 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11945 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36528458 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103595819 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91394334 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4295156 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5297473 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 384542604 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22919 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 374214780 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1210476 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34753044 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 100302329 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 799 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136651264 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.738466 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.024544 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 46878553 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11940 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11939 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36493417 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103352368 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91160183 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4261604 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5303451 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 383671023 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22900 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 373754233 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1199031 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 33881433 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 97712598 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 780 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136134435 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.745479 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.022556 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 25105050 18.37% 18.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19938594 14.59% 32.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20566375 15.05% 48.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18171632 13.30% 61.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24028761 17.58% 78.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15737538 11.52% 90.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8814188 6.45% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3372330 2.47% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 916796 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24740289 18.17% 18.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19905513 14.62% 32.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20515084 15.07% 47.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18158642 13.34% 61.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24030824 17.65% 78.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15691878 11.53% 90.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8802431 6.47% 96.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3372838 2.48% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 916936 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136651264 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136134435 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8713 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4693 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8938 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4692 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -469,127 +447,127 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46317 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46049 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 3518 0.02% 0.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 440 0.00% 0.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 3482 0.02% 0.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 434 0.00% 0.36% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 186929 1.05% 1.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4248 0.02% 1.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241299 1.36% 2.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 186470 1.05% 1.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 3938 0.02% 1.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241178 1.36% 2.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9275439 52.33% 55.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7953254 44.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9277159 52.37% 55.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7942822 44.84% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126461637 33.79% 33.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2175765 0.58% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 4 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6779975 1.81% 36.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8474577 2.26% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3430301 0.92% 39.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1595259 0.43% 39.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20865413 5.58% 45.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7172902 1.92% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7130224 1.91% 49.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101650995 27.16% 76.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88302442 23.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126226981 33.77% 33.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2175715 0.58% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 4 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6775957 1.81% 36.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8464752 2.26% 38.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3426733 0.92% 39.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1595441 0.43% 39.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20845390 5.58% 45.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7170609 1.92% 47.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7125607 1.91% 49.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101514689 27.16% 76.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88257068 23.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 374214780 # Type of FU issued -system.cpu.iq.rate 2.731341 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17724852 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047365 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654627146 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 288999508 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 250114053 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249389006 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130333197 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118063719 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 263337797 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128601835 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11086522 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 373754233 # Type of FU issued +system.cpu.iq.rate 2.738308 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17715164 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047398 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653197592 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 287339977 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 249810515 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249359504 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130249499 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118015221 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 262881293 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128588104 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11104968 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8947071 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 108758 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14277 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9018751 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8703620 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 109542 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14223 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8784600 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 174712 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1900 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 184473 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1790 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5139321 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 272764 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 35129 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 384567184 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 874047 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103595819 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91394334 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11885 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 347 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 280 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14277 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1299093 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 369514 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1668607 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 370257441 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100364532 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3957339 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5013781 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 291002 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 36408 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 383695470 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 852736 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103352368 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91160183 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11866 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 327 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 282 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14223 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1256888 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 362770 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1619658 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 369836414 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100211998 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3917819 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1661 # number of nop insts executed -system.cpu.iew.exec_refs 187583075 # number of memory reference insts executed -system.cpu.iew.exec_branches 32009347 # Number of branches executed -system.cpu.iew.exec_stores 87218543 # Number of stores executed -system.cpu.iew.exec_rate 2.702456 # Inst execution rate -system.cpu.iew.wb_sent 368846220 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 368177772 # cumulative count of insts written-back -system.cpu.iew.wb_producers 183055174 # num instructions producing a value -system.cpu.iew.wb_consumers 363803620 # num instructions consuming a value +system.cpu.iew.exec_nop 1547 # number of nop insts executed +system.cpu.iew.exec_refs 187429987 # number of memory reference insts executed +system.cpu.iew.exec_branches 31988466 # Number of branches executed +system.cpu.iew.exec_stores 87217989 # Number of stores executed +system.cpu.iew.exec_rate 2.709604 # Inst execution rate +system.cpu.iew.wb_sent 368475660 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 367825736 # cumulative count of insts written-back +system.cpu.iew.wb_producers 182824140 # num instructions producing a value +system.cpu.iew.wb_consumers 363330392 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.687277 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.503170 # average fanout of values written-back +system.cpu.iew.wb_rate 2.694873 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.503190 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 35502239 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34630475 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1589851 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131511943 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.654246 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.658719 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1553283 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131120654 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.662167 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.659302 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34696225 26.38% 26.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28452590 21.63% 48.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13345612 10.15% 58.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11442919 8.70% 66.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13780020 10.48% 77.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7417113 5.64% 82.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3869989 2.94% 85.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3892889 2.96% 88.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14614586 11.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34358811 26.20% 26.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28410916 21.67% 47.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13299289 10.14% 58.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11469684 8.75% 66.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13783827 10.51% 77.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7406623 5.65% 82.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3875247 2.96% 85.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3903446 2.98% 88.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14612811 11.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131511943 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131120654 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -600,238 +578,230 @@ system.cpu.commit.branches 30563497 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14614586 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14612811 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 501462134 # The number of ROB reads -system.cpu.rob.rob_writes 774278104 # The number of ROB writes -system.cpu.timesIdled 6640 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 356471 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 500200856 # The number of ROB reads +system.cpu.rob.rob_writes 772408679 # The number of ROB writes +system.cpu.timesIdled 6691 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 356510 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated -system.cpu.cpi 0.501792 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.501792 # CPI: Total CPI of All Threads -system.cpu.ipc 1.992856 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.992856 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1769894079 # number of integer regfile reads -system.cpu.int_regfile_writes 233026497 # number of integer regfile writes -system.cpu.fp_regfile_reads 188140638 # number of floating regfile reads -system.cpu.fp_regfile_writes 132514898 # number of floating regfile writes -system.cpu.misc_regfile_reads 1201076625 # number of misc regfile reads +system.cpu.cpi 0.499900 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.499900 # CPI: Total CPI of All Threads +system.cpu.ipc 2.000402 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.000402 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1768035388 # number of integer regfile reads +system.cpu.int_regfile_writes 232615737 # number of integer regfile writes +system.cpu.fp_regfile_reads 188041949 # number of floating regfile reads +system.cpu.fp_regfile_writes 132439422 # number of floating regfile writes +system.cpu.misc_regfile_reads 1200568638 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.throughput 20069641 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 17607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 17606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1035 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2841 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2841 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31671 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10259 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 41930 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1013312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1374592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1374592 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 11777500 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 20175639 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 17638 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 17637 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1039 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2838 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2838 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31713 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10277 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 41990 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1014784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 362112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 1376896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1376896 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 11796500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24288488 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24305488 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7388212 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7381711 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 13947 # number of replacements -system.cpu.icache.tags.tagsinuse 1848.346697 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 37578823 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15836 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2372.999684 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13966 # number of replacements +system.cpu.icache.tags.tagsinuse 1849.581585 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 37434387 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15856 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2360.897263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1848.346697 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.902513 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.902513 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1889 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1849.581585 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.903116 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.903116 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1890 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 205 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 206 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1530 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.922363 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 75208123 # Number of tag accesses -system.cpu.icache.tags.data_accesses 75208123 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 37578823 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37578823 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37578823 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37578823 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37578823 # number of overall hits -system.cpu.icache.overall_hits::total 37578823 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17320 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17320 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17320 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17320 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17320 # number of overall misses -system.cpu.icache.overall_misses::total 17320 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 450229234 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 450229234 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 450229234 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 450229234 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 450229234 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 450229234 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37596143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37596143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37596143 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37596143 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37596143 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37596143 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000461 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000461 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000461 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000461 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000461 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000461 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25994.759469 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25994.759469 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25994.759469 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25994.759469 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25994.759469 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25994.759469 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2351 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::4 1531 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.922852 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 74919290 # Number of tag accesses +system.cpu.icache.tags.data_accesses 74919290 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 37434387 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37434387 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37434387 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37434387 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37434387 # number of overall hits +system.cpu.icache.overall_hits::total 37434387 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17330 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17330 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17330 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17330 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17330 # number of overall misses +system.cpu.icache.overall_misses::total 17330 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 451723484 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 451723484 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 451723484 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 451723484 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 451723484 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 451723484 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37451717 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37451717 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37451717 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37451717 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37451717 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37451717 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000463 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000463 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000463 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000463 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000463 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000463 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26065.982920 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 26065.982920 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 26065.982920 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 26065.982920 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 26065.982920 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 26065.982920 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1035 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 94.040000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 39.807692 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1482 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1482 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1482 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1482 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1482 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1482 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15838 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15838 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15838 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -841,185 +811,177 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 39 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 39 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 52 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3032 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1430 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4462 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2824 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2824 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3032 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 4254 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7286 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3032 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 4254 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7286 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 177153750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 90029000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 267182750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 164034250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 164034250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 177153750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 254063250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 431217000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 177153750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 254063250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 431217000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191487 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.808366 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253480 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994016 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994016 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191487 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922777 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.356388 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191487 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922777 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.356388 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58428.017810 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62957.342657 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59879.594352 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58085.782578 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58085.782578 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58428.017810 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59723.377997 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59184.326105 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58428.017810 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59723.377997 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59184.326105 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 39 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 51 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3029 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1439 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4468 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2820 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2820 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3029 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4259 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7288 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3029 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4259 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7288 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 176626500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 86490250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 263116750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 165285750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 165285750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176626500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 251776000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 428402500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176626500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 251776000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 428402500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191020 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807973 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253317 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993658 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993658 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191020 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922061 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.355929 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191020 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922061 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.355929 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58311.819082 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60104.412787 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58889.156222 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58611.968085 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58611.968085 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58311.819082 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59116.224466 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58781.901756 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58311.819082 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59116.224466 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58781.901756 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1413 # number of replacements -system.cpu.dcache.tags.tagsinuse 3103.986618 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 170973728 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4610 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37087.576573 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1416 # number of replacements +system.cpu.dcache.tags.tagsinuse 3111.494128 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170791722 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4619 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 36975.908638 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3103.986618 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.757809 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.757809 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3197 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 682 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2449 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.780518 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 342002086 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 342002086 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 88920204 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88920204 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031597 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031597 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11020 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11020 # number of LoadLockedReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 3111.494128 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.759642 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.759642 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3203 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 686 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2450 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.781982 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 341638239 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 341638239 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 88738255 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88738255 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031563 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031563 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11009 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11009 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170951801 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170951801 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170951801 # number of overall hits -system.cpu.dcache.overall_hits::total 170951801 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3952 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3952 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21068 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21068 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 170769818 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170769818 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170769818 # number of overall hits +system.cpu.dcache.overall_hits::total 170769818 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3984 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3984 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21102 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21102 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25020 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25020 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25020 # number of overall misses -system.cpu.dcache.overall_misses::total 25020 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 237491705 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 237491705 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1258064893 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1258064893 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 25086 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25086 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25086 # number of overall misses +system.cpu.dcache.overall_misses::total 25086 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 232475203 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 232475203 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1255700879 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1255700879 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1495556598 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1495556598 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1495556598 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1495556598 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88924156 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88924156 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 1488176082 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1488176082 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1488176082 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1488176082 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88742239 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88742239 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11022 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11022 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11011 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11011 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170976821 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170976821 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170976821 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170976821 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 170794904 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170794904 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170794904 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170794904 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000146 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000146 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000146 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000146 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60094.054909 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60094.054909 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59714.490839 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59714.490839 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58352.209588 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58352.209588 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59506.249597 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59506.249597 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59774.444365 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59774.444365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59774.444365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59774.444365 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 27944 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 406 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.827586 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 102 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59322.972255 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59322.972255 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59322.972255 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59322.972255 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 26768 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1267 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 424 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 63.132075 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 97.461538 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1035 # number of writebacks -system.cpu.dcache.writebacks::total 1035 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2181 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2181 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18227 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18227 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1039 # number of writebacks +system.cpu.dcache.writebacks::total 1039 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2202 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2202 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18265 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18265 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20408 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20408 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20408 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20408 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1771 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1771 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2841 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2841 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4612 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4612 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4612 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4612 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 115481540 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 115481540 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 201937248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 201937248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 317418788 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 317418788 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317418788 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 317418788 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 20467 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20467 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20467 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20467 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1782 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1782 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2837 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2837 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4619 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4619 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4619 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4619 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 111706789 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 111706789 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 203137000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 203137000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 314843789 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 314843789 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 314843789 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 314843789 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -1028,14 +990,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65206.967815 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65206.967815 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71079.636748 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71079.636748 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68824.542064 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68824.542064 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68824.542064 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68824.542064 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62686.189113 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62686.189113 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71602.749383 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71602.749383 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68162.760121 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68162.760121 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68162.760121 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68162.760121 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 130b22828..55140cd28 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.631518 # Number of seconds simulated -sim_ticks 631518097500 # Number of ticks simulated -final_tick 631518097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.629599 # Number of seconds simulated +sim_ticks 629599373500 # Number of ticks simulated +final_tick 629599373500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 171044 # Simulator instruction rate (inst/s) -host_op_rate 171044 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59250964 # Simulator tick rate (ticks/s) -host_mem_usage 240608 # Number of bytes of host memory used -host_seconds 10658.36 # Real time elapsed on the host +host_inst_rate 142688 # Simulator instruction rate (inst/s) +host_op_rate 142688 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49278187 # Simulator tick rate (ticks/s) +host_mem_usage 277460 # Number of bytes of host memory used +host_seconds 12776.43 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 176128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30295488 # Number of bytes read from this memory -system.physmem.bytes_read::total 30471616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 176128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 176128 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 176768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30295936 # Number of bytes read from this memory +system.physmem.bytes_read::total 30472704 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176768 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2752 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473367 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476119 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2762 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 473374 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476136 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 278896 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47972478 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48251374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 278896 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 278896 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6780664 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6780664 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6780664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 278896 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47972478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55032038 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476119 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 280763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48119387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48400150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 280763 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 280763 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6801328 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6801328 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6801328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 280763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48119387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55201478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476136 # Number of read requests accepted system.physmem.writeReqs 66908 # Number of write requests accepted -system.physmem.readBursts 476119 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 476136 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66908 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30465984 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue -system.physmem.bytesWritten 4281664 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30471616 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 30452800 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue +system.physmem.bytesWritten 4280256 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30472704 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4282112 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 29449 # Per bank write bursts -system.physmem.perBankRdBursts::1 29798 # Per bank write bursts -system.physmem.perBankRdBursts::2 29850 # Per bank write bursts -system.physmem.perBankRdBursts::3 29793 # Per bank write bursts -system.physmem.perBankRdBursts::4 29695 # Per bank write bursts -system.physmem.perBankRdBursts::5 29771 # Per bank write bursts -system.physmem.perBankRdBursts::6 29867 # Per bank write bursts -system.physmem.perBankRdBursts::7 29856 # Per bank write bursts -system.physmem.perBankRdBursts::8 29771 # Per bank write bursts -system.physmem.perBankRdBursts::9 29894 # Per bank write bursts -system.physmem.perBankRdBursts::10 29844 # Per bank write bursts -system.physmem.perBankRdBursts::11 29915 # Per bank write bursts -system.physmem.perBankRdBursts::12 29793 # Per bank write bursts -system.physmem.perBankRdBursts::13 29587 # Per bank write bursts -system.physmem.perBankRdBursts::14 29511 # Per bank write bursts -system.physmem.perBankRdBursts::15 29637 # Per bank write bursts +system.physmem.perBankRdBursts::0 29443 # Per bank write bursts +system.physmem.perBankRdBursts::1 29785 # Per bank write bursts +system.physmem.perBankRdBursts::2 29834 # Per bank write bursts +system.physmem.perBankRdBursts::3 29781 # Per bank write bursts +system.physmem.perBankRdBursts::4 29679 # Per bank write bursts +system.physmem.perBankRdBursts::5 29744 # Per bank write bursts +system.physmem.perBankRdBursts::6 29853 # Per bank write bursts +system.physmem.perBankRdBursts::7 29847 # Per bank write bursts +system.physmem.perBankRdBursts::8 29759 # Per bank write bursts +system.physmem.perBankRdBursts::9 29871 # Per bank write bursts +system.physmem.perBankRdBursts::10 29836 # Per bank write bursts +system.physmem.perBankRdBursts::11 29910 # Per bank write bursts +system.physmem.perBankRdBursts::12 29783 # Per bank write bursts +system.physmem.perBankRdBursts::13 29571 # Per bank write bursts +system.physmem.perBankRdBursts::14 29499 # Per bank write bursts +system.physmem.perBankRdBursts::15 29630 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -74,7 +74,7 @@ system.physmem.perBankWrBursts::6 4262 # Pe system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts system.physmem.perBankWrBursts::9 4334 # Per bank write bursts -system.physmem.perBankWrBursts::10 4241 # Per bank write bursts +system.physmem.perBankWrBursts::10 4219 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4100 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 631518039500 # Total gap between requests +system.physmem.totGap 629599315500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 476119 # Read request sizes (log2) +system.physmem.readPktSize::6 476136 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,11 +97,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66908 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 408579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 429 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 405282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66881 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3493 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -129,223 +129,175 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 2991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 2994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 182335 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 190.554573 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 126.681752 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 408.631079 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 68422 37.53% 37.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 48844 26.79% 64.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 37964 20.82% 85.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 20159 11.06% 96.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 264 0.14% 96.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 246 0.13% 96.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 141 0.08% 96.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 184 0.10% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 113 0.06% 96.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 137 0.08% 96.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 96 0.05% 96.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 186 0.10% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 81 0.04% 96.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 159 0.09% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 151 0.08% 97.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 133 0.07% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 108 0.06% 97.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 148 0.08% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 143 0.08% 97.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 80 0.04% 97.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 131 0.07% 97.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 1760 0.97% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 1531 0.84% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 10 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 19 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 18 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 8 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 14 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 14 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 13 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 14 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 6 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 10 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 10 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 20 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 12 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 11 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 18 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 13 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 12 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 17 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 12 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 11 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 14 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 18 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 12 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 10 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 14 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136 17 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 14 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 13 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 6 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 12 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 9 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 8 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 11 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648 18 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712 9 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776 16 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840 12 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904 17 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968 14 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032 15 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 5 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 16 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 14 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288 17 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 13 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416 15 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480 11 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544 18 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608 12 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672 8 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736 9 0.00% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 12 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864 6 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928 11 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 11 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 15 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 12 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184 12 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248 11 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312 16 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376 12 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440 11 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504 13 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568 16 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632 12 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696 12 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760 17 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824 10 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888 11 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952 22 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016 11 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080 8 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144 12 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208 26 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272 26 0.01% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336 39 0.02% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400 37 0.02% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464 7 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528 7 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592 6 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656 3 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720 7 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784 8 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848 54 0.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 182335 # Bytes accessed per row activation -system.physmem.totQLat 2888040000 # Total ticks spent queuing -system.physmem.totMemAccLat 14116017500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2380155000 # Total ticks spent in databus transfers -system.physmem.totBankLat 8847822500 # Total ticks spent accessing banks -system.physmem.avgQLat 6066.92 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 18586.65 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 21634 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 530.927244 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 283.070424 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 451.227629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7470 34.53% 34.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 2793 12.91% 47.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 292 1.35% 48.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 662 3.06% 51.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 618 2.86% 54.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 184 0.85% 55.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 105 0.49% 56.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 67 0.31% 56.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9443 43.65% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 21634 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4040 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 114.953218 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.941709 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1121.982719 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4021 99.53% 99.53% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-12287 1 0.02% 99.55% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 6 0.15% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 11 0.27% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4040 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4040 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.554208 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.524474 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.020237 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3080 76.24% 76.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 645 15.97% 92.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 312 7.72% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 2 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4040 # Writes before turning the bus around for reads +system.physmem.totQLat 3865744500 # Total ticks spent queuing +system.physmem.totMemAccLat 15098494500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2379125000 # Total ticks spent in databus transfers +system.physmem.totBankLat 8853625000 # Total ticks spent accessing banks +system.physmem.avgQLat 8124.30 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 18606.89 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29653.57 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 48.24 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.78 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 48.25 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 6.78 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31731.19 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 48.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.80 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 48.40 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 6.80 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.43 # Data bus utilization in percentage system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.28 # Average write queue length when enqueuing -system.physmem.readRowHits 310714 # Number of row buffer hits during reads -system.physmem.writeRowHits 49883 # Number of row buffer hits during writes -system.physmem.readRowHitRate 65.27 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.55 # Row buffer hit rate for writes -system.physmem.avgGap 1162958.82 # Average gap between requests -system.physmem.pageHitRate 66.42 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 25.73 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 55031937 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 409266 # Transaction distribution -system.membus.trans_dist::ReadResp 409265 # Transaction distribution +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing +system.physmem.readRowHits 304858 # Number of row buffer hits during reads +system.physmem.writeRowHits 50638 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes +system.physmem.avgGap 1159389.14 # Average gap between requests +system.physmem.pageHitRate 65.50 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 25.10 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 55201376 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 409283 # Transaction distribution +system.membus.trans_dist::ReadResp 409282 # Transaction distribution system.membus.trans_dist::Writeback 66908 # Transaction distribution system.membus.trans_dist::ReadExReq 66853 # Transaction distribution system.membus.trans_dist::ReadExResp 66853 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019145 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1019145 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34753664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34753664 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34753664 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019179 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1019179 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34754752 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34754752 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34754752 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1230652000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1216217500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4488013500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4476344750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 388926557 # Number of BP lookups -system.cpu.branchPred.condPredicted 255987580 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 25808786 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 317451636 # Number of BTB lookups -system.cpu.branchPred.BTBHits 258383726 # Number of BTB hits +system.cpu.branchPred.lookups 388794194 # Number of BP lookups +system.cpu.branchPred.condPredicted 256437181 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 25515612 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 316966671 # Number of BTB lookups +system.cpu.branchPred.BTBHits 257889505 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.393100 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 57269217 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 6785 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.361710 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 56977055 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 6765 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 522276153 # DTB read hits -system.cpu.dtb.read_misses 591029 # DTB read misses +system.cpu.dtb.read_hits 520530320 # DTB read hits +system.cpu.dtb.read_misses 596868 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 522867182 # DTB read accesses -system.cpu.dtb.write_hits 283024283 # DTB write hits -system.cpu.dtb.write_misses 50282 # DTB write misses +system.cpu.dtb.read_accesses 521127188 # DTB read accesses +system.cpu.dtb.write_hits 282735636 # DTB write hits +system.cpu.dtb.write_misses 50248 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 283074565 # DTB write accesses -system.cpu.dtb.data_hits 805300436 # DTB hits -system.cpu.dtb.data_misses 641311 # DTB misses +system.cpu.dtb.write_accesses 282785884 # DTB write accesses +system.cpu.dtb.data_hits 803265956 # DTB hits +system.cpu.dtb.data_misses 647116 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 805941747 # DTB accesses -system.cpu.itb.fetch_hits 394923336 # ITB hits -system.cpu.itb.fetch_misses 673 # ITB misses +system.cpu.dtb.data_accesses 803913072 # DTB accesses +system.cpu.itb.fetch_hits 392575649 # ITB hits +system.cpu.itb.fetch_misses 637 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 394924009 # ITB accesses +system.cpu.itb.fetch_accesses 392576286 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -359,238 +311,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1263036196 # number of cpu cycles simulated +system.cpu.numCycles 1259198748 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 410109214 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3275361918 # Number of instructions fetch has processed -system.cpu.fetch.Branches 388926557 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 315652943 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 630278695 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 157942220 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 76359250 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 149 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7183 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 394923336 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11250823 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1248398019 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.623652 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.139094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 407695740 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3264617465 # Number of instructions fetch has processed +system.cpu.fetch.Branches 388794194 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 314866560 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 628012855 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 156754099 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 76226521 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 146 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6801 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 392575649 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11023705 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1242691149 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.627055 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.139887 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 618119324 49.51% 49.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 57470502 4.60% 54.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43321703 3.47% 57.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71848580 5.76% 63.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129169735 10.35% 73.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46220345 3.70% 77.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41223036 3.30% 80.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7614963 0.61% 81.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 233409831 18.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 614678294 49.46% 49.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 57194010 4.60% 54.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43037577 3.46% 57.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71548664 5.76% 63.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 128942698 10.38% 73.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 45555972 3.67% 77.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41222741 3.32% 80.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8274333 0.67% 81.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 232236860 18.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1248398019 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.307930 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.593245 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 438388192 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 62722156 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 606598506 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9057712 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 131631453 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 31714965 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12425 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3194311917 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46335 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 131631453 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 467678494 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 27888696 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 27235 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 586017174 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 35154967 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3095577926 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 161 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 15278 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 28853292 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2054701913 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3579840200 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3494452830 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 85387369 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1242691149 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.308763 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.592615 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 436055809 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 62292865 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 604244409 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9361042 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 130737024 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 31725769 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12419 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3186787270 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46304 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 130737024 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 465340122 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 27154826 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 26997 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 583972819 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 35459361 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3088232608 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 174 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 15483 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 29158265 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2049406757 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3572462908 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3487065334 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 85397573 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 669732843 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4230 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 109697167 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 743928173 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 351370571 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 69056444 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8824928 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2623617019 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 88 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2160251371 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17943532 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 800506398 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 726504541 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1248398019 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.730419 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.803325 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 664437687 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4235 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 98 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 110031896 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 740965992 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 350476523 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68460641 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8808840 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2617422170 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 92 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2156741664 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17943359 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 794308745 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 722892982 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 53 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1242691149 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.735541 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.803084 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 451794387 36.19% 36.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 196881068 15.77% 51.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 251357257 20.13% 72.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120660419 9.67% 81.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 104720933 8.39% 90.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79314003 6.35% 96.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 24236778 1.94% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17665275 1.42% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1767899 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 447799861 36.03% 36.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 195733301 15.75% 51.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 250780419 20.18% 71.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120973704 9.73% 81.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 105324665 8.48% 90.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 78133504 6.29% 96.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 24822476 2.00% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17360375 1.40% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1762844 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1248398019 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1242691149 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1146213 3.11% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 25664248 69.68% 72.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 10022787 27.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1146236 3.14% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 25360136 69.42% 72.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 10022546 27.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1234386709 57.14% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 17098 0.00% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27851280 1.29% 58.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254692 0.38% 58.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204649 0.33% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 589426190 27.29% 86.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 293107997 13.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1232941102 57.17% 57.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 17091 0.00% 57.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27851332 1.29% 58.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254696 0.38% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204650 0.33% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587650943 27.25% 86.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 292819094 13.58% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2160251371 # Type of FU issued -system.cpu.iq.rate 1.710364 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36833248 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017050 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5472576321 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3336085108 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1990052081 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 151101220 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88112403 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 73609796 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2119632115 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 77449752 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62130294 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2156741664 # Type of FU issued +system.cpu.iq.rate 1.712789 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36528918 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016937 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5459545573 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3323652243 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1987168817 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 151101181 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 88152162 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 73609871 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2115818130 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 77449700 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62140575 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 232858147 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 12904 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76517 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 140575675 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 229895966 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17367 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 75928 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 139681627 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4420 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2986 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4415 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2851 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 131631453 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13854870 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540713 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2987064964 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 734565 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 743928173 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 351370571 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 134613 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 130737024 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13158740 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 531547 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2980853453 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 734148 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 740965992 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 350476523 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 92 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 133073 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 1496 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76517 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 25801220 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 30372 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 25831592 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2066130188 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 522867337 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 94121183 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 75928 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 25509079 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 28871 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25537950 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2062960594 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 521127327 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 93781070 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363447857 # number of nop insts executed -system.cpu.iew.exec_refs 805942372 # number of memory reference insts executed -system.cpu.iew.exec_branches 277625839 # Number of branches executed -system.cpu.iew.exec_stores 283075035 # Number of stores executed -system.cpu.iew.exec_rate 1.635844 # Inst execution rate -system.cpu.iew.wb_sent 2066015513 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2063661877 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1180966911 # num instructions producing a value -system.cpu.iew.wb_consumers 1753315239 # num instructions consuming a value +system.cpu.iew.exec_nop 363431191 # number of nop insts executed +system.cpu.iew.exec_refs 803913709 # number of memory reference insts executed +system.cpu.iew.exec_branches 277349504 # Number of branches executed +system.cpu.iew.exec_stores 282786382 # Number of stores executed +system.cpu.iew.exec_rate 1.638312 # Inst execution rate +system.cpu.iew.wb_sent 2062843616 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2060778688 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1180081311 # num instructions producing a value +system.cpu.iew.wb_consumers 1751769057 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.633890 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.673562 # average fanout of values written-back +system.cpu.iew.wb_rate 1.636579 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.673651 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 961121274 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 954910834 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 25796748 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1116766566 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.798932 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.506928 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 25503576 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1111954125 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.806718 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.513025 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 497624741 44.56% 44.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 228755331 20.48% 65.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119853188 10.73% 75.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 58815833 5.27% 81.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 50567042 4.53% 85.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24161277 2.16% 87.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19140455 1.71% 89.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 16628477 1.49% 90.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101220222 9.06% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 493953799 44.42% 44.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 227598258 20.47% 64.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 120157352 10.81% 75.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 59117436 5.32% 81.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 49692095 4.47% 85.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24169379 2.17% 87.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 18838880 1.69% 89.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 16341629 1.47% 90.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102085297 9.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1116766566 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1111954125 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -601,229 +553,229 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 101220222 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 102085297 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3980018812 # The number of ROB reads -system.cpu.rob.rob_writes 6071851301 # The number of ROB writes -system.cpu.timesIdled 346634 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 14638177 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3968130856 # The number of ROB reads +system.cpu.rob.rob_writes 6058536012 # The number of ROB writes +system.cpu.timesIdled 350219 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16507599 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.692817 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.692817 # CPI: Total CPI of All Threads -system.cpu.ipc 1.443382 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.443382 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2627972093 # number of integer regfile reads -system.cpu.int_regfile_writes 1496658985 # number of integer regfile writes -system.cpu.fp_regfile_reads 78811105 # number of floating regfile reads -system.cpu.fp_regfile_writes 52661052 # number of floating regfile writes +system.cpu.cpi 0.690712 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.690712 # CPI: Total CPI of All Threads +system.cpu.ipc 1.447780 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.447780 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2624503768 # number of integer regfile reads +system.cpu.int_regfile_writes 1494046892 # number of integer regfile writes +system.cpu.fp_regfile_reads 78811207 # number of floating regfile reads +system.cpu.fp_regfile_writes 52661075 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 165988542 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1470277 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1470276 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 95971 # Transaction distribution +system.cpu.toL2Bus.throughput 166495312 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1470280 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1470279 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 95977 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 71640 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 71640 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20049 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159755 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3179804 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 641536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104183232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 104824768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 104824768 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20109 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159707 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3179816 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 643456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104181888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 104825344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 104825344 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 914915000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 914925500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 15531000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 15572000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2359590250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2358250250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 8311 # number of replacements -system.cpu.icache.tags.tagsinuse 1658.001589 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 394910393 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 10024 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 39396.487729 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 8345 # number of replacements +system.cpu.icache.tags.tagsinuse 1652.999012 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 392562699 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 10054 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 39045.424607 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1658.001589 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.809571 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.809571 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1713 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1652.999012 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.807128 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.807128 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1709 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1567 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.836426 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 789856696 # Number of tag accesses -system.cpu.icache.tags.data_accesses 789856696 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 394910393 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 394910393 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 394910393 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 394910393 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 394910393 # number of overall hits -system.cpu.icache.overall_hits::total 394910393 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12943 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12943 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12943 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12943 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12943 # number of overall misses -system.cpu.icache.overall_misses::total 12943 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 383664999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 383664999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 383664999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 383664999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 383664999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 383664999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 394923336 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 394923336 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 394923336 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 394923336 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 394923336 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 394923336 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 1553 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.834473 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 785161352 # Number of tag accesses +system.cpu.icache.tags.data_accesses 785161352 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 392562699 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 392562699 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 392562699 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 392562699 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 392562699 # number of overall hits +system.cpu.icache.overall_hits::total 392562699 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12950 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12950 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12950 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12950 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12950 # number of overall misses +system.cpu.icache.overall_misses::total 12950 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 384762999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 384762999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 384762999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 384762999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 384762999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 384762999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 392575649 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 392575649 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 392575649 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 392575649 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 392575649 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 392575649 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29642.663911 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29642.663911 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29642.663911 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29642.663911 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29642.663911 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29642.663911 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 707 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29711.428494 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29711.428494 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29711.428494 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29711.428494 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29711.428494 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29711.428494 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 621 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 54.384615 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 47.769231 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2918 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2918 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2918 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2918 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2918 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2918 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10025 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10025 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10025 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10025 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10025 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10025 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281678249 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281678249 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281678249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281678249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281678249 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281678249 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28097.580948 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28097.580948 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28097.580948 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 28097.580948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28097.580948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 28097.580948 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2895 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2895 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2895 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2895 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2895 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2895 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10055 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10055 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10055 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10055 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10055 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10055 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 283775749 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 283775749 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 283775749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 283775749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 283775749 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 283775749 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000026 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28222.351964 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28222.351964 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28222.351964 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28222.351964 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28222.351964 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28222.351964 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 443340 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32689.012035 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1090033 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 476076 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.289620 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 443357 # 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average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.274689 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309018 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.308794 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.274689 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309018 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.308794 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60085.626358 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.048910 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60822.045504 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72824.727387 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72824.727387 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60085.626358 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62521.440235 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62507.310411 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60085.626358 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62521.440235 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62507.310411 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1527796 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.588575 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 667945835 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1531892 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 436.026714 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 408904250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.588575 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1527769 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.584887 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 666211737 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1531865 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 434.902382 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 409920250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.584887 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999655 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999655 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 284 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 969 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 967 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2365 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 392 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 390 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1343398986 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1343398986 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 458212871 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 458212871 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 209732941 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 209732941 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 23 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 23 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 667945812 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 667945812 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 667945812 # number of overall hits -system.cpu.dcache.overall_hits::total 667945812 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1925756 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1925756 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1061955 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1061955 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 1339886951 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1339886951 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 456456827 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 456456827 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 209754882 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 209754882 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 28 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 28 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 666211709 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 666211709 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 666211709 # number of overall hits +system.cpu.dcache.overall_hits::total 666211709 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1925791 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1925791 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1040014 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1040014 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2987711 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2987711 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2987711 # number of overall misses -system.cpu.dcache.overall_misses::total 2987711 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 77391157750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 77391157750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 46191876602 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 46191876602 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 78000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 78000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 123583034352 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 123583034352 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 123583034352 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 123583034352 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 460138627 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 460138627 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2965805 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2965805 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2965805 # number of overall misses +system.cpu.dcache.overall_misses::total 2965805 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 77884724250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 77884724250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 53548786128 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 53548786128 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 73000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 73000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 131433510378 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 131433510378 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 131433510378 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 131433510378 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 458382618 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 458382618 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 24 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 24 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 670933523 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 670933523 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 670933523 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 670933523 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004185 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004185 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005038 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005038 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.041667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.041667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004453 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004453 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004453 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004453 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40187.416137 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40187.416137 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43497.018802 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43497.018802 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41363.784634 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41363.784634 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41363.784634 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41363.784634 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17901 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 132 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 338 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 29 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 669177514 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 669177514 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 669177514 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 669177514 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004201 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004201 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004934 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.004934 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034483 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034483 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004432 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004432 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004432 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004432 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40442.978625 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40442.978625 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51488.524316 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51488.524316 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 73000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 73000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 44316.302110 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 44316.302110 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 44316.302110 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 44316.302110 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 18203 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 134 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 374 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.961538 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 132 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.671123 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 134 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 95971 # number of writebacks -system.cpu.dcache.writebacks::total 95971 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465505 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 465505 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990315 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 990315 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1455820 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1455820 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1455820 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1455820 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460251 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460251 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 95977 # number of writebacks +system.cpu.dcache.writebacks::total 95977 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465566 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 465566 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 968374 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 968374 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1433940 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1433940 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1433940 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1433940 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460225 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460225 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71640 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 71640 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1531891 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1531891 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1531891 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1531891 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41321289000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 41321289000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5347166250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5347166250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 76000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 76000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46668455250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46668455250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46668455250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46668455250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003174 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003174 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1531865 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1531865 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1531865 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1531865 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41848820250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 41848820250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5798224000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5798224000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47647044250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 47647044250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47647044250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47647044250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003186 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003186 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041667 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041667 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002283 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002283 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28297.387915 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28297.387915 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74639.394891 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74639.394891 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 76000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 76000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30464.605674 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30464.605674 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30464.605674 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30464.605674 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002289 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002289 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002289 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002289 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28659.158863 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28659.158863 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80935.566723 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80935.566723 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31103.944701 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31103.944701 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31103.944701 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31103.944701 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index b6f8c26dc..067d517cb 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.629535 # Number of seconds simulated -sim_ticks 629535413500 # Number of ticks simulated -final_tick 629535413500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.629657 # Number of seconds simulated +sim_ticks 629657386500 # Number of ticks simulated +final_tick 629657386500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 106173 # Simulator instruction rate (inst/s) -host_op_rate 144593 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48281629 # Simulator tick rate (ticks/s) -host_mem_usage 278772 # Number of bytes of host memory used -host_seconds 13038.82 # Real time elapsed on the host +host_inst_rate 85982 # Simulator instruction rate (inst/s) +host_op_rate 117096 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39107572 # Simulator tick rate (ticks/s) +host_mem_usage 322024 # Number of bytes of host memory used +host_seconds 16100.65 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 155136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30242496 # Number of bytes read from this memory -system.physmem.bytes_read::total 30397632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 155136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 155136 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 155392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30242880 # Number of bytes read from this memory +system.physmem.bytes_read::total 30398272 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 155392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 155392 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472539 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2428 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 472545 # Number of read requests responded to by this memory +system.physmem.num_reads::total 474973 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 246429 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48039388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48285817 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 246429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 246429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6719673 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6719673 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6719673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 246429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48039388 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55005490 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 474963 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 246788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48030692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48277480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 246788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 246788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6718371 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6718371 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6718371 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 246788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48030692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54995851 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 474973 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 474963 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 474973 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30390400 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue -system.physmem.bytesWritten 4229888 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30397632 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 30370688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 27584 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228672 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30398272 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 431 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4262 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 29871 # Per bank write bursts -system.physmem.perBankRdBursts::1 29675 # Per bank write bursts -system.physmem.perBankRdBursts::2 29749 # Per bank write bursts -system.physmem.perBankRdBursts::3 29712 # Per bank write bursts -system.physmem.perBankRdBursts::4 29816 # Per bank write bursts -system.physmem.perBankRdBursts::5 29834 # Per bank write bursts -system.physmem.perBankRdBursts::6 29642 # Per bank write bursts -system.physmem.perBankRdBursts::7 29444 # Per bank write bursts -system.physmem.perBankRdBursts::8 29480 # Per bank write bursts -system.physmem.perBankRdBursts::9 29489 # Per bank write bursts -system.physmem.perBankRdBursts::10 29547 # Per bank write bursts -system.physmem.perBankRdBursts::11 29649 # Per bank write bursts -system.physmem.perBankRdBursts::12 29701 # Per bank write bursts -system.physmem.perBankRdBursts::13 29813 # Per bank write bursts -system.physmem.perBankRdBursts::14 29629 # Per bank write bursts -system.physmem.perBankRdBursts::15 29799 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 4296 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 29858 # Per bank write bursts +system.physmem.perBankRdBursts::1 29659 # Per bank write bursts +system.physmem.perBankRdBursts::2 29728 # Per bank write bursts +system.physmem.perBankRdBursts::3 29690 # Per bank write bursts +system.physmem.perBankRdBursts::4 29781 # Per bank write bursts +system.physmem.perBankRdBursts::5 29808 # Per bank write bursts +system.physmem.perBankRdBursts::6 29619 # Per bank write bursts +system.physmem.perBankRdBursts::7 29428 # Per bank write bursts +system.physmem.perBankRdBursts::8 29461 # Per bank write bursts +system.physmem.perBankRdBursts::9 29473 # Per bank write bursts +system.physmem.perBankRdBursts::10 29524 # Per bank write bursts +system.physmem.perBankRdBursts::11 29641 # Per bank write bursts +system.physmem.perBankRdBursts::12 29683 # Per bank write bursts +system.physmem.perBankRdBursts::13 29785 # Per bank write bursts +system.physmem.perBankRdBursts::14 29611 # Per bank write bursts +system.physmem.perBankRdBursts::15 29793 # Per bank write bursts system.physmem.perBankWrBursts::0 4174 # Per bank write bursts -system.physmem.perBankWrBursts::1 4102 # Per bank write bursts -system.physmem.perBankWrBursts::2 4138 # Per bank write bursts -system.physmem.perBankWrBursts::3 4148 # Per bank write bursts -system.physmem.perBankWrBursts::4 4226 # Per bank write bursts -system.physmem.perBankWrBursts::5 4224 # Per bank write bursts -system.physmem.perBankWrBursts::6 4173 # Per bank write bursts -system.physmem.perBankWrBursts::7 4096 # Per bank write bursts -system.physmem.perBankWrBursts::8 4096 # Per bank write bursts +system.physmem.perBankWrBursts::1 4100 # Per bank write bursts +system.physmem.perBankWrBursts::2 4137 # Per bank write bursts +system.physmem.perBankWrBursts::3 4146 # Per bank write bursts +system.physmem.perBankWrBursts::4 4223 # Per bank write bursts +system.physmem.perBankWrBursts::5 4223 # Per bank write bursts +system.physmem.perBankWrBursts::6 4171 # Per bank write bursts +system.physmem.perBankWrBursts::7 4094 # Per bank write bursts +system.physmem.perBankWrBursts::8 4094 # Per bank write bursts system.physmem.perBankWrBursts::9 4093 # Per bank write bursts -system.physmem.perBankWrBursts::10 4095 # Per bank write bursts +system.physmem.perBankWrBursts::10 4093 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::13 4094 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts system.physmem.perBankWrBursts::15 4140 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 629535350500 # Total gap between requests +system.physmem.totGap 629657309500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 474963 # Read request sizes (log2) +system.physmem.readPktSize::6 474973 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,11 +97,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -129,194 +129,157 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 190822 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 181.419082 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 122.160667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 377.205430 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 76972 40.34% 40.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 49989 26.20% 66.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 37639 19.72% 86.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 19482 10.21% 96.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 187 0.10% 96.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 252 0.13% 96.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 85 0.04% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 218 0.11% 96.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 85 0.04% 96.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 231 0.12% 97.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 52 0.03% 97.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 225 0.12% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 65 0.03% 97.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 188 0.10% 97.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 60 0.03% 97.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 181 0.09% 97.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 44 0.02% 97.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 201 0.11% 97.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 67 0.04% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 181 0.09% 97.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 66 0.03% 97.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 3167 1.66% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 20 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 13 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 12 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 12 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 13 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 17 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 15 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 15 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 19 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 10 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 18 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 13 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 11 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 14 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 14 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 15 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 21 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 12 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 17 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 16 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 16 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 13 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 12 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 12 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 14 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 9 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136 19 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 10 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 20 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 10 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 16 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 12 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 21 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 13 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648 16 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712 15 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776 18 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840 7 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904 15 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968 17 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032 14 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 12 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 28 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 16 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288 14 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 7 0.00% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416 17 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480 11 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544 14 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608 12 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672 19 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736 10 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 13 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864 9 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928 17 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 8 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 17 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 7 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184 9 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248 9 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312 13 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376 11 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440 14 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504 12 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568 15 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632 15 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696 31 0.02% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760 73 0.04% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824 59 0.03% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888 4 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952 3 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016 6 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080 8 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144 53 0.03% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 190822 # Bytes accessed per row activation -system.physmem.totQLat 3804806750 # Total ticks spent queuing -system.physmem.totMemAccLat 15248020500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2374250000 # Total ticks spent in databus transfers -system.physmem.totBankLat 9068963750 # Total ticks spent accessing banks -system.physmem.avgQLat 8012.65 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 19098.59 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 28167 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 403.324742 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 187.656646 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 439.024801 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14746 52.35% 52.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 2789 9.90% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 571 2.03% 64.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 164 0.58% 64.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 93 0.33% 65.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 524 1.86% 67.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 314 1.11% 68.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 86 0.31% 68.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8880 31.53% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 28167 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3992 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.707415 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.187766 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.851977 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 3989 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.03% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::31744-32767 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3992 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3992 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.551353 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.521439 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.024563 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3052 76.45% 76.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 627 15.71% 92.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 310 7.77% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 1 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3992 # Writes before turning the bus around for reads +system.physmem.totQLat 3604221250 # Total ticks spent queuing +system.physmem.totMemAccLat 15074013750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2372710000 # Total ticks spent in databus transfers +system.physmem.totBankLat 9097082500 # Total ticks spent accessing banks +system.physmem.avgQLat 7595.16 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 19170.24 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32111.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 48.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31765.39 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 48.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 6.72 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 48.29 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 48.28 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 6.72 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.43 # Data bus utilization in percentage system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 6.84 # Average write queue length when enqueuing -system.physmem.readRowHits 300749 # Number of row buffer hits during reads -system.physmem.writeRowHits 49371 # Number of row buffer hits during writes -system.physmem.readRowHitRate 63.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.69 # Row buffer hit rate for writes -system.physmem.avgGap 1163520.10 # Average gap between requests -system.physmem.pageHitRate 64.72 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 24.30 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 55005389 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 408886 # Transaction distribution -system.membus.trans_dist::ReadResp 408885 # Transaction distribution +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing +system.physmem.readRowHits 295971 # Number of row buffer hits during reads +system.physmem.writeRowHits 49954 # Number of row buffer hits during writes +system.physmem.readRowHitRate 62.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.58 # Row buffer hit rate for writes +system.physmem.avgGap 1163724.00 # Average gap between requests +system.physmem.pageHitRate 63.98 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 24.27 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 54995851 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 408896 # Transaction distribution +system.membus.trans_dist::ReadResp 408896 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4262 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4262 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4296 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4296 # Transaction distribution system.membus.trans_dist::ReadExReq 66077 # Transaction distribution system.membus.trans_dist::ReadExResp 66077 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024547 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1024547 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34627840 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34627840 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34627840 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024636 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1024636 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34628544 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34628544 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34628544 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1215457500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1215525500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4442862738 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4444359954 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 438247722 # Number of BP lookups -system.cpu.branchPred.condPredicted 350864471 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 30620817 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 248480162 # Number of BTB lookups -system.cpu.branchPred.BTBHits 229339460 # Number of BTB hits +system.cpu.branchPred.lookups 438199522 # Number of BP lookups +system.cpu.branchPred.condPredicted 350949441 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 30620410 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 248742563 # Number of BTB lookups +system.cpu.branchPred.BTBHits 229772650 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.296889 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 52915671 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2805331 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.373676 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 52962534 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2805242 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -402,100 +365,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1259070828 # number of cpu cycles simulated +system.cpu.numCycles 1259314774 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 354141020 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2279761292 # Number of instructions fetch has processed -system.cpu.fetch.Branches 438247722 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 282255131 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 601258233 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 157188182 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 134732573 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11340 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 159 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 334734643 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11658358 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1216659303 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.575913 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.175897 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 354212583 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2278943291 # Number of instructions fetch has processed +system.cpu.fetch.Branches 438199522 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 282735184 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 601285341 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 157201665 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 134990206 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 592 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11080 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 114 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 334803997 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11648696 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1217029612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.574413 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.174582 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 615445842 50.58% 50.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42369042 3.48% 54.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 95794203 7.87% 61.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 57788183 4.75% 66.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 71908380 5.91% 72.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 44699403 3.67% 76.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31096366 2.56% 78.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31485891 2.59% 81.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226071993 18.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 615789102 50.60% 50.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42212896 3.47% 54.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 95956201 7.88% 61.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 57716133 4.74% 66.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 72254915 5.94% 72.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 44707595 3.67% 76.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31168110 2.56% 78.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31500430 2.59% 81.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 225724230 18.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1216659303 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.348072 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.810670 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 405371770 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 106745247 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 560687148 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17351012 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 126504126 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 44828011 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11498 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3022924000 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 26519 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 126504126 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 441422956 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38086039 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 457739 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 539750713 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 70437730 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2941757147 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 93 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4808697 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 54385461 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 740 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2930215043 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14237570542 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12151139431 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 84006834 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1217029612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.347967 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.809669 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 405265267 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 107157501 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 560735859 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17352207 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 126518778 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 44627065 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11198 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3022541715 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25538 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 126518778 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 441244328 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38456610 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 454301 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 539911121 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 70444474 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2941731616 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 86 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4811465 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 54362751 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 733 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2929353177 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14237214542 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12151315514 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 83979009 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 937074953 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20556 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18072 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 179296103 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 971747851 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 485687926 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 36754298 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 38315968 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2792666387 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27976 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2435151733 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13267287 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 894813074 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2341267254 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6592 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1216659303 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.001507 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.873340 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 936213087 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20203 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 17724 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 179723252 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 971631963 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 486198822 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36723664 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 38677099 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2793016392 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27622 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2435260833 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13305109 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 895166670 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2343525890 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6238 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1217029612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.000987 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.873461 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 380682463 31.29% 31.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183043299 15.04% 46.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 204121257 16.78% 63.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 169552429 13.94% 77.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 132904836 10.92% 87.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 92976040 7.64% 95.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37964484 3.12% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12393775 1.02% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3020720 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 381057421 31.31% 31.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183026992 15.04% 46.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 204041316 16.77% 63.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 169676462 13.94% 77.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 132865899 10.92% 87.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 92968001 7.64% 95.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 37978061 3.12% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12373824 1.02% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3041636 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1216659303 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1217029612 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 714585 0.82% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24381 0.03% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 714935 0.82% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24383 0.03% 0.84% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available @@ -523,13 +486,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55158409 62.92% 63.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 31764976 36.24% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55166828 62.92% 63.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 31766374 36.23% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1104245990 45.35% 45.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11223912 0.46% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1104417509 45.35% 45.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11223990 0.46% 45.81% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.81% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.81% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.81% # Type of FU issued @@ -548,93 +511,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.81% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.81% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.81% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876479 0.28% 46.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5502438 0.23% 46.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23399832 0.96% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 840060400 34.50% 81.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 442467389 18.17% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876473 0.28% 46.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5501794 0.23% 46.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23394204 0.96% 47.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 839996872 34.49% 81.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 442474698 18.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2435151733 # Type of FU issued -system.cpu.iq.rate 1.934086 # Inst issue rate -system.cpu.iq.fu_busy_cnt 87662351 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.035999 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6065394864 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3604907210 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2250139818 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 122497543 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82667139 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56433103 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2459502901 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 63311183 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 84462690 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2435260833 # Type of FU issued +system.cpu.iq.rate 1.933798 # Inst issue rate +system.cpu.iq.fu_busy_cnt 87672520 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.036001 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6066045738 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3605651148 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2250091074 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 122483169 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 82625914 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56426435 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2459629474 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63303879 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 84463938 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 340360670 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 9529 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1430281 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 208692629 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 340244782 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 10257 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1430041 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 209203525 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 365 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 356 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 126504126 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16045638 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1563592 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2792706809 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1386483 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 971747851 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 485687926 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 17990 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1559989 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2525 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1430281 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 32383306 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1525297 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 33908603 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2359934527 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 794158761 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 75217206 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 126518778 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16487163 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1561706 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2793056470 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1389243 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 971631963 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 486198822 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 17636 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1558036 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2522 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1430041 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 32401956 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1516006 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 33917962 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2359922616 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 794093704 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 75338217 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12446 # number of nop insts executed -system.cpu.iew.exec_refs 1217435347 # number of memory reference insts executed -system.cpu.iew.exec_branches 319532182 # Number of branches executed -system.cpu.iew.exec_stores 423276586 # Number of stores executed -system.cpu.iew.exec_rate 1.874346 # Inst execution rate -system.cpu.iew.wb_sent 2332318600 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2306572921 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1349155649 # num instructions producing a value -system.cpu.iew.wb_consumers 2527421878 # num instructions consuming a value +system.cpu.iew.exec_nop 12456 # number of nop insts executed +system.cpu.iew.exec_refs 1217365234 # number of memory reference insts executed +system.cpu.iew.exec_branches 319562430 # Number of branches executed +system.cpu.iew.exec_stores 423271530 # Number of stores executed +system.cpu.iew.exec_rate 1.873974 # Inst execution rate +system.cpu.iew.wb_sent 2332280723 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2306517509 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1349120960 # num instructions producing a value +system.cpu.iew.wb_consumers 2527351065 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.831964 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.533807 # average fanout of values written-back +system.cpu.iew.wb_rate 1.831566 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.533808 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 907370579 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 907720231 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 30609580 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1090155177 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.729420 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.397089 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 30609492 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1090510834 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.728856 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.396955 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 449868742 41.27% 41.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288583282 26.47% 67.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95106533 8.72% 76.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 70222065 6.44% 82.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46473839 4.26% 87.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22181225 2.03% 89.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15848509 1.45% 90.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10986576 1.01% 91.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90884406 8.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 450229589 41.29% 41.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288600221 26.46% 67.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95089363 8.72% 76.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 70207190 6.44% 82.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46482431 4.26% 87.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22180112 2.03% 89.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15844912 1.45% 90.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10980043 1.01% 91.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 90896973 8.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1090155177 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1090510834 # Number of insts commited each cycle system.cpu.commit.committedInsts 1384381606 # Number of instructions committed system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -645,240 +608,240 @@ system.cpu.commit.branches 298259106 # Nu system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 90884406 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 90896973 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3791959363 # The number of ROB reads -system.cpu.rob.rob_writes 5711929117 # The number of ROB writes -system.cpu.timesIdled 353184 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 42411525 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3792652105 # The number of ROB reads +system.cpu.rob.rob_writes 5712643141 # The number of ROB writes +system.cpu.timesIdled 352993 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 42285162 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384370590 # Number of Instructions Simulated system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated -system.cpu.cpi 0.909490 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.909490 # CPI: Total CPI of All Threads -system.cpu.ipc 1.099518 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.099518 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11767673388 # number of integer regfile reads -system.cpu.int_regfile_writes 2220511965 # number of integer regfile writes -system.cpu.fp_regfile_reads 68796181 # number of floating regfile reads -system.cpu.fp_regfile_writes 49544953 # number of floating regfile writes -system.cpu.misc_regfile_reads 1678583418 # number of misc regfile reads +system.cpu.cpi 0.909666 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.909666 # CPI: Total CPI of All Threads +system.cpu.ipc 1.099305 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.099305 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11767299799 # number of integer regfile reads +system.cpu.int_regfile_writes 2220455487 # number of integer regfile writes +system.cpu.fp_regfile_reads 68795103 # number of floating regfile reads +system.cpu.fp_regfile_writes 49537962 # number of floating regfile writes +system.cpu.misc_regfile_reads 1678438007 # number of misc regfile reads system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes -system.cpu.toL2Bus.throughput 169029894 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1493831 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1493830 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96313 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 4265 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 4265 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72518 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72518 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54300 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178976 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3233276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1601152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104536256 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 106137408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 106137408 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 272896 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 929776999 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 168942873 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1493289 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1493289 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 96321 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 4299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 4299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 72517 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 72517 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53208 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3179025 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3232233 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1565120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104535936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 106101056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 106101056 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 275072 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 929534000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 44342246 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 43545495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2368551488 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2368755772 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 23332 # number of replacements -system.cpu.icache.tags.tagsinuse 1641.273486 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 334698554 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 25017 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13378.844546 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 22771 # number of replacements +system.cpu.icache.tags.tagsinuse 1640.597248 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 334768394 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24455 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13689.159436 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1641.273486 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801403 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801403 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1685 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1551 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.822754 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 669498564 # Number of tag accesses -system.cpu.icache.tags.data_accesses 669498564 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 334702534 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 334702534 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 334702534 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 334702534 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 334702534 # number of overall hits -system.cpu.icache.overall_hits::total 334702534 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 32107 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 32107 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 32107 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 32107 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 32107 # number of overall misses -system.cpu.icache.overall_misses::total 32107 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 545585992 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 545585992 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 545585992 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 545585992 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 545585992 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 545585992 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 334734641 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 334734641 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 334734641 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 334734641 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 334734641 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 334734641 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000096 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000096 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000096 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000096 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000096 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000096 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16992.742766 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16992.742766 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16992.742766 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16992.742766 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16992.742766 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16992.742766 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2092 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.597248 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801073 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801073 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1684 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1545 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.822266 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 669636743 # Number of tag accesses +system.cpu.icache.tags.data_accesses 669636743 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 334772400 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 334772400 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 334772400 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 334772400 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 334772400 # number of overall hits +system.cpu.icache.overall_hits::total 334772400 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 31595 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 31595 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 31595 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 31595 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 31595 # number of overall misses +system.cpu.icache.overall_misses::total 31595 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 539866742 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 539866742 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 539866742 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 539866742 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 539866742 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 539866742 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 334803995 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 334803995 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 334803995 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 334803995 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 334803995 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 334803995 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000094 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000094 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000094 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000094 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000094 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000094 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17087.094224 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17087.094224 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17087.094224 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17087.094224 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17087.094224 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17087.094224 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1720 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 38 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 34 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 55.052632 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 50.588235 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2825 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2825 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2825 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2825 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2825 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2825 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 29282 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75913.113626 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67307.989164 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67307.989164 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72567.386831 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74727.105460 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74716.056771 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72567.386831 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74727.105460 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74716.056771 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -898,177 +861,177 @@ system.cpu.l2cache.demand_mshr_hits::total 26 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2424 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406462 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 408886 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4262 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 4262 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2428 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406468 # 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number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145637750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25686438000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25832075750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42624262 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42624262 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3924978750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3924978750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145637750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29611416750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29757054500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145637750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29611416750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29757054500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.096890 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277534 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274500 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999297 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999297 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911181 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911181 # 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number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 472545 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 474973 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2428 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 472545 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 474973 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145726000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25804582750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25950308750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42964296 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42964296 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3615056500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3615056500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145726000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29419639250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29565365250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145726000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29419639250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29565365250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.099284 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277540 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274613 # 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mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60018.945634 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63484.905946 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63464.325281 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59400.074913 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59400.074913 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62664.492772 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62651.310734 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62664.492772 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62651.310734 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54709.755286 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54709.755286 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60018.945634 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62257.857453 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62246.412428 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60018.945634 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62257.857453 # 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number of replacements +system.cpu.dcache.tags.tagsinuse 4094.373897 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 971355471 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1537053 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 631.959647 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 402104250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.373897 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999603 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999603 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 977 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2409 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 402 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 973 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2410 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 400 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1949922120 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1949922120 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 695282746 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 695282746 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276093049 # 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number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 835085 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2796744 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2796744 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2796744 # number of overall misses -system.cpu.dcache.overall_misses::total 2796744 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80415220057 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80415220057 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58619966916 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58619966916 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 211750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 211750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 139035186973 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 139035186973 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 139035186973 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 139035186973 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 697236861 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 697236861 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2788949 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2788949 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2788949 # number of overall misses +system.cpu.dcache.overall_misses::total 2788949 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 697175034 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 974172539 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 974172539 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 974172539 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 974172539 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 974110712 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 974110712 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 974110712 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 974110712 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002803 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002803 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003043 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003043 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003015 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003015 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002871 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002871 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002871 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002871 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41151.733678 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41151.733678 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69567.943800 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69567.943800 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70583.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70583.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49713.233307 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49713.233307 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 49713.233307 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 49713.233307 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2265 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 939 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 52 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.002863 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002863 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002863 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002863 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41981.375162 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41981.375162 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65520.412942 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65520.412942 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 75000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 75000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 49029.584851 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 49029.584851 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 49029.584851 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 49029.584851 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2327 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 933 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 51 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.557692 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10.550562 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.627451 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10.483146 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96313 # number of writebacks -system.cpu.dcache.writebacks::total 96313 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489564 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 489564 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765848 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 765848 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 96321 # number of writebacks +system.cpu.dcache.writebacks::total 96321 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489326 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 489326 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 758271 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 758271 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1255412 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1255412 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1255412 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1255412 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464551 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464551 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76781 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76781 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541332 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541332 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541332 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541332 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42792151524 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 42792151524 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4993494488 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4993494488 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47785646012 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 47785646012 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47785646012 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 47785646012 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 1247597 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1247597 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1247597 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1247597 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464538 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464538 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76814 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76814 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541352 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541352 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541352 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541352 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42911632024 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 42911632024 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4684436204 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4684436204 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47596068228 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 47596068228 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47596068228 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47596068228 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002101 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002101 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses @@ -1077,14 +1040,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001582 system.cpu.dcache.demand_mshr_miss_rate::total 0.001582 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001582 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.614800 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.614800 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65035.549003 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65035.549003 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.824837 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.824837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.824837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.824837 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29300.456543 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29300.456543 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60984.146171 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60984.146171 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30879.428079 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30879.428079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30879.428079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30879.428079 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 391c7c37b..f3edc5948 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.043690 # Number of seconds simulated -sim_ticks 43690025000 # Number of ticks simulated -final_tick 43690025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.043459 # Number of seconds simulated +sim_ticks 43458818000 # Number of ticks simulated +final_tick 43458818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133116 # Simulator instruction rate (inst/s) -host_op_rate 133116 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65834414 # Simulator tick rate (ticks/s) -host_mem_usage 238716 # Number of bytes of host memory used -host_seconds 663.64 # Real time elapsed on the host +host_inst_rate 114678 # Simulator instruction rate (inst/s) +host_op_rate 114678 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56415550 # Simulator tick rate (ticks/s) +host_mem_usage 273516 # Number of bytes of host memory used +host_seconds 770.33 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,27 +25,27 @@ system.physmem.num_reads::cpu.data 158412 # Nu system.physmem.num_reads::total 165515 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10404938 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 232052236 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 242457174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10404938 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10404938 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 166990245 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 166990245 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 166990245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10404938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 232052236 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 409447420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 10460294 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 233286787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 243747080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10460294 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10460294 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 167878657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 167878657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 167878657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10460294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 233286787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 411625737 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 165515 # Number of read requests accepted system.physmem.writeReqs 113997 # Number of write requests accepted system.physmem.readBursts 165515 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 113997 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10592832 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue -system.physmem.bytesWritten 7294912 # Total number of bytes written to DRAM +system.physmem.bytesReadDRAM 10592576 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue +system.physmem.bytesWritten 7294400 # Total number of bytes written to DRAM system.physmem.bytesReadSys 10592960 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 7295808 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10379 # Per bank write bursts @@ -58,10 +58,10 @@ system.physmem.perBankRdBursts::6 9796 # Pe system.physmem.perBankRdBursts::7 10273 # Per bank write bursts system.physmem.perBankRdBursts::8 10509 # Per bank write bursts system.physmem.perBankRdBursts::9 10590 # Per bank write bursts -system.physmem.perBankRdBursts::10 10479 # Per bank write bursts +system.physmem.perBankRdBursts::10 10477 # Per bank write bursts system.physmem.perBankRdBursts::11 10188 # Per bank write bursts -system.physmem.perBankRdBursts::12 10237 # Per bank write bursts -system.physmem.perBankRdBursts::13 10581 # Per bank write bursts +system.physmem.perBankRdBursts::12 10236 # Per bank write bursts +system.physmem.perBankRdBursts::13 10580 # Per bank write bursts system.physmem.perBankRdBursts::14 10468 # Per bank write bursts system.physmem.perBankRdBursts::15 10593 # Per bank write bursts system.physmem.perBankWrBursts::0 7081 # Per bank write bursts @@ -69,20 +69,20 @@ system.physmem.perBankWrBursts::1 7259 # Pe system.physmem.perBankWrBursts::2 7255 # Per bank write bursts system.physmem.perBankWrBursts::3 6998 # Per bank write bursts system.physmem.perBankWrBursts::4 7125 # Per bank write bursts -system.physmem.perBankWrBursts::5 7173 # Per bank write bursts +system.physmem.perBankWrBursts::5 7170 # Per bank write bursts system.physmem.perBankWrBursts::6 6769 # Per bank write bursts -system.physmem.perBankWrBursts::7 7091 # Per bank write bursts -system.physmem.perBankWrBursts::8 7219 # Per bank write bursts +system.physmem.perBankWrBursts::7 7092 # Per bank write bursts +system.physmem.perBankWrBursts::8 7216 # Per bank write bursts system.physmem.perBankWrBursts::9 6938 # Per bank write bursts -system.physmem.perBankWrBursts::10 7084 # Per bank write bursts +system.physmem.perBankWrBursts::10 7083 # Per bank write bursts system.physmem.perBankWrBursts::11 6989 # Per bank write bursts -system.physmem.perBankWrBursts::12 6964 # Per bank write bursts +system.physmem.perBankWrBursts::12 6963 # Per bank write bursts system.physmem.perBankWrBursts::13 7284 # Per bank write bursts -system.physmem.perBankWrBursts::14 7282 # Per bank write bursts +system.physmem.perBankWrBursts::14 7281 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 43690004000 # Total gap between requests +system.physmem.totGap 43458797000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -97,10 +97,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 113997 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 73680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 16364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 4951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 69517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19662 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10165 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -129,195 +129,147 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 51391 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.059076 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 166.605304 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 670.587406 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 21918 42.65% 42.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 7689 14.96% 57.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4202 8.18% 65.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 3191 6.21% 72.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 2222 4.32% 76.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1690 3.29% 79.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1284 2.50% 82.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1159 2.26% 84.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 851 1.66% 86.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 652 1.27% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 530 1.03% 88.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 483 0.94% 89.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 404 0.79% 90.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 335 0.65% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 260 0.51% 91.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 388 0.75% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 222 0.43% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 237 0.46% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 182 0.35% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 255 0.50% 93.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 215 0.42% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 327 0.64% 94.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 148 0.29% 95.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 683 1.33% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 243 0.47% 96.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 177 0.34% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 59 0.11% 97.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 192 0.37% 97.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 83 0.16% 97.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 80 0.16% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 48 0.09% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 87 0.17% 98.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 58 0.11% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 48 0.09% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 18 0.04% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 40 0.08% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 31 0.06% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 14 0.03% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 34 0.07% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 26 0.05% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 13 0.03% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 18 0.04% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 10 0.02% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 16 0.03% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 12 0.02% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 26 0.05% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 7 0.01% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 17 0.03% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 6 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 16 0.03% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 10 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 11 0.02% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 2 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 13 0.03% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 10 0.02% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 3 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 6 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 3 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 7 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 8 0.02% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 20 0.04% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 11 0.02% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 15 0.03% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 14 0.03% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 7 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 5 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 13 0.03% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 7 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 2 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 6 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 6 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 7 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 5 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 5 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 5 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 7 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 8 0.02% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 5 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 5 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 4 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 5 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 4 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 4 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 3 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 5 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 4 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 6 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 6 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.00% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 24 0.05% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 73 0.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 51391 # Bytes accessed per row activation -system.physmem.totQLat 6031819750 # Total ticks spent queuing -system.physmem.totMemAccLat 8481513500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 827565000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1622128750 # Total ticks spent accessing banks -system.physmem.avgQLat 36443.18 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 9800.61 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 41807 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 385.014950 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 230.118388 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 358.708548 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12628 30.21% 30.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8632 20.65% 50.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4415 10.56% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2749 6.58% 67.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2263 5.41% 73.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1680 4.02% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1442 3.45% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1629 3.90% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6369 15.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 41807 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6909 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.954842 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 351.043824 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6907 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6909 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6909 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.496599 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.404036 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.150839 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6289 91.03% 91.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 13 0.19% 91.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 61 0.88% 92.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 166 2.40% 94.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 127 1.84% 96.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 73 1.06% 97.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 63 0.91% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 29 0.42% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 18 0.26% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 12 0.17% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 7 0.10% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 3 0.04% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 3 0.04% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.01% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.03% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 3 0.04% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 2 0.03% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 3 0.04% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 2 0.03% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 3 0.04% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 2 0.03% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 19 0.28% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 5 0.07% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6909 # Writes before turning the bus around for reads +system.physmem.totQLat 5306478250 # Total ticks spent queuing +system.physmem.totMemAccLat 7800537000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 827545000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1666513750 # Total ticks spent accessing banks +system.physmem.avgQLat 32061.57 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 10069.02 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51243.79 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 242.45 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 166.97 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 242.46 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 166.99 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47130.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 243.74 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 167.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 243.75 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 167.88 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.20 # Data bus utilization in percentage -system.physmem.busUtilRead 1.89 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.30 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.01 # Average write queue length when enqueuing -system.physmem.readRowHits 151507 # Number of row buffer hits during reads -system.physmem.writeRowHits 76598 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.19 # Row buffer hit rate for writes -system.physmem.avgGap 156308.15 # Average gap between requests -system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 10.59 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 409447420 # Throughput (bytes/s) +system.physmem.busUtil 3.22 # Data bus utilization in percentage +system.physmem.busUtilRead 1.90 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.31 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.84 # Average write queue length when enqueuing +system.physmem.readRowHits 144461 # Number of row buffer hits during reads +system.physmem.writeRowHits 82889 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.28 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.71 # Row buffer hit rate for writes +system.physmem.avgGap 155480.97 # Average gap between requests +system.physmem.pageHitRate 81.34 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 10.25 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 411625737 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 34625 # Transaction distribution system.membus.trans_dist::ReadResp 34625 # Transaction distribution system.membus.trans_dist::Writeback 113997 # Transaction distribution @@ -329,40 +281,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 17888768 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17888768 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1218631000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1219845000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 1521663500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1520840750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 18742723 # Number of BP lookups -system.cpu.branchPred.condPredicted 12318363 # Number of conditional branches predicted +system.cpu.branchPred.lookups 18742760 # Number of BP lookups +system.cpu.branchPred.condPredicted 12318400 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 4775680 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 15507309 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4664026 # Number of BTB hits +system.cpu.branchPred.BTBLookups 15507492 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4664025 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.076308 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 30.075947 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1660965 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277713 # DTB read hits +system.cpu.dtb.read_hits 20277780 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367861 # DTB read accesses -system.cpu.dtb.write_hits 14728970 # DTB write hits +system.cpu.dtb.read_accesses 20367928 # DTB read accesses +system.cpu.dtb.write_hits 14729056 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14736222 # DTB write accesses -system.cpu.dtb.data_hits 35006683 # DTB hits +system.cpu.dtb.write_accesses 14736308 # DTB write accesses +system.cpu.dtb.data_hits 35006836 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35104083 # DTB accesses -system.cpu.itb.fetch_hits 12367758 # ITB hits +system.cpu.dtb.data_accesses 35104236 # DTB accesses +system.cpu.itb.fetch_hits 12367757 # ITB hits system.cpu.itb.fetch_misses 11021 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12378779 # ITB accesses +system.cpu.itb.fetch_accesses 12378778 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -376,18 +328,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 87380051 # number of cpu cycles simulated +system.cpu.numCycles 86917637 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 8074237 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10668486 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74161830 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 8074236 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10668524 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74162131 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126481080 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 126481381 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 66044 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 293674 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14174544 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 14174243 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 35060070 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 4449011 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 216169 # Number of Branches Incorrectly Predicted As Not Taken). @@ -398,12 +350,12 @@ system.cpu.execution_unit.executions 44777932 # Nu system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77196544 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77191042 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 232942 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17804423 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69575628 # Number of cycles cpu stages are processed. -system.cpu.activity 79.624156 # Percentage of cycles cpu is active +system.cpu.timesIdled 229429 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17341864 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69575773 # Number of cycles cpu stages are processed. +system.cpu.activity 80.047934 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -415,62 +367,62 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 0.989126 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.983891 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.989126 # CPI: Total CPI of All Threads -system.cpu.ipc 1.010994 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.983891 # CPI: Total CPI of All Threads +system.cpu.ipc 1.016372 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.010994 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 34724442 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 52655609 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.260447 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 44924893 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42455158 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 48.586786 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 44349560 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43030491 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.245212 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65259184 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22120867 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 25.315695 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 41338146 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46041905 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 52.691552 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.016372 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 34262012 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 52655625 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.581059 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 44462439 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42455198 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 48.845320 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 43887105 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43030532 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.507250 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 64797015 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22120622 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 25.450096 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 40875399 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46042238 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 52.972262 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 84371 # number of replacements -system.cpu.icache.tags.tagsinuse 1906.431852 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 12250505 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1905.831723 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 12250503 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 86417 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 141.760360 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 141.760337 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1906.431852 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.930875 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.930875 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1905.831723 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.930582 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.930582 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2046 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1090 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 24821911 # Number of tag accesses system.cpu.icache.tags.data_accesses 24821911 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 12250505 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12250505 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12250505 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12250505 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12250505 # number of overall hits -system.cpu.icache.overall_hits::total 12250505 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 117242 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 117242 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 117242 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 117242 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 117242 # number of overall misses -system.cpu.icache.overall_misses::total 117242 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2020332731 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2020332731 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2020332731 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2020332731 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2020332731 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2020332731 # number of overall miss cycles +system.cpu.icache.ReadReq_hits::cpu.inst 12250503 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12250503 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12250503 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12250503 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12250503 # number of overall hits +system.cpu.icache.overall_hits::total 12250503 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 117244 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 117244 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 117244 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 117244 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 117244 # number of overall misses +system.cpu.icache.overall_misses::total 117244 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1999895234 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1999895234 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1999895234 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1999895234 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1999895234 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1999895234 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 12367747 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 12367747 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 12367747 # number of demand (read+write) accesses @@ -483,106 +435,106 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.009480 system.cpu.icache.demand_miss_rate::total 0.009480 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.009480 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.009480 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17232.158535 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17232.158535 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17232.158535 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17232.158535 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17232.158535 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17232.158535 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 376 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17057.548651 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17057.548651 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17057.548651 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17057.548651 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17057.548651 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17057.548651 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 343 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 192 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 22.117647 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 22.866667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 48 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30825 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30825 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30825 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30825 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30825 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30825 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30827 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30827 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30827 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30827 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30827 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30827 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86417 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 86417 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 86417 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 86417 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 86417 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 86417 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1432321765 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1432321765 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1432321765 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1432321765 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1432321765 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1432321765 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1419611513 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1419611513 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1419611513 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1419611513 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1419611513 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1419611513 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006987 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.006987 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.006987 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16574.537012 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16574.537012 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16574.537012 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16574.537012 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16574.537012 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16574.537012 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16427.456554 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16427.456554 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16427.456554 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16427.456554 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16427.456554 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16427.456554 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 672540151 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 146994 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 146994 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168351 # Transaction distribution +system.cpu.toL2Bus.throughput 676121104 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 146995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 146995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168352 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143769 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143769 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 172834 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577043 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 749877 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577046 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 749880 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5530688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23852608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29383296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29383296 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23852736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 29383424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29383424 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 397908000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 397910000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 130875735 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 130829487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 325637219 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 323146469 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu.l2cache.tags.replacements 131591 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30890.802594 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 151432 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 30877.243576 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 151434 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 163651 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.925335 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.925347 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27098.006137 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.747165 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1785.049292 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.826966 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061272 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.054475 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.942712 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 27092.654478 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.905024 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1776.684074 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.826802 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061276 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.054220 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.942299 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32060 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1155 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 17071 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13589 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1156 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 17173 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13478 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 108 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978394 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3980332 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3980332 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 3980348 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3980348 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 79314 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33055 # 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number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 146994 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 168351 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 168351 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 60578 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 146995 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 168352 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168352 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 143769 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143769 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 86417 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 204346 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 290763 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 290764 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 86417 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 204346 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 290763 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 290764 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082194 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454331 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.235554 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454323 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.235552 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082194 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.775215 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.569244 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.775211 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.569242 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082194 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775215 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.569244 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77449.774743 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74243.223603 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74901.018051 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102780.810222 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102780.810222 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77449.774743 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 97822.780156 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 96948.482011 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77449.774743 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 97822.780156 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 96948.482011 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.775211 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.569242 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75659.158102 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71659.999273 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72480.389892 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98554.368172 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98554.368172 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75659.158102 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93881.825556 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 93099.808174 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75659.158102 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93881.825556 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 93099.808174 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -661,80 +613,80 @@ system.cpu.l2cache.demand_mshr_misses::total 165515 system.cpu.l2cache.overall_mshr_misses::cpu.inst 7103 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 165515 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 460945750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1695556500 # 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number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454331 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235554 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454323 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235552 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910419 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910419 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775215 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.569244 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.569242 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775215 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.569244 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64894.516402 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61607.314149 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62281.653430 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 90544.455268 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 90544.455268 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64894.516402 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85517.007866 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84632.003142 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64894.516402 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85517.007866 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84632.003142 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.569242 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63113.684359 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59038.405639 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59874.411552 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86340.150126 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86340.150126 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63113.684359 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81596.831364 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80803.635622 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63113.684359 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81596.831364 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80803.635622 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 200250 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.382661 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33754883 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204346 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.184946 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 297515000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.382661 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995211 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995211 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 200251 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.081511 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33755026 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204347 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.184838 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 302612000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.081511 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995137 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995137 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 922 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3118 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3108 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 69984376 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 69984376 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20180292 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180292 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574591 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574591 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 33754883 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33754883 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33754883 # number of overall hits -system.cpu.dcache.overall_hits::total 33754883 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96346 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96346 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1038786 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1038786 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1135132 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1135132 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1135132 # number of overall misses -system.cpu.dcache.overall_misses::total 1135132 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5098666234 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5098666234 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 85921765380 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 85921765380 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91020431614 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91020431614 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91020431614 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91020431614 # number of overall miss cycles +system.cpu.dcache.tags.tag_accesses 69984377 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 69984377 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20180293 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180293 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574733 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574733 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 33755026 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33755026 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33755026 # number of overall hits +system.cpu.dcache.overall_hits::total 33755026 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96345 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96345 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1038644 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1038644 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1134989 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1134989 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1134989 # number of overall misses +system.cpu.dcache.overall_misses::total 1134989 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4945314984 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4945314984 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 82211352380 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 82211352380 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 87156667364 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 87156667364 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 87156667364 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 87156667364 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -745,54 +697,54 @@ system.cpu.dcache.overall_accesses::cpu.data 34890015 system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071085 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071085 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52920.372761 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 52920.372761 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82713.634358 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 82713.634358 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80184.887409 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80184.887409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80184.887409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80184.887409 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5745787 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071075 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071075 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032530 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032530 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032530 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032530 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51329.233318 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51329.233318 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79152.580076 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 79152.580076 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76790.759526 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76790.759526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76790.759526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76790.759526 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5467849 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 77 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116736 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116872 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.220352 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.784936 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 77 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168351 # number of writebacks -system.cpu.dcache.writebacks::total 168351 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35580 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35580 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895206 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895206 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 930786 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 930786 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 930786 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 930786 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168352 # number of writebacks +system.cpu.dcache.writebacks::total 168352 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35578 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35578 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895064 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895064 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930642 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930642 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930642 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930642 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204346 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204346 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204346 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204346 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2437943016 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2437943016 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13723508765 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13723508765 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16161451781 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16161451781 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16161451781 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16161451781 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 204347 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2366861266 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2366861266 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13170287765 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13170287765 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15537149031 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15537149031 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15537149031 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15537149031 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -801,14 +753,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40120.182602 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40120.182602 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95580.921890 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95580.921890 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79088.662274 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 79088.662274 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79088.662274 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 79088.662274 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 38949.779749 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 38949.779749 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91727.871326 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91727.871326 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76033.164328 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76033.164328 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76033.164328 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76033.164328 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 629fb2f13..7573bf6de 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024877 # Number of seconds simulated -sim_ticks 24876941500 # Number of ticks simulated -final_tick 24876941500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024671 # Number of seconds simulated +sim_ticks 24670906500 # Number of ticks simulated +final_tick 24670906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 202143 # Simulator instruction rate (inst/s) -host_op_rate 202143 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63181048 # Simulator tick rate (ticks/s) -host_mem_usage 239772 # Number of bytes of host memory used -host_seconds 393.74 # Real time elapsed on the host +host_inst_rate 168282 # Simulator instruction rate (inst/s) +host_op_rate 168282 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52161952 # Simulator tick rate (ticks/s) +host_mem_usage 276592 # Number of bytes of host memory used +host_seconds 472.97 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 490624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10154752 # Number of bytes read from this memory -system.physmem.bytes_read::total 10645376 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 490624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 490624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7297216 # Number of bytes written to this memory -system.physmem.bytes_written::total 7297216 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7666 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158668 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166334 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114019 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114019 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19722039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 408199376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 427921415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19722039 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19722039 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 293332522 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 293332522 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 293332522 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19722039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 408199376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 721253937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166334 # Number of read requests accepted -system.physmem.writeReqs 114019 # Number of write requests accepted -system.physmem.readBursts 166334 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114019 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10645312 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 64 # Total number of bytes read from write queue -system.physmem.bytesWritten 7297024 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10645376 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7297216 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 489344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10153856 # Number of bytes read from this memory +system.physmem.bytes_read::total 10643200 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 489344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 489344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7297088 # Number of bytes written to this memory +system.physmem.bytes_written::total 7297088 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7646 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158654 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166300 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114017 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114017 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19834861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 411572068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 431406929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19834861 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19834861 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 295777052 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 295777052 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 295777052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19834861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 411572068 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 727183981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166300 # Number of read requests accepted +system.physmem.writeReqs 114017 # Number of write requests accepted +system.physmem.readBursts 166300 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114017 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10642752 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 7295296 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10643200 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7297088 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10436 # Per bank write bursts -system.physmem.perBankRdBursts::1 10466 # Per bank write bursts -system.physmem.perBankRdBursts::2 10310 # Per bank write bursts -system.physmem.perBankRdBursts::3 10058 # Per bank write bursts -system.physmem.perBankRdBursts::4 10431 # Per bank write bursts -system.physmem.perBankRdBursts::5 10410 # Per bank write bursts -system.physmem.perBankRdBursts::6 9846 # Per bank write bursts -system.physmem.perBankRdBursts::7 10323 # Per bank write bursts -system.physmem.perBankRdBursts::8 10612 # Per bank write bursts -system.physmem.perBankRdBursts::9 10641 # Per bank write bursts -system.physmem.perBankRdBursts::10 10552 # Per bank write bursts -system.physmem.perBankRdBursts::11 10231 # Per bank write bursts -system.physmem.perBankRdBursts::12 10282 # Per bank write bursts +system.physmem.perBankRdBursts::0 10427 # Per bank write bursts +system.physmem.perBankRdBursts::1 10465 # Per bank write bursts +system.physmem.perBankRdBursts::2 10308 # Per bank write bursts +system.physmem.perBankRdBursts::3 10056 # Per bank write bursts +system.physmem.perBankRdBursts::4 10424 # Per bank write bursts +system.physmem.perBankRdBursts::5 10403 # Per bank write bursts +system.physmem.perBankRdBursts::6 9851 # Per bank write bursts +system.physmem.perBankRdBursts::7 10318 # Per bank write bursts +system.physmem.perBankRdBursts::8 10615 # Per bank write bursts +system.physmem.perBankRdBursts::9 10643 # Per bank write bursts +system.physmem.perBankRdBursts::10 10551 # Per bank write bursts +system.physmem.perBankRdBursts::11 10228 # Per bank write bursts +system.physmem.perBankRdBursts::12 10273 # Per bank write bursts system.physmem.perBankRdBursts::13 10619 # Per bank write bursts -system.physmem.perBankRdBursts::14 10489 # Per bank write bursts -system.physmem.perBankRdBursts::15 10627 # Per bank write bursts -system.physmem.perBankWrBursts::0 7083 # Per bank write bursts -system.physmem.perBankWrBursts::1 7258 # Per bank write bursts +system.physmem.perBankRdBursts::14 10486 # Per bank write bursts +system.physmem.perBankRdBursts::15 10626 # Per bank write bursts +system.physmem.perBankWrBursts::0 7082 # Per bank write bursts +system.physmem.perBankWrBursts::1 7259 # Per bank write bursts system.physmem.perBankWrBursts::2 7255 # Per bank write bursts -system.physmem.perBankWrBursts::3 6998 # Per bank write bursts +system.physmem.perBankWrBursts::3 6997 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7177 # Per bank write bursts +system.physmem.perBankWrBursts::5 7170 # Per bank write bursts system.physmem.perBankWrBursts::6 6771 # Per bank write bursts -system.physmem.perBankWrBursts::7 7092 # Per bank write bursts -system.physmem.perBankWrBursts::8 7228 # Per bank write bursts +system.physmem.perBankWrBursts::7 7086 # Per bank write bursts +system.physmem.perBankWrBursts::8 7221 # Per bank write bursts system.physmem.perBankWrBursts::9 6941 # Per bank write bursts -system.physmem.perBankWrBursts::10 7087 # Per bank write bursts -system.physmem.perBankWrBursts::11 6989 # Per bank write bursts -system.physmem.perBankWrBursts::12 6966 # Per bank write bursts +system.physmem.perBankWrBursts::10 7084 # Per bank write bursts +system.physmem.perBankWrBursts::11 6991 # Per bank write bursts +system.physmem.perBankWrBursts::12 6963 # Per bank write bursts system.physmem.perBankWrBursts::13 7287 # Per bank write bursts -system.physmem.perBankWrBursts::14 7286 # Per bank write bursts +system.physmem.perBankWrBursts::14 7284 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 24876907500 # Total gap between requests +system.physmem.totGap 24670873000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166334 # Read request sizes (log2) +system.physmem.readPktSize::6 166300 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114019 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 71615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56813 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 31969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114017 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 69085 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 53344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 32724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -129,233 +129,193 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52112 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 344.289837 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 164.462354 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 671.053187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 22533 43.24% 43.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 7819 15.00% 58.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4221 8.10% 66.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 3179 6.10% 72.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 2215 4.25% 76.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1656 3.18% 79.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1349 2.59% 82.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1165 2.24% 84.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 821 1.58% 86.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 640 1.23% 87.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 526 1.01% 88.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 503 0.97% 89.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 384 0.74% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 279 0.54% 90.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 312 0.60% 91.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 436 0.84% 92.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 202 0.39% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 182 0.35% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 166 0.32% 93.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 352 0.68% 93.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 220 0.42% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 250 0.48% 94.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 131 0.25% 95.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 818 1.57% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 224 0.43% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 79 0.15% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 35 0.07% 97.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 217 0.42% 97.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 119 0.23% 97.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 48 0.09% 98.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 34 0.07% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 83 0.16% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 65 0.12% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 27 0.05% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 17 0.03% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 59 0.11% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 39 0.07% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 22 0.04% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 18 0.03% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 32 0.06% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 16 0.03% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 9 0.02% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 20 0.04% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 18 0.03% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 13 0.02% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 16 0.03% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 32 0.06% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 16 0.03% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 10 0.02% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 12 0.02% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 13 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 13 0.02% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 4 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 12 0.02% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 12 0.02% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 14 0.03% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 6 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 9 0.02% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 11 0.02% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 10 0.02% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 10 0.02% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 14 0.03% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 6 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 9 0.02% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 6 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 11 0.02% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 4 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 4 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 9 0.02% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 5 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 5 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 6 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 3 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 4 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 6 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 3 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 6 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 3 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 4 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 6 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 5 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 5 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 3 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 9 0.02% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 6 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 4 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 4 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 10 0.02% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 4 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 2 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 4 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 15 0.03% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 82 0.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52112 # Bytes accessed per row activation -system.physmem.totQLat 6294270000 # Total ticks spent queuing -system.physmem.totMemAccLat 8641432500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 831665000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1515497500 # Total ticks spent accessing banks -system.physmem.avgQLat 37841.38 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 9111.23 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 43247 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 376.488173 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 224.222062 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 355.745587 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13435 31.07% 31.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8988 20.78% 51.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4626 10.70% 62.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2682 6.20% 68.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2451 5.67% 74.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1626 3.76% 78.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1548 3.58% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1315 3.04% 84.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6576 15.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 43247 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6943 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.949301 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 342.898812 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6941 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6943 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6943 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.417831 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.341311 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.942818 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6412 92.35% 92.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 14 0.20% 92.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 48 0.69% 93.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 135 1.94% 95.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 111 1.60% 96.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 69 0.99% 97.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 62 0.89% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 19 0.27% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 14 0.20% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 9 0.13% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.04% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 6 0.09% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 5 0.07% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.06% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 3 0.04% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.01% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 3 0.04% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.01% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 4 0.06% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 2 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 1 0.01% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 10 0.14% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 2 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6943 # Writes before turning the bus around for reads +system.physmem.totQLat 5579601250 # Total ticks spent queuing +system.physmem.totMemAccLat 7987531250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 831465000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1576465000 # Total ticks spent accessing banks +system.physmem.avgQLat 33552.83 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 9480.04 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51952.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 427.92 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 293.32 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 427.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 293.33 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 48032.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 431.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 295.70 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 431.41 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 295.78 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 5.63 # Data bus utilization in percentage -system.physmem.busUtilRead 3.34 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.29 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.35 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.70 # Average write queue length when enqueuing -system.physmem.readRowHits 152220 # Number of row buffer hits during reads -system.physmem.writeRowHits 76017 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.67 # Row buffer hit rate for writes -system.physmem.avgGap 88734.23 # Average gap between requests -system.physmem.pageHitRate 81.41 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 11.97 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 721253937 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 35533 # Transaction distribution -system.membus.trans_dist::ReadResp 35533 # Transaction distribution -system.membus.trans_dist::Writeback 114019 # Transaction distribution -system.membus.trans_dist::ReadExReq 130801 # Transaction distribution -system.membus.trans_dist::ReadExResp 130801 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446687 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 446687 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17942592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17942592 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17942592 # Total data (bytes) +system.physmem.busUtil 5.68 # Data bus utilization in percentage +system.physmem.busUtilRead 3.37 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.31 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.84 # Average write queue length when enqueuing +system.physmem.readRowHits 144952 # Number of row buffer hits during reads +system.physmem.writeRowHits 82533 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.17 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.39 # Row buffer hit rate for writes +system.physmem.avgGap 88010.62 # Average gap between requests +system.physmem.pageHitRate 81.15 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 12.46 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 727183981 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 35502 # Transaction distribution +system.membus.trans_dist::ReadResp 35502 # Transaction distribution +system.membus.trans_dist::Writeback 114017 # Transaction distribution +system.membus.trans_dist::ReadExReq 130798 # Transaction distribution +system.membus.trans_dist::ReadExResp 130798 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446617 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 446617 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 17940288 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17940288 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1242193000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1242249500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 5.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 1539567000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1535210250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 16535475 # Number of BP lookups -system.cpu.branchPred.condPredicted 10680150 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 413128 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11281450 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7332394 # Number of BTB hits +system.cpu.branchPred.lookups 16545461 # Number of BP lookups +system.cpu.branchPred.condPredicted 10688882 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 416220 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11528806 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7341014 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 64.995138 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1986702 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 41528 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 63.675406 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1988101 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 40517 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22396974 # DTB read hits -system.cpu.dtb.read_misses 220986 # DTB read misses -system.cpu.dtb.read_acv 45 # DTB read access violations -system.cpu.dtb.read_accesses 22617960 # DTB read accesses -system.cpu.dtb.write_hits 15703419 # DTB write hits -system.cpu.dtb.write_misses 41132 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 15744551 # DTB write accesses -system.cpu.dtb.data_hits 38100393 # DTB hits -system.cpu.dtb.data_misses 262118 # DTB misses -system.cpu.dtb.data_acv 49 # DTB access violations -system.cpu.dtb.data_accesses 38362511 # DTB accesses -system.cpu.itb.fetch_hits 13901400 # ITB hits -system.cpu.itb.fetch_misses 35038 # ITB misses +system.cpu.dtb.read_hits 22395847 # DTB read hits +system.cpu.dtb.read_misses 219375 # DTB read misses +system.cpu.dtb.read_acv 51 # DTB read access violations +system.cpu.dtb.read_accesses 22615222 # DTB read accesses +system.cpu.dtb.write_hits 15705719 # DTB write hits +system.cpu.dtb.write_misses 41176 # DTB write misses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_accesses 15746895 # DTB write accesses +system.cpu.dtb.data_hits 38101566 # DTB hits +system.cpu.dtb.data_misses 260551 # DTB misses +system.cpu.dtb.data_acv 53 # DTB access violations +system.cpu.dtb.data_accesses 38362117 # DTB accesses +system.cpu.itb.fetch_hits 13909771 # ITB hits +system.cpu.itb.fetch_misses 35326 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13936438 # ITB accesses +system.cpu.itb.fetch_accesses 13945097 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -369,238 +329,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 49753887 # number of cpu cycles simulated +system.cpu.numCycles 49341816 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15785706 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105319377 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16535475 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9319096 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19535939 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1995771 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7614067 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7763 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 310803 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 76 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13901400 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 208167 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44703895 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.355933 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.120018 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15790710 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105357061 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16545461 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9329115 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19544756 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1999793 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7570274 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7578 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 314157 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 37 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13909771 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 205601 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44679590 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.358058 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.120608 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25167956 56.30% 56.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1528006 3.42% 59.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1366750 3.06% 62.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1512499 3.38% 66.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4138976 9.26% 75.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1846420 4.13% 79.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 671442 1.50% 81.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1071050 2.40% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7400796 16.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25134834 56.26% 56.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1529938 3.42% 59.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1370308 3.07% 62.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1511826 3.38% 66.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4137251 9.26% 75.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1848058 4.14% 79.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 674230 1.51% 81.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1068805 2.39% 83.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7404340 16.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44703895 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.332345 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.116807 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16874554 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7142634 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18558802 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 783225 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1344680 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3743647 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 107085 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103596223 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 302671 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1344680 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17346175 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4853031 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 85455 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18830704 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2243850 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102345999 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 509 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2584 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2124299 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61632193 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123331325 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123012632 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 318692 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44679590 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.335323 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.135249 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16882265 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7097756 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18571135 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 780643 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1347791 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3745694 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 106722 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103639332 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 302042 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1347791 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17356196 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4802628 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 85206 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18838214 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2249555 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102372003 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 486 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2542 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2130672 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61646955 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123349032 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123030884 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 318147 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9085312 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5523 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5521 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4830878 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23230757 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16269125 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1199559 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 452349 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90724395 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5268 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88415459 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 94171 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10689316 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4663748 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 685 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44703895 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.977802 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.109542 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9100074 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5525 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5523 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4824517 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23234080 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16271017 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1195142 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 460766 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90738136 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5320 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88425930 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 95845 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10681231 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4663960 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 737 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44679590 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.979112 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.109137 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16507369 36.93% 36.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6840922 15.30% 52.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5582133 12.49% 64.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4775843 10.68% 75.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4724672 10.57% 85.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2622986 5.87% 91.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1924028 4.30% 96.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1282580 2.87% 99.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 443362 0.99% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16474837 36.87% 36.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6839728 15.31% 52.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5595634 12.52% 64.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4775900 10.69% 75.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4713198 10.55% 85.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2628457 5.88% 91.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1926364 4.31% 96.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1289803 2.89% 99.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 435669 0.98% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44703895 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44679590 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 126532 6.78% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 788261 42.26% 49.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 950494 50.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 126495 6.81% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 783002 42.16% 48.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 947503 51.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49348241 55.81% 55.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43886 0.05% 55.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121319 0.14% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49357567 55.82% 55.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43846 0.05% 55.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121254 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 91 0.00% 56.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 121135 0.14% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38977 0.04% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22847876 25.84% 82.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15893880 17.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 59 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38967 0.04% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22848069 25.84% 82.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15894942 17.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88415459 # Type of FU issued -system.cpu.iq.rate 1.777056 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1865287 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021097 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222890546 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101022608 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86533727 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 603725 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 414375 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294393 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 89978801 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 301945 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1469946 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88425930 # Type of FU issued +system.cpu.iq.rate 1.792109 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1857000 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021001 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222881148 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101028016 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86544064 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 603147 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 414515 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294050 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 89981281 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 301649 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1467705 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2954119 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4771 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18244 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1655748 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2957442 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4633 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18287 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1657640 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3011 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 95424 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2832 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 88581 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1344680 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3730457 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 74850 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100207935 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 218697 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23230757 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16269125 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5268 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 49823 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6563 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18244 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 192844 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 159688 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 352532 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87575579 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22621211 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 839880 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1347791 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3663804 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 77381 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100225939 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 227298 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23234080 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16271017 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5320 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49801 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6534 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18287 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 195800 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 160651 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 356451 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87582928 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22618546 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 843002 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9478272 # number of nop insts executed -system.cpu.iew.exec_refs 38366084 # number of memory reference insts executed -system.cpu.iew.exec_branches 15081989 # Number of branches executed -system.cpu.iew.exec_stores 15744873 # Number of stores executed -system.cpu.iew.exec_rate 1.760176 # Inst execution rate -system.cpu.iew.wb_sent 87218892 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86828120 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33348545 # num instructions producing a value -system.cpu.iew.wb_consumers 43472168 # num instructions consuming a value +system.cpu.iew.exec_nop 9482483 # number of nop insts executed +system.cpu.iew.exec_refs 38365741 # number of memory reference insts executed +system.cpu.iew.exec_branches 15084551 # Number of branches executed +system.cpu.iew.exec_stores 15747195 # Number of stores executed +system.cpu.iew.exec_rate 1.775024 # Inst execution rate +system.cpu.iew.wb_sent 87227797 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86838114 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33351220 # num instructions producing a value +system.cpu.iew.wb_consumers 43473707 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.745152 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.767124 # average fanout of values written-back +system.cpu.iew.wb_rate 1.759929 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.767158 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8870802 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8889589 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 308267 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43359215 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.037414 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.791048 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 311933 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43331799 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.038703 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.791883 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20533772 47.36% 47.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7032064 16.22% 63.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3351851 7.73% 71.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2056930 4.74% 76.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2048633 4.72% 80.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1170984 2.70% 83.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1108500 2.56% 86.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 718184 1.66% 87.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5338297 12.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20501224 47.31% 47.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7041698 16.25% 63.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3356099 7.75% 71.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2051116 4.73% 76.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2049317 4.73% 80.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1167384 2.69% 83.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1102119 2.54% 86.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 716210 1.65% 87.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5346632 12.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43359215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43331799 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -611,230 +571,229 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5338297 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5346632 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 133915050 # The number of ROB reads -system.cpu.rob.rob_writes 195770285 # The number of ROB writes -system.cpu.timesIdled 83590 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5049992 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133898086 # The number of ROB reads +system.cpu.rob.rob_writes 195811124 # The number of ROB writes +system.cpu.timesIdled 85852 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 4662226 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.625114 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.625114 # CPI: Total CPI of All Threads -system.cpu.ipc 1.599709 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.599709 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115901393 # number of integer regfile reads -system.cpu.int_regfile_writes 57502981 # number of integer regfile writes -system.cpu.fp_regfile_reads 249622 # number of floating regfile reads -system.cpu.fp_regfile_writes 240154 # number of floating regfile writes -system.cpu.misc_regfile_reads 38048 # number of misc regfile reads +system.cpu.cpi 0.619936 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.619936 # CPI: Total CPI of All Threads +system.cpu.ipc 1.613069 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.613069 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115913702 # number of integer regfile reads +system.cpu.int_regfile_writes 57508814 # number of integer regfile writes +system.cpu.fp_regfile_reads 249357 # number of floating regfile reads +system.cpu.fp_regfile_writes 240037 # number of floating regfile writes +system.cpu.misc_regfile_reads 38036 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1204366702 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 155800 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 155799 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143411 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143411 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 187341 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580010 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 767351 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5994880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23966080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29960960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29960960 # Total data (bytes) +system.cpu.toL2Bus.throughput 1213726946 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 155524 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 155523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168929 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143419 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143419 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186761 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580053 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 766814 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5976320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23967424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 29943744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29943744 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 403000500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 402865000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 141888472 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 141399227 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 326227248 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 324564248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 91622 # number of replacements -system.cpu.icache.tags.tagsinuse 1926.124790 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13794941 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 93670 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.271709 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 20019697250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1926.124790 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.940491 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.940491 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 91332 # number of replacements +system.cpu.icache.tags.tagsinuse 1925.493490 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13803368 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 93380 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 147.819319 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19891128250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1925.493490 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.940182 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.940182 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1531 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 359 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1527 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 358 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27896466 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27896466 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13794941 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13794941 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13794941 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13794941 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13794941 # number of overall hits -system.cpu.icache.overall_hits::total 13794941 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 106457 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 106457 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 106457 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 106457 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 106457 # number of overall misses -system.cpu.icache.overall_misses::total 106457 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2019960968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2019960968 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2019960968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2019960968 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2019960968 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2019960968 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13901398 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13901398 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13901398 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13901398 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13901398 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13901398 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007658 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007658 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007658 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007658 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007658 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007658 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18974.430690 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18974.430690 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18974.430690 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18974.430690 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18974.430690 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18974.430690 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 691 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 27912922 # Number of tag accesses +system.cpu.icache.tags.data_accesses 27912922 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 13803368 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13803368 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13803368 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13803368 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13803368 # number of overall hits +system.cpu.icache.overall_hits::total 13803368 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 106403 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 106403 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 106403 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 106403 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 106403 # number of overall misses +system.cpu.icache.overall_misses::total 106403 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2000796974 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2000796974 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2000796974 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2000796974 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2000796974 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2000796974 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13909771 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13909771 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13909771 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13909771 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13909771 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13909771 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007650 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007650 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007650 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007650 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007650 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007650 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18803.952652 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18803.952652 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18803.952652 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18803.952652 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18803.952652 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18803.952652 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 263 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.187500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.916667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12786 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12786 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12786 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12786 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12786 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12786 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93671 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 93671 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 93671 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 93671 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 93671 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 93671 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1551735028 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1551735028 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1551735028 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1551735028 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1551735028 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1551735028 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006738 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006738 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006738 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006738 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006738 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006738 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16565.799746 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16565.799746 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16565.799746 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16565.799746 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16565.799746 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16565.799746 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 13022 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 13022 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 13022 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 13022 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 13022 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 13022 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93381 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 93381 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 93381 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 93381 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 93381 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 93381 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1534559773 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1534559773 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1534559773 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1534559773 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1534559773 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1534559773 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006713 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006713 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006713 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006713 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006713 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006713 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16433.319123 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16433.319123 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16433.319123 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16433.319123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16433.319123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16433.319123 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 132428 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30694.665852 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 159970 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164497 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.972480 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 132391 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30672.416469 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 159732 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 164458 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.971263 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26341.005950 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2105.517354 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 2248.142548 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.803864 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064255 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.068608 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.936727 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32069 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1443 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 18046 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12352 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 26335.603733 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.899695 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 2234.913041 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.803699 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064145 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.068204 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.936048 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32067 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1463 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 18089 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12275 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 61 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978668 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4053036 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4053036 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 86004 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 34262 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 120266 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83920.575592 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82987.785702 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 201444 # number of replacements -system.cpu.dcache.tags.tagsinuse 4074.011744 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34183901 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205540 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 166.312645 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 220306250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4074.011744 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.994632 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994632 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 201466 # number of replacements +system.cpu.dcache.tags.tagsinuse 4073.410780 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34191132 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205562 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 166.330022 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 225470250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4073.410780 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.994485 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994485 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1078 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2940 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1081 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2933 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 71186914 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 71186914 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20609776 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20609776 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574069 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574069 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 56 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 56 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34183845 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34183845 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34183845 # number of overall hits -system.cpu.dcache.overall_hits::total 34183845 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 267478 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 267478 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1039308 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1039308 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1306786 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1306786 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1306786 # number of overall misses -system.cpu.dcache.overall_misses::total 1306786 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 16319754498 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 16319754498 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 88798095012 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 88798095012 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 105117849510 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 105117849510 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 105117849510 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 105117849510 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20877254 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20877254 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 71201646 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 71201646 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20617040 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20617040 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574040 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574040 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 52 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 52 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34191080 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34191080 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34191080 # number of overall hits +system.cpu.dcache.overall_hits::total 34191080 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 267573 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 267573 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1039337 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1039337 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1306910 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1306910 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1306910 # number of overall misses +system.cpu.dcache.overall_misses::total 1306910 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15791609498 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15791609498 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 85266584825 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 85266584825 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 101058194323 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 101058194323 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 101058194323 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 101058194323 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20884613 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20884613 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 56 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 56 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35490631 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35490631 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35490631 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35490631 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 52 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 52 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35497990 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35497990 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35497990 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35497990 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012812 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012812 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071120 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071120 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036821 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036821 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036821 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036821 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61013.445958 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61013.445958 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85439.633883 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 85439.633883 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80439.987504 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80439.987504 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80439.987504 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80439.987504 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5138864 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071122 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071122 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036816 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036816 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036816 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036816 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59017.948365 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59017.948365 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82039.400911 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 82039.400911 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77326.054834 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77326.054834 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77326.054834 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77326.054834 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4861037 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 131 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 112181 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 111685 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.808684 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.524529 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 131 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168930 # number of writebacks -system.cpu.dcache.writebacks::total 168930 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205345 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 205345 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895901 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895901 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1101246 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1101246 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1101246 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1101246 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62133 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62133 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143407 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143407 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205540 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205540 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205540 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205540 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2525887252 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2525887252 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14052510994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14052510994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16578398246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16578398246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16578398246 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16578398246 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 168929 # number of writebacks +system.cpu.dcache.writebacks::total 168929 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205428 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 205428 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895920 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895920 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1101348 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1101348 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1101348 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1101348 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62145 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62145 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143417 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143417 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205562 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205562 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205562 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205562 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2457360502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2457360502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13489619744 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13489619744 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15946980246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15946980246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15946980246 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15946980246 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002976 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002976 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.005791 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005791 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40652.909919 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40652.909919 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97990.411863 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97990.411863 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80657.770974 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80657.770974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80657.770974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80657.770974 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39542.368686 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39542.368686 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 94058.722076 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 94058.722076 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77577.471741 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77577.471741 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77577.471741 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77577.471741 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 9978094b9..e2e70aeb1 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026790 # Number of seconds simulated -sim_ticks 26790388000 # Number of ticks simulated -final_tick 26790388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026596 # Number of seconds simulated +sim_ticks 26596403000 # Number of ticks simulated +final_tick 26596403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134448 # Simulator instruction rate (inst/s) -host_op_rate 190799 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50797444 # Simulator tick rate (ticks/s) -host_mem_usage 278572 # Number of bytes of host memory used -host_seconds 527.40 # Real time elapsed on the host +host_inst_rate 110554 # Simulator instruction rate (inst/s) +host_op_rate 156889 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41466984 # Simulator tick rate (ticks/s) +host_mem_usage 321816 # Number of bytes of host memory used +host_seconds 641.39 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 297344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7942912 # Number of bytes read from this memory -system.physmem.bytes_read::total 8240256 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 297344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 297344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5371968 # Number of bytes written to this memory -system.physmem.bytes_written::total 5371968 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4646 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124108 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128754 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83937 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83937 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11098906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 296483649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 307582555 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11098906 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11098906 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 200518484 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 200518484 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 200518484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11098906 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 296483649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 508101040 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128754 # Number of read requests accepted -system.physmem.writeReqs 83937 # Number of write requests accepted -system.physmem.readBursts 128754 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83937 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8240128 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371648 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8240256 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5371968 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 297984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7942976 # Number of bytes read from this memory +system.physmem.bytes_read::total 8240960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 297984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 297984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372480 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372480 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4656 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124109 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128765 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83945 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83945 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11203921 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 298648505 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 309852426 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11203921 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11203921 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 202000248 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 202000248 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 202000248 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11203921 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 298648505 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 511852674 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128766 # Number of read requests accepted +system.physmem.writeReqs 83945 # Number of write requests accepted +system.physmem.readBursts 128766 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83945 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8240704 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue +system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8241024 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5372480 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 308 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8131 # Per bank write bursts -system.physmem.perBankRdBursts::1 8390 # Per bank write bursts -system.physmem.perBankRdBursts::2 8247 # Per bank write bursts -system.physmem.perBankRdBursts::3 8163 # Per bank write bursts -system.physmem.perBankRdBursts::4 8302 # Per bank write bursts -system.physmem.perBankRdBursts::5 8446 # Per bank write bursts -system.physmem.perBankRdBursts::6 8088 # Per bank write bursts -system.physmem.perBankRdBursts::7 7962 # Per bank write bursts -system.physmem.perBankRdBursts::8 8060 # Per bank write bursts -system.physmem.perBankRdBursts::9 7613 # Per bank write bursts -system.physmem.perBankRdBursts::10 7786 # Per bank write bursts -system.physmem.perBankRdBursts::11 7812 # Per bank write bursts -system.physmem.perBankRdBursts::12 7879 # Per bank write bursts -system.physmem.perBankRdBursts::13 7885 # Per bank write bursts -system.physmem.perBankRdBursts::14 7978 # Per bank write bursts -system.physmem.perBankRdBursts::15 8010 # Per bank write bursts -system.physmem.perBankWrBursts::0 5179 # Per bank write bursts -system.physmem.perBankWrBursts::1 5375 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 300 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 8143 # Per bank write bursts +system.physmem.perBankRdBursts::1 8388 # Per bank write bursts +system.physmem.perBankRdBursts::2 8255 # Per bank write bursts +system.physmem.perBankRdBursts::3 8165 # Per bank write bursts +system.physmem.perBankRdBursts::4 8298 # Per bank write bursts +system.physmem.perBankRdBursts::5 8451 # Per bank write bursts +system.physmem.perBankRdBursts::6 8084 # Per bank write bursts +system.physmem.perBankRdBursts::7 7964 # Per bank write bursts +system.physmem.perBankRdBursts::8 8055 # Per bank write bursts +system.physmem.perBankRdBursts::9 7611 # Per bank write bursts +system.physmem.perBankRdBursts::10 7782 # Per bank write bursts +system.physmem.perBankRdBursts::11 7815 # Per bank write bursts +system.physmem.perBankRdBursts::12 7881 # Per bank write bursts +system.physmem.perBankRdBursts::13 7884 # Per bank write bursts +system.physmem.perBankRdBursts::14 7976 # Per bank write bursts +system.physmem.perBankRdBursts::15 8009 # Per bank write bursts +system.physmem.perBankWrBursts::0 5177 # Per bank write bursts +system.physmem.perBankWrBursts::1 5376 # Per bank write bursts system.physmem.perBankWrBursts::2 5289 # Per bank write bursts system.physmem.perBankWrBursts::3 5157 # Per bank write bursts -system.physmem.perBankWrBursts::4 5265 # Per bank write bursts +system.physmem.perBankWrBursts::4 5267 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5207 # Per bank write bursts -system.physmem.perBankWrBursts::7 5048 # Per bank write bursts -system.physmem.perBankWrBursts::8 5029 # Per bank write bursts +system.physmem.perBankWrBursts::6 5201 # Per bank write bursts +system.physmem.perBankWrBursts::7 5049 # Per bank write bursts +system.physmem.perBankWrBursts::8 5030 # Per bank write bursts system.physmem.perBankWrBursts::9 5089 # Per bank write bursts -system.physmem.perBankWrBursts::10 5251 # Per bank write bursts +system.physmem.perBankWrBursts::10 5246 # Per bank write bursts system.physmem.perBankWrBursts::11 5144 # Per bank write bursts system.physmem.perBankWrBursts::12 5342 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts -system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5226 # Per bank write bursts +system.physmem.perBankWrBursts::14 5452 # Per bank write bursts +system.physmem.perBankWrBursts::15 5225 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26790282500 # Total gap between requests +system.physmem.totGap 26596386500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128754 # Read request sizes (log2) +system.physmem.readPktSize::6 128766 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83937 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 73147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54223 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83945 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 71874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54925 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1900 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -129,219 +129,173 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 359.276222 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.215706 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 692.456870 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 15075 39.80% 39.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 5750 15.18% 54.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 3421 9.03% 64.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2320 6.12% 70.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1668 4.40% 74.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1547 4.08% 78.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1100 2.90% 81.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 895 2.36% 83.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 687 1.81% 85.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 539 1.42% 87.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 385 1.02% 88.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 594 1.57% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 272 0.72% 90.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 354 0.93% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 173 0.46% 91.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 239 0.63% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 118 0.31% 92.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 247 0.65% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 108 0.29% 93.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 279 0.74% 94.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 118 0.31% 94.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 446 1.18% 95.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 106 0.28% 96.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 237 0.63% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 43 0.11% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 118 0.31% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 42 0.11% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 85 0.22% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 20 0.05% 97.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 62 0.16% 97.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 22 0.06% 97.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 44 0.12% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 19 0.05% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 33 0.09% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 16 0.04% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 33 0.09% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 8 0.02% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 24 0.06% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 13 0.03% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 33 0.09% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 14 0.04% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 23 0.06% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 10 0.03% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 16 0.04% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 9 0.02% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 18 0.05% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 4 0.01% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 17 0.04% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 11 0.03% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 19 0.05% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 11 0.03% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 26 0.07% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 4 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 7 0.02% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 10 0.03% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 5 0.01% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 7 0.02% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 10 0.03% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 9 0.02% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 4 0.01% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 16 0.04% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 7 0.02% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 9 0.02% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 5 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 10 0.03% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 10 0.03% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 11 0.03% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 6 0.02% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 10 0.03% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 7 0.02% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 6 0.02% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 5 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 5 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 2 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 12 0.03% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 4 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 8 0.02% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 5 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 9 0.02% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 2 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 7 0.02% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 4 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 6 0.02% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 7 0.02% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 7 0.02% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 10 0.03% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 5 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 2 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 6 0.02% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 6 0.02% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 3 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 5 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 4 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 5 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 4 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 4 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 5 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 5 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 4 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 4 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 5 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 3 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 3 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 4 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 6 0.02% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 37 0.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37879 # Bytes accessed per row activation -system.physmem.totQLat 3022726750 # Total ticks spent queuing -system.physmem.totMemAccLat 4971045500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 643760000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1304558750 # Total ticks spent accessing banks -system.physmem.avgQLat 23477.12 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 10132.34 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 29627 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 410.695649 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 253.351666 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 359.831379 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7793 26.30% 26.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6034 20.37% 46.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3130 10.56% 57.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2203 7.44% 64.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2053 6.93% 71.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1365 4.61% 76.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1045 3.53% 79.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1191 4.02% 83.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4813 16.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 29627 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5084 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.322974 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 394.325536 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5082 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5084 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5084 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.507474 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.421096 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.063173 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4555 89.59% 89.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 21 0.41% 90.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 58 1.14% 91.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 170 3.34% 94.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 125 2.46% 96.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 57 1.12% 98.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 23 0.45% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 15 0.30% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 10 0.20% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 6 0.12% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.10% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 5 0.10% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 4 0.08% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 2 0.04% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.08% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 2 0.04% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.02% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.02% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 1 0.02% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 13 0.26% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 3 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5084 # Writes before turning the bus around for reads +system.physmem.totQLat 2537399000 # Total ticks spent queuing +system.physmem.totMemAccLat 4590111500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 643805000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1408907500 # Total ticks spent accessing banks +system.physmem.avgQLat 19706.27 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 10942.04 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38609.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 307.58 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 200.51 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 307.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 200.52 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 35648.31 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 309.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 201.95 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 309.85 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 202.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.97 # Data bus utilization in percentage -system.physmem.busUtilRead 2.40 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.57 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.70 # Average write queue length when enqueuing -system.physmem.readRowHits 117872 # Number of row buffer hits during reads -system.physmem.writeRowHits 56933 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.83 # Row buffer hit rate for writes -system.physmem.avgGap 125958.70 # Average gap between requests -system.physmem.pageHitRate 82.19 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 11.78 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 508101040 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26500 # Transaction distribution -system.membus.trans_dist::ReadResp 26500 # Transaction distribution -system.membus.trans_dist::Writeback 83937 # Transaction distribution -system.membus.trans_dist::UpgradeReq 308 # Transaction distribution -system.membus.trans_dist::UpgradeResp 308 # Transaction distribution -system.membus.trans_dist::ReadExReq 102254 # Transaction distribution -system.membus.trans_dist::ReadExResp 102254 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342061 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 342061 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13612224 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13612224 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13612224 # Total data (bytes) +system.physmem.busUtil 4.00 # Data bus utilization in percentage +system.physmem.busUtilRead 2.42 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.58 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing +system.physmem.readRowHits 112537 # Number of row buffer hits during reads +system.physmem.writeRowHits 62593 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.40 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.56 # Row buffer hit rate for writes +system.physmem.avgGap 125035.31 # Average gap between requests +system.physmem.pageHitRate 82.33 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 11.63 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 511852674 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26511 # Transaction distribution +system.membus.trans_dist::ReadResp 26510 # Transaction distribution +system.membus.trans_dist::Writeback 83945 # Transaction distribution +system.membus.trans_dist::UpgradeReq 300 # Transaction distribution +system.membus.trans_dist::UpgradeResp 300 # Transaction distribution +system.membus.trans_dist::ReadExReq 102255 # Transaction distribution +system.membus.trans_dist::ReadExResp 102255 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342076 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 342076 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13613440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13613440 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13613440 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 934459500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 934794000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1203485442 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1201882201 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 16615535 # Number of BP lookups -system.cpu.branchPred.condPredicted 12754556 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 602333 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10795457 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7770077 # Number of BTB hits +system.cpu.branchPred.lookups 16626299 # Number of BP lookups +system.cpu.branchPred.condPredicted 12761376 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 603542 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10553987 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7772041 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.975434 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1823925 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 112966 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 73.640805 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1823891 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 112970 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -427,136 +381,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 53580777 # number of cpu cycles simulated +system.cpu.numCycles 53192807 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12546836 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85170403 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16615535 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9594002 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21183792 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2362024 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10685029 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 63 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 557 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 20 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11675856 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 179932 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46149323 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.583841 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.333163 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12548027 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85225985 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16626299 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9595932 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21195811 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2371567 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10764095 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 172 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 524 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11679981 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 179230 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46249849 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.580108 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.332376 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24986446 54.14% 54.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2137638 4.63% 58.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1962079 4.25% 63.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2043997 4.43% 67.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1466310 3.18% 70.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1377582 2.99% 73.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 960310 2.08% 75.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1185958 2.57% 78.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10029003 21.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25074842 54.22% 54.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2134843 4.62% 58.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1965334 4.25% 63.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2045724 4.42% 67.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1467866 3.17% 70.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1377638 2.98% 73.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 956719 2.07% 75.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1188096 2.57% 78.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10038787 21.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46149323 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.310103 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.589570 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14635353 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9029918 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19485051 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1368887 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1630114 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3325603 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 104819 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116788167 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 363460 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1630114 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16340014 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2585458 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1028005 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19100045 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5465687 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 114914880 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 172 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17272 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4606354 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 316 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115243032 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529540867 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 476170049 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2600 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46249849 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.312567 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.602209 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14635842 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9109376 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19493309 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1372783 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1638539 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3331010 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 104505 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116880506 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 361697 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1638539 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16346771 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2652791 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1020533 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19105290 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5485925 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 114999580 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 152 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17445 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4623062 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 183 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115318587 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529932404 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 476522297 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2751 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16110360 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20388 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20384 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12995984 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29602749 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22439249 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3932152 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4401403 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111507434 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 36062 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107242523 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 272405 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10768427 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25739903 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2276 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46149323 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.323816 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.990206 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16185915 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20374 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20369 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13024660 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29615928 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22451967 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3877153 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4417845 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111572377 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 35991 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107273861 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 274045 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10831021 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25918238 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2205 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46249849 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.319442 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.990414 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10919279 23.66% 23.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8079518 17.51% 41.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7423472 16.09% 57.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7094481 15.37% 72.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5420902 11.75% 84.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3930329 8.52% 92.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1841974 3.99% 96.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 869423 1.88% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 569945 1.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10978806 23.74% 23.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8116860 17.55% 41.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7434269 16.07% 57.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7097763 15.35% 72.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5421519 11.72% 84.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3913580 8.46% 92.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1842525 3.98% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 870168 1.88% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 574359 1.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46149323 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46249849 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112279 4.53% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1361817 54.98% 59.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1002641 40.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 113368 4.58% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1353818 54.73% 59.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1006223 40.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56635396 52.81% 52.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91455 0.09% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56655592 52.81% 52.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91505 0.09% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 208 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 217 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued @@ -582,84 +536,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28883502 26.93% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21631955 20.17% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28893939 26.93% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21632601 20.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107242523 # Type of FU issued -system.cpu.iq.rate 2.001511 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2476739 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023095 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263382945 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122340040 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105564996 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 568 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 856 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 168 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109718975 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 287 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2181751 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107273861 # Type of FU issued +system.cpu.iq.rate 2.016699 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2473411 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023057 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263544444 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122467509 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105589962 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 583 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 918 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 177 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109746981 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 291 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2178933 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2295641 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6455 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29983 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1883511 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2308820 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6717 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29962 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1896229 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 679 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 670 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1630114 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1093825 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45147 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111553302 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 294819 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29602749 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22439249 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 20142 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6322 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5200 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29983 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 391827 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 180696 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 572523 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106211851 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28585179 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1030672 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1638539 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1135526 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 46796 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111618146 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 297287 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29615928 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22451967 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 20071 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6522 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5186 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29962 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 392730 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 181164 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 573894 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106245086 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28594669 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1028775 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9806 # number of nop insts executed -system.cpu.iew.exec_refs 49926975 # number of memory reference insts executed -system.cpu.iew.exec_branches 14599283 # Number of branches executed -system.cpu.iew.exec_stores 21341796 # Number of stores executed -system.cpu.iew.exec_rate 1.982275 # Inst execution rate -system.cpu.iew.wb_sent 105782073 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105565164 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53316718 # num instructions producing a value -system.cpu.iew.wb_consumers 103963305 # num instructions consuming a value +system.cpu.iew.exec_nop 9778 # number of nop insts executed +system.cpu.iew.exec_refs 49940992 # number of memory reference insts executed +system.cpu.iew.exec_branches 14602318 # Number of branches executed +system.cpu.iew.exec_stores 21346323 # Number of stores executed +system.cpu.iew.exec_rate 1.997358 # Inst execution rate +system.cpu.iew.wb_sent 105809508 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105590139 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53305824 # num instructions producing a value +system.cpu.iew.wb_consumers 103866304 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.970206 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.512842 # average fanout of values written-back +system.cpu.iew.wb_rate 1.985045 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.513216 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10921742 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10986690 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 499421 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44519209 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.260427 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.765009 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 500884 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44611310 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.255760 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.762475 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15470185 34.75% 34.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11634994 26.13% 60.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3452010 7.75% 68.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2868846 6.44% 75.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1865323 4.19% 79.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1954753 4.39% 83.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 686748 1.54% 85.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 559469 1.26% 86.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6026881 13.54% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15517142 34.78% 34.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11686207 26.20% 60.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3450926 7.74% 68.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2867812 6.43% 75.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1872959 4.20% 79.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1945129 4.36% 83.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 689747 1.55% 85.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 566134 1.27% 86.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6015254 13.48% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44519209 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44611310 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -670,243 +624,243 @@ system.cpu.commit.branches 13741485 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6026881 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6015254 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 150021199 # The number of ROB reads -system.cpu.rob.rob_writes 224747411 # The number of ROB writes -system.cpu.timesIdled 76674 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7431454 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 150189875 # The number of ROB reads +system.cpu.rob.rob_writes 224886049 # The number of ROB writes +system.cpu.timesIdled 80066 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6942958 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.755642 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.755642 # CPI: Total CPI of All Threads -system.cpu.ipc 1.323378 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.323378 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511545132 # number of integer regfile reads -system.cpu.int_regfile_writes 103340839 # number of integer regfile writes -system.cpu.fp_regfile_reads 806 # number of floating regfile reads -system.cpu.fp_regfile_writes 694 # number of floating regfile writes -system.cpu.misc_regfile_reads 49339612 # number of misc regfile reads +system.cpu.cpi 0.750170 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.750170 # CPI: Total CPI of All Threads +system.cpu.ipc 1.333030 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.333030 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511686083 # number of integer regfile reads +system.cpu.int_regfile_writes 103364033 # number of integer regfile writes +system.cpu.fp_regfile_reads 870 # number of floating regfile reads +system.cpu.fp_regfile_writes 762 # number of floating regfile writes +system.cpu.misc_regfile_reads 49348247 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.throughput 773036658 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 87363 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 87363 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 129182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 325 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 325 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107048 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107048 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63452 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454686 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 518138 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2013952 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18662976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 20676928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 20676928 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 33024 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 291143497 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 778162370 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 87191 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 87190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 129156 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 314 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 314 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63123 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454609 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 517732 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2003904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18660352 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 20664256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 20664256 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 32064 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 291006496 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 48712731 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 48441979 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 260354993 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 259878236 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 29638 # number of replacements -system.cpu.icache.tags.tagsinuse 1806.211071 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 11640103 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 31672 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 367.520302 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 29471 # number of replacements +system.cpu.icache.tags.tagsinuse 1806.055358 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 11644351 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 31508 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 369.568078 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1806.211071 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.881939 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.881939 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2034 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 676 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.993164 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 23383696 # Number of tag accesses -system.cpu.icache.tags.data_accesses 23383696 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 11640118 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11640118 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11640118 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11640118 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11640118 # number of overall hits -system.cpu.icache.overall_hits::total 11640118 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 35738 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 35738 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 35738 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 35738 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 35738 # number of overall misses -system.cpu.icache.overall_misses::total 35738 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 828271479 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 828271479 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 828271479 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 828271479 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 828271479 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 828271479 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11675856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11675856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11675856 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11675856 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11675856 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11675856 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003061 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003061 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003061 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003061 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003061 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003061 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23176.212407 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23176.212407 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23176.212407 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23176.212407 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23176.212407 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23176.212407 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 856 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1806.055358 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.881863 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.881863 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2037 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1253 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 681 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.994629 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 23391772 # Number of tag accesses +system.cpu.icache.tags.data_accesses 23391772 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 11644361 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11644361 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11644361 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11644361 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11644361 # number of overall hits +system.cpu.icache.overall_hits::total 11644361 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 35619 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 35619 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 35619 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 35619 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 35619 # number of overall misses +system.cpu.icache.overall_misses::total 35619 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 813918226 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 813918226 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 813918226 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 813918226 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 813918226 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 813918226 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11679980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11679980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11679980 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11679980 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11679980 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11679980 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003050 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003050 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003050 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003050 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003050 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003050 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22850.675931 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22850.675931 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22850.675931 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22850.675931 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22850.675931 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22850.675931 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1148 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42.800000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 52.181818 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # 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number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 31984 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 671357769 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 671357769 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 671357769 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 671357769 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 671357769 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 671357769 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002739 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002739 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002739 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002739 # 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Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041758 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.055649 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.911193 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31113 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1837 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 20828 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7917 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 394 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949493 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 2819349 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 2819349 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80385.110173 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -915,202 +869,202 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83937 # number of writebacks -system.cpu.l2cache.writebacks::total 83937 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 83945 # number of writebacks +system.cpu.l2cache.writebacks::total 83945 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71014.366544 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4656 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21855 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26511 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 300 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 300 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102255 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102255 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4656 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124110 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 303015250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8444145250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8747160500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 303015250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8444145250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8747160500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.148702 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394644 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.305814 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.955414 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68987.943262 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68301.714383 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10047.663333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10047.663333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67834.470197 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67834.470197 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65080.594931 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68037.589638 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67930.668810 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65080.594931 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68037.589638 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67930.668810 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 158331 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.839586 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 44347897 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 162427 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 273.032790 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 363282250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.839586 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993369 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993369 # 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Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2254 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1757 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2276 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 92273995 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 92273995 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 26048802 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26048802 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18266579 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18266579 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15981 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15981 # 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number of overall hits -system.cpu.dcache.overall_hits::total 44315381 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 125140 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 125140 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1583322 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1583322 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1708462 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1708462 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1708462 # number of overall misses -system.cpu.dcache.overall_misses::total 1708462 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5205484954 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5205484954 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 127036653749 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 127036653749 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 856750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 856750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 132242138703 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 132242138703 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 132242138703 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 132242138703 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26173942 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26173942 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 44328960 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44328960 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44328960 # number of overall hits +system.cpu.dcache.overall_hits::total 44328960 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 125143 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 125143 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1582186 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1582186 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 44 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 44 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1707329 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1707329 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1707329 # number of overall misses +system.cpu.dcache.overall_misses::total 1707329 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5010352449 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5010352449 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 122380602729 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 122380602729 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 944750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 944750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 127390955178 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 127390955178 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 127390955178 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 127390955178 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26186388 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26186388 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16022 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16022 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16033 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16033 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46023843 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46023843 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46023843 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46023843 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004781 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004781 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079765 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079765 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002559 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002559 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037121 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037121 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037121 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037121 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41597.290666 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41597.290666 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80234.250360 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80234.250360 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20896.341463 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20896.341463 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77404.202554 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77404.202554 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77404.202554 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77404.202554 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4865 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1223 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.510949 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 87.357143 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46036289 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46036289 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46036289 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46036289 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004779 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004779 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079708 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079708 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002744 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002744 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037087 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037087 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037087 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037087 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40037.017244 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40037.017244 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77349.061823 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77349.061823 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21471.590909 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21471.590909 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74614.181085 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74614.181085 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74614.181085 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74614.181085 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4179 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1300 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 140 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.850000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 86.666667 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129182 # number of writebacks -system.cpu.dcache.writebacks::total 129182 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69727 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69727 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475983 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475983 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1545710 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1545710 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1545710 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1545710 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 129156 # number of writebacks +system.cpu.dcache.writebacks::total 129156 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69730 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69730 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1474872 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1474872 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 44 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 44 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1544602 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1544602 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1544602 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1544602 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107339 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107339 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162752 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162752 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162752 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162752 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2263243564 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2263243564 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8680214182 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8680214182 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10943457746 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10943457746 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10943457746 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10943457746 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40843.187772 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40843.187772 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80867.291311 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80867.291311 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67240.081511 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67240.081511 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67240.081511 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67240.081511 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107314 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107314 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162727 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162727 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162727 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162727 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2176479313 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2176479313 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8375757941 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8375757941 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10552237254 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10552237254 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10552237254 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10552237254 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002116 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002116 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39277.413477 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39277.413477 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78049.070401 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78049.070401 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64846.259404 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 64846.259404 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64846.259404 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 64846.259404 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 01fe4f841..f20aedd28 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.009838 # Number of seconds simulated -sim_ticks 1009838214500 # Number of ticks simulated -final_tick 1009838214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.007337 # Number of seconds simulated +sim_ticks 1007336591500 # Number of ticks simulated +final_tick 1007336591500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128161 # Simulator instruction rate (inst/s) -host_op_rate 128161 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71119760 # Simulator tick rate (ticks/s) -host_mem_usage 230508 # Number of bytes of host memory used -host_seconds 14199.12 # Real time elapsed on the host +host_inst_rate 109896 # Simulator instruction rate (inst/s) +host_op_rate 109896 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60832901 # Simulator tick rate (ticks/s) +host_mem_usage 265436 # Number of bytes of host memory used +host_seconds 16559.08 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,64 +25,64 @@ system.physmem.num_reads::cpu.data 1958829 # Nu system.physmem.num_reads::total 1959688 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1018055 # Number of write requests responded to by this memory system.physmem.num_writes::total 1018055 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 54440 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 124143704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 124198144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 54440 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 54440 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 64520751 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 64520751 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 64520751 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 54440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 124143704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 188718895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 54576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 124452002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 124506578 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 54576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 54576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 64680982 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 64680982 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 64680982 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 54576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 124452002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 189187560 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1959688 # Number of read requests accepted system.physmem.writeReqs 1018055 # Number of write requests accepted system.physmem.readBursts 1959688 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1018055 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125384704 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 35328 # Total number of bytes read from write queue -system.physmem.bytesWritten 65154176 # Total number of bytes written to DRAM +system.physmem.bytesReadDRAM 125336064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83968 # Total number of bytes read from write queue +system.physmem.bytesWritten 65153920 # Total number of bytes written to DRAM system.physmem.bytesReadSys 125420032 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 65155520 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 552 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 1312 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118719 # Per bank write bursts -system.physmem.perBankRdBursts::1 114075 # Per bank write bursts -system.physmem.perBankRdBursts::2 116210 # Per bank write bursts -system.physmem.perBankRdBursts::3 117697 # Per bank write bursts -system.physmem.perBankRdBursts::4 117769 # Per bank write bursts -system.physmem.perBankRdBursts::5 117504 # Per bank write bursts -system.physmem.perBankRdBursts::6 119870 # Per bank write bursts -system.physmem.perBankRdBursts::7 124481 # Per bank write bursts -system.physmem.perBankRdBursts::8 126964 # Per bank write bursts -system.physmem.perBankRdBursts::9 130062 # Per bank write bursts -system.physmem.perBankRdBursts::10 128627 # Per bank write bursts -system.physmem.perBankRdBursts::11 130265 # Per bank write bursts -system.physmem.perBankRdBursts::12 125943 # Per bank write bursts -system.physmem.perBankRdBursts::13 125205 # Per bank write bursts -system.physmem.perBankRdBursts::14 122569 # Per bank write bursts -system.physmem.perBankRdBursts::15 123176 # Per bank write bursts +system.physmem.perBankRdBursts::0 118685 # Per bank write bursts +system.physmem.perBankRdBursts::1 114026 # Per bank write bursts +system.physmem.perBankRdBursts::2 116162 # Per bank write bursts +system.physmem.perBankRdBursts::3 117671 # Per bank write bursts +system.physmem.perBankRdBursts::4 117731 # Per bank write bursts +system.physmem.perBankRdBursts::5 117464 # Per bank write bursts +system.physmem.perBankRdBursts::6 119807 # Per bank write bursts +system.physmem.perBankRdBursts::7 124441 # Per bank write bursts +system.physmem.perBankRdBursts::8 126920 # Per bank write bursts +system.physmem.perBankRdBursts::9 130015 # Per bank write bursts +system.physmem.perBankRdBursts::10 128574 # Per bank write bursts +system.physmem.perBankRdBursts::11 130216 # Per bank write bursts +system.physmem.perBankRdBursts::12 125899 # Per bank write bursts +system.physmem.perBankRdBursts::13 125145 # Per bank write bursts +system.physmem.perBankRdBursts::14 122505 # Per bank write bursts +system.physmem.perBankRdBursts::15 123115 # Per bank write bursts system.physmem.perBankWrBursts::0 61223 # Per bank write bursts system.physmem.perBankWrBursts::1 61467 # Per bank write bursts system.physmem.perBankWrBursts::2 60558 # Per bank write bursts -system.physmem.perBankWrBursts::3 61216 # Per bank write bursts +system.physmem.perBankWrBursts::3 61215 # Per bank write bursts system.physmem.perBankWrBursts::4 61647 # Per bank write bursts -system.physmem.perBankWrBursts::5 63084 # Per bank write bursts -system.physmem.perBankWrBursts::6 64137 # Per bank write bursts +system.physmem.perBankWrBursts::5 63083 # Per bank write bursts +system.physmem.perBankWrBursts::6 64136 # Per bank write bursts system.physmem.perBankWrBursts::7 65614 # Per bank write bursts system.physmem.perBankWrBursts::8 65332 # Per bank write bursts -system.physmem.perBankWrBursts::9 65770 # Per bank write bursts -system.physmem.perBankWrBursts::10 65297 # Per bank write bursts -system.physmem.perBankWrBursts::11 65611 # Per bank write bursts -system.physmem.perBankWrBursts::12 64149 # Per bank write bursts -system.physmem.perBankWrBursts::13 64192 # Per bank write bursts -system.physmem.perBankWrBursts::14 64551 # Per bank write bursts +system.physmem.perBankWrBursts::9 65769 # Per bank write bursts +system.physmem.perBankWrBursts::10 65294 # Per bank write bursts +system.physmem.perBankWrBursts::11 65608 # Per bank write bursts +system.physmem.perBankWrBursts::12 64146 # Per bank write bursts +system.physmem.perBankWrBursts::13 64202 # Per bank write bursts +system.physmem.perBankWrBursts::14 64550 # Per bank write bursts system.physmem.perBankWrBursts::15 64186 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1009838141500 # Total gap between requests +system.physmem.totGap 1007336518500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -97,10 +97,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1018055 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1662258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 204908 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 70586 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 21384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1664981 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 198590 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70959 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23846 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -129,234 +129,213 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 45504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 45756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 45744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 45701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 45665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 45697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 45681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 45686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 45671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 45688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 45723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 45729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 45793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 45986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 46199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 46502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 48930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1862398 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 102.290110 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 79.389553 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 186.671437 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1500560 80.57% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 201450 10.82% 91.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 59792 3.21% 94.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 29273 1.57% 96.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 16605 0.89% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 10399 0.56% 97.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 7221 0.39% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 6896 0.37% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 4046 0.22% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3343 0.18% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 3041 0.16% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2820 0.15% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1620 0.09% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1539 0.08% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1515 0.08% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1490 0.08% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 1330 0.07% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1307 0.07% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 969 0.05% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 1340 0.07% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 596 0.03% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 2192 0.12% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 189 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 700 0.04% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 112 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 81 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 79 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 79 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 66 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 52 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 55 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 71 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 36 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 40 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 43 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 52 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 33 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 31 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 35 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 28 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 29 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 30 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 34 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 33 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 22 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 20 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 22 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 24 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 16 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 19 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 21 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 28 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 15 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 19 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 14 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 18 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 13 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 13 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 16 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 25 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 17 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 18 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 21 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 22 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 15 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 12 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 17 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 19 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 13 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 14 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 8 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 17 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 11 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 11 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 10 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 12 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 106 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 10 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 8 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 6 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 9 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 6 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 15 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 13 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 10 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 11 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 12 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 7 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 4 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 11 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 10 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 5 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 11 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 8 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 5 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 7 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 10 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 8 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 5 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 6 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 14 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 9 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 13 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 64 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 154 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1862398 # Bytes accessed per row activation -system.physmem.totQLat 23048924250 # Total ticks spent queuing -system.physmem.totMemAccLat 84969451750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9795680000 # Total ticks spent in databus transfers -system.physmem.totBankLat 52124847500 # Total ticks spent accessing banks -system.physmem.avgQLat 11764.84 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 26606.04 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 26939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 28117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 34916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 48946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 53936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 56821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 58079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 58536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 58949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 59504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 64559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 64811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 64584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 72712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 60810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 14814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1266500 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 109.102187 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 83.148932 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 142.836675 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 979529 77.34% 77.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 199046 15.72% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 36524 2.88% 95.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 14982 1.18% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8864 0.70% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4419 0.35% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2809 0.22% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2238 0.18% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 18089 1.43% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1266500 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 58142 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.680816 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 161.230571 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 58099 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 58142 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 58142 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.509374 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.424358 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.849185 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 29010 49.90% 49.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1046 1.80% 51.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 6657 11.45% 63.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 16493 28.37% 91.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 3312 5.70% 97.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 1061 1.82% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 264 0.45% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 97 0.17% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 56 0.10% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 17 0.03% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 18 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 13 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 5 0.01% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 6 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 5 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 5 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 3 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 3 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 2 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 2 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 28 0.05% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 9 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 6 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::59 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 58142 # Writes before turning the bus around for reads +system.physmem.totQLat 19659284500 # Total ticks spent queuing +system.physmem.totMemAccLat 80383790750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9791880000 # Total ticks spent in databus transfers +system.physmem.totBankLat 50932626250 # Total ticks spent accessing banks +system.physmem.avgQLat 10038.56 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 26007.58 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43370.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 124.16 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 64.52 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 124.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 64.52 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41046.15 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 124.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 64.68 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 124.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 64.68 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.47 # Data bus utilization in percentage +system.physmem.busUtil 1.48 # Data bus utilization in percentage system.physmem.busUtilRead 0.97 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.50 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.29 # Average write queue length when enqueuing -system.physmem.readRowHits 771409 # Number of row buffer hits during reads -system.physmem.writeRowHits 343363 # Number of row buffer hits during writes -system.physmem.readRowHitRate 39.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 33.73 # Row buffer hit rate for writes -system.physmem.avgGap 339128.71 # Average gap between requests -system.physmem.pageHitRate 37.44 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 12.16 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 188718895 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1178392 # Transaction distribution -system.membus.trans_dist::ReadResp 1178392 # Transaction distribution +system.physmem.busUtilWrite 0.51 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing +system.physmem.readRowHits 753336 # Number of row buffer hits during reads +system.physmem.writeRowHits 422191 # Number of row buffer hits during writes +system.physmem.readRowHitRate 38.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.47 # Row buffer hit rate for writes +system.physmem.avgGap 338288.60 # Average gap between requests +system.physmem.pageHitRate 39.49 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 12.29 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 189187560 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1178393 # Transaction distribution +system.membus.trans_dist::ReadResp 1178393 # Transaction distribution system.membus.trans_dist::Writeback 1018055 # Transaction distribution -system.membus.trans_dist::ReadExReq 781296 # Transaction distribution -system.membus.trans_dist::ReadExResp 781296 # Transaction distribution +system.membus.trans_dist::ReadExReq 781295 # Transaction distribution +system.membus.trans_dist::ReadExResp 781295 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937431 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 4937431 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575552 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 190575552 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 190575552 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11785228500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11782666500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 18364778000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18347417750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 326538257 # Number of BP lookups -system.cpu.branchPred.condPredicted 252572868 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 138234365 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 220428800 # Number of BTB lookups -system.cpu.branchPred.BTBHits 135446379 # Number of BTB hits +system.cpu.branchPred.lookups 326511183 # Number of BP lookups +system.cpu.branchPred.condPredicted 252559725 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 138218265 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 220270477 # Number of BTB lookups +system.cpu.branchPred.BTBHits 135614039 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.446771 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 61.567052 # BTB Hit Percentage system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444831817 # DTB read hits +system.cpu.dtb.read_hits 444830139 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449728895 # DTB read accesses -system.cpu.dtb.write_hits 160846718 # DTB write hits +system.cpu.dtb.read_accesses 449727217 # DTB read accesses +system.cpu.dtb.write_hits 160844128 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162548022 # DTB write accesses -system.cpu.dtb.data_hits 605678535 # DTB hits +system.cpu.dtb.write_accesses 162545432 # DTB write accesses +system.cpu.dtb.data_hits 605674267 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612276917 # DTB accesses -system.cpu.itb.fetch_hits 231928870 # ITB hits +system.cpu.dtb.data_accesses 612272649 # DTB accesses +system.cpu.itb.fetch_hits 232118114 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 231928892 # ITB accesses +system.cpu.itb.fetch_accesses 232118136 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -370,34 +349,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2019676430 # number of cpu cycles simulated +system.cpu.numCycles 2014673184 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 172263299 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 154274958 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1667627607 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 172428181 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154083002 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1667622783 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3043830224 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3043825400 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 231 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651720859 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617884928 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 120516333 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 11119574 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 131635907 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 83564055 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 61.169113 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139356886 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 576 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651695392 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617886274 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 120493688 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 11126119 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 131619807 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 83580161 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.161629 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139354623 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1742060649 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1742144730 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7515544 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 447943086 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1571733344 # Number of cycles cpu stages are processed. -system.cpu.activity 77.821047 # Percentage of cycles cpu is active +system.cpu.timesIdled 7512368 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 442846963 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571826221 # Number of cycles cpu stages are processed. +system.cpu.activity 78.018918 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -409,78 +388,78 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.109846 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.107097 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.109846 # CPI: Total CPI of All Threads -system.cpu.ipc 0.901026 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.107097 # CPI: Total CPI of All Threads +system.cpu.ipc 0.903263 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.901026 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 833031386 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1186645044 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 58.754216 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1085876271 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933800159 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.235137 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1047285367 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 972391063 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.145884 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1610051904 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409624526 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.281691 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 998329594 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1021346836 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 50.569825 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.903263 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 827756857 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186916327 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 58.913591 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1081059316 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933613868 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.340711 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1042290381 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972382803 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 48.265039 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1605047974 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409625210 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.332092 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 993337465 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021335719 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 50.694858 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 668.332859 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 231927731 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 668.288600 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 232116975 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 269997.358556 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 270217.665891 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 668.332859 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.326334 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.326334 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 668.288600 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.326313 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.326313 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 858 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 785 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.418945 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 463858599 # Number of tag accesses -system.cpu.icache.tags.data_accesses 463858599 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 231927731 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 231927731 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 231927731 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 231927731 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 231927731 # number of overall hits -system.cpu.icache.overall_hits::total 231927731 # number of overall hits +system.cpu.icache.tags.tag_accesses 464237087 # Number of tag accesses +system.cpu.icache.tags.data_accesses 464237087 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 232116975 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 232116975 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 232116975 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 232116975 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 232116975 # number of overall hits +system.cpu.icache.overall_hits::total 232116975 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1139 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1139 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1139 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1139 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1139 # number of overall misses system.cpu.icache.overall_misses::total 1139 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 82716500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 82716500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 82716500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 82716500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 82716500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 82716500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 231928870 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 231928870 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 231928870 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 231928870 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 231928870 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 231928870 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 81449500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 81449500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 81449500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 81449500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 81449500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 81449500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 232118114 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 232118114 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 232118114 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 232118114 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 232118114 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 232118114 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72622.036874 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72622.036874 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72622.036874 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72622.036874 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72622.036874 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72622.036874 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71509.657594 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71509.657594 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71509.657594 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71509.657594 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 71509.657594 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71509.657594 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 162 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -501,134 +480,134 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 859 system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65136250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 65136250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65136250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 65136250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65136250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 65136250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 63326500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 63326500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 63326500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 63326500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 63326500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 63326500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75827.997672 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75827.997672 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75827.997672 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75827.997672 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75827.997672 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75827.997672 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73721.187427 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73721.187427 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73721.187427 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73721.187427 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73721.187427 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73721.187427 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 811573074 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7222683 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7222683 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3693280 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1889623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1889623 # Transaction distribution +system.cpu.toL2Bus.throughput 813589109 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7222688 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7222688 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3693283 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1889624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1889624 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1718 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916174 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21917892 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916189 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21917907 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819502528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 819557504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 819557504 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819503104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 819558080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 819558080 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10096073000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10096080500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1445250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1443000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13991718500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13971303500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.l2cache.tags.replacements 1926957 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30919.698369 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8958682 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 30916.680897 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8958690 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1956750 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.578348 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 67892812750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14931.951876 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.659960 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15953.086532 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.455687 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001058 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.486850 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.943594 # Average percentage of cache occupancy +system.cpu.l2cache.tags.avg_refs 4.578352 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 67897094750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14926.990701 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.739406 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15954.950790 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.455536 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001060 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.486906 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.943502 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29793 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 613 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 725 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 586 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 752 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12815 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15482 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909210 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 106291061 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 106291061 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.data 6044291 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6044291 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3693280 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3693280 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108327 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108327 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7152618 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7152618 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7152618 # number of overall hits -system.cpu.l2cache.overall_hits::total 7152618 # number of overall hits +system.cpu.l2cache.tags.tag_accesses 106291134 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 106291134 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.data 6044295 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6044295 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3693283 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3693283 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108329 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108329 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7152624 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7152624 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -640,91 +619,91 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 1018055 # number of writebacks system.cpu.l2cache.writebacks::total 1018055 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177533 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1178392 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781296 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 781296 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177534 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1178393 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781295 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 781295 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73894.946802 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73889.852109 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60169.965076 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68868.811219 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68862.470118 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75612.321210 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75612.321210 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60169.965076 # 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Number of tag accesses -system.cpu.dcache.tags.data_accesses 1219759777 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 437268777 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437268777 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156014425 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156014425 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 593283202 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 593283202 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 593283202 # number of overall hits -system.cpu.dcache.overall_hits::total 593283202 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7326886 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7326886 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4714077 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4714077 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 12040963 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 12040963 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 12040963 # number of overall misses -system.cpu.dcache.overall_misses::total 12040963 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 183066004000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 183066004000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 258278135000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 258278135000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 441344139000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 441344139000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 441344139000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 441344139000 # number of overall miss cycles +system.cpu.dcache.tags.tag_accesses 1219759783 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1219759783 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 437268768 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437268768 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 156029638 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156029638 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593298406 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593298406 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593298406 # number of overall hits +system.cpu.dcache.overall_hits::total 593298406 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7326895 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7326895 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4698864 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4698864 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 12025759 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 12025759 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12025759 # number of overall misses +system.cpu.dcache.overall_misses::total 12025759 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 180765205750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 180765205750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 250221551250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 250221551250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 430986757000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 430986757000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 430986757000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 430986757000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -735,54 +714,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029329 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029329 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.019892 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.019892 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019892 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019892 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24985.512809 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24985.512809 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54788.696706 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54788.696706 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36653.558274 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36653.558274 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36653.558274 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36653.558274 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12098433 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7855784 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 422647 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 73423 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.625385 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 106.993503 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029235 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029235 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.019867 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.019867 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.019867 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019867 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24671.461206 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24671.461206 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53251.498926 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53251.498926 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35838.632472 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35838.632472 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35838.632472 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35838.632472 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 11447989 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7764770 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 416735 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 73422 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.470668 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 105.755359 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3693280 # number of writebacks -system.cpu.dcache.writebacks::total 3693280 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104620 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104620 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2824896 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2824896 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2929516 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2929516 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2929516 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2929516 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222266 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222266 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889181 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889181 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111447 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111447 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111447 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111447 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 165959957500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 165959957500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84276720000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84276720000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250236677500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 250236677500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 250236677500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 250236677500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3693283 # number of writebacks +system.cpu.dcache.writebacks::total 3693283 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104624 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104624 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2809682 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2809682 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2914306 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2914306 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2914306 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2914306 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222271 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222271 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889182 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889182 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111453 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111453 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111453 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111453 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 163647011750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 163647011750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 81975016250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 81975016250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245622028000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 245622028000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245622028000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 245622028000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -791,14 +770,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22978.931751 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22978.931751 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44610.188224 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44610.188224 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27463.988706 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27463.988706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27463.988706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27463.988706 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22658.663978 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22658.663978 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43391.804628 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43391.804628 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26957.503704 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26957.503704 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26957.503704 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26957.503704 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 09d12ecba..2f4d3475f 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.685387 # Number of seconds simulated -sim_ticks 685386545000 # Number of ticks simulated -final_tick 685386545000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.682192 # Number of seconds simulated +sim_ticks 682191807000 # Number of ticks simulated +final_tick 682191807000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166100 # Simulator instruction rate (inst/s) -host_op_rate 166100 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65575812 # Simulator tick rate (ticks/s) -host_mem_usage 231660 # Number of bytes of host memory used -host_seconds 10451.82 # Real time elapsed on the host +host_inst_rate 139307 # Simulator instruction rate (inst/s) +host_op_rate 139307 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54741914 # Simulator tick rate (ticks/s) +host_mem_usage 268504 # Number of bytes of host memory used +host_seconds 12461.96 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125792064 # Number of bytes read from this memory -system.physmem.bytes_read::total 125853824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65263104 # Number of bytes written to this memory -system.physmem.bytes_written::total 65263104 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 965 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965501 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966466 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019736 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019736 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 90110 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 183534481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 183624591 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 90110 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 90110 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 95220871 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 95220871 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 95220871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 90110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 183534481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 278845462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966466 # Number of read requests accepted -system.physmem.writeReqs 1019736 # Number of write requests accepted -system.physmem.readBursts 1966466 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1019736 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125817344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 36480 # Total number of bytes read from write queue -system.physmem.bytesWritten 65263104 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125853824 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65263104 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 570 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 61696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125800064 # Number of bytes read from this memory +system.physmem.bytes_read::total 125861760 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61696 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65265984 # Number of bytes written to this memory +system.physmem.bytes_written::total 65265984 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 964 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965626 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966590 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019781 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019781 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 90438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 184405709 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 184496147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 90438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 90438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 95671017 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 95671017 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 95671017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 90438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 184405709 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 280167164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966590 # Number of read requests accepted +system.physmem.writeReqs 1019781 # Number of write requests accepted +system.physmem.readBursts 1966590 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1019781 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125780416 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 81344 # Total number of bytes read from write queue +system.physmem.bytesWritten 65264896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125861760 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65265984 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1271 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119017 # Per bank write bursts -system.physmem.perBankRdBursts::1 114428 # Per bank write bursts -system.physmem.perBankRdBursts::2 116569 # Per bank write bursts -system.physmem.perBankRdBursts::3 118023 # Per bank write bursts -system.physmem.perBankRdBursts::4 118127 # Per bank write bursts -system.physmem.perBankRdBursts::5 117816 # Per bank write bursts -system.physmem.perBankRdBursts::6 120202 # Per bank write bursts -system.physmem.perBankRdBursts::7 124913 # Per bank write bursts -system.physmem.perBankRdBursts::8 127544 # Per bank write bursts -system.physmem.perBankRdBursts::9 130446 # Per bank write bursts -system.physmem.perBankRdBursts::10 129104 # Per bank write bursts -system.physmem.perBankRdBursts::11 130773 # Per bank write bursts -system.physmem.perBankRdBursts::12 126663 # Per bank write bursts -system.physmem.perBankRdBursts::13 125636 # Per bank write bursts -system.physmem.perBankRdBursts::14 122981 # Per bank write bursts -system.physmem.perBankRdBursts::15 123654 # Per bank write bursts -system.physmem.perBankWrBursts::0 61274 # Per bank write bursts -system.physmem.perBankWrBursts::1 61571 # Per bank write bursts -system.physmem.perBankWrBursts::2 60654 # Per bank write bursts -system.physmem.perBankWrBursts::3 61312 # Per bank write bursts -system.physmem.perBankWrBursts::4 61747 # Per bank write bursts -system.physmem.perBankWrBursts::5 63190 # Per bank write bursts -system.physmem.perBankWrBursts::6 64213 # Per bank write bursts -system.physmem.perBankWrBursts::7 65700 # Per bank write bursts -system.physmem.perBankWrBursts::8 65483 # Per bank write bursts -system.physmem.perBankWrBursts::9 65878 # Per bank write bursts -system.physmem.perBankWrBursts::10 65419 # Per bank write bursts -system.physmem.perBankWrBursts::11 65720 # Per bank write bursts -system.physmem.perBankWrBursts::12 64327 # Per bank write bursts -system.physmem.perBankWrBursts::13 64305 # Per bank write bursts -system.physmem.perBankWrBursts::14 64649 # Per bank write bursts -system.physmem.perBankWrBursts::15 64294 # Per bank write bursts +system.physmem.perBankRdBursts::0 118991 # Per bank write bursts +system.physmem.perBankRdBursts::1 114394 # Per bank write bursts +system.physmem.perBankRdBursts::2 116519 # Per bank write bursts +system.physmem.perBankRdBursts::3 118029 # Per bank write bursts +system.physmem.perBankRdBursts::4 118142 # Per bank write bursts +system.physmem.perBankRdBursts::5 117777 # Per bank write bursts +system.physmem.perBankRdBursts::6 120156 # Per bank write bursts +system.physmem.perBankRdBursts::7 124892 # Per bank write bursts +system.physmem.perBankRdBursts::8 127514 # Per bank write bursts +system.physmem.perBankRdBursts::9 130376 # Per bank write bursts +system.physmem.perBankRdBursts::10 129025 # Per bank write bursts +system.physmem.perBankRdBursts::11 130742 # Per bank write bursts +system.physmem.perBankRdBursts::12 126628 # Per bank write bursts +system.physmem.perBankRdBursts::13 125605 # Per bank write bursts +system.physmem.perBankRdBursts::14 122932 # Per bank write bursts +system.physmem.perBankRdBursts::15 123597 # Per bank write bursts +system.physmem.perBankWrBursts::0 61284 # Per bank write bursts +system.physmem.perBankWrBursts::1 61572 # Per bank write bursts +system.physmem.perBankWrBursts::2 60658 # Per bank write bursts +system.physmem.perBankWrBursts::3 61323 # Per bank write bursts +system.physmem.perBankWrBursts::4 61765 # Per bank write bursts +system.physmem.perBankWrBursts::5 63192 # Per bank write bursts +system.physmem.perBankWrBursts::6 64214 # Per bank write bursts +system.physmem.perBankWrBursts::7 65706 # Per bank write bursts +system.physmem.perBankWrBursts::8 65482 # Per bank write bursts +system.physmem.perBankWrBursts::9 65855 # Per bank write bursts +system.physmem.perBankWrBursts::10 65405 # Per bank write bursts +system.physmem.perBankWrBursts::11 65740 # Per bank write bursts +system.physmem.perBankWrBursts::12 64329 # Per bank write bursts +system.physmem.perBankWrBursts::13 64310 # Per bank write bursts +system.physmem.perBankWrBursts::14 64647 # Per bank write bursts +system.physmem.perBankWrBursts::15 64282 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 4 # Number of times write queue was full causing retry -system.physmem.totGap 685386422500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 682191684500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1966466 # Read request sizes (log2) +system.physmem.readPktSize::6 1966590 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1019736 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1645035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 231982 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 68923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19945 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1019781 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1642976 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 230548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -129,235 +129,203 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 45483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 45666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 45709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 45696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 45650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 45681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 45674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 45697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 45708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 45706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 45762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 45739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 45791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 45957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 46127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 46326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 49473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 48655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1821867 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 104.857955 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 80.098310 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 197.882118 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1460616 80.17% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 186071 10.21% 90.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 71892 3.95% 94.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 32365 1.78% 96.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 16766 0.92% 97.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 10653 0.58% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 7007 0.38% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 6870 0.38% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 3886 0.21% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3166 0.17% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2723 0.15% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 1980 0.11% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1594 0.09% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1502 0.08% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1242 0.07% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1240 0.07% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 1003 0.06% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1017 0.06% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 831 0.05% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 807 0.04% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 751 0.04% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 2873 0.16% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 389 0.02% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 742 0.04% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 289 0.02% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 237 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 196 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 198 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 161 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 147 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 132 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 165 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 370 0.02% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 134 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 101 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 83 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 73 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 67 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 51 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 72 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 49 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 40 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 35 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 42 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 36 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 34 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 27 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 45 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 32 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 23 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 19 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 28 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 20 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 15 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 21 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 35 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 14 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 9 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 10 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 15 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 20 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 9 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 19 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 21 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 16 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 11 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 15 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 12 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 9 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 10 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 16 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 24 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 17 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 8 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 15 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 14 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 12 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 12 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 18 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 22 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 17 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 11 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 8 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 12 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 14 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 17 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 26 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 14 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 4 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 11 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 10 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 9 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 14 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 22 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 13 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 10 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 9 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 9 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 10 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 7 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 17 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 89 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 28 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 7 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 7 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 123 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1821867 # Bytes accessed per row activation -system.physmem.totQLat 24443368500 # Total ticks spent queuing -system.physmem.totMemAccLat 84807426000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9829480000 # Total ticks spent in databus transfers -system.physmem.totBankLat 50534577500 # Total ticks spent accessing banks -system.physmem.avgQLat 12433.70 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 25705.62 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 23411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 31804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 54150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 57221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 58425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 59086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 59586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 60134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 64812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 65271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 65616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 73465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 64939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 60584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 17452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1251998 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 113.111439 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 84.586325 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 150.844327 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 955672 76.33% 76.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 201584 16.10% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 38062 3.04% 95.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 16101 1.29% 96.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 9606 0.77% 97.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4835 0.39% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3234 0.26% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2576 0.21% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20328 1.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1251998 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 58888 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.373692 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 161.339848 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 58850 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 11 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 58888 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 58888 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.317009 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.233410 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.918536 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 34047 57.82% 57.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 20086 34.11% 91.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 4266 7.24% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 290 0.49% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 84 0.14% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 30 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 14 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 5 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 4 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 3 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 12 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 19 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 9 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-65 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::78-79 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::86-87 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-89 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-105 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::106-107 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 58888 # Writes before turning the bus around for reads +system.physmem.totQLat 20653307250 # Total ticks spent queuing +system.physmem.totMemAccLat 80037239750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9826595000 # Total ticks spent in databus transfers +system.physmem.totBankLat 49557337500 # Total ticks spent accessing banks +system.physmem.avgQLat 10508.88 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 25215.93 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43139.32 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 183.57 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 95.22 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 183.62 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 95.22 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 40724.81 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 184.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 95.67 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 184.50 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 95.67 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.18 # Data bus utilization in percentage -system.physmem.busUtilRead 1.43 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.12 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.01 # Average write queue length when enqueuing -system.physmem.readRowHits 819101 # Number of row buffer hits during reads -system.physmem.writeRowHits 344664 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 33.80 # Row buffer hit rate for writes -system.physmem.avgGap 229517.77 # Average gap between requests -system.physmem.pageHitRate 38.98 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 7.14 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 278845462 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1191273 # Transaction distribution -system.membus.trans_dist::ReadResp 1191273 # Transaction distribution -system.membus.trans_dist::Writeback 1019736 # Transaction distribution -system.membus.trans_dist::ReadExReq 775193 # Transaction distribution -system.membus.trans_dist::ReadExResp 775193 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952668 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4952668 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191116928 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 191116928 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 191116928 # Total data (bytes) +system.physmem.busUtil 2.19 # Data bus utilization in percentage +system.physmem.busUtilRead 1.44 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.75 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.29 # Average write queue length when enqueuing +system.physmem.readRowHits 797879 # Number of row buffer hits during reads +system.physmem.writeRowHits 422825 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.46 # Row buffer hit rate for writes +system.physmem.avgGap 228435.01 # Average gap between requests +system.physmem.pageHitRate 40.89 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 7.23 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 280167164 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1191439 # Transaction distribution +system.membus.trans_dist::ReadResp 1191439 # Transaction distribution +system.membus.trans_dist::Writeback 1019781 # Transaction distribution +system.membus.trans_dist::ReadExReq 775151 # Transaction distribution +system.membus.trans_dist::ReadExResp 775151 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952961 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4952961 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191127744 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 191127744 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 191127744 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11873404000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11872683000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 18493738500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18474077250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 381642976 # Number of BP lookups -system.cpu.branchPred.condPredicted 296606399 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16082111 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 262443817 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259723367 # Number of BTB hits +system.cpu.branchPred.lookups 381618384 # Number of BP lookups +system.cpu.branchPred.condPredicted 296575373 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16092188 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 262164042 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259697812 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.963416 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24699577 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3003 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.059280 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24705469 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3069 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613972689 # DTB read hits -system.cpu.dtb.read_misses 11257711 # DTB read misses +system.cpu.dtb.read_hits 613976008 # DTB read hits +system.cpu.dtb.read_misses 11261750 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625230400 # DTB read accesses -system.cpu.dtb.write_hits 212364531 # DTB write hits -system.cpu.dtb.write_misses 7123508 # DTB write misses +system.cpu.dtb.read_accesses 625237758 # DTB read accesses +system.cpu.dtb.write_hits 212363538 # DTB write hits +system.cpu.dtb.write_misses 7134748 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219488039 # DTB write accesses -system.cpu.dtb.data_hits 826337220 # DTB hits -system.cpu.dtb.data_misses 18381219 # DTB misses +system.cpu.dtb.write_accesses 219498286 # DTB write accesses +system.cpu.dtb.data_hits 826339546 # DTB hits +system.cpu.dtb.data_misses 18396498 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 844718439 # DTB accesses -system.cpu.itb.fetch_hits 391054896 # ITB hits -system.cpu.itb.fetch_misses 42 # ITB misses +system.cpu.dtb.data_accesses 844736044 # DTB accesses +system.cpu.itb.fetch_hits 391110222 # ITB hits +system.cpu.itb.fetch_misses 44 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 391054938 # ITB accesses +system.cpu.itb.fetch_accesses 391110266 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -371,138 +339,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1370773091 # number of cpu cycles simulated +system.cpu.numCycles 1364383615 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402523002 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3161115412 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381642976 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 284422944 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 574525052 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140645567 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 190952168 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1444 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 391054896 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8064214 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1284797805 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.460399 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.144459 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402585287 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3161125101 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381618384 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284403281 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574536383 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140665925 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 188120516 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1448 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 4 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 391110222 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8062763 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1282059246 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.465662 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.145744 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 710272753 55.28% 55.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42667609 3.32% 58.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21782496 1.70% 60.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39699327 3.09% 63.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129330544 10.07% 73.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61540269 4.79% 78.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38580495 3.00% 81.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28116157 2.19% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212808155 16.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 707522863 55.19% 55.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42675531 3.33% 58.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21787283 1.70% 60.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39707555 3.10% 63.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129310443 10.09% 73.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61549431 4.80% 78.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38571496 3.01% 81.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28142716 2.20% 83.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212791928 16.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1284797805 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.278414 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.306082 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 434521910 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 172167391 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542471492 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18841651 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116795361 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58349498 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 879 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3088463521 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2045 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116795361 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 457475867 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116907635 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7798 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535572514 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 58038630 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3006337354 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 608843 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1808950 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 51752219 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2247576032 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3898866654 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3898722180 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 144473 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1282059246 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.279700 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.316889 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 434597074 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 169317553 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542454813 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18875119 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116814687 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58354170 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 898 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3088496267 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2037 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116814687 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 457547940 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 113953082 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6967 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535589228 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 58147342 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3006454755 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 609106 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1833248 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 51828481 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2247677853 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3898974365 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3898830865 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 143499 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 871373069 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 157 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 156 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 123546719 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679659315 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255464076 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67507479 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 36716823 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2724801247 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 120 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2509489521 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3207288 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 979575578 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 416138423 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1284797805 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.953217 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.971436 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 871474890 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 178 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 177 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 123676155 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679702242 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255475560 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67614908 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 37053481 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2724914461 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 131 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2509610552 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3196332 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 979670705 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 416123894 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 102 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1282059246 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.957484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.971278 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 442944970 34.48% 34.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 203642722 15.85% 50.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185470521 14.44% 64.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153370563 11.94% 76.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133097213 10.36% 87.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80758631 6.29% 93.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65098641 5.07% 98.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15296137 1.19% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5118407 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 440049739 34.32% 34.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 203670606 15.89% 50.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185671301 14.48% 64.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153363283 11.96% 76.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133052268 10.38% 87.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80767651 6.30% 93.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65047769 5.07% 98.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15319478 1.19% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5117151 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1284797805 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1282059246 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2193136 11.83% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11923525 64.32% 76.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4420966 23.85% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2188252 11.81% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11925862 64.39% 76.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4407339 23.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643778581 65.50% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 107 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643881644 65.50% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 99 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 275 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 160 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 33 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 265 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 161 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 23 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued @@ -524,84 +493,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641602507 25.57% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224107818 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641614566 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224113754 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2509489521 # Type of FU issued -system.cpu.iq.rate 1.830711 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18537627 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007387 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6323623582 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3703265011 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2413078875 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1898180 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1217876 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 850894 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2527088869 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 938279 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62595515 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2509610552 # Type of FU issued +system.cpu.iq.rate 1.839373 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18521453 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007380 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6321098058 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3703474382 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2413201675 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1900077 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1218284 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 852187 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2527192648 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 939357 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62588107 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 235063652 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 262733 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 107683 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94735574 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 235106579 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 263309 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 109146 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94747058 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 113 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1541249 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 184 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1530387 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116795361 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 56591518 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1298088 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2866959659 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8943399 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679659315 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255464076 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 120 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 282702 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18018 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 107683 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10360004 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8558145 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18918149 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2462143246 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625230973 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47346275 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116814687 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 54760955 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1302145 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2867095326 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8936600 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679702242 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255475560 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 131 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 285836 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18373 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 109146 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10363389 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8561306 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18924695 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2462265598 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625238282 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47344954 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142158292 # number of nop insts executed -system.cpu.iew.exec_refs 844719037 # number of memory reference insts executed -system.cpu.iew.exec_branches 300873221 # Number of branches executed -system.cpu.iew.exec_stores 219488064 # Number of stores executed -system.cpu.iew.exec_rate 1.796171 # Inst execution rate -system.cpu.iew.wb_sent 2441862108 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2413929769 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388272639 # num instructions producing a value -system.cpu.iew.wb_consumers 1764258225 # num instructions consuming a value +system.cpu.iew.exec_nop 142180734 # number of nop insts executed +system.cpu.iew.exec_refs 844736593 # number of memory reference insts executed +system.cpu.iew.exec_branches 300891924 # Number of branches executed +system.cpu.iew.exec_stores 219498311 # Number of stores executed +system.cpu.iew.exec_rate 1.804673 # Inst execution rate +system.cpu.iew.wb_sent 2442007403 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2414053862 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388335082 # num instructions producing a value +system.cpu.iew.wb_consumers 1764294016 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.760999 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.786887 # average fanout of values written-back +system.cpu.iew.wb_rate 1.769337 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.786907 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 826504574 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 826637792 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16081360 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1168002444 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.558028 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.499439 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16091391 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1165244559 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.561715 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.500982 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 654033697 56.00% 56.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174911016 14.98% 70.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86140681 7.38% 78.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53576194 4.59% 82.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34697975 2.97% 85.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25994339 2.23% 88.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21604457 1.85% 89.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22883851 1.96% 91.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94160234 8.06% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 651170378 55.88% 55.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 175014835 15.02% 70.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86149099 7.39% 78.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53527990 4.59% 82.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34710349 2.98% 85.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26102733 2.24% 88.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21568948 1.85% 89.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22887442 1.96% 91.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94112785 8.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1168002444 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1165244559 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -612,225 +581,224 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94160234 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94112785 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3634347710 # The number of ROB reads -system.cpu.rob.rob_writes 5409463480 # The number of ROB writes -system.cpu.timesIdled 947782 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 85975286 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3631770492 # The number of ROB reads +system.cpu.rob.rob_writes 5409749589 # The number of ROB writes +system.cpu.timesIdled 953701 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 82324369 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.789596 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.789596 # CPI: Total CPI of All Threads -system.cpu.ipc 1.266471 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.266471 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3318031256 # number of integer regfile reads -system.cpu.int_regfile_writes 1931984794 # number of integer regfile writes -system.cpu.fp_regfile_reads 30556 # number of floating regfile reads -system.cpu.fp_regfile_writes 536 # number of floating regfile writes +system.cpu.cpi 0.785915 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.785915 # CPI: Total CPI of All Threads +system.cpu.ipc 1.272402 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.272402 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3318200326 # number of integer regfile reads +system.cpu.int_regfile_writes 1932098427 # number of integer regfile writes +system.cpu.fp_regfile_reads 30699 # number of floating regfile reads +system.cpu.fp_regfile_writes 520 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1205179048 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7297603 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7297603 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3725230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1883628 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1883628 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1930 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085762 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22087692 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825951744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 826013504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 826013504 # Total data (bytes) +system.cpu.toL2Bus.throughput 1210780745 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7297678 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7297678 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3724768 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1883565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1883565 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1928 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085326 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22087254 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825923008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 825984704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 825984704 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10178550909 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10177843430 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1610000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1605500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14084464250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14065476499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 773.100738 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 391053395 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 965 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 405236.678756 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 773.695817 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 391108717 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 964 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 405714.436722 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 773.100738 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.377491 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.377491 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 964 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 907 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.470703 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 782110757 # Number of tag accesses -system.cpu.icache.tags.data_accesses 782110757 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 391053395 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 391053395 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 391053395 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 391053395 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 391053395 # number of overall hits -system.cpu.icache.overall_hits::total 391053395 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1501 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1501 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1501 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1501 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1501 # number of overall misses -system.cpu.icache.overall_misses::total 1501 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 108152500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 108152500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 108152500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 108152500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 108152500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 108152500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 391054896 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 391054896 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 391054896 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 391054896 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 391054896 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 391054896 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 773.695817 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.377781 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.377781 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 963 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 906 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.470215 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 782221404 # Number of tag accesses +system.cpu.icache.tags.data_accesses 782221404 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 391108717 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 391108717 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 391108717 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 391108717 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 391108717 # number of overall hits +system.cpu.icache.overall_hits::total 391108717 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1503 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1503 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1503 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1503 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1503 # number of overall misses +system.cpu.icache.overall_misses::total 1503 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 108284500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 108284500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 108284500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 108284500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 108284500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 108284500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 391110220 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 391110220 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 391110220 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 391110220 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 391110220 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 391110220 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72053.630913 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72053.630913 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72053.630913 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72053.630913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72053.630913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72053.630913 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 156 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72045.575516 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72045.575516 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72045.575516 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72045.575516 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72045.575516 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72045.575516 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 349 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 78 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 69.800000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 964 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190475 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1191439 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775151 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 775151 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 964 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1965626 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1966590 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 964 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1965626 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1966590 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 62625000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 84983280750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 85045905750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 55444498500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 55444498500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 62625000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 140427779250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 140490404250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 62625000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 140427779250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 140490404250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163131 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163242 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411543 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411543 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163152 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163263 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411534 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411534 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214101 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214183 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214114 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214196 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214101 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214183 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64218.652850 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73672.039296 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 73664.381506 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74244.965125 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74244.965125 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64218.652850 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73898.001069 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73893.251142 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64218.652850 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73898.001069 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73893.251142 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214114 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214196 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64963.692946 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71386.027216 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71380.830869 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71527.352090 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71527.352090 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64963.692946 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71441.759139 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71438.583665 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64963.692946 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71441.759139 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71438.583665 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9176170 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.561673 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 694256138 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9180266 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 75.624839 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 9176183 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.522150 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 694277633 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9180279 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 75.627073 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 5178034250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.561673 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997940 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997940 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.522150 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997930 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997930 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 690 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2994 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 408 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 705 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2966 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 421 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1430860164 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1430860164 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 538716411 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 538716411 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155539725 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155539725 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 694256136 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694256136 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 694256136 # number of overall hits -system.cpu.dcache.overall_hits::total 694256136 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11395033 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11395033 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5188777 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5188777 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 1430905565 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1430905565 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 538740047 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 538740047 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155537583 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155537583 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 694277630 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694277630 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 694277630 # number of overall hits +system.cpu.dcache.overall_hits::total 694277630 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11394090 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11394090 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5190919 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5190919 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16583810 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16583810 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16583810 # number of overall misses -system.cpu.dcache.overall_misses::total 16583810 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 343354515500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 343354515500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 296317441834 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 296317441834 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 92250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 639671957334 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 639671957334 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 639671957334 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 639671957334 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 550111444 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 550111444 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 16585009 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16585009 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16585009 # number of overall misses +system.cpu.dcache.overall_misses::total 16585009 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 335805939499 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 335805939499 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 289123962439 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 289123962439 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 201500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 201500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 624929901938 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 624929901938 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 624929901938 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 624929901938 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 550134137 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 550134137 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710839946 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710839946 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710839946 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710839946 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020714 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020714 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032283 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032283 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023330 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023330 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023330 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023330 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30131.945691 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30131.945691 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57107.376523 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57107.376523 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38572.074652 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38572.074652 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38572.074652 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38572.074652 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12375504 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8646342 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 745563 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 710862639 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710862639 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710862639 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710862639 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020711 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020711 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032296 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032296 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023331 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023331 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023331 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023331 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 29471.940234 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 29471.940234 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55698.030048 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55698.030048 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 201500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 201500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37680.407767 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37680.407767 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37680.407767 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37680.407767 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 11880802 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8587513 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 745209 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 65135 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.598871 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 132.744945 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.942913 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 131.841759 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3725230 # number of writebacks -system.cpu.dcache.writebacks::total 3725230 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4098384 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4098384 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3305161 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3305161 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7403545 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7403545 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7403545 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7403545 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296649 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296649 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883616 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883616 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3724768 # number of writebacks +system.cpu.dcache.writebacks::total 3724768 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4097367 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4097367 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3307364 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3307364 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7404731 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7404731 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7404731 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7404731 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296723 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296723 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883555 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883555 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180265 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180265 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180265 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180265 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171833895250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 171833895250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80710616128 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 80710616128 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 89750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 89750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 252544511378 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 252544511378 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 252544511378 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 252544511378 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9180278 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180278 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180278 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180278 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 169103281751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 169103281751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78582140948 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 78582140948 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 247685422699 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 247685422699 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 247685422699 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 247685422699 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013264 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013264 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012915 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012915 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23549.700040 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23549.700040 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42848.763298 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42848.763298 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 89750 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 89750 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27509.501237 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27509.501237 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27509.501237 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27509.501237 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012914 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012914 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012914 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012914 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23175.236576 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23175.236576 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41720.120171 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41720.120171 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 199500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 199500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26980.165818 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26980.165818 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26980.165818 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26980.165818 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 8c6f8359f..06e7873ee 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.533762 # Number of seconds simulated -sim_ticks 533761922000 # Number of ticks simulated -final_tick 533761922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.530994 # Number of seconds simulated +sim_ticks 530994193500 # Number of ticks simulated +final_tick 530994193500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 155948 # Simulator instruction rate (inst/s) -host_op_rate 173972 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53891847 # Simulator tick rate (ticks/s) -host_mem_usage 269768 # Number of bytes of host memory used -host_seconds 9904.32 # Real time elapsed on the host +host_inst_rate 125227 # Simulator instruction rate (inst/s) +host_op_rate 139700 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43051016 # Simulator tick rate (ticks/s) +host_mem_usage 313040 # Number of bytes of host memory used +host_seconds 12334.07 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 47616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143740736 # Number of bytes read from this memory -system.physmem.bytes_read::total 143788352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70437056 # Number of bytes written to this memory -system.physmem.bytes_written::total 70437056 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 744 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245949 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246693 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100579 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100579 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 89208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 269297472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 269386680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 89208 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89208 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 131963434 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 131963434 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 131963434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 89208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 269297472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 401350114 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246694 # Number of read requests accepted -system.physmem.writeReqs 1100579 # Number of write requests accepted -system.physmem.readBursts 2246694 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1100579 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 143750848 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 37568 # Total number of bytes read from write queue -system.physmem.bytesWritten 70435904 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 143788416 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 70437056 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 587 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 47488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143709888 # Number of bytes read from this memory +system.physmem.bytes_read::total 143757376 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47488 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70419456 # Number of bytes written to this memory +system.physmem.bytes_written::total 70419456 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 742 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2245467 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246209 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100304 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100304 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 89432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 270643050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 270732482 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 89432 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89432 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 132618128 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 132618128 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 132618128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 89432 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 270643050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 403350610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246209 # Number of read requests accepted +system.physmem.writeReqs 1100304 # Number of write requests accepted +system.physmem.readBursts 2246209 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1100304 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 143663936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 93440 # Total number of bytes read from write queue +system.physmem.bytesWritten 70418368 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 143757376 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 70419456 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1460 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 139629 # Per bank write bursts -system.physmem.perBankRdBursts::1 136292 # Per bank write bursts -system.physmem.perBankRdBursts::2 133828 # Per bank write bursts -system.physmem.perBankRdBursts::3 136435 # Per bank write bursts -system.physmem.perBankRdBursts::4 134766 # Per bank write bursts -system.physmem.perBankRdBursts::5 135151 # Per bank write bursts -system.physmem.perBankRdBursts::6 136244 # Per bank write bursts -system.physmem.perBankRdBursts::7 136309 # Per bank write bursts -system.physmem.perBankRdBursts::8 143829 # Per bank write bursts -system.physmem.perBankRdBursts::9 146501 # Per bank write bursts -system.physmem.perBankRdBursts::10 144298 # Per bank write bursts -system.physmem.perBankRdBursts::11 146295 # Per bank write bursts -system.physmem.perBankRdBursts::12 145712 # Per bank write bursts -system.physmem.perBankRdBursts::13 146106 # Per bank write bursts -system.physmem.perBankRdBursts::14 142241 # Per bank write bursts -system.physmem.perBankRdBursts::15 142471 # Per bank write bursts -system.physmem.perBankWrBursts::0 69077 # Per bank write bursts -system.physmem.perBankWrBursts::1 67426 # Per bank write bursts -system.physmem.perBankWrBursts::2 65726 # Per bank write bursts -system.physmem.perBankWrBursts::3 66343 # Per bank write bursts -system.physmem.perBankWrBursts::4 66130 # Per bank write bursts -system.physmem.perBankWrBursts::5 66357 # Per bank write bursts -system.physmem.perBankWrBursts::6 67984 # Per bank write bursts -system.physmem.perBankWrBursts::7 68878 # Per bank write bursts -system.physmem.perBankWrBursts::8 70373 # Per bank write bursts -system.physmem.perBankWrBursts::9 70997 # Per bank write bursts -system.physmem.perBankWrBursts::10 70493 # Per bank write bursts -system.physmem.perBankWrBursts::11 70981 # Per bank write bursts -system.physmem.perBankWrBursts::12 70269 # Per bank write bursts -system.physmem.perBankWrBursts::13 70812 # Per bank write bursts -system.physmem.perBankWrBursts::14 69646 # Per bank write bursts -system.physmem.perBankWrBursts::15 69069 # Per bank write bursts +system.physmem.perBankRdBursts::0 139551 # Per bank write bursts +system.physmem.perBankRdBursts::1 136202 # Per bank write bursts +system.physmem.perBankRdBursts::2 133682 # Per bank write bursts +system.physmem.perBankRdBursts::3 136207 # Per bank write bursts +system.physmem.perBankRdBursts::4 134706 # Per bank write bursts +system.physmem.perBankRdBursts::5 135350 # Per bank write bursts +system.physmem.perBankRdBursts::6 136147 # Per bank write bursts +system.physmem.perBankRdBursts::7 135992 # Per bank write bursts +system.physmem.perBankRdBursts::8 143786 # Per bank write bursts +system.physmem.perBankRdBursts::9 146457 # Per bank write bursts +system.physmem.perBankRdBursts::10 144536 # Per bank write bursts +system.physmem.perBankRdBursts::11 146082 # Per bank write bursts +system.physmem.perBankRdBursts::12 145807 # Per bank write bursts +system.physmem.perBankRdBursts::13 145943 # Per bank write bursts +system.physmem.perBankRdBursts::14 141988 # Per bank write bursts +system.physmem.perBankRdBursts::15 142313 # Per bank write bursts +system.physmem.perBankWrBursts::0 69095 # Per bank write bursts +system.physmem.perBankWrBursts::1 67437 # Per bank write bursts +system.physmem.perBankWrBursts::2 65633 # Per bank write bursts +system.physmem.perBankWrBursts::3 66265 # Per bank write bursts +system.physmem.perBankWrBursts::4 66084 # Per bank write bursts +system.physmem.perBankWrBursts::5 66429 # Per bank write bursts +system.physmem.perBankWrBursts::6 67953 # Per bank write bursts +system.physmem.perBankWrBursts::7 68751 # Per bank write bursts +system.physmem.perBankWrBursts::8 70388 # Per bank write bursts +system.physmem.perBankWrBursts::9 70973 # Per bank write bursts +system.physmem.perBankWrBursts::10 70609 # Per bank write bursts +system.physmem.perBankWrBursts::11 70934 # Per bank write bursts +system.physmem.perBankWrBursts::12 70330 # Per bank write bursts +system.physmem.perBankWrBursts::13 70711 # Per bank write bursts +system.physmem.perBankWrBursts::14 69591 # Per bank write bursts +system.physmem.perBankWrBursts::15 69104 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 533761847000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 530994124500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2246694 # Read request sizes (log2) +system.physmem.readPktSize::6 2246209 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1100579 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1621644 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 445219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 135704 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 43528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1100304 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1619262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 446010 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 134777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 44683 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -129,216 +129,178 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 48877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 49060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 49089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 49071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 49076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 49104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 49085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 49081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 49079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 49128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 49123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 49158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 49172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 49261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 49504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 49899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 50373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 52060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 52016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 51492 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 52976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 52139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2078319 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.049035 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 79.954808 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 184.695982 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1660986 79.92% 79.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 227336 10.94% 90.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 68882 3.31% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 37662 1.81% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 25035 1.20% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 12093 0.58% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 8438 0.41% 98.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 8141 0.39% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 4391 0.21% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3442 0.17% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2829 0.14% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 1974 0.09% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1676 0.08% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1442 0.07% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1174 0.06% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1106 0.05% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 969 0.05% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 858 0.04% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 735 0.04% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 673 0.03% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 651 0.03% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3128 0.15% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 421 0.02% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 240 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 179 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 200 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 207 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 498 0.02% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 133 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 147 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 136 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 128 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 89 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 121 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 102 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 117 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 77 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 74 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 59 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 70 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 60 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 54 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 55 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 76 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 49 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 45 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 33 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 66 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 39 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 33 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 36 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 47 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 27 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 23 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 22 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 27 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 21 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 25 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 26 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 40 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 20 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 18 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 16 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 30 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 10 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 21 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 16 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 36 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 15 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 15 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 13 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 17 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 11 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 17 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 17 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 32 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 10 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 14 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 15 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 31 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 15 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 10 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 9 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 206 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 22 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 6 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 20 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 37 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 13 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 6 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 4 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 3 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 6 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 4 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 88 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2078319 # Bytes accessed per row activation -system.physmem.totQLat 32815970750 # Total ticks spent queuing -system.physmem.totMemAccLat 104054627000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 11230535000 # Total ticks spent in databus transfers -system.physmem.totBankLat 60008121250 # Total ticks spent accessing banks -system.physmem.avgQLat 14610.15 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 26716.50 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 48522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 58770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 63067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 64531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 65202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 65713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 66239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 70263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 71854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 72330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 80202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 72456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 68391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 66809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 65859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 22753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 6508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1604351 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 105.964762 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.430314 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 134.227606 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1240784 77.34% 77.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 261404 16.29% 93.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44793 2.79% 96.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 17157 1.07% 97.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 10128 0.63% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4810 0.30% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3056 0.19% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2546 0.16% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19673 1.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1604351 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 64945 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 34.562861 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 155.173168 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 64902 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 64945 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 64945 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.941828 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.872806 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.740981 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 45649 70.29% 70.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 15339 23.62% 93.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 3628 5.59% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 219 0.34% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 37 0.06% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 12 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 13 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 7 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 4 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 17 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::66-67 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-69 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-77 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-81 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::82-83 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-85 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-89 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::90-91 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 64945 # Writes before turning the bus around for reads +system.physmem.totQLat 28406230500 # Total ticks spent queuing +system.physmem.totMemAccLat 98095071750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 11223745000 # Total ticks spent in databus transfers +system.physmem.totBankLat 58465096250 # Total ticks spent accessing banks +system.physmem.avgQLat 12654.52 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 26045.27 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46326.66 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 269.32 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 131.96 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 269.39 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 131.96 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 43699.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 270.56 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 132.62 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 270.73 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 132.62 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.13 # Data bus utilization in percentage -system.physmem.busUtilRead 2.10 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.33 # Average write queue length when enqueuing -system.physmem.readRowHits 932061 # Number of row buffer hits during reads -system.physmem.writeRowHits 336288 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 30.56 # Row buffer hit rate for writes -system.physmem.avgGap 159461.70 # Average gap between requests -system.physmem.pageHitRate 37.90 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 5.96 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 401350114 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1420099 # Transaction distribution -system.membus.trans_dist::ReadResp 1420098 # Transaction distribution -system.membus.trans_dist::Writeback 1100579 # Transaction distribution -system.membus.trans_dist::ReadExReq 826595 # Transaction distribution -system.membus.trans_dist::ReadExResp 826595 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593966 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5593966 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214225408 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 214225408 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 214225408 # Total data (bytes) +system.physmem.busUtil 3.15 # Data bus utilization in percentage +system.physmem.busUtilRead 2.11 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.04 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.38 # Average write queue length when enqueuing +system.physmem.readRowHits 908698 # Number of row buffer hits during reads +system.physmem.writeRowHits 419053 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.09 # Row buffer hit rate for writes +system.physmem.avgGap 158670.87 # Average gap between requests +system.physmem.pageHitRate 39.69 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 6.04 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 403350610 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1419771 # Transaction distribution +system.membus.trans_dist::ReadResp 1419771 # Transaction distribution +system.membus.trans_dist::Writeback 1100304 # Transaction distribution +system.membus.trans_dist::ReadExReq 826438 # Transaction distribution +system.membus.trans_dist::ReadExResp 826438 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5592722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5592722 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214176832 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 214176832 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 214176832 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12926034750 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 12918660500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 21084340000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 21056537500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 303426723 # Number of BP lookups -system.cpu.branchPred.condPredicted 249665263 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15197446 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 174885075 # Number of BTB lookups -system.cpu.branchPred.BTBHits 161766496 # Number of BTB hits +system.cpu.branchPred.lookups 303422540 # Number of BP lookups +system.cpu.branchPred.condPredicted 249650550 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15218950 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 174790549 # Number of BTB lookups +system.cpu.branchPred.BTBHits 161666933 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.498743 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17552924 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 181 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.491805 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17552768 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 208 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -424,132 +386,133 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1067523845 # number of cpu cycles simulated +system.cpu.numCycles 1061988388 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 299169160 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2189552617 # Number of instructions fetch has processed -system.cpu.fetch.Branches 303426723 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 179319420 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 435766349 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 88088140 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 164108706 # Number of cycles fetch has spent blocked -system.cpu.fetch.PendingTrapStallCycles 249 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 289578845 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5989031 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 969003000 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.499478 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.206212 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 298972523 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2188716520 # Number of instructions fetch has processed +system.cpu.fetch.Branches 303422540 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 179219701 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 435616214 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 87982008 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 163592873 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 98 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 289402821 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5967581 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 968083151 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.501232 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.206704 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 533236766 55.03% 55.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25461427 2.63% 57.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39064672 4.03% 61.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48308848 4.99% 66.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43759414 4.52% 71.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46393042 4.79% 75.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38404129 3.96% 79.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18940871 1.95% 81.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175433831 18.10% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 532467013 55.00% 55.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25400980 2.62% 57.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39071584 4.04% 61.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48282365 4.99% 66.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43747142 4.52% 71.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46387901 4.79% 75.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38401401 3.97% 79.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18925667 1.95% 81.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175399098 18.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 969003000 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.284234 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.051057 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 331406137 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 141956827 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 405364012 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20318148 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 69957876 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46020737 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 686 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2369052643 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2441 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 69957876 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 354906744 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 70525275 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17150 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 400533325 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 73062630 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2306235389 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 151230 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5013278 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 60135849 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 19 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2282078057 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10649208068 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9763247621 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 332 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 968083151 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285712 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.060961 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 331186258 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 141449476 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 405224090 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20322579 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69900748 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46031045 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 725 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2368410495 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2465 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 69900748 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 354622933 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 70003752 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 18690 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 400463677 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 73073351 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2305921736 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 149865 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5017686 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 60142463 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2281817078 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10647699630 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9761875654 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 372 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 575758127 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 542 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 539 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 160926093 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624728249 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220785157 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 86065935 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 71218939 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2202289570 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 584 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2018746767 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4010968 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 474628449 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1127376318 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 414 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 969003000 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.083324 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906240 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 575497148 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 824 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 821 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 160915749 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624658588 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220783882 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 86055084 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 71680407 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2202175358 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 849 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2018579412 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4016690 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 474511400 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1127247409 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 679 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 968083151 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.085130 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.905910 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 286111139 29.53% 29.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 153618591 15.85% 45.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 160911412 16.61% 61.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120366979 12.42% 74.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 123454210 12.74% 87.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73801369 7.62% 94.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38320646 3.95% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9892378 1.02% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2526276 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 285219249 29.46% 29.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 153603913 15.87% 45.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 160908478 16.62% 61.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120369215 12.43% 74.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 123515877 12.76% 87.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73725483 7.62% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38349194 3.96% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9869125 1.02% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2522617 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 969003000 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 968083151 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 901909 3.77% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5511 0.02% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18267438 76.34% 80.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4754077 19.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 891948 3.74% 3.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5659 0.02% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18285123 76.74% 80.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4644794 19.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236913920 61.27% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 925199 0.05% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236892590 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 924644 0.05% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -571,90 +534,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 31 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 35 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 6 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 5 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587869811 29.12% 90.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193037777 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587766580 29.12% 90.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192995535 9.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2018746767 # Type of FU issued -system.cpu.iq.rate 1.891055 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23928935 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011853 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5034436167 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2677107941 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1957305969 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 270 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 526 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2042675566 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 136 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64599963 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2018579412 # Type of FU issued +system.cpu.iq.rate 1.900755 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23827524 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011804 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5033085915 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2676877502 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957286875 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 274 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 546 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 114 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2042406797 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 139 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64607409 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138801480 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 270727 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192405 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45938112 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138731819 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 269264 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192926 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45936837 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4771665 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4636852 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 69957876 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 33460674 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1602950 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2202290297 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7880065 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624728249 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220785157 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 522 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 477902 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 97314 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192405 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8143338 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9598007 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17741345 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1988017569 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 574014855 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30729198 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69900748 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 32985264 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1607893 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2202176322 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7875030 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624658588 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220783882 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 787 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 480489 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 97297 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192926 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8154150 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9614096 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17768246 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1987907812 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 573917969 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30671600 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 143 # number of nop insts executed -system.cpu.iew.exec_refs 764181270 # number of memory reference insts executed -system.cpu.iew.exec_branches 238318975 # Number of branches executed -system.cpu.iew.exec_stores 190166415 # Number of stores executed -system.cpu.iew.exec_rate 1.862270 # Inst execution rate -system.cpu.iew.wb_sent 1965726867 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1957306072 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1295394361 # num instructions producing a value -system.cpu.iew.wb_consumers 2059160488 # num instructions consuming a value +system.cpu.iew.exec_nop 115 # number of nop insts executed +system.cpu.iew.exec_refs 764035004 # number of memory reference insts executed +system.cpu.iew.exec_branches 238344765 # Number of branches executed +system.cpu.iew.exec_stores 190117035 # Number of stores executed +system.cpu.iew.exec_rate 1.871873 # Inst execution rate +system.cpu.iew.wb_sent 1965721385 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957286989 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1295353169 # num instructions producing a value +system.cpu.iew.wb_consumers 2059124619 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.833501 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.629089 # average fanout of values written-back +system.cpu.iew.wb_rate 1.843040 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.629080 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 479315418 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 479201419 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15196786 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 899045124 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.916560 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.718243 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15218256 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 898182403 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.918401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.718632 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 410462230 45.66% 45.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193303811 21.50% 67.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72810970 8.10% 75.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35275316 3.92% 79.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18883906 2.10% 81.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30780783 3.42% 84.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19963318 2.22% 86.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11415613 1.27% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106149177 11.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 409520932 45.59% 45.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193341126 21.53% 67.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72856392 8.11% 75.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35266381 3.93% 79.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18923261 2.11% 81.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30757515 3.42% 84.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19970325 2.22% 86.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11453537 1.28% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106092934 11.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 899045124 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 898182403 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -665,98 +628,99 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106149177 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106092934 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2995284619 # The number of ROB reads -system.cpu.rob.rob_writes 4474886700 # The number of ROB writes -system.cpu.timesIdled 1153694 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 98520845 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2994364142 # The number of ROB reads +system.cpu.rob.rob_writes 4474601624 # The number of ROB writes +system.cpu.timesIdled 1160522 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 93905237 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.691149 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.691149 # CPI: Total CPI of All Threads -system.cpu.ipc 1.446865 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.446865 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9956057659 # number of integer regfile reads -system.cpu.int_regfile_writes 1937206435 # number of integer regfile writes -system.cpu.fp_regfile_reads 98 # number of floating regfile reads -system.cpu.fp_regfile_writes 94 # number of floating regfile writes -system.cpu.misc_regfile_reads 737611057 # number of misc regfile reads +system.cpu.cpi 0.687566 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.687566 # CPI: Total CPI of All Threads +system.cpu.ipc 1.454407 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.454407 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9955508978 # number of integer regfile reads +system.cpu.int_regfile_writes 1937309574 # number of integer regfile writes +system.cpu.fp_regfile_reads 108 # number of floating regfile reads +system.cpu.fp_regfile_writes 108 # number of floating regfile writes +system.cpu.misc_regfile_reads 737568033 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1604912326 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7709455 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7709454 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3782070 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1893493 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1893493 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1550 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22986415 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22987965 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856591488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 856641088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 856641088 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10474747083 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 1613255878 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7708873 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7708872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3782409 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1893555 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1893555 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1549 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22985720 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22987269 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856579904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 856629440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 856629440 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 10474986844 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1295998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1289999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14769977492 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14746367742 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 19 # number of replacements -system.cpu.icache.tags.tagsinuse 628.273269 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 289577640 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 775 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 373648.567742 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 17 # number of replacements +system.cpu.icache.tags.tagsinuse 631.201883 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 289401615 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 772 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 374872.558290 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 628.273269 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.306774 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.306774 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 756 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 631.201883 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.308204 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.308204 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 755 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 727 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.369141 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 579158465 # Number of tag accesses -system.cpu.icache.tags.data_accesses 579158465 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 289577640 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 289577640 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 289577640 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 289577640 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 289577640 # number of overall hits -system.cpu.icache.overall_hits::total 289577640 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1205 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1205 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1205 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1205 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1205 # number of overall misses -system.cpu.icache.overall_misses::total 1205 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 81284498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 81284498 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 81284498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 81284498 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 81284498 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 81284498 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 289578845 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 289578845 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 289578845 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 289578845 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 289578845 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 289578845 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 729 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.368652 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 578806417 # Number of tag accesses +system.cpu.icache.tags.data_accesses 578806417 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 289401622 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 289401622 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 289401622 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 289401622 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 289401622 # number of overall hits +system.cpu.icache.overall_hits::total 289401622 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1199 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1199 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1199 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1199 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1199 # number of overall misses +system.cpu.icache.overall_misses::total 1199 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 84823499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 84823499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 84823499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 84823499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 84823499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 84823499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 289402821 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 289402821 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 289402821 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 289402821 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 289402821 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 289402821 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67456.014938 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67456.014938 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67456.014938 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67456.014938 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67456.014938 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67456.014938 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70745.203503 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70745.203503 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70745.203503 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70745.203503 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70745.203503 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70745.203503 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 202 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -765,129 +729,133 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 50.500000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 430 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 430 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 430 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 430 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 430 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 430 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 424 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 424 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 424 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 424 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 775 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 775 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 775 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55854002 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 55854002 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55854002 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 55854002 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55854002 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 55854002 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56494501 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 56494501 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56494501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 56494501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56494501 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 56494501 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72069.680000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72069.680000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72069.680000 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72069.680000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72069.680000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72069.680000 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72896.130323 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72896.130323 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72896.130323 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72896.130323 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72896.130323 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72896.130323 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 2214011 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31532.870200 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9247003 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2243785 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.121163 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 21623958250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14303.376165 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.256077 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 17209.237958 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.436504 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000618 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.525184 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.962307 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 2213521 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31530.649727 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9247246 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2243295 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.122171 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 21629133000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14295.824986 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.209231 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 17214.615510 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.436274 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000617 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.525348 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.962239 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29774 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1894 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 23751 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3958 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1889 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 23754 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3955 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908630 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 111217422 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 111217422 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184174 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436448 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436448 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958656 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233863 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.233921 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958656 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233863 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.233921 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61990.566038 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73512.487941 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 73506.466360 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76805.320847 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76805.320847 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61990.566038 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74724.406103 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74720.199679 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61990.566038 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74724.406103 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74720.199679 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9598076 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.041397 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 656012597 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9602172 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 68.319188 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 3547188250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.041397 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998057 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998057 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9597556 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.017894 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 656035033 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9601652 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 68.325225 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 3543401250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.017894 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998051 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998051 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 635 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2403 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1057 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 619 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2366 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1110 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1355899932 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1355899932 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 489056209 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 489056209 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 166956265 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 166956265 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 1355956994 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1355956994 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 489079777 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 489079777 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 166955126 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166955126 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 64 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 64 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 656012474 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 656012474 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 656012474 # number of overall hits -system.cpu.dcache.overall_hits::total 656012474 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11506498 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11506498 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5629782 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5629782 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 656034903 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 656034903 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 656034903 # number of overall hits +system.cpu.dcache.overall_hits::total 656034903 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11511719 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11511719 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5630921 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5630921 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17136280 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17136280 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17136280 # number of overall misses -system.cpu.dcache.overall_misses::total 17136280 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 363307841237 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 363307841237 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 307618244019 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 307618244019 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 233500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 233500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 670926085256 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 670926085256 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 670926085256 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 670926085256 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500562707 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500562707 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17142640 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17142640 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17142640 # number of overall misses +system.cpu.dcache.overall_misses::total 17142640 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 356637028987 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 356637028987 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 299385068793 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 299385068793 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 231500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 231500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 656022097780 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 656022097780 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 656022097780 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 656022097780 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500591496 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500591496 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 65 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 65 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673148754 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673148754 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673148754 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673148754 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022987 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022987 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032620 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032620 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046154 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046154 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025457 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025457 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025457 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025457 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31574.145430 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31574.145430 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54641.235490 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54641.235490 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39152.376435 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39152.376435 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39152.376435 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39152.376435 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24574937 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3988182 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1212192 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65130 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.273139 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61.234178 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 673177543 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673177543 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673177543 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673177543 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022996 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022996 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032627 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032627 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025465 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025465 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025465 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025465 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30980.345245 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30980.345245 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53168.046363 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53168.046363 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38268.440437 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38268.440437 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38268.440437 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38268.440437 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23433940 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3966170 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1210564 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65132 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.357870 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 60.894338 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3782070 # number of writebacks -system.cpu.dcache.writebacks::total 3782070 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3797817 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3797817 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3736290 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3736290 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3782409 # number of writebacks +system.cpu.dcache.writebacks::total 3782409 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3803620 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3803620 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3737364 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3737364 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7534107 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7534107 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7534107 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7534107 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708681 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7708681 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893492 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893492 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9602173 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9602173 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9602173 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9602173 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198180916008 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 198180916008 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89373429339 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 89373429339 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287554345347 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 287554345347 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287554345347 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 287554345347 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015400 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015400 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25708.797135 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25708.797135 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47200.320540 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47200.320540 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29946.799058 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29946.799058 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29946.799058 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29946.799058 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 7540984 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7540984 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7540984 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7540984 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708099 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7708099 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893557 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893557 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9601656 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9601656 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9601656 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9601656 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 194575797258 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 194575797258 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86895396246 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 86895396246 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 281471193504 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 281471193504 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 281471193504 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 281471193504 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015398 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015398 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010972 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010972 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014263 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25243.032978 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25243.032978 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45890.034599 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45890.034599 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29314.859177 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29314.859177 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29314.859177 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29314.859177 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 3f6e9d455..17c346b69 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041680 # Number of seconds simulated -sim_ticks 41680207000 # Number of ticks simulated -final_tick 41680207000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041684 # Number of seconds simulated +sim_ticks 41683573000 # Number of ticks simulated +final_tick 41683573000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131207 # Simulator instruction rate (inst/s) -host_op_rate 131207 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59505524 # Simulator tick rate (ticks/s) -host_mem_usage 234284 # Number of bytes of host memory used -host_seconds 700.44 # Real time elapsed on the host +host_inst_rate 119929 # Simulator instruction rate (inst/s) +host_op_rate 119929 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54395175 # Simulator tick rate (ticks/s) +host_mem_usage 269084 # Number of bytes of host memory used +host_seconds 766.31 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4290190 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3292114 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7582304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4290190 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4290190 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4290190 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3292114 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7582304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4289843 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3291848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7581692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4289843 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4289843 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4289843 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3291848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7581692 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 4938 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 4938 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 41680133000 # Total gap between requests +system.physmem.totGap 41683192000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1090 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -154,65 +154,60 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 743 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 421.641992 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 209.527903 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 761.351186 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 254 34.19% 34.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 96 12.92% 47.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 62 8.34% 55.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 50 6.73% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 29 3.90% 66.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 32 4.31% 70.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 22 2.96% 73.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 25 3.36% 76.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 15 2.02% 78.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 12 1.62% 80.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 14 1.88% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 16 2.15% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 32 4.31% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 17 2.29% 90.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 0.67% 91.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 5 0.67% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 8 1.08% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 5 0.67% 94.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 6 0.81% 94.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 6 0.81% 95.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.27% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 1 0.13% 96.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 1 0.13% 96.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 3 0.40% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 2 0.27% 96.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.13% 97.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.27% 97.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 2 0.27% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.13% 97.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 1 0.13% 97.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 1 0.13% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 1 0.13% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.13% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.13% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.13% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.13% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.13% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.13% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 1 0.13% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.13% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.13% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 1 0.13% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.13% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 1 0.13% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 1 0.13% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 743 # Bytes accessed per row activation -system.physmem.totQLat 34070750 # Total ticks spent queuing -system.physmem.totMemAccLat 126424500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 284 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 541.521127 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 335.427822 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.351632 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 58 20.42% 20.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 54 19.01% 39.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 24 8.45% 47.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12 4.23% 52.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 10 3.52% 55.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9 3.17% 58.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5 1.76% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5 1.76% 62.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 107 37.68% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 284 # Bytes accessed per row activation +system.physmem.totQLat 37971250 # Total ticks spent queuing +system.physmem.totMemAccLat 131493750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 24690000 # Total ticks spent in databus transfers -system.physmem.totBankLat 67663750 # Total ticks spent accessing banks -system.physmem.avgQLat 6899.71 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13702.66 # Average bank access latency per DRAM burst +system.physmem.totBankLat 68832500 # Total ticks spent accessing banks +system.physmem.avgQLat 7689.60 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13939.35 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25602.37 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26628.95 # Average memory access latency per DRAM burst system.physmem.avgRdBW 7.58 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 7.58 # Average system read bandwidth in MiByte/s @@ -221,16 +216,16 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4195 # Number of row buffer hits during reads +system.physmem.readRowHits 4086 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.95 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.75 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8440691.17 # Average gap between requests -system.physmem.pageHitRate 84.95 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.90 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 7582304 # Throughput (bytes/s) +system.physmem.avgGap 8441310.65 # Average gap between requests +system.physmem.pageHitRate 82.75 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.04 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 7581692 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3216 # Transaction distribution system.membus.trans_dist::ReadResp 3216 # Transaction distribution system.membus.trans_dist::ReadExReq 1722 # Transaction distribution @@ -241,9 +236,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 316032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 5775000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 5776500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 45973500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 45941000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 13412627 # Number of BP lookups @@ -259,18 +254,18 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996265 # DTB read hits +system.cpu.dtb.read_hits 19996264 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996275 # DTB read accesses -system.cpu.dtb.write_hits 6501862 # DTB write hits +system.cpu.dtb.read_accesses 19996274 # DTB read accesses +system.cpu.dtb.write_hits 6501866 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501885 # DTB write accesses -system.cpu.dtb.data_hits 26498127 # DTB hits +system.cpu.dtb.write_accesses 6501889 # DTB write accesses +system.cpu.dtb.data_hits 26498130 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498160 # DTB accesses +system.cpu.dtb.data_accesses 26498163 # DTB accesses system.cpu.itb.fetch_hits 9956950 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv @@ -288,18 +283,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83360415 # number of cpu cycles simulated +system.cpu.numCycles 83367147 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 5905662 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73570552 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 73570553 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136146024 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 136146025 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38521866 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 38521865 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 26722393 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken). @@ -310,12 +305,12 @@ system.cpu.execution_unit.executions 57404027 # Nu system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 82971123 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 82970332 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10519 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7752655 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75607760 # Number of cycles cpu stages are processed. -system.cpu.activity 90.699836 # Percentage of cycles cpu is active +system.cpu.timesIdled 10410 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7759392 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75607755 # Number of cycles cpu stages are processed. +system.cpu.activity 90.692506 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -327,36 +322,36 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.907047 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.907121 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.907047 # CPI: Total CPI of All Threads -system.cpu.ipc 1.102478 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.907121 # CPI: Total CPI of All Threads +system.cpu.ipc 1.102389 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.102478 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27680069 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 55680346 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.794708 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34108732 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49251683 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 59.082819 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33509067 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49851348 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.802183 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65333914 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.624774 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29500658 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53859757 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.610711 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.102389 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27686803 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 55680344 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.789312 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34115467 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49251680 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 59.078044 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33515800 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49851347 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.797353 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65340657 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18026490 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.623014 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29507392 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53859755 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.605491 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 7635 # number of replacements -system.cpu.icache.tags.tagsinuse 1492.182806 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1492.188372 # Cycle average of tags in use system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1492.182806 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.728605 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.728605 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1492.188372 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.728608 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.728608 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1885 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id @@ -378,12 +373,12 @@ system.cpu.icache.demand_misses::cpu.inst 11399 # n system.cpu.icache.demand_misses::total 11399 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11399 # number of overall misses system.cpu.icache.overall_misses::total 11399 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 325866750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 325866750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 325866750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 325866750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 325866750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 325866750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 329283500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 329283500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 329283500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 329283500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 329283500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 329283500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 9956950 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 9956950 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 9956950 # number of demand (read+write) accesses @@ -396,12 +391,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28587.310290 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28587.310290 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28587.310290 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28587.310290 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28587.310290 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28587.310290 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28887.051496 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28887.051496 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28887.051496 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28887.051496 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28887.051496 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28887.051496 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -422,26 +417,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 9520 system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 266339500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 266339500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 266339500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 266339500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 266339500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 266339500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268822750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 268822750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268822750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 268822750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268822750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 268822750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27976.838235 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27976.838235 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27976.838235 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27976.838235 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27976.838235 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27976.838235 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28237.683824 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28237.683824 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28237.683824 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28237.683824 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28237.683824 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28237.683824 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 18195687 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 18194218 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution @@ -457,19 +452,19 @@ system.cpu.toL2Bus.data_through_bus 758400 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 14812000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 14800250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3559500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3515750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2189.577948 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2189.597840 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 6793 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.069775 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.842967 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.748644 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 350.986337 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.844631 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.766792 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 350.986416 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055565 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.010711 # Average percentage of cache occupancy @@ -507,17 +502,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 189282000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32395250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 221677250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 122425750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 122425750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 189282000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 154821000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 344103000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 189282000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 154821000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 344103000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191765250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32319750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 224085000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 125611500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 125611500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 191765250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 157931250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 349696500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 191765250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 157931250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 349696500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses) @@ -542,17 +537,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67745.884037 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76765.995261 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68929.493159 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71095.092915 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71095.092915 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67745.884037 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72211.287313 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69684.690158 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67745.884037 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72211.287313 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69684.690158 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68634.663565 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76587.085308 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69678.171642 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72945.121951 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72945.121951 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68634.663565 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73661.963619 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70817.436209 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68634.663565 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73661.963619 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70817.436209 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -572,17 +567,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154136500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27132250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 181268750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101289750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101289750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 154136500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128422000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 282558500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 154136500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128422000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 282558500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 156642750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27057250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 183700000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 104540000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 104540000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 156642750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131597250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 288240000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 156642750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131597250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 288240000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses @@ -594,31 +589,31 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55166.964925 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64294.431280 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56364.661070 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58820.993031 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58820.993031 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59898.320896 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57221.243418 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59898.320896 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57221.243418 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56063.976378 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64116.706161 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57120.646766 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60708.478513 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60708.478513 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56063.976378 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61379.314366 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58371.810450 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56063.976378 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61379.314366 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58371.810450 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1441.367780 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26488450 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1441.382253 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26488456 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11915.632029 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11915.634728 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1441.367780 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.351896 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.351896 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.382253 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.351900 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.351900 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 403 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id @@ -626,28 +621,28 @@ system.cpu.dcache.tags.tag_accesses 52996825 # Nu system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 19995621 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995621 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492829 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492829 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26488450 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26488450 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26488450 # number of overall hits -system.cpu.dcache.overall_hits::total 26488450 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492835 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492835 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26488456 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26488456 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26488456 # number of overall hits +system.cpu.dcache.overall_hits::total 26488456 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 577 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 577 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8274 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8274 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 8851 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8851 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8851 # number of overall misses -system.cpu.dcache.overall_misses::total 8851 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 41023250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 41023250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 492650500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 492650500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 533673750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 533673750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 533673750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 533673750 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 8268 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8268 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 8845 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8845 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8845 # number of overall misses +system.cpu.dcache.overall_misses::total 8845 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40979500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40979500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 507652000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 507652000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 548631500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 548631500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 548631500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 548631500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -658,25 +653,25 @@ system.cpu.dcache.overall_accesses::cpu.data 26497301 system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001273 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001273 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001272 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001272 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71097.487002 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71097.487002 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59541.999033 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59541.999033 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60295.305615 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60295.305615 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60295.305615 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60295.305615 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23884 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71021.663778 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71021.663778 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61399.612966 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61399.612966 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62027.303561 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62027.303561 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62027.303561 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62027.303561 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 25755 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 841 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 844 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.399524 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.515403 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -684,12 +679,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 102 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6526 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6526 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6628 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6628 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6628 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6628 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6520 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6520 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6622 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6622 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6622 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6622 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -698,14 +693,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33418750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33418750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124443250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 124443250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 157862000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 157862000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157862000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 157862000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33343250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33343250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127629000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 127629000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160972250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 160972250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 160972250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 160972250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -714,14 +709,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70355.263158 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70355.263158 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71191.790618 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71191.790618 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71013.045434 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71013.045434 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71013.045434 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71013.045434 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70196.315789 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70196.315789 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73014.302059 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73014.302059 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72412.168241 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72412.168241 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72412.168241 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72412.168241 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index b0acaf58e..c3a9e9ab9 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023462 # Number of seconds simulated -sim_ticks 23461709500 # Number of ticks simulated -final_tick 23461709500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023455 # Number of seconds simulated +sim_ticks 23455364500 # Number of ticks simulated +final_tick 23455364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 186682 # Simulator instruction rate (inst/s) -host_op_rate 186682 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52030153 # Simulator tick rate (ticks/s) -host_mem_usage 235304 # Number of bytes of host memory used -host_seconds 450.93 # Real time elapsed on the host +host_inst_rate 164985 # Simulator instruction rate (inst/s) +host_op_rate 164985 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45970553 # Simulator tick rate (ticks/s) +host_mem_usage 272156 # Number of bytes of host memory used +host_seconds 510.23 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 195968 # Nu system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2166 # Number of read requests responded to by this memory system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8352674 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5908521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14261194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8352674 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8352674 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8352674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5908521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14261194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 8354933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5910119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14265052 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8354933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8354933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8354933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5910119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14265052 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5228 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5228 # Number of DRAM read bursts, including those serviced by the write queue @@ -41,20 +41,20 @@ system.physmem.bytesWrittenSys 0 # To system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 466 # Per bank write bursts +system.physmem.perBankRdBursts::0 469 # Per bank write bursts system.physmem.perBankRdBursts::1 290 # Per bank write bursts -system.physmem.perBankRdBursts::2 300 # Per bank write bursts -system.physmem.perBankRdBursts::3 524 # Per bank write bursts +system.physmem.perBankRdBursts::2 301 # Per bank write bursts +system.physmem.perBankRdBursts::3 519 # Per bank write bursts system.physmem.perBankRdBursts::4 220 # Per bank write bursts -system.physmem.perBankRdBursts::5 226 # Per bank write bursts -system.physmem.perBankRdBursts::6 219 # Per bank write bursts +system.physmem.perBankRdBursts::5 227 # Per bank write bursts +system.physmem.perBankRdBursts::6 220 # Per bank write bursts system.physmem.perBankRdBursts::7 288 # Per bank write bursts -system.physmem.perBankRdBursts::8 240 # Per bank write bursts -system.physmem.perBankRdBursts::9 279 # Per bank write bursts +system.physmem.perBankRdBursts::8 236 # Per bank write bursts +system.physmem.perBankRdBursts::9 278 # Per bank write bursts system.physmem.perBankRdBursts::10 248 # Per bank write bursts -system.physmem.perBankRdBursts::11 254 # Per bank write bursts -system.physmem.perBankRdBursts::12 400 # Per bank write bursts -system.physmem.perBankRdBursts::13 336 # Per bank write bursts +system.physmem.perBankRdBursts::11 255 # Per bank write bursts +system.physmem.perBankRdBursts::12 401 # Per bank write bursts +system.physmem.perBankRdBursts::13 338 # Per bank write bursts system.physmem.perBankRdBursts::14 491 # Per bank write bursts system.physmem.perBankRdBursts::15 447 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 23461582500 # Total gap between requests +system.physmem.totGap 23455237500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 84 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -154,84 +154,78 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 750 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 442.026667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 206.409345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 807.667918 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 266 35.47% 35.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 111 14.80% 50.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 59 7.87% 58.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 40 5.33% 63.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 26 3.47% 66.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 30 4.00% 70.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 24 3.20% 74.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 16 2.13% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 9 1.20% 77.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 13 1.73% 79.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 15 2.00% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 13 1.73% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 37 4.93% 87.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 11 1.47% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 6 0.80% 90.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 3 0.40% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 7 0.93% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 7 0.93% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 3 0.40% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.40% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 8 1.07% 94.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 1 0.13% 94.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3 0.40% 94.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 2 0.27% 95.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 4 0.53% 95.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 2 0.27% 95.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.13% 96.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.13% 96.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 3 0.40% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.40% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 1 0.13% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 3 0.40% 97.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.13% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.13% 97.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 3 0.40% 98.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.13% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.13% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 2 0.27% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 1 0.13% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.13% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.13% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 1 0.13% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.13% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 1 0.13% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.13% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.27% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 750 # Bytes accessed per row activation -system.physmem.totQLat 37518750 # Total ticks spent queuing -system.physmem.totMemAccLat 134402500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 339 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 526.348083 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 311.933424 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 425.197716 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 81 23.89% 23.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 64 18.88% 42.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 21 6.19% 48.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 17 5.01% 53.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 9 2.65% 56.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8 2.36% 59.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 2.06% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 0.88% 61.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 129 38.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 339 # Bytes accessed per row activation +system.physmem.totQLat 42838250 # Total ticks spent queuing +system.physmem.totMemAccLat 141220750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26140000 # Total ticks spent in databus transfers -system.physmem.totBankLat 70743750 # Total ticks spent accessing banks -system.physmem.avgQLat 7176.50 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13531.70 # Average bank access latency per DRAM burst +system.physmem.totBankLat 72242500 # Total ticks spent accessing banks +system.physmem.avgQLat 8194.00 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13818.38 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25708.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27012.39 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.26 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.27 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.11 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4478 # Number of row buffer hits during reads +system.physmem.readRowHits 4346 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.65 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.13 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4487678.37 # Average gap between requests -system.physmem.pageHitRate 85.65 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.19 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 14261194 # Throughput (bytes/s) +system.physmem.avgGap 4486464.71 # Average gap between requests +system.physmem.pageHitRate 83.13 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.10 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 14265052 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3523 # Transaction distribution system.membus.trans_dist::ReadResp 3523 # Transaction distribution system.membus.trans_dist::ReadExReq 1705 # Transaction distribution @@ -242,40 +236,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 334592 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 334592 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6831000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6760500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 49012250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 48963750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14847721 # Number of BP lookups -system.cpu.branchPred.condPredicted 10774921 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 922205 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8301784 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6957680 # Number of BTB hits +system.cpu.branchPred.lookups 14848335 # Number of BP lookups +system.cpu.branchPred.condPredicted 10770516 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 922016 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8296689 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6955595 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.809456 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1467978 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3097 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 83.835793 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1468520 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3112 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23117785 # DTB read hits -system.cpu.dtb.read_misses 192281 # DTB read misses +system.cpu.dtb.read_hits 23116922 # DTB read hits +system.cpu.dtb.read_misses 193562 # DTB read misses system.cpu.dtb.read_acv 4 # DTB read access violations -system.cpu.dtb.read_accesses 23310066 # DTB read accesses -system.cpu.dtb.write_hits 7068175 # DTB write hits -system.cpu.dtb.write_misses 1137 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 7069312 # DTB write accesses -system.cpu.dtb.data_hits 30185960 # DTB hits -system.cpu.dtb.data_misses 193418 # DTB misses -system.cpu.dtb.data_acv 8 # DTB access violations -system.cpu.dtb.data_accesses 30379378 # DTB accesses -system.cpu.itb.fetch_hits 14734161 # ITB hits -system.cpu.itb.fetch_misses 103 # ITB misses +system.cpu.dtb.read_accesses 23310484 # DTB read accesses +system.cpu.dtb.write_hits 7068693 # DTB write hits +system.cpu.dtb.write_misses 1118 # DTB write misses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_accesses 7069811 # DTB write accesses +system.cpu.dtb.data_hits 30185615 # DTB hits +system.cpu.dtb.data_misses 194680 # DTB misses +system.cpu.dtb.data_acv 6 # DTB access violations +system.cpu.dtb.data_accesses 30380295 # DTB accesses +system.cpu.itb.fetch_hits 14732180 # ITB hits +system.cpu.itb.fetch_misses 100 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14734264 # ITB accesses +system.cpu.itb.fetch_accesses 14732280 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -289,139 +283,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 46923420 # number of cpu cycles simulated +system.cpu.numCycles 46910730 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15463381 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 126961894 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14847721 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8425658 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22130056 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4473003 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5559398 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2205 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14734161 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 324644 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46671603 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.720324 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.376096 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15458006 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 126949517 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14848335 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8424115 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22129467 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4471319 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5547804 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2176 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14732180 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 325492 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46652781 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.721156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.376288 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24541547 52.58% 52.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2361252 5.06% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1192515 2.56% 60.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1742111 3.73% 63.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2755701 5.90% 69.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1149393 2.46% 72.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1220691 2.62% 74.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 771780 1.65% 76.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10936613 23.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24523314 52.57% 52.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2362460 5.06% 57.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1191709 2.55% 60.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1744531 3.74% 63.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2756035 5.91% 69.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1149513 2.46% 72.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1216156 2.61% 74.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 771099 1.65% 76.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10937964 23.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46671603 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316425 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.705725 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17289395 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4257221 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20524693 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1095542 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3504752 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2511898 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12167 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 123979126 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 31595 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3504752 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18431780 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 963421 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7928 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20455398 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3308324 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121154570 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 87 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 400162 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2430153 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 88974225 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157440425 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 150394655 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7045769 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46652781 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316523 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.706194 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17279755 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4249359 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20525557 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1094653 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3503457 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2516236 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12079 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 123971467 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32460 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3503457 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18421615 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 960025 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8092 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20456033 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3303559 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 121144333 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 76 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 398869 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2427038 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 88958437 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 157404324 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 150359413 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7044910 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20546864 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 749 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 744 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8783261 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25363133 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8241349 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2569635 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 893782 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105438334 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 961 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96565072 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 178504 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20784578 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15622466 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 572 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46671603 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.069033 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.876517 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 20531076 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 753 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 746 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8762869 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25364686 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8245053 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2579677 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 916866 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 105436349 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1901 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96572685 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 177506 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20788885 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15603704 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1512 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46652781 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.070031 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.877189 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12133902 26.00% 26.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9340972 20.01% 46.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8404137 18.01% 64.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6285068 13.47% 77.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4921137 10.54% 88.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2853571 6.11% 94.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1727806 3.70% 97.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 798697 1.71% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 206313 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12130850 26.00% 26.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9330795 20.00% 46.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8389374 17.98% 63.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6281972 13.47% 77.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4924466 10.56% 88.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2864469 6.14% 94.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1724344 3.70% 97.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 801135 1.72% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 205376 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46671603 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46652781 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 187905 11.99% 11.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 187827 11.99% 11.99% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 11.99% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 11.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 198 0.01% 12.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7114 0.45% 12.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5683 0.36% 12.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 843073 53.81% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 444038 28.34% 94.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78699 5.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 195 0.01% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7087 0.45% 12.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5615 0.36% 12.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 842803 53.78% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 445934 28.46% 95.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77665 4.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58732393 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 479878 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58739096 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 479860 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2798409 2.90% 64.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115272 0.12% 64.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2387143 2.47% 66.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 310920 0.32% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 760028 0.79% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2798014 2.90% 64.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115391 0.12% 64.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2386555 2.47% 66.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 310970 0.32% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 759904 0.79% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued @@ -443,84 +437,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23829441 24.68% 92.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7151262 7.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23830824 24.68% 92.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7151745 7.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96565072 # Type of FU issued -system.cpu.iq.rate 2.057929 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1566710 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016224 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226434513 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117518300 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87069210 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15112448 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8740080 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7062492 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90145382 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7986393 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1518186 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96572685 # Type of FU issued +system.cpu.iq.rate 2.058648 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1567126 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016227 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 226432918 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117523015 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87074868 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15109865 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8738386 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7061397 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90154911 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7984893 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1517468 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5366935 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18425 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34629 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1740246 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5368488 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18513 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34393 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1743950 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10551 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2023 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10556 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2089 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3504752 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 133474 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18356 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115674265 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 366324 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25363133 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8241349 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 961 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2994 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 3503457 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 134155 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17977 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 115673905 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 371989 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25364686 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8245053 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1901 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2671 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 35 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34629 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 535207 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 494157 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1029364 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95337689 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23310553 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1227383 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 34393 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 533358 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 495038 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1028396 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95341973 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23310954 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1230712 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10234970 # number of nop insts executed -system.cpu.iew.exec_refs 30380075 # number of memory reference insts executed -system.cpu.iew.exec_branches 12022158 # Number of branches executed -system.cpu.iew.exec_stores 7069522 # Number of stores executed -system.cpu.iew.exec_rate 2.031772 # Inst execution rate -system.cpu.iew.wb_sent 94652012 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94131702 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64474346 # num instructions producing a value -system.cpu.iew.wb_consumers 89850691 # num instructions consuming a value +system.cpu.iew.exec_nop 10235655 # number of nop insts executed +system.cpu.iew.exec_refs 30380968 # number of memory reference insts executed +system.cpu.iew.exec_branches 12023807 # Number of branches executed +system.cpu.iew.exec_stores 7070014 # Number of stores executed +system.cpu.iew.exec_rate 2.032413 # Inst execution rate +system.cpu.iew.wb_sent 94656410 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94136265 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64475750 # num instructions producing a value +system.cpu.iew.wb_consumers 89852391 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.006071 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717572 # average fanout of values written-back +system.cpu.iew.wb_rate 2.006711 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717574 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23772316 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23771863 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 910471 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43166851 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.129019 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.746086 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 910264 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43149324 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.129884 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.746526 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16723468 38.74% 38.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9908468 22.95% 61.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4486822 10.39% 72.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2263317 5.24% 77.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1605459 3.72% 81.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1122723 2.60% 83.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 719573 1.67% 85.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 818065 1.90% 87.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5518956 12.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16704227 38.71% 38.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9920088 22.99% 61.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4481212 10.39% 72.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2253745 5.22% 77.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1606057 3.72% 81.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1123881 2.60% 83.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 722151 1.67% 85.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 820935 1.90% 87.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5517028 12.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43166851 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43149324 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -531,173 +525,173 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5518956 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5517028 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153322226 # The number of ROB reads -system.cpu.rob.rob_writes 234879469 # The number of ROB writes -system.cpu.timesIdled 5401 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 251817 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 153306174 # The number of ROB reads +system.cpu.rob.rob_writes 234877097 # The number of ROB writes +system.cpu.timesIdled 5272 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 257949 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.557420 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.557420 # CPI: Total CPI of All Threads -system.cpu.ipc 1.793981 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.793981 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129048096 # number of integer regfile reads -system.cpu.int_regfile_writes 70519803 # number of integer regfile writes -system.cpu.fp_regfile_reads 6188545 # number of floating regfile reads -system.cpu.fp_regfile_writes 6044303 # number of floating regfile writes -system.cpu.misc_regfile_reads 714547 # number of misc regfile reads +system.cpu.cpi 0.557269 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.557269 # CPI: Total CPI of All Threads +system.cpu.ipc 1.794466 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.794466 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129050731 # number of integer regfile reads +system.cpu.int_regfile_writes 70522819 # number of integer regfile writes +system.cpu.fp_regfile_reads 6187407 # number of floating regfile reads +system.cpu.fp_regfile_writes 6043154 # number of floating regfile writes +system.cpu.misc_regfile_reads 714454 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 37824354 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 12026 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 12026 # Transaction distribution +system.cpu.toL2Bus.throughput 37351626 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 11849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 11849 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1731 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1731 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23020 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22666 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4603 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27623 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 736640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27269 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 725312 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 887424 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 876096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 876096 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 7042000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 6953500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17847250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17562000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3547000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3539750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 9576 # number of replacements -system.cpu.icache.tags.tagsinuse 1596.482984 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14719872 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11510 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1278.876803 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9398 # number of replacements +system.cpu.icache.tags.tagsinuse 1599.250917 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14718111 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11333 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1298.695050 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1596.482984 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.779533 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.779533 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1934 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 766 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1599.250917 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.780884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.780884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1935 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 761 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 924 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.944336 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 29479830 # Number of tag accesses -system.cpu.icache.tags.data_accesses 29479830 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 14719872 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14719872 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14719872 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14719872 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14719872 # number of overall hits -system.cpu.icache.overall_hits::total 14719872 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14288 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14288 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14288 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14288 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14288 # number of overall misses -system.cpu.icache.overall_misses::total 14288 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 413271500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 413271500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 413271500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 413271500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 413271500 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29427.743816 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29427.743816 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29427.743816 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 165 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 68.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 41.250000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # 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miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.297325 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984980 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.984980 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.266030 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.270184 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.963952 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.380025 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.266030 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.384978 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.270184 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963952 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.380025 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67821.113651 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74969.088937 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68756.457565 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72909.237537 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72909.237537 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67821.113651 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73347.645429 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70110.797628 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67821.113651 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73347.645429 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70110.797628 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.384978 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68991.998694 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79441.431670 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70359.352824 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73669.648094 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73669.648094 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68991.998694 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74898.084026 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71438.934583 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68991.998694 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74898.084026 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71438.934583 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -774,135 +768,136 @@ system.cpu.l2cache.demand_mshr_misses::total 5228 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2166 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5228 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 168834750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 28858250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 197693000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 103390750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 103390750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168834750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132249000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 301083750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168834750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132249000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 301083750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266030 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 172480500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30915000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 203395500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 104707750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 104707750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 172480500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 135622750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 308103250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 172480500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 135622750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 308103250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.270184 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.893411 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.292949 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.297325 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984980 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984980 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.266030 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.270184 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.380025 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266030 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.384978 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.270184 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.380025 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55138.716525 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62599.240781 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56114.958842 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60639.736070 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60639.736070 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55138.716525 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61056.786704 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57590.617827 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55138.716525 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61056.786704 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57590.617827 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.384978 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56329.359895 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67060.737527 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57733.607721 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61412.170088 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61412.170088 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56329.359895 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62614.381348 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58933.291890 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56329.359895 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62614.381348 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58933.291890 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 159 # number of replacements -system.cpu.dcache.tags.tagsinuse 1459.152638 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28079168 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1460.308394 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28078942 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2247 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12496.291945 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12496.191366 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1459.152638 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.356238 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.356238 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1460.308394 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.356521 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.356521 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1391 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.509766 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 56179001 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 56179001 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21586035 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21586035 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492869 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492869 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 264 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 264 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28078904 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28078904 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28078904 # number of overall hits -system.cpu.dcache.overall_hits::total 28078904 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 974 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 974 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8234 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8234 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 56178581 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 56178581 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21585827 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21585827 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492868 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492868 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 247 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 247 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28078695 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28078695 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28078695 # number of overall hits +system.cpu.dcache.overall_hits::total 28078695 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 989 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 989 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8235 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8235 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9208 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9208 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9208 # number of overall misses -system.cpu.dcache.overall_misses::total 9208 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58289250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58289250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 505816795 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 505816795 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9224 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9224 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9224 # number of overall misses +system.cpu.dcache.overall_misses::total 9224 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 64012750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 64012750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 517866286 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 517866286 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 564106045 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 564106045 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 564106045 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 564106045 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21587009 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21587009 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 581879036 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 581879036 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 581879036 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 581879036 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21586816 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21586816 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 265 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 265 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28088112 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28088112 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28088112 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28088112 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 248 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 248 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28087919 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28087919 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28087919 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28087919 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001267 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001267 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003774 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003774 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004032 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004032 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59845.225873 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59845.225873 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61430.264149 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61430.264149 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64724.721941 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64724.721941 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62886.009229 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62886.009229 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61262.602628 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61262.602628 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61262.602628 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61262.602628 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24052 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63083.156548 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63083.156548 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63083.156548 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63083.156548 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24818 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 336 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 346 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 71.583333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 71.728324 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 109 # number of writebacks system.cpu.dcache.writebacks::total 109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 459 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6503 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6503 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6962 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6962 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6962 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6962 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 474 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 474 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6504 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6504 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6978 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6978 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6978 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6978 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 515 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses @@ -913,36 +908,36 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2246 system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35552000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 35552000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126441497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 126441497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37612750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37612750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127737997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 127737997 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161993497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161993497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161993497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161993497 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165350747 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 165350747 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 165350747 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 165350747 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003774 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003774 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004032 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004032 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69033.009709 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69033.009709 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73045.347776 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73045.347776 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73034.466019 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73034.466019 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73794.336800 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73794.336800 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72125.332591 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72125.332591 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72125.332591 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72125.332591 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73620.101069 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73620.101069 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73620.101069 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73620.101069 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index a1592fc7b..975655111 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.074220 # Number of seconds simulated -sim_ticks 74219931000 # Number of ticks simulated -final_tick 74219931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.074212 # Number of seconds simulated +sim_ticks 74211770500 # Number of ticks simulated +final_tick 74211770500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128899 # Simulator instruction rate (inst/s) -host_op_rate 141133 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55523526 # Simulator tick rate (ticks/s) -host_mem_usage 273064 # Number of bytes of host memory used -host_seconds 1336.73 # Real time elapsed on the host +host_inst_rate 109728 # Simulator instruction rate (inst/s) +host_op_rate 120142 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47260193 # Simulator tick rate (ticks/s) +host_mem_usage 316324 # Number of bytes of host memory used +host_seconds 1570.28 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 131072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 111680 # Number of bytes read from this memory -system.physmem.bytes_read::total 242752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112000 # Number of bytes read from this memory +system.physmem.bytes_read::total 243072 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 131072 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 131072 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 2048 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1745 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3793 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1765995 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1504717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3270712 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1765995 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1765995 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1765995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1504717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3270712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3794 # Number of read requests accepted +system.physmem.num_reads::cpu.data 1750 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3798 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1766189 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1509195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3275383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1766189 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1766189 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1766189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1509195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3275383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3799 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3794 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3799 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 242816 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 243136 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 242816 # Total read bytes from the system interface side +system.physmem.bytesReadSys 243136 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 306 # Per bank write bursts system.physmem.perBankRdBursts::1 215 # Per bank write bursts -system.physmem.perBankRdBursts::2 133 # Per bank write bursts +system.physmem.perBankRdBursts::2 132 # Per bank write bursts system.physmem.perBankRdBursts::3 308 # Per bank write bursts system.physmem.perBankRdBursts::4 298 # Per bank write bursts system.physmem.perBankRdBursts::5 299 # Per bank write bursts -system.physmem.perBankRdBursts::6 264 # Per bank write bursts -system.physmem.perBankRdBursts::7 216 # Per bank write bursts +system.physmem.perBankRdBursts::6 265 # Per bank write bursts +system.physmem.perBankRdBursts::7 218 # Per bank write bursts system.physmem.perBankRdBursts::8 246 # Per bank write bursts -system.physmem.perBankRdBursts::9 215 # Per bank write bursts +system.physmem.perBankRdBursts::9 214 # Per bank write bursts system.physmem.perBankRdBursts::10 289 # Per bank write bursts -system.physmem.perBankRdBursts::11 193 # Per bank write bursts -system.physmem.perBankRdBursts::12 189 # Per bank write bursts -system.physmem.perBankRdBursts::13 206 # Per bank write bursts -system.physmem.perBankRdBursts::14 217 # Per bank write bursts +system.physmem.perBankRdBursts::11 192 # Per bank write bursts +system.physmem.perBankRdBursts::12 190 # Per bank write bursts +system.physmem.perBankRdBursts::13 208 # Per bank write bursts +system.physmem.perBankRdBursts::14 219 # Per bank write bursts system.physmem.perBankRdBursts::15 200 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 74219912500 # Total gap between requests +system.physmem.totGap 74211752000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3794 # Read request sizes (log2) +system.physmem.readPktSize::6 3799 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2838 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 780 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 138 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -154,101 +154,102 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 334.192469 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.652659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 576.534776 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 257 35.84% 35.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 120 16.74% 52.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 71 9.90% 62.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 49 6.83% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 19 2.65% 71.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 26 3.63% 75.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 20 2.79% 78.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 17 2.37% 80.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 17 2.37% 83.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 40 5.58% 88.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 17 2.37% 91.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 6 0.84% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 6 0.84% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 8 1.12% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 6 0.84% 94.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 5 0.70% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 4 0.56% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1 0.14% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.28% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.28% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.28% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 2 0.28% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 1 0.14% 97.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 1 0.14% 97.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 1 0.14% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.14% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.14% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.28% 98.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 1 0.14% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 2 0.28% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.14% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.14% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.14% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 1 0.14% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.14% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 1 0.14% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 1 0.14% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.14% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.14% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 1 0.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation -system.physmem.totQLat 25208000 # Total ticks spent queuing -system.physmem.totMemAccLat 100718000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 18970000 # Total ticks spent in databus transfers -system.physmem.totBankLat 56540000 # Total ticks spent accessing banks -system.physmem.avgQLat 6644.18 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14902.48 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 398.476190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 217.440190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 401.372897 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 87 34.52% 34.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 58 23.02% 57.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 17 6.75% 64.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 5 1.98% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 2.78% 69.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8 3.17% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 1.59% 73.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 1.19% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 63 25.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 252 # Bytes accessed per row activation +system.physmem.totQLat 23847500 # Total ticks spent queuing +system.physmem.totMemAccLat 100702500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 18995000 # Total ticks spent in databus transfers +system.physmem.totBankLat 57860000 # Total ticks spent accessing banks +system.physmem.avgQLat 6277.31 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15230.32 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26546.65 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26507.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.27 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.28 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3077 # Number of row buffer hits during reads +system.physmem.readRowHits 3018 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.10 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19562443.99 # Average gap between requests -system.physmem.pageHitRate 81.10 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.24 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 3270712 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 2723 # Transaction distribution -system.membus.trans_dist::ReadResp 2722 # Transaction distribution +system.physmem.avgGap 19534549.09 # Average gap between requests +system.physmem.pageHitRate 79.44 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.21 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 3275383 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2728 # Transaction distribution +system.membus.trans_dist::ReadResp 2727 # Transaction distribution system.membus.trans_dist::ReadExReq 1071 # Transaction distribution system.membus.trans_dist::ReadExResp 1071 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7587 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7587 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 242752 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 242752 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 242752 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7597 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7597 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243072 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 243072 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 243072 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 4681000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4687500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35532250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35592500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 94784239 # Number of BP lookups -system.cpu.branchPred.condPredicted 74783977 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6281559 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44678373 # Number of BTB lookups -system.cpu.branchPred.BTBHits 43049971 # Number of BTB hits +system.cpu.branchPred.lookups 94795806 # Number of BP lookups +system.cpu.branchPred.condPredicted 74795654 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6279989 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 44691885 # Number of BTB lookups +system.cpu.branchPred.BTBHits 43051051 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.355279 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4356641 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 88400 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 96.328564 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4354918 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 88426 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -334,135 +335,135 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148439863 # number of cpu cycles simulated +system.cpu.numCycles 148423542 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39656875 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380179667 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94784239 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47406612 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80370607 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27283097 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7220794 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6206 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 39654967 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380195915 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94795806 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47405969 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80368300 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27279262 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7212539 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5988 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36850851 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1831977 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148240291 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.801605 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.152871 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 36848695 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1833193 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148225221 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.802047 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.153051 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68038529 45.90% 45.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5265458 3.55% 49.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10540663 7.11% 56.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10285699 6.94% 63.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8660453 5.84% 69.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6545120 4.42% 73.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6246377 4.21% 77.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8002820 5.40% 83.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24655172 16.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68026374 45.89% 45.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5263091 3.55% 49.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10536182 7.11% 56.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10285653 6.94% 63.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8660137 5.84% 69.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6544581 4.42% 73.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6243734 4.21% 77.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8007959 5.40% 83.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24657510 16.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148240291 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.638536 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.561170 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45513767 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5886575 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74804066 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1203498 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20832385 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14327909 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164350 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392779624 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 733803 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20832385 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50900716 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 730751 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 603183 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70558259 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4614997 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371307860 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 42 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 339068 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3661204 # Number of times rename has blocked due to LSQ full +system.cpu.fetch.rateDist::total 148225221 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.638684 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.561561 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45510679 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5881311 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74801618 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1201370 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20830243 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14327753 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164034 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392767808 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 749358 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20830243 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50895494 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 723680 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 602483 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70555782 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4617539 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371309891 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 37 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 338990 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3664355 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 25 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631703204 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1588513521 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1506815662 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3203425 # Number of floating rename lookups +system.cpu.rename.RenamedOperands 631718613 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1588504211 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1506839397 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3198087 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333659065 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25072 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25068 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13010227 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43012674 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16416368 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5733538 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3666489 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329189946 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 47154 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249456447 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 789359 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139503196 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 362394637 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1938 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148240291 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.682784 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.761427 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 333674474 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25005 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25002 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13030816 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43005440 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16429294 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5701095 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3639070 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 329189812 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 47090 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 249460239 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 787524 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139505237 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 362363758 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1874 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 148225221 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.682981 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761692 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56059626 37.82% 37.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22638758 15.27% 53.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24824129 16.75% 69.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20343397 13.72% 83.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12534810 8.46% 92.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6516110 4.40% 96.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4026087 2.72% 99.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1116064 0.75% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181310 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56054819 37.82% 37.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22642547 15.28% 53.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24806201 16.74% 69.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20327492 13.71% 83.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12550892 8.47% 92.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6518173 4.40% 96.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4029511 2.72% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1113373 0.75% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 182213 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148240291 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148225221 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 965209 38.57% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5593 0.22% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1158969 46.31% 85.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 372730 14.89% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 964965 38.34% 38.34% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5593 0.22% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 99 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 49 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1170821 46.51% 85.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 375623 14.92% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194899827 78.13% 78.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 979613 0.39% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194894311 78.13% 78.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 979316 0.39% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued @@ -481,93 +482,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33082 0.01% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164367 0.07% 78.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 255141 0.10% 78.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76420 0.03% 78.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 466123 0.19% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206380 0.08% 79.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71866 0.03% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33075 0.01% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164356 0.07% 78.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 254647 0.10% 78.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76432 0.03% 78.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 465549 0.19% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206388 0.08% 79.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71859 0.03% 79.03% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38355265 15.38% 94.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13948042 5.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38358541 15.38% 94.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13955444 5.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249456447 # Type of FU issued -system.cpu.iq.rate 1.680522 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2502650 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010032 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646705187 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466563017 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237885267 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3740007 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2195697 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1842613 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250082678 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1876419 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2013206 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 249460239 # Type of FU issued +system.cpu.iq.rate 1.680732 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2517150 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010090 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 646712991 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466571759 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237891174 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3737382 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2188885 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1841279 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 250102160 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1875229 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2007089 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13163190 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11604 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18881 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3771734 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13155956 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11631 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18977 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3784660 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 107 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 100 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20832385 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18544 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 886 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329254297 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 785292 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43012674 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16416368 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 24746 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 181 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 276 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18881 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3889950 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3760088 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7650038 # Number of branch mispredicts detected at execute +system.cpu.iew.iewSquashCycles 20830243 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18508 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 911 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 329253924 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 785902 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43005440 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16429294 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 24682 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 206 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 274 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18977 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3891616 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3758665 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7650281 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 242960344 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36851914 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6496103 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecLoadInsts 36855491 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6499895 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17197 # number of nop insts executed -system.cpu.iew.exec_refs 50500351 # number of memory reference insts executed -system.cpu.iew.exec_branches 53426054 # Number of branches executed -system.cpu.iew.exec_stores 13648437 # Number of stores executed -system.cpu.iew.exec_rate 1.636759 # Inst execution rate -system.cpu.iew.wb_sent 240785488 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239727880 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148473973 # num instructions producing a value -system.cpu.iew.wb_consumers 267261246 # num instructions consuming a value +system.cpu.iew.exec_nop 17022 # number of nop insts executed +system.cpu.iew.exec_refs 50506525 # number of memory reference insts executed +system.cpu.iew.exec_branches 53424421 # Number of branches executed +system.cpu.iew.exec_stores 13651034 # Number of stores executed +system.cpu.iew.exec_rate 1.636939 # Inst execution rate +system.cpu.iew.wb_sent 240787816 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239732453 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148473522 # num instructions producing a value +system.cpu.iew.wb_consumers 267271209 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.614983 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back +system.cpu.iew.wb_rate 1.615192 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555516 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140583409 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 140583033 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6128231 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127407906 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.480841 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.185453 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6126865 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 127394978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.480992 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.186196 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57701601 45.29% 45.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31696921 24.88% 70.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13777775 10.81% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7640604 6.00% 86.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4387783 3.44% 90.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1321955 1.04% 91.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1703214 1.34% 92.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1308007 1.03% 93.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7870046 6.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57713917 45.30% 45.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31674198 24.86% 70.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13788488 10.82% 80.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7625423 5.99% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4380329 3.44% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1321262 1.04% 91.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1701589 1.34% 92.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1311888 1.03% 93.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7877884 6.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127407906 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 127394978 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -578,230 +579,230 @@ system.cpu.commit.branches 40300311 # Nu system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7870046 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7877884 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448786959 # The number of ROB reads -system.cpu.rob.rob_writes 679450685 # The number of ROB writes -system.cpu.timesIdled 2806 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 199572 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 448765817 # The number of ROB reads +system.cpu.rob.rob_writes 679447245 # The number of ROB writes +system.cpu.timesIdled 2831 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 198321 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated -system.cpu.cpi 0.861505 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.861505 # CPI: Total CPI of All Threads -system.cpu.ipc 1.160760 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.160760 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1079416198 # number of integer regfile reads -system.cpu.int_regfile_writes 384871537 # number of integer regfile writes -system.cpu.fp_regfile_reads 2913086 # number of floating regfile reads -system.cpu.fp_regfile_writes 2499105 # number of floating regfile writes -system.cpu.misc_regfile_reads 64870078 # number of misc regfile reads +system.cpu.cpi 0.861410 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.861410 # CPI: Total CPI of All Threads +system.cpu.ipc 1.160887 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.160887 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1079439987 # number of integer regfile reads +system.cpu.int_regfile_writes 384873432 # number of integer regfile writes +system.cpu.fp_regfile_reads 2912671 # number of floating regfile reads +system.cpu.fp_regfile_writes 2497165 # number of floating regfile writes +system.cpu.misc_regfile_reads 64868455 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.toL2Bus.throughput 5170363 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 4900 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 4899 # Transaction distribution +system.cpu.toL2Bus.throughput 5152821 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 4879 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 4878 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 18 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1079 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1079 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8253 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3722 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11975 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 264064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 383744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 383744 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8203 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3730 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11933 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 262464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 382400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 382400 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3016500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 3006000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6553746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6511747 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3047989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3051239 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2395 # number of replacements -system.cpu.icache.tags.tagsinuse 1347.740461 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 36845513 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4126 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8930.080708 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2374 # number of replacements +system.cpu.icache.tags.tagsinuse 1347.666302 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 36843383 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4101 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8983.999756 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740461 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.658076 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.658076 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1731 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 544 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 27 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1037 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.845215 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 73705828 # Number of tag accesses -system.cpu.icache.tags.data_accesses 73705828 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 36845513 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36845513 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36845513 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36845513 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36845513 # number of overall hits -system.cpu.icache.overall_hits::total 36845513 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5338 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5338 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5338 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5338 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5338 # number of overall misses -system.cpu.icache.overall_misses::total 5338 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 225943745 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 225943745 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 225943745 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 225943745 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 225943745 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 225943745 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36850851 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36850851 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36850851 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36850851 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36850851 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36850851 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42327.415699 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42327.415699 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42327.415699 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42327.415699 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42327.415699 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42327.415699 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1128 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1347.666302 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.658040 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.658040 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1727 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 534 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1040 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.843262 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 73701491 # Number of tag accesses +system.cpu.icache.tags.data_accesses 73701491 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 36843383 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36843383 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36843383 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36843383 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36843383 # number of overall hits +system.cpu.icache.overall_hits::total 36843383 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5312 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5312 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5312 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5312 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5312 # number of overall misses +system.cpu.icache.overall_misses::total 5312 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 224724996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 224724996 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 224724996 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 224724996 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 224724996 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 224724996 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36848695 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36848695 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36848695 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36848695 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36848695 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36848695 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000144 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000144 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000144 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000144 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000144 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000144 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42305.157380 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42305.157380 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42305.157380 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42305.157380 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42305.157380 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42305.157380 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1646 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.368421 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 86.631579 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1211 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1211 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1211 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1211 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1211 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1211 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4127 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4127 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4127 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4127 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4127 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4127 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168102254 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 168102254 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168102254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 168102254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168102254 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 168102254 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40732.312576 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40732.312576 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40732.312576 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40732.312576 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40732.312576 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40732.312576 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1210 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1210 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1210 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1210 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1210 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1210 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4102 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4102 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4102 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4102 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4102 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4102 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 167739253 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 167739253 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 167739253 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 167739253 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 167739253 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 167739253 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000111 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000111 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40892.065578 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40892.065578 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40892.065578 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40892.065578 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40892.065578 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40892.065578 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1967.449595 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2163 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2732 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.791728 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 1968.326603 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2138 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2737 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.781147 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 4.994097 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569547 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 536.885951 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 4.994032 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.493487 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 537.839084 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043505 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.016384 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.060042 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2732 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 604 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043503 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.016414 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.060069 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2737 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 602 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1970 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.083374 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 51787 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 51787 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2074 # 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number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1079 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1079 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4127 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1852 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 5979 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4127 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1852 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 5979 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.497456 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.886158 # 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miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.497456 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.948164 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.637063 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.497456 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.948164 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.637063 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69765.343400 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75017.883212 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71079.437546 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.766573 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.766573 # 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miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.639980 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69750.365497 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73703.985507 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70745.258935 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68055.555556 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68055.555556 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69750.365497 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70268.739353 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69989.771833 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69750.365497 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70268.739353 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.559131 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992586 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992586 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496487 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.634554 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496487 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.634554 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57226.573939 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62760.014837 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942888 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.637630 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.499512 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942888 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.637630 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57210.224500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61426.730486 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58259.714076 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55487.861811 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55487.861811 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57210.224500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57792.142857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57478.283759 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57210.224500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57792.142857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57478.283759 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 57 # number of replacements -system.cpu.dcache.tags.tagsinuse 1406.103051 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 46786126 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1852 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25262.487041 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 59 # number of replacements +system.cpu.dcache.tags.tagsinuse 1407.038554 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 46795712 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1856 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25213.206897 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1406.103051 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.343287 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.343287 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1795 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1407.038554 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.343515 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.343515 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 353 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1378 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.438232 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 93593354 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 93593354 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 34384681 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34384681 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356564 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356564 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22474 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22474 # number of LoadLockedReq hits +system.cpu.dcache.tags.occ_task_id_percent::1024 0.438721 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 93612504 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 93612504 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 34394263 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34394263 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356566 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356566 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22476 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22476 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46741245 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46741245 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46741245 # number of overall hits -system.cpu.dcache.overall_hits::total 46741245 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1900 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1900 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7723 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7723 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 46750829 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46750829 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46750829 # number of overall hits +system.cpu.dcache.overall_hits::total 46750829 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1889 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1889 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7721 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7721 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9623 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9623 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9623 # number of overall misses -system.cpu.dcache.overall_misses::total 9623 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 121712227 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 121712227 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623746 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 465623746 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9610 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9610 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9610 # number of overall misses +system.cpu.dcache.overall_misses::total 9610 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 119060977 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 119060977 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 479134996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 479134996 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 587335973 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 587335973 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 587335973 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 587335973 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34386581 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34386581 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 598195973 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 598195973 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 598195973 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 598195973 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34396152 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34396152 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22476 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22476 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22478 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22478 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46750868 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46750868 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46750868 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46750868 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 46760439 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46760439 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46760439 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46760439 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64059.066842 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64059.066842 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.527774 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.527774 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63028.574378 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63028.574378 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62056.080300 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62056.080300 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61034.601787 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61034.601787 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61034.601787 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61034.601787 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 314 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62247.239646 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62247.239646 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62247.239646 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62247.239646 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 566 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 318 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.818182 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 78.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 51.454545 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 79.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1126 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1126 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6645 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6645 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1111 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1111 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6643 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6643 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7771 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7771 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7771 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7771 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 774 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 7754 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7754 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7754 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7754 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 778 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 778 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1078 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1078 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1852 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1852 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1852 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1852 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53118011 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 53118011 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73393498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 73393498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126511509 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 126511509 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126511509 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 126511509 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52580511 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52580511 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73988748 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 73988748 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126569259 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 126569259 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126569259 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 126569259 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses @@ -990,14 +991,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68627.921189 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68627.921189 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68083.022263 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68083.022263 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68310.750000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68310.750000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68310.750000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68310.750000 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67584.204370 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67584.204370 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68635.202226 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68635.202226 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68194.643858 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68194.643858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68194.643858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68194.643858 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 1427887bb..cc1011ed3 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.144463 # Number of seconds simulated -sim_ticks 144463317000 # Number of ticks simulated -final_tick 144463317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.144377 # Number of seconds simulated +sim_ticks 144377116000 # Number of ticks simulated +final_tick 144377116000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81167 # Simulator instruction rate (inst/s) -host_op_rate 136043 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 88782348 # Simulator tick rate (ticks/s) -host_mem_usage 282908 # Number of bytes of host memory used -host_seconds 1627.16 # Real time elapsed on the host +host_inst_rate 66784 # Simulator instruction rate (inst/s) +host_op_rate 111936 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73006862 # Simulator tick rate (ticks/s) +host_mem_usage 319660 # Number of bytes of host memory used +host_seconds 1977.58 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 217088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125568 # Number of bytes read from this memory -system.physmem.bytes_read::total 342656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217088 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3392 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1962 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5354 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1502721 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 869203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2371924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1502721 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1502721 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1502721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 869203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2371924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5354 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125056 # Number of bytes read from this memory +system.physmem.bytes_read::total 343040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217984 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3406 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1954 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5360 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1509824 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 866176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2376000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1509824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1509824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1509824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 866176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2376000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5361 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5354 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5361 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 342656 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 343104 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 342656 # Total read bytes from the system interface side +system.physmem.bytesReadSys 343104 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 163 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 289 # Per bank write bursts -system.physmem.perBankRdBursts::1 357 # Per bank write bursts -system.physmem.perBankRdBursts::2 453 # Per bank write bursts -system.physmem.perBankRdBursts::3 356 # Per bank write bursts -system.physmem.perBankRdBursts::4 332 # Per bank write bursts -system.physmem.perBankRdBursts::5 326 # Per bank write bursts -system.physmem.perBankRdBursts::6 402 # Per bank write bursts -system.physmem.perBankRdBursts::7 377 # Per bank write bursts -system.physmem.perBankRdBursts::8 341 # Per bank write bursts -system.physmem.perBankRdBursts::9 276 # Per bank write bursts -system.physmem.perBankRdBursts::10 232 # Per bank write bursts -system.physmem.perBankRdBursts::11 277 # Per bank write bursts -system.physmem.perBankRdBursts::12 205 # Per bank write bursts -system.physmem.perBankRdBursts::13 465 # Per bank write bursts -system.physmem.perBankRdBursts::14 384 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 150 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 281 # Per bank write bursts +system.physmem.perBankRdBursts::1 346 # Per bank write bursts +system.physmem.perBankRdBursts::2 449 # Per bank write bursts +system.physmem.perBankRdBursts::3 351 # Per bank write bursts +system.physmem.perBankRdBursts::4 335 # Per bank write bursts +system.physmem.perBankRdBursts::5 328 # Per bank write bursts +system.physmem.perBankRdBursts::6 398 # Per bank write bursts +system.physmem.perBankRdBursts::7 381 # Per bank write bursts +system.physmem.perBankRdBursts::8 343 # Per bank write bursts +system.physmem.perBankRdBursts::9 292 # Per bank write bursts +system.physmem.perBankRdBursts::10 228 # Per bank write bursts +system.physmem.perBankRdBursts::11 284 # Per bank write bursts +system.physmem.perBankRdBursts::12 208 # Per bank write bursts +system.physmem.perBankRdBursts::13 469 # Per bank write bursts +system.physmem.perBankRdBursts::14 386 # Per bank write bursts system.physmem.perBankRdBursts::15 282 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 144463266500 # Total gap between requests +system.physmem.totGap 144377080000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5354 # Read request sizes (log2) +system.physmem.readPktSize::6 5361 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4312 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 880 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 145 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -154,346 +154,337 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 957 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 353.103448 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.307957 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 612.115437 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 385 40.23% 40.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 164 17.14% 57.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 81 8.46% 65.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 46 4.81% 70.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 43 4.49% 75.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 20 2.09% 77.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 26 2.72% 79.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 19 1.99% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 17 1.78% 83.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 26 2.72% 86.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 27 2.82% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 7 0.73% 89.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 7 0.73% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 7 0.73% 91.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 3 0.31% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 5 0.52% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 6 0.63% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 6 0.63% 93.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 4 0.42% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 2 0.21% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 2 0.21% 94.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 3 0.31% 94.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 7 0.73% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 1 0.10% 95.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 5 0.52% 96.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 4 0.42% 96.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 2 0.21% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 2 0.21% 96.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 2 0.21% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 3 0.31% 97.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 2 0.21% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 1 0.10% 97.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 1 0.10% 97.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 1 0.10% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 1 0.10% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 1 0.10% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 2 0.21% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 1 0.10% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 2 0.21% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 3 0.31% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 1 0.10% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 1 0.10% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 1 0.10% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 1 0.10% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 1 0.10% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 1 0.10% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736 1 0.10% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312 1 0.10% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696 1 0.10% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952 1 0.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 957 # Bytes accessed per row activation -system.physmem.totQLat 28783000 # Total ticks spent queuing -system.physmem.totMemAccLat 137846750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26770000 # Total ticks spent in databus transfers -system.physmem.totBankLat 82293750 # Total ticks spent accessing banks -system.physmem.avgQLat 5375.98 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 15370.52 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 327 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 508.672783 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 294.998238 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 425.682375 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 88 26.91% 26.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 53 16.21% 43.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 28 8.56% 51.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 16 4.89% 56.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 9 2.75% 59.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6 1.83% 61.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 0.92% 62.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 0.92% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 121 37.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 327 # Bytes accessed per row activation +system.physmem.totQLat 28551000 # Total ticks spent queuing +system.physmem.totMemAccLat 139987250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26805000 # Total ticks spent in databus transfers +system.physmem.totBankLat 84631250 # Total ticks spent accessing banks +system.physmem.avgQLat 5325.69 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15786.47 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25746.50 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26112.15 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.38 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.38 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4397 # Number of row buffer hits during reads +system.physmem.readRowHits 4274 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.13 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.72 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 26982306.03 # Average gap between requests -system.physmem.pageHitRate 82.13 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 2371924 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3822 # Transaction distribution -system.membus.trans_dist::ReadResp 3822 # Transaction distribution -system.membus.trans_dist::UpgradeReq 163 # Transaction distribution -system.membus.trans_dist::UpgradeResp 163 # Transaction distribution -system.membus.trans_dist::ReadExReq 1532 # Transaction distribution -system.membus.trans_dist::ReadExResp 1532 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11034 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11034 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11034 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342656 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342656 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 342656 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 342656 # Total data (bytes) +system.physmem.avgGap 26930997.95 # Average gap between requests +system.physmem.pageHitRate 79.72 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.40 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 2375113 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3828 # Transaction distribution +system.membus.trans_dist::ReadResp 3825 # Transaction distribution +system.membus.trans_dist::UpgradeReq 150 # Transaction distribution +system.membus.trans_dist::UpgradeResp 150 # Transaction distribution +system.membus.trans_dist::ReadExReq 1533 # Transaction distribution +system.membus.trans_dist::ReadExResp 1533 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11019 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11019 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11019 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342912 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342912 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 342912 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 342912 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6950000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6993500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50662837 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 50706850 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 18648233 # Number of BP lookups -system.cpu.branchPred.condPredicted 18648233 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1490176 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11407549 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10790529 # Number of BTB hits +system.cpu.branchPred.lookups 18662333 # Number of BP lookups +system.cpu.branchPred.condPredicted 18662333 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1490477 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11407057 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10802916 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.591126 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1320367 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 22841 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.703796 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1319575 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 23217 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 289221873 # number of cpu cycles simulated +system.cpu.numCycles 289035036 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 23458043 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 206724218 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18648233 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12110896 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 54209097 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 15518774 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 178161359 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1571 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9111 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22353211 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 224061 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269612469 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.268180 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.756310 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 23466628 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 206674196 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18662333 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 12122491 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 54224578 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 15529649 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 177872737 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1739 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9780 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22363082 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 227556 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 269352720 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.269654 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.757498 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 216842563 80.43% 80.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2848142 1.06% 81.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2312055 0.86% 82.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2633842 0.98% 83.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3218714 1.19% 84.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3388946 1.26% 85.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3831195 1.42% 87.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2559437 0.95% 88.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31977575 11.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 216567147 80.40% 80.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2849140 1.06% 81.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2312743 0.86% 82.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2640443 0.98% 83.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3223496 1.20% 84.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3388678 1.26% 85.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3828931 1.42% 87.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2559342 0.95% 88.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31982800 11.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269612469 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064477 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.714760 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36899359 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 167130004 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 41545229 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10264627 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13773250 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336001462 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 13773250 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44972487 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116686698 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 32545 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 42701689 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51445800 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 329633775 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10827 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26123597 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22730549 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 382342090 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 917586713 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 605878272 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4127660 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 269352720 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064568 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.715049 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36872291 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 166882879 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 41583049 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10237266 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 13777235 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336030589 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 13777235 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44927552 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116592006 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 33482 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 42725844 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51296601 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 329644603 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10793 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25973281 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22738118 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 382392326 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 917644681 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 605892364 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4122807 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 122912640 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2051 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2042 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 105140052 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 84507276 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 30107186 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58355212 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 18979888 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322730905 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 260501994 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 116055 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 100987191 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 210203655 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269612469 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.966209 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.343680 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 122962876 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2119 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2126 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 104910685 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 84442386 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 30099715 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 58118082 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 18905602 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 322699954 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4280 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 260615725 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 114961 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 100953398 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 209924725 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3035 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 269352720 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.967563 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.344835 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 143429912 53.20% 53.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55567346 20.61% 73.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34108148 12.65% 86.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19044980 7.06% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10887634 4.04% 97.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4152283 1.54% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1816697 0.67% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 472473 0.18% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 132996 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143250903 53.18% 53.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55370436 20.56% 73.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34176648 12.69% 86.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19094867 7.09% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10869897 4.04% 97.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4155062 1.54% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1825131 0.68% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 476500 0.18% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 133276 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269612469 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269352720 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 130605 4.82% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2279077 84.03% 88.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 302412 11.15% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 130941 4.84% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2275620 84.10% 88.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 299199 11.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1210810 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 162055944 62.21% 62.67% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 789191 0.30% 62.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7035649 2.70% 65.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1445882 0.56% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 65414513 25.11% 91.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22550005 8.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1210799 0.46% 0.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 162097443 62.20% 62.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 790400 0.30% 62.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7035783 2.70% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1447528 0.56% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 65478586 25.12% 91.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22555186 8.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 260501994 # Type of FU issued -system.cpu.iq.rate 0.900699 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2712094 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010411 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 788557578 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 420384868 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 255147075 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4887028 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3615221 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2349564 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 259544026 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2459252 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18903382 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 260615725 # Type of FU issued +system.cpu.iq.rate 0.901675 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2705760 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010382 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 788512519 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 420334227 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 255242293 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4892372 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3608187 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2352192 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 259648600 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2462086 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18920241 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27857689 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25992 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 283319 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9591469 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27792799 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26588 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 290410 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9583998 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49752 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 49921 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13773250 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 85040639 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5471570 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 322734974 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 133239 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 84507276 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 30107186 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1979 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2708196 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13910 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 283319 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 639398 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 901242 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1540640 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 258732431 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64645019 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1769563 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 13777235 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 85064772 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5446513 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 322704234 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 135340 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 84442386 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 30099715 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2049 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2678194 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12950 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 290410 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 639185 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 902051 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1541236 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 258833919 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64703526 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1781806 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 86992194 # number of memory reference insts executed -system.cpu.iew.exec_branches 14265859 # Number of branches executed -system.cpu.iew.exec_stores 22347175 # Number of stores executed -system.cpu.iew.exec_rate 0.894581 # Inst execution rate -system.cpu.iew.wb_sent 258096693 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 257496639 # cumulative count of insts written-back -system.cpu.iew.wb_producers 205928299 # num instructions producing a value -system.cpu.iew.wb_consumers 369130530 # num instructions consuming a value +system.cpu.iew.exec_refs 87053484 # number of memory reference insts executed +system.cpu.iew.exec_branches 14272898 # Number of branches executed +system.cpu.iew.exec_stores 22349958 # Number of stores executed +system.cpu.iew.exec_rate 0.895511 # Inst execution rate +system.cpu.iew.wb_sent 258192676 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 257594485 # cumulative count of insts written-back +system.cpu.iew.wb_producers 206043233 # num instructions producing a value +system.cpu.iew.wb_consumers 369200904 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.890308 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557874 # average fanout of values written-back +system.cpu.iew.wb_rate 0.891222 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.558079 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 101448840 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 101415579 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1491529 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255839219 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.865244 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.654327 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1491917 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 255575485 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.866137 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.656618 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156486617 61.17% 61.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57197635 22.36% 83.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14067876 5.50% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12054068 4.71% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4176261 1.63% 95.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2944387 1.15% 96.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 904564 0.35% 96.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1049058 0.41% 97.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6958753 2.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 156360594 61.18% 61.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57109316 22.35% 83.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13985683 5.47% 89.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12037857 4.71% 93.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4182593 1.64% 95.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2963821 1.16% 96.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 909345 0.36% 96.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1046624 0.41% 97.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6979652 2.73% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255839219 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 255575485 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -504,240 +495,240 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. system.cpu.commit.function_calls 797818 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6958753 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6979652 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571692690 # The number of ROB reads -system.cpu.rob.rob_writes 659422914 # The number of ROB writes -system.cpu.timesIdled 5933064 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19609404 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 571374796 # The number of ROB reads +system.cpu.rob.rob_writes 659361249 # The number of ROB writes +system.cpu.timesIdled 5927783 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19682316 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 2.189894 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.189894 # CPI: Total CPI of All Threads -system.cpu.ipc 0.456643 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.456643 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 451224153 # number of integer regfile reads -system.cpu.int_regfile_writes 233957254 # number of integer regfile writes -system.cpu.fp_regfile_reads 3215586 # number of floating regfile reads -system.cpu.fp_regfile_writes 2009211 # number of floating regfile writes -system.cpu.cc_regfile_reads 102809513 # number of cc regfile reads -system.cpu.cc_regfile_writes 59799383 # number of cc regfile writes -system.cpu.misc_regfile_reads 133324417 # number of misc regfile reads +system.cpu.cpi 2.188479 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.188479 # CPI: Total CPI of All Threads +system.cpu.ipc 0.456938 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.456938 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 451403378 # number of integer regfile reads +system.cpu.int_regfile_writes 234040975 # number of integer regfile writes +system.cpu.fp_regfile_reads 3219859 # number of floating regfile reads +system.cpu.fp_regfile_writes 2011879 # number of floating regfile writes +system.cpu.cc_regfile_reads 102824885 # number of cc regfile reads +system.cpu.cc_regfile_writes 59817361 # number of cc regfile writes +system.cpu.misc_regfile_reads 133392985 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.toL2Bus.throughput 3898568 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7250 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7248 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 163 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 163 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13403 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4348 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17751 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 423616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 552704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 552704 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 10496 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4495500 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 3846371 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7125 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7121 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 15 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 150 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 150 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1541 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13184 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4308 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17492 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 417024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 545664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 545664 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 9664 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4430500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10760250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10573999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3467413 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3437150 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 4653 # number of replacements -system.cpu.icache.tags.tagsinuse 1619.938452 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22344300 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6620 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3375.271903 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4547 # number of replacements +system.cpu.icache.tags.tagsinuse 1629.451963 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22354297 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6517 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3430.151450 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1619.938452 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.790986 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.790986 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1967 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 767 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 797 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.960449 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 44713203 # Number of tag accesses -system.cpu.icache.tags.data_accesses 44713203 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22344300 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22344300 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22344300 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22344300 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22344300 # number of overall hits -system.cpu.icache.overall_hits::total 22344300 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8910 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8910 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8910 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8910 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8910 # number of overall misses -system.cpu.icache.overall_misses::total 8910 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 368144999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 368144999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 368144999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 368144999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 368144999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 368144999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22353210 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22353210 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22353210 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22353210 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22353210 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22353210 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41318.181706 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41318.181706 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41318.181706 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41318.181706 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 877 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1629.451963 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.795631 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.795631 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1970 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 757 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 807 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.961914 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 44732829 # Number of tag accesses +system.cpu.icache.tags.data_accesses 44732829 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22354297 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22354297 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22354297 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22354297 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22354297 # number of overall hits +system.cpu.icache.overall_hits::total 22354297 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8784 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8784 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8784 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8784 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8784 # number of overall misses +system.cpu.icache.overall_misses::total 8784 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 365846249 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 365846249 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 365846249 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 365846249 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 365846249 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 365846249 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22363081 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22363081 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22363081 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22363081 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22363081 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22363081 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000393 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000393 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000393 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000393 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000393 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000393 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41649.163138 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41649.163138 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41649.163138 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41649.163138 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41649.163138 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41649.163138 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 800 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.850000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 57.142857 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2126 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2126 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2126 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2126 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2126 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2126 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6784 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6784 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6784 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6784 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6784 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6784 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 271638749 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 271638749 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 271638749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 271638749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271638749 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 271638749 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000303 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000303 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40041.089180 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40041.089180 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2116 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2116 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2116 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2116 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2116 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2116 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6668 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6668 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6668 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6668 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6668 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6668 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 272166001 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 272166001 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 272166001 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 272166001 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 272166001 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 272166001 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000298 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000298 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000298 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000298 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000298 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000298 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40816.736803 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40816.736803 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40816.736803 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40816.736803 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40816.736803 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40816.736803 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2543.926920 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3266 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3826 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.853633 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2545.733703 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3149 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3831 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.821979 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1.725256 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2230.334814 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 311.866849 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068064 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.009517 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.077634 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3826 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 876 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 145 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2560 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.116760 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 75773 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 75773 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 3227 # number of ReadReq hits +system.cpu.l2cache.tags.occ_blocks::writebacks 1.666971 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2237.371026 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 306.695706 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000051 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068279 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.009360 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.077690 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3831 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 881 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 143 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2568 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.116913 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 74812 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 74812 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 3110 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 36 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3263 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 13 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55488.258317 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55488.258317 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56232.315820 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57654.042989 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56750.512964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56232.315820 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57654.042989 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56750.512964 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 57 # number of replacements -system.cpu.dcache.tags.tagsinuse 1438.861304 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 66102356 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2004 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32985.207585 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1432.023881 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 66143701 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1995 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33154.737343 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1438.861304 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.351284 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.351284 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1947 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1432.023881 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.349615 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.349615 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1938 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 432 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1395 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.475342 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 132211530 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 132211530 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 45588097 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45588097 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514029 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514029 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66102126 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66102126 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66102126 # number of overall hits -system.cpu.dcache.overall_hits::total 66102126 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 935 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 935 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1702 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1702 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2637 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2637 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2637 # number of overall misses -system.cpu.dcache.overall_misses::total 2637 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 62763567 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 62763567 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 113907163 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 113907163 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 176670730 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 176670730 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 176670730 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 176670730 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45589032 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45589032 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 427 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1393 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.473145 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 132294203 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 132294203 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 45629460 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45629460 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514040 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514040 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 66143500 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 66143500 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 66143500 # number of overall hits +system.cpu.dcache.overall_hits::total 66143500 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 913 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 913 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1691 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1691 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2604 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2604 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2604 # number of overall misses +system.cpu.dcache.overall_misses::total 2604 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59632801 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59632801 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 113805150 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 113805150 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 173437951 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 173437951 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 173437951 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 173437951 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45630373 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45630373 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66104763 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66104763 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66104763 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66104763 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000083 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67126.809626 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67126.809626 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66925.477673 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66925.477673 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66996.863860 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66996.863860 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66996.863860 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66996.863860 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 66146104 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66146104 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66146104 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66146104 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000082 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000082 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65315.225630 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 65315.225630 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67300.502661 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67300.502661 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66604.435868 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66604.435868 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66604.435868 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66604.435868 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 319 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 77 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 79.750000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 13 # number of writebacks -system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 468 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 468 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 15 # number of writebacks +system.cpu.dcache.writebacks::total 15 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 455 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 455 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 469 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 469 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 469 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 469 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 467 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1701 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1701 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2168 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2168 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2168 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33590500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33590500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109769587 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 109769587 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 143360087 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 143360087 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 143360087 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 143360087 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 456 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 456 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 456 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 456 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 458 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1690 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1690 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2148 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2148 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2148 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2148 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33615250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33615250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109709600 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 109709600 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 143324850 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 143324850 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 143324850 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 143324850 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000083 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71928.265525 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71928.265525 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64532.385068 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64532.385068 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66125.501384 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66125.501384 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66125.501384 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66125.501384 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000082 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73395.742358 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73395.742358 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64916.923077 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64916.923077 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66724.790503 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66724.790503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66724.790503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66724.790503 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |