diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-06-21 16:42:04 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-06-21 16:42:04 +0100 |
| commit | 9c8710430eb671b5e89f291b9f0a10b6156ac633 (patch) | |
| tree | d25fd7e25b7a326ddbfeb812ec4603eb5a5f2719 /tests/long | |
| parent | 1fac3a292ad53811fec534d8a3e49cb86a70aeb8 (diff) | |
| download | gem5-9c8710430eb671b5e89f291b9f0a10b6156ac633.tar.xz | |
stats: Update stats to reflect ARM changes
Diffstat (limited to 'tests/long')
21 files changed, 2048 insertions, 2048 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 8a8cb49d0..26497932e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.847227 # Nu sim_ticks 2847227406000 # Number of ticks simulated final_tick 2847227406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 262523 # Simulator instruction rate (inst/s) -host_op_rate 317894 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5870765699 # Simulator tick rate (ticks/s) -host_mem_usage 664268 # Number of bytes of host memory used -host_seconds 484.98 # Real time elapsed on the host +host_inst_rate 166460 # Simulator instruction rate (inst/s) +host_op_rate 201569 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3722516357 # Simulator tick rate (ticks/s) +host_mem_usage 624360 # Number of bytes of host memory used +host_seconds 764.87 # Real time elapsed on the host sim_insts 127319545 # Number of instructions simulated sim_ops 154173476 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -456,7 +456,7 @@ system.cpu0.dtb.flush_tlb 66 # Nu system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3513 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3449 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 1354 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 1959 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -540,7 +540,7 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2216 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2152 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1406,7 +1406,7 @@ system.cpu1.dtb.flush_tlb 66 # Nu system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2060 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1996 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 164 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 367 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1495,7 +1495,7 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1166 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1102 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index ddbc8e898..12eb20a39 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.858505 # Nu sim_ticks 2858505242500 # Number of ticks simulated final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 258042 # Simulator instruction rate (inst/s) -host_op_rate 311992 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6591883972 # Simulator tick rate (ticks/s) -host_mem_usage 625700 # Number of bytes of host memory used -host_seconds 433.64 # Real time elapsed on the host +host_inst_rate 152549 # Simulator instruction rate (inst/s) +host_op_rate 184443 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3896990443 # Simulator tick rate (ticks/s) +host_mem_usage 585436 # Number of bytes of host memory used +host_seconds 733.52 # Real time elapsed on the host sim_insts 111897168 # Number of instructions simulated sim_ops 135292215 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -418,7 +418,7 @@ system.cpu.dtb.flush_tlb 64 # Nu system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4350 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 4286 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 1526 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 1789 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -498,7 +498,7 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2992 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2928 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 208966b9b..6bd1b06da 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.832863 # Nu sim_ticks 2832862976500 # Number of ticks simulated final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118022 # Simulator instruction rate (inst/s) -host_op_rate 143150 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2956132692 # Simulator tick rate (ticks/s) -host_mem_usage 626728 # Number of bytes of host memory used -host_seconds 958.30 # Real time elapsed on the host +host_inst_rate 69451 # Simulator instruction rate (inst/s) +host_op_rate 84238 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1739551926 # Simulator tick rate (ticks/s) +host_mem_usage 585172 # Number of bytes of host memory used +host_seconds 1628.50 # Real time elapsed on the host sim_insts 113100501 # Number of instructions simulated sim_ops 137180951 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -410,7 +410,7 @@ system.cpu.checker.dtb.flush_tlb 128 # Nu system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 4283 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 4219 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.dtb.prefetch_faults 1622 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -480,7 +480,7 @@ system.cpu.checker.itb.flush_tlb 128 # Nu system.cpu.checker.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 2976 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_entries 2912 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -588,7 +588,7 @@ system.cpu.dtb.flush_tlb 128 # Nu system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 4253 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 362 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -690,7 +690,7 @@ system.cpu.itb.flush_tlb 128 # Nu system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3089 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3025 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 6bbe66965..a155d5f42 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.825960 # Nu sim_ticks 2825959731500 # Number of ticks simulated final_tick 2825959731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 153141 # Simulator instruction rate (inst/s) -host_op_rate 185771 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3602870624 # Simulator tick rate (ticks/s) -host_mem_usage 666712 # Number of bytes of host memory used -host_seconds 784.36 # Real time elapsed on the host +host_inst_rate 99061 # Simulator instruction rate (inst/s) +host_op_rate 120168 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2330545961 # Simulator tick rate (ticks/s) +host_mem_usage 626024 # Number of bytes of host memory used +host_seconds 1212.57 # Real time elapsed on the host sim_insts 120118276 # Number of instructions simulated sim_ops 145712235 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -485,7 +485,7 @@ system.cpu0.dtb.flush_tlb 66 # Nu system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3541 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3477 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 219 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 2242 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -584,7 +584,7 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2345 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2281 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1729,7 +1729,7 @@ system.cpu1.dtb.flush_tlb 66 # Nu system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2051 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1987 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 47 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 392 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1830,7 +1830,7 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1194 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1130 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 95f1cb47c..5c309f807 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.832863 # Nu sim_ticks 2832862976500 # Number of ticks simulated final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 159277 # Simulator instruction rate (inst/s) -host_op_rate 193189 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3989457396 # Simulator tick rate (ticks/s) -host_mem_usage 626716 # Number of bytes of host memory used -host_seconds 710.09 # Real time elapsed on the host +host_inst_rate 93807 # Simulator instruction rate (inst/s) +host_op_rate 113780 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2349621266 # Simulator tick rate (ticks/s) +host_mem_usage 586720 # Number of bytes of host memory used +host_seconds 1205.67 # Real time elapsed on the host sim_insts 113100501 # Number of instructions simulated sim_ops 137180951 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -444,7 +444,7 @@ system.cpu.dtb.flush_tlb 64 # Nu system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 4253 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 362 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -546,7 +546,7 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3089 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3025 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index a15af7782..3d5089040 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.823729 # Nu sim_ticks 2823728611500 # Number of ticks simulated final_tick 2823728611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 403127 # Simulator instruction rate (inst/s) -host_op_rate 488997 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9263554618 # Simulator tick rate (ticks/s) -host_mem_usage 632872 # Number of bytes of host memory used -host_seconds 304.82 # Real time elapsed on the host +host_inst_rate 236626 # Simulator instruction rate (inst/s) +host_op_rate 287030 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5437492370 # Simulator tick rate (ticks/s) +host_mem_usage 592088 # Number of bytes of host memory used +host_seconds 519.31 # Real time elapsed on the host sim_insts 122881667 # Number of instructions simulated sim_ops 149056790 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -313,12 +313,12 @@ system.physmem.wrPerTurnAround::128-131 5 0.14% 99.94% # Wr system.physmem.wrPerTurnAround::140-143 1 0.03% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 1 0.03% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 3632 # Writes before turning the bus around for reads -system.physmem.totQLat 1343217000 # Total ticks spent queuing -system.physmem.totMemAccLat 3470892000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1343214500 # Total ticks spent queuing +system.physmem.totMemAccLat 3470889500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 567380000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11837.01 # Average queueing delay per DRAM burst +system.physmem.avgQLat 11836.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30587.01 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30586.99 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.57 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.57 # Average system read bandwidth in MiByte/s @@ -340,28 +340,28 @@ system.physmem_0.preEnergy 85919625 # En system.physmem_0.readEnergy 459334200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 228024720 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 179708830080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 71920019610 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1621544120250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1874104093725 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.482603 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2641247036500 # Time in different power states +system.physmem_0.actBackEnergy 71920006785 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1621544131500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1874104092150 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.482602 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2641247054000 # Time in different power states system.physmem_0.memoryStateTime::REF 91875680000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 18345228000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 18345210500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 139988520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 76201125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 425778600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 218570400 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 179708830080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 71085149730 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1620445707000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1872100225455 # Total energy per rank (pJ) +system.physmem_1.actBackEnergy 71085141180 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1620445714500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1872100224405 # Total energy per rank (pJ) system.physmem_1.averagePower 667.494295 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2642466728000 # Time in different power states +system.physmem_1.memoryStateTime::IDLE 2642466740000 # Time in different power states system.physmem_1.memoryStateTime::REF 91875680000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17119309500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17119297500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory @@ -447,7 +447,7 @@ system.cpu0.dtb.flush_tlb 171 # Nu system.cpu0.dtb.flush_tlb_mva 362 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2823 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2759 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 830 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -519,7 +519,7 @@ system.cpu0.itb.flush_tlb 171 # Nu system.cpu0.itb.flush_tlb_mva 362 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1759 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1695 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -610,9 +610,9 @@ system.cpu0.op_class::total 68312506 # Cl system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 833701 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.996712 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 45908569 # Total number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 45908566 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 834213 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.032191 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 55.032187 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 482.062806 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.552141 # Average occupied blocks per requestor @@ -628,14 +628,14 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 60 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 193086189 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 193086189 # Number of data accesses +system.cpu0.dcache.tags.tag_accesses 193086177 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 193086177 # Number of data accesses system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 11466814 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 3604015 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu2.data 4048059 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 6693194 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25812082 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu3.data 6693191 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25812079 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 8805127 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu1.data 2681872 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu2.data 3150720 # number of WriteReq hits @@ -659,13 +659,13 @@ system.cpu0.dcache.StoreCondReq_hits::total 460674 # system.cpu0.dcache.demand_hits::cpu0.data 20271941 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu1.data 6285887 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu2.data 7198779 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 10848839 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 44605446 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu3.data 10848836 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 44605443 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.data 20450256 # number of overall hits system.cpu0.dcache.overall_hits::cpu1.data 6342658 # number of overall hits system.cpu0.dcache.overall_hits::cpu2.data 7266236 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 10934832 # number of overall hits -system.cpu0.dcache.overall_hits::total 44993982 # number of overall hits +system.cpu0.dcache.overall_hits::cpu3.data 10934829 # number of overall hits +system.cpu0.dcache.overall_hits::total 44993979 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 170779 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu1.data 51895 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu2.data 83860 # number of ReadReq misses @@ -701,12 +701,12 @@ system.cpu0.dcache.overall_misses::cpu3.data 1489048 system.cpu0.dcache.overall_misses::total 2139394 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 835936000 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 1210061000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 3349862000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5395859000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 3349856000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5395853000 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1273084500 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 5046790496 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 61121830312 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 67441705308 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 61121825312 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 67441700308 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28644500 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 55618500 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 110733000 # number of LoadLockedReq miss cycles @@ -715,17 +715,17 @@ system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 615000 system.cpu0.dcache.StoreCondReq_miss_latency::total 615000 # number of StoreCondReq miss cycles system.cpu0.dcache.demand_miss_latency::cpu1.data 2109020500 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::cpu2.data 6256851496 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu3.data 64471692312 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 72837564308 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu3.data 64471681312 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 72837553308 # number of demand (read+write) miss cycles system.cpu0.dcache.overall_miss_latency::cpu1.data 2109020500 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::cpu2.data 6256851496 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu3.data 64471692312 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 72837564308 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu3.data 64471681312 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 72837553308 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 11637593 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu1.data 3655910 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu2.data 4131919 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu3.data 6912790 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 26338212 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu3.data 6912787 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 26338209 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 8917442 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu1.data 2716710 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu2.data 3254660 # number of WriteReq accesses(hits+misses) @@ -749,13 +749,13 @@ system.cpu0.dcache.StoreCondReq_accesses::total 460703 system.cpu0.dcache.demand_accesses::cpu0.data 20555035 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu1.data 6372620 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu2.data 7386579 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu3.data 12295162 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 46609396 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu3.data 12295159 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 46609393 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 20787280 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu1.data 6448850 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu2.data 7473366 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu3.data 12423880 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 47133376 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu3.data 12423877 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 47133373 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.014675 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.014195 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.020296 # miss rate for ReadReq accesses @@ -791,12 +791,12 @@ system.cpu0.dcache.overall_miss_rate::cpu3.data 0.119854 system.cpu0.dcache.overall_miss_rate::total 0.045390 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16108.218518 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14429.537324 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15254.658555 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10255.752381 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15254.631232 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10255.740977 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36542.984672 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48554.844102 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 49825.128421 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45635.940309 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 49825.124345 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45635.936926 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12251.710864 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14540.784314 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13724.962816 # average LoadLockedReq miss latency @@ -805,12 +805,12 @@ system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 22777.777778 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21206.896552 # average StoreCondReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24316.240647 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 33316.568136 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 44576.275363 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36346.996835 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 44576.267758 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36346.991346 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19860.446173 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30207.364921 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 43297.255906 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34045.886035 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 43297.248519 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34045.880893 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 335985 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 31302 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 12606 # number of cycles access was blocked @@ -878,16 +878,16 @@ system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 14048 system.cpu0.dcache.overall_mshr_uncacheable_misses::total 32609 # number of overall MSHR uncacheable misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 782633000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1020579500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 1612658500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3415871000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 1612657500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3415870000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238246500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2646664500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 4858846947 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8743757947 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 247386000 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 228071000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 457589000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 933046000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 457588500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 933045500 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8958000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 27255500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 37981000 # number of LoadLockedReq MSHR miss cycles @@ -896,12 +896,12 @@ system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 588000 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 588000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2020879500 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3667244000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 6471505447 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12159628947 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 6471504447 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12159627947 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2268265500 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3895315000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 6929094447 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13092674947 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 6929092947 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13092673447 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 601507000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1484874500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1676185500 # number of ReadReq MSHR uncacheable cycles @@ -938,16 +938,16 @@ system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019204 system.cpu0.dcache.overall_mshr_miss_rate::total 0.010428 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15111.370701 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13547.035946 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14352.220037 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14263.104931 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14352.211137 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14263.100756 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35542.984672 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 47288.043381 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50343.441853 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46677.937588 # average WriteReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12935.215686 # average SoftPFReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14373.014873 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15398.223239 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14418.884253 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15398.206414 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14418.876526 # average SoftPFReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12889.208633 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 18478.305085 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14370.412410 # average LoadLockedReq mshr miss latency @@ -956,12 +956,12 @@ system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 21777.777778 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21777.777778 # average StoreCondReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23327.979083 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27929.203001 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 30982.374541 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28489.492883 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 30982.369753 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28489.490540 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21448.507858 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26467.592561 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 29041.360835 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26637.061177 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 29041.354548 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26637.058126 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175673.773364 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 208696.345748 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215171.437741 # average ReadReq mshr uncacheable latency @@ -973,14 +973,14 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115384.311080 system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 1971000 # number of replacements system.cpu0.icache.tags.tagsinuse 511.470268 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 93100004 # Total number of references to valid blocks. +system.cpu0.icache.tags.total_refs 93100003 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 1971512 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 47.222641 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 12494493500 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 436.802699 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_blocks::cpu1.inst 12.961360 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_blocks::cpu2.inst 25.140810 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 36.565400 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu3.inst 36.565399 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.853130 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu1.inst 0.025315 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu2.inst 0.049103 # Average percentage of cache occupancy @@ -992,24 +992,24 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 196 system.cpu0.icache.tags.age_task_id_blocks_1024::2 260 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 97085384 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 97085384 # Number of data accesses +system.cpu0.icache.tags.tag_accesses 97085383 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 97085383 # Number of data accesses system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 56179314 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 17648655 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu2.inst 9977787 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu3.inst 9294248 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 93100004 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu3.inst 9294247 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 93100003 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 56179314 # number of demand (read+write) hits system.cpu0.icache.demand_hits::cpu1.inst 17648655 # number of demand (read+write) hits system.cpu0.icache.demand_hits::cpu2.inst 9977787 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu3.inst 9294248 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 93100004 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu3.inst 9294247 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 93100003 # number of demand (read+write) hits system.cpu0.icache.overall_hits::cpu0.inst 56179314 # number of overall hits system.cpu0.icache.overall_hits::cpu1.inst 17648655 # number of overall hits system.cpu0.icache.overall_hits::cpu2.inst 9977787 # number of overall hits -system.cpu0.icache.overall_hits::cpu3.inst 9294248 # number of overall hits -system.cpu0.icache.overall_hits::total 93100004 # number of overall hits +system.cpu0.icache.overall_hits::cpu3.inst 9294247 # number of overall hits +system.cpu0.icache.overall_hits::total 93100003 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 743108 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::cpu1.inst 211772 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::cpu2.inst 473406 # number of ReadReq misses @@ -1027,31 +1027,31 @@ system.cpu0.icache.overall_misses::cpu3.inst 585545 system.cpu0.icache.overall_misses::total 2013831 # number of overall misses system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2898883500 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6546923000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 7956020485 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 17401826985 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 7956012985 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 17401819485 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency::cpu1.inst 2898883500 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::cpu2.inst 6546923000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu3.inst 7956020485 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 17401826985 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu3.inst 7956012985 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 17401819485 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency::cpu1.inst 2898883500 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::cpu2.inst 6546923000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu3.inst 7956020485 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 17401826985 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu3.inst 7956012985 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 17401819485 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 56922422 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::cpu1.inst 17860427 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::cpu2.inst 10451193 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu3.inst 9879793 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 95113835 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu3.inst 9879792 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 95113834 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 56922422 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::cpu1.inst 17860427 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::cpu2.inst 10451193 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu3.inst 9879793 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 95113835 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu3.inst 9879792 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 95113834 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 56922422 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::cpu1.inst 17860427 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::cpu2.inst 10451193 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu3.inst 9879793 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 95113835 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu3.inst 9879792 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 95113834 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013055 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011857 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.045297 # miss rate for ReadReq accesses @@ -1069,16 +1069,16 @@ system.cpu0.icache.overall_miss_rate::cpu3.inst 0.059267 system.cpu0.icache.overall_miss_rate::total 0.021173 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13688.700584 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13829.404359 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13587.376692 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8641.155581 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13587.363883 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8641.151857 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13688.700584 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13829.404359 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13587.376692 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8641.155581 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13587.363883 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8641.151857 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13688.700584 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13829.404359 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13587.376692 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8641.155581 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13587.363883 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8641.151857 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 4652 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 239 # number of cycles access was blocked @@ -1107,16 +1107,16 @@ system.cpu0.icache.overall_mshr_misses::cpu3.inst 543263 system.cpu0.icache.overall_mshr_misses::total 1228441 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2687111500 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 6073517000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 7028549489 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 15789177989 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 7028544489 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 15789172989 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2687111500 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 6073517000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 7028549489 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 15789177989 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 7028544489 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 15789172989 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2687111500 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6073517000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 7028549489 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 15789177989 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 7028544489 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 15789172989 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011857 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.045297 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.054987 # mshr miss rate for ReadReq accesses @@ -1131,16 +1131,16 @@ system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.054987 system.cpu0.icache.overall_mshr_miss_rate::total 0.012915 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12688.700584 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12829.404359 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12937.655406 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12853.021015 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12937.646203 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12853.016945 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12688.700584 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12829.404359 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12937.655406 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12853.021015 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12937.646203 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12853.016945 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12688.700584 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12829.404359 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12937.655406 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12853.021015 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12937.646203 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12853.016945 # average overall mshr miss latency system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1216,7 +1216,7 @@ system.cpu1.dtb.flush_tlb 154 # Nu system.cpu1.dtb.flush_tlb_mva 179 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1302 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1245 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 243 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1300,7 +1300,7 @@ system.cpu1.itb.flush_tlb 154 # Nu system.cpu1.itb.flush_tlb_mva 179 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 792 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 732 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1469,7 +1469,7 @@ system.cpu2.dtb.flush_tlb 152 # Nu system.cpu2.dtb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 1478 # Number of entries that have been flushed from TLB +system.cpu2.dtb.flush_entries 1416 # Number of entries that have been flushed from TLB system.cpu2.dtb.align_faults 270 # Number of TLB faults due to alignment restrictions system.cpu2.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1552,7 +1552,7 @@ system.cpu2.itb.flush_tlb 152 # Nu system.cpu2.itb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 885 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 822 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1629,13 +1629,13 @@ system.cpu2.kern.inst.arm 0 # nu system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.tickCycles 41357618 # Number of cycles that the object actually ticked system.cpu2.idleCycles 100616145 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 13553669 # Number of BP lookups -system.cpu3.branchPred.condPredicted 7461566 # Number of conditional branches predicted +system.cpu3.branchPred.lookups 13553665 # Number of BP lookups +system.cpu3.branchPred.condPredicted 7461562 # Number of conditional branches predicted system.cpu3.branchPred.condIncorrect 296736 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 8400668 # Number of BTB lookups +system.cpu3.branchPred.BTBLookups 8400664 # Number of BTB lookups system.cpu3.branchPred.BTBHits 4438644 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 52.836798 # BTB Hit Percentage +system.cpu3.branchPred.BTBHitPct 52.836823 # BTB Hit Percentage system.cpu3.branchPred.usedRAS 3086842 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 16263 # Number of incorrect RAS predictions. system.cpu3.branchPred.indirectLookups 2014355 # Number of indirect predictor lookups. @@ -1706,7 +1706,7 @@ system.cpu3.dtb.walker.walkCompletionTime::65536-73727 1 0.02% system.cpu3.dtb.walker.walkCompletionTime::81920-90111 3 0.05% 100.00% # Table walker service (enqueue to completion) latency system.cpu3.dtb.walker.walkCompletionTime::total 6403 # Table walker service (enqueue to completion) latency system.cpu3.dtb.walker.walksPending::samples -8551346564 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 0.449587 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 0.449586 # Table walker pending requests distribution system.cpu3.dtb.walker.walksPending::stdev 0.363024 # Table walker pending requests distribution system.cpu3.dtb.walker.walksPending::0-1 -8598250064 100.55% 100.55% # Table walker pending requests distribution system.cpu3.dtb.walker.walksPending::2-3 33569000 -0.39% 100.16% # Table walker pending requests distribution @@ -1737,25 +1737,25 @@ system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2561 system.cpu3.dtb.walker.walkRequestOrigin::total 36842 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 7461875 # DTB read hits +system.cpu3.dtb.read_hits 7461865 # DTB read hits system.cpu3.dtb.read_misses 28710 # DTB read misses -system.cpu3.dtb.write_hits 5703324 # DTB write hits +system.cpu3.dtb.write_hits 5703323 # DTB write hits system.cpu3.dtb.write_misses 5571 # DTB write misses system.cpu3.dtb.flush_tlb 157 # Number of times complete TLB was flushed system.cpu3.dtb.flush_tlb_mva 225 # Number of times TLB was flushed by MVA system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 1703 # Number of entries that have been flushed from TLB +system.cpu3.dtb.flush_entries 1649 # Number of entries that have been flushed from TLB system.cpu3.dtb.align_faults 376 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 690 # Number of TLB faults due to prefetch +system.cpu3.dtb.prefetch_faults 696 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 330 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 7490585 # DTB read accesses -system.cpu3.dtb.write_accesses 5708895 # DTB write accesses +system.cpu3.dtb.perms_faults 324 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 7490575 # DTB read accesses +system.cpu3.dtb.write_accesses 5708894 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 13165199 # DTB hits +system.cpu3.dtb.hits 13165188 # DTB hits system.cpu3.dtb.misses 34281 # DTB misses -system.cpu3.dtb.accesses 13199480 # DTB accesses +system.cpu3.dtb.accesses 13199469 # DTB accesses system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1787,34 +1787,34 @@ system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DT system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.cpu3.itb.walker.walks 4255 # Table walker walks requested -system.cpu3.itb.walker.walksShort 4255 # Table walker walks initiated with short descriptors -system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1348 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walks 4271 # Table walker walks requested +system.cpu3.itb.walker.walksShort 4271 # Table walker walks initiated with short descriptors +system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1364 # Level at which table walker walks with short descriptors terminate system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2480 # Level at which table walker walks with short descriptors terminate system.cpu3.itb.walker.walksSquashedBefore 427 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 3828 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1433.646813 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 5723.775049 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-8191 3573 93.34% 93.34% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::8192-16383 172 4.49% 97.83% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::16384-24575 42 1.10% 98.93% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::24576-32767 19 0.50% 99.43% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-40959 8 0.21% 99.63% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::samples 3844 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1432.232050 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 5712.962295 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-8191 3589 93.37% 93.37% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::8192-16383 172 4.47% 97.84% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::16384-24575 42 1.09% 98.93% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::24576-32767 19 0.49% 99.43% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-40959 8 0.21% 99.64% # Table walker wait (enqueue to first request) latency system.cpu3.itb.walker.walkWaitTime::40960-49151 2 0.05% 99.69% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::49152-57343 3 0.08% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::49152-57343 3 0.08% 99.77% # Table walker wait (enqueue to first request) latency system.cpu3.itb.walker.walkWaitTime::57344-65535 3 0.08% 99.84% # Table walker wait (enqueue to first request) latency system.cpu3.itb.walker.walkWaitTime::65536-73727 3 0.08% 99.92% # Table walker wait (enqueue to first request) latency system.cpu3.itb.walker.walkWaitTime::73728-81919 1 0.03% 99.95% # Table walker wait (enqueue to first request) latency system.cpu3.itb.walker.walkWaitTime::81920-90111 1 0.03% 99.97% # Table walker wait (enqueue to first request) latency system.cpu3.itb.walker.walkWaitTime::98304-106495 1 0.03% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 3828 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 3844 # Table walker wait (enqueue to first request) latency system.cpu3.itb.walker.walkCompletionTime::samples 1607 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 11553.827007 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 9422.694802 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 7714.919558 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 11557.249533 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 9424.986938 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 7716.115539 # Table walker service (enqueue to completion) latency system.cpu3.itb.walker.walkCompletionTime::0-8191 693 43.12% 43.12% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::8192-16383 629 39.14% 82.27% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::16384-24575 247 15.37% 97.64% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::8192-16383 628 39.08% 82.20% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::16384-24575 248 15.43% 97.64% # Table walker service (enqueue to completion) latency system.cpu3.itb.walker.walkCompletionTime::24576-32767 18 1.12% 98.76% # Table walker service (enqueue to completion) latency system.cpu3.itb.walker.walkCompletionTime::32768-40959 11 0.68% 99.44% # Table walker service (enqueue to completion) latency system.cpu3.itb.walker.walkCompletionTime::40960-49151 4 0.25% 99.69% # Table walker service (enqueue to completion) latency @@ -1836,14 +1836,14 @@ system.cpu3.itb.walker.walkPageSizes::4K 845 71.61% 71.61% # Ta system.cpu3.itb.walker.walkPageSizes::1M 335 28.39% 100.00% # Table walker page sizes translated system.cpu3.itb.walker.walkPageSizes::total 1180 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4255 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4255 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4271 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4271 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1180 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1180 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 5435 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 9881127 # ITB inst hits -system.cpu3.itb.inst_misses 4255 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin::total 5451 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 9881110 # ITB inst hits +system.cpu3.itb.inst_misses 4271 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits @@ -1852,17 +1852,17 @@ system.cpu3.itb.flush_tlb 157 # Nu system.cpu3.itb.flush_tlb_mva 225 # Number of times TLB was flushed by MVA system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 1190 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_entries 1130 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 704 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 688 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 9885382 # ITB inst accesses -system.cpu3.itb.hits 9881127 # DTB hits -system.cpu3.itb.misses 4255 # DTB misses -system.cpu3.itb.accesses 9885382 # DTB accesses +system.cpu3.itb.inst_accesses 9885381 # ITB inst accesses +system.cpu3.itb.hits 9881110 # DTB hits +system.cpu3.itb.misses 4271 # DTB misses +system.cpu3.itb.accesses 9885381 # DTB accesses system.cpu3.numPwrStateTransitions 1752 # Number of power state transitions system.cpu3.pwrStateClkGateDist::samples 876 # Distribution of time spent in the clock gated state system.cpu3.pwrStateClkGateDist::mean 24094343.119863 # Distribution of time spent in the clock gated state @@ -1877,26 +1877,26 @@ system.cpu3.pwrStateResidencyTicks::CLK_GATED 21106644573 system.cpu3.numCycles 55785273 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 20908003 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 53885921 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 13553669 # Number of branches that fetch encountered +system.cpu3.fetch.icacheStallCycles 20908000 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 53885903 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 13553665 # Number of branches that fetch encountered system.cpu3.fetch.predictedBranches 9478152 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 32386359 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.Cycles 32386357 # Number of cycles fetch has run and was not squashing or blocked system.cpu3.fetch.SquashCycles 1568366 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 62721 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.TlbCycles 62842 # Number of cycles fetch has spent waiting for tlb system.cpu3.fetch.MiscStallCycles 789 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.PendingDrainCycles 205 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 111844 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingTrapStallCycles 111743 # Number of stall cycles due to pending traps system.cpu3.fetch.PendingQuiesceStallCycles 71140 # Number of stall cycles due to pending quiesce instructions system.cpu3.fetch.IcacheWaitRetryStallCycles 397 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 9879794 # Number of cache lines fetched +system.cpu3.fetch.CacheLines 9879793 # Number of cache lines fetched system.cpu3.fetch.IcacheSquashes 204446 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 2262 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 54325621 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.ItlbSquashes 2275 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 54325636 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::mean 1.196451 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.331638 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.331637 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 39861207 73.37% 73.37% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 39861224 73.37% 73.37% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::1 1851185 3.41% 76.78% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::2 1193872 2.20% 78.98% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::3 3684209 6.78% 85.76% # Number of instructions fetched each cycle (Total) @@ -1904,70 +1904,70 @@ system.cpu3.fetch.rateDist::4 942616 1.74% 87.50% # Nu system.cpu3.fetch.rateDist::5 608186 1.12% 88.62% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::6 2968602 5.46% 94.08% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::7 642558 1.18% 95.26% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 2573186 4.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 2573184 4.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 54325621 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::total 54325636 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.branchRate 0.242961 # Number of branch fetches per cycle system.cpu3.fetch.rate 0.965952 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 14640830 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 30019697 # Number of cycles decode is blocked +system.cpu3.decode.IdleCycles 14640847 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 30019695 # Number of cycles decode is blocked system.cpu3.decode.RunCycles 7950688 # Number of cycles decode is running system.cpu3.decode.UnblockCycles 1013386 # Number of cycles decode is unblocking system.cpu3.decode.SquashCycles 700819 # Number of cycles decode is squashing system.cpu3.decode.BranchResolved 1055619 # Number of times decode resolved a branch system.cpu3.decode.BranchMispred 84442 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 46804919 # Number of instructions handled by decode +system.cpu3.decode.DecodedInsts 46804905 # Number of instructions handled by decode system.cpu3.decode.SquashedInsts 276831 # Number of squashed instructions handled by decode system.cpu3.rename.SquashCycles 700819 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 15165685 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 3026849 # Number of cycles rename is blocking +system.cpu3.rename.IdleCycles 15165703 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 3026847 # Number of cycles rename is blocking system.cpu3.rename.serializeStallCycles 21377967 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 8430789 # Number of cycles rename is running +system.cpu3.rename.RunCycles 8430788 # Number of cycles rename is running system.cpu3.rename.UnblockCycles 5623288 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 44934032 # Number of instructions processed by rename +system.cpu3.rename.RenamedInsts 44934013 # Number of instructions processed by rename system.cpu3.rename.ROBFullEvents 688 # Number of times rename has blocked due to ROB full system.cpu3.rename.IQFullEvents 1185922 # Number of times rename has blocked due to IQ full system.cpu3.rename.LQFullEvents 108960 # Number of times rename has blocked due to LQ full system.cpu3.rename.SQFullEvents 3941702 # Number of times rename has blocked due to SQ full -system.cpu3.rename.RenamedOperands 46859897 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 206319121 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 50493322 # Number of integer rename lookups +system.cpu3.rename.RenamedOperands 46859874 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 206319060 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 50493308 # Number of integer rename lookups system.cpu3.rename.fp_rename_lookups 4028 # Number of floating rename lookups system.cpu3.rename.CommittedMaps 39227152 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 7632745 # Number of HB maps that are undone due to squashing +system.cpu3.rename.UndoneMaps 7632722 # Number of HB maps that are undone due to squashing system.cpu3.rename.serializingInsts 719514 # count of serializing insts renamed system.cpu3.rename.tempSerializingInsts 667644 # count of temporary serializing insts renamed system.cpu3.rename.skidInsts 5723010 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 7961886 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 6281204 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 1151663 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 1548732 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 43283754 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.memDep0.insertedLoads 7961881 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 6281202 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 1151665 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 1548744 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 43283738 # Number of instructions added to the IQ (excludes non-spec) system.cpu3.iq.iqNonSpecInstsAdded 518690 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 41211343 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 55539 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 6082671 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 14072351 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqInstsIssued 41211324 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 55538 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 6082655 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 14072346 # Number of squashed operands that are examined and possibly removed from graph system.cpu3.iq.iqSquashedNonSpecRemoved 54569 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 54325621 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.758599 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.457347 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::samples 54325636 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.758598 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.457345 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 38109275 70.15% 70.15% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 38109289 70.15% 70.15% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::1 5329887 9.81% 79.96% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 4096389 7.54% 87.50% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 3334773 6.14% 93.64% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 1373143 2.53% 96.17% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 820036 1.51% 97.68% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 4096392 7.54% 87.50% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 3334775 6.14% 93.64% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 1373146 2.53% 96.17% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 820032 1.51% 97.68% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::6 873869 1.61% 99.29% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 257599 0.47% 99.76% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 130650 0.24% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 257598 0.47% 99.76% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 130648 0.24% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 54325621 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 54325636 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IntAlu 64574 10.28% 10.28% # attempts to use FU when none available system.cpu3.iq.fu_full::IntMult 0 0.00% 10.28% # attempts to use FU when none available @@ -1999,11 +1999,11 @@ system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 10.28% # at system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.28% # attempts to use FU when none available system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 10.28% # attempts to use FU when none available system.cpu3.iq.fu_full::MemRead 290075 46.19% 56.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 273390 43.53% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 273387 43.53% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 62 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 27512271 66.76% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 27512260 66.76% 66.76% # Type of FU issued system.cpu3.iq.FU_type_0::IntMult 31067 0.08% 66.83% # Type of FU issued system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.83% # Type of FU issued system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.83% # Type of FU issued @@ -2032,40 +2032,40 @@ system.cpu3.iq.FU_type_0::SimdFloatMisc 2328 0.01% 66.84% # Ty system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.84% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 66.84% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 7676586 18.63% 85.47% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 5989019 14.53% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 7676579 18.63% 85.47% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 5989018 14.53% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 41211343 # Type of FU issued -system.cpu3.iq.rate 0.738750 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 628039 # FU busy when requested +system.cpu3.iq.FU_type_0::total 41211324 # Type of FU issued +system.cpu3.iq.rate 0.738749 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 628036 # FU busy when requested system.cpu3.iq.fu_busy_rate 0.015239 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 137423296 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 49907895 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 40057354 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.int_inst_queue_reads 137423269 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 49907863 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 40057337 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 8589 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 4965 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 3611 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 41834646 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 41834624 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 4674 # Number of floating point alu accesses system.cpu3.iew.lsq.thread0.forwLoads 172531 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 1192076 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 1192071 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 1205 # Number of memory responses ignored because the instruction is squashed system.cpu3.iew.lsq.thread0.memOrderViolation 28350 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 578137 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedStores 578135 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 104077 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.rescheduledLoads 104076 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 43928 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu3.iew.iewSquashCycles 700819 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 2631103 # Number of cycles IEW is blocking +system.cpu3.iew.iewBlockCycles 2631101 # Number of cycles IEW is blocking system.cpu3.iew.iewUnblockCycles 281724 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 43863625 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispatchedInsts 43863606 # Number of instructions dispatched to IQ system.cpu3.iew.iewDispSquashedInsts 65733 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 7961886 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 6281204 # Number of dispatched store instructions +system.cpu3.iew.iewDispLoadInsts 7961881 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 6281202 # Number of dispatched store instructions system.cpu3.iew.iewDispNonSpecInsts 267636 # Number of dispatched non-speculative instructions system.cpu3.iew.iewIQFullEvents 25569 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 250025 # Number of times the LSQ has become full, causing a stall @@ -2073,41 +2073,41 @@ system.cpu3.iew.memOrderViolationEvents 28350 # Nu system.cpu3.iew.predictedTakenIncorrect 127807 # Number of branches that were predicted taken incorrectly system.cpu3.iew.predictedNotTakenIncorrect 129932 # Number of branches that were predicted not taken incorrectly system.cpu3.iew.branchMispredicts 257739 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 40889959 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 7546719 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 287191 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewExecutedInsts 40889941 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 7546714 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 287190 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 61181 # number of nop insts executed -system.cpu3.iew.exec_refs 13479054 # number of memory reference insts executed -system.cpu3.iew.exec_branches 7536416 # Number of branches executed -system.cpu3.iew.exec_stores 5932335 # Number of stores executed +system.cpu3.iew.exec_nop 61178 # number of nop insts executed +system.cpu3.iew.exec_refs 13479048 # number of memory reference insts executed +system.cpu3.iew.exec_branches 7536415 # Number of branches executed +system.cpu3.iew.exec_stores 5932334 # Number of stores executed system.cpu3.iew.exec_rate 0.732988 # Inst execution rate -system.cpu3.iew.wb_sent 40598245 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 40060965 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 21086862 # num instructions producing a value -system.cpu3.iew.wb_consumers 37255215 # num instructions consuming a value +system.cpu3.iew.wb_sent 40598229 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 40060948 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 21086851 # num instructions producing a value +system.cpu3.iew.wb_consumers 37255196 # num instructions consuming a value system.cpu3.iew.wb_rate 0.718128 # insts written-back per cycle system.cpu3.iew.wb_fanout 0.566011 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 6097187 # The number of squashed insts skipped by commit +system.cpu3.commit.commitSquashedInsts 6097168 # The number of squashed insts skipped by commit system.cpu3.commit.commitNonSpecStalls 464121 # The number of times commit has been forced to stall to communicate backwards system.cpu3.commit.branchMispredicts 213352 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 53027988 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.712050 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::samples 53028005 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.712049 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::stdev 1.609623 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 38640336 72.87% 72.87% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 38640353 72.87% 72.87% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::1 6301176 11.88% 84.75% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 3204029 6.04% 90.79% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 3204030 6.04% 90.79% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::3 1405492 2.65% 93.44% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 791559 1.49% 94.94% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 551412 1.04% 95.98% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 791558 1.49% 94.94% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 551411 1.04% 95.98% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::6 959183 1.81% 97.78% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 243958 0.46% 98.24% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 243959 0.46% 98.24% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::8 930843 1.76% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 53027988 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::total 53028005 # Number of insts commited each cycle system.cpu3.commit.committedInsts 30988188 # Number of instructions committed system.cpu3.commit.committedOps 37758554 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed @@ -2154,10 +2154,10 @@ system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::total 37758554 # Class of committed instruction system.cpu3.commit.bw_lim_events 930843 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 90355965 # The number of ROB reads -system.cpu3.rob.rob_writes 89008997 # The number of ROB writes -system.cpu3.timesIdled 227180 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1459652 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.rob.rob_reads 90355963 # The number of ROB reads +system.cpu3.rob.rob_writes 89008957 # The number of ROB writes +system.cpu3.timesIdled 227178 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1459637 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu3.quiesceCycles 5161855344 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu3.committedInsts 30949407 # Number of Instructions Simulated system.cpu3.committedOps 37719773 # Number of Ops (including micro ops) Simulated @@ -2165,13 +2165,13 @@ system.cpu3.cpi 1.802467 # CP system.cpu3.cpi_total 1.802467 # CPI: Total CPI of All Threads system.cpu3.ipc 0.554795 # IPC: Instructions Per Cycle system.cpu3.ipc_total 0.554795 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 44810806 # number of integer regfile reads -system.cpu3.int_regfile_writes 25112765 # number of integer regfile writes +system.cpu3.int_regfile_reads 44810788 # number of integer regfile reads +system.cpu3.int_regfile_writes 25112754 # number of integer regfile writes system.cpu3.fp_regfile_reads 14550 # number of floating regfile reads system.cpu3.fp_regfile_writes 12084 # number of floating regfile writes -system.cpu3.cc_regfile_reads 144202792 # number of cc regfile reads -system.cpu3.cc_regfile_writes 15932581 # number of cc regfile writes -system.cpu3.misc_regfile_reads 98044086 # number of misc regfile reads +system.cpu3.cc_regfile_reads 144202732 # number of cc regfile reads +system.cpu3.cc_regfile_writes 15932572 # number of cc regfile writes +system.cpu3.misc_regfile_reads 98044257 # number of misc regfile reads system.cpu3.misc_regfile_writes 343753 # number of misc regfile writes system.iobus.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30152 # Transaction distribution @@ -2351,9 +2351,9 @@ system.iocache.overall_avg_mshr_miss_latency::total 70054.816134 system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 100820 # number of replacements system.l2c.tags.tagsinuse 65104.875407 # Cycle average of tags in use -system.l2c.tags.total_refs 5136845 # Total number of references to valid blocks. +system.l2c.tags.total_refs 5136861 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 165990 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 30.946714 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 30.946810 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 79348480000 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 49045.638268 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.902700 # Average occupied blocks per requestor @@ -2398,8 +2398,8 @@ system.l2c.tags.age_task_id_blocks_1024::3 8177 # system.l2c.tags.age_task_id_blocks_1024::4 54718 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000900 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.993515 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 45392022 # Number of tag accesses -system.l2c.tags.data_accesses 45392022 # Number of data accesses +system.l2c.tags.tag_accesses 45392150 # Number of tag accesses +system.l2c.tags.data_accesses 45392150 # Number of data accesses system.l2c.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.l2c.ReadReq_hits::cpu0.dtb.walker 4238 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 2128 # number of ReadReq hits @@ -2408,8 +2408,8 @@ system.l2c.ReadReq_hits::cpu1.itb.walker 869 # nu system.l2c.ReadReq_hits::cpu2.dtb.walker 12508 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.itb.walker 1155 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.dtb.walker 20749 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.itb.walker 3757 # number of ReadReq hits -system.l2c.ReadReq_hits::total 46942 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.itb.walker 3773 # number of ReadReq hits +system.l2c.ReadReq_hits::total 46958 # number of ReadReq hits system.l2c.WritebackDirty_hits::writebacks 692418 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 692418 # number of WritebackDirty hits system.l2c.WritebackClean_hits::writebacks 1933833 # number of WritebackClean hits @@ -2450,10 +2450,10 @@ system.l2c.demand_hits::cpu2.itb.walker 1155 # nu system.l2c.demand_hits::cpu2.inst 468084 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 116508 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.dtb.walker 20749 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.itb.walker 3757 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.itb.walker 3773 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.inst 537076 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 184948 # number of demand (read+write) hits -system.l2c.demand_hits::total 2680059 # number of demand (read+write) hits +system.l2c.demand_hits::total 2680075 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 4238 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 2128 # number of overall hits system.l2c.overall_hits::cpu0.inst 735257 # number of overall hits @@ -2467,10 +2467,10 @@ system.l2c.overall_hits::cpu2.itb.walker 1155 # nu system.l2c.overall_hits::cpu2.inst 468084 # number of overall hits system.l2c.overall_hits::cpu2.data 116508 # number of overall hits system.l2c.overall_hits::cpu3.dtb.walker 20749 # number of overall hits -system.l2c.overall_hits::cpu3.itb.walker 3757 # number of overall hits +system.l2c.overall_hits::cpu3.itb.walker 3773 # number of overall hits system.l2c.overall_hits::cpu3.inst 537076 # number of overall hits system.l2c.overall_hits::cpu3.data 184948 # number of overall hits -system.l2c.overall_hits::total 2680059 # number of overall hits +system.l2c.overall_hits::total 2680075 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses @@ -2552,12 +2552,12 @@ system.l2c.ReadExReq_miss_latency::cpu3.data 4215756000 system.l2c.ReadExReq_miss_latency::total 7427120500 # number of ReadExReq miss cycles system.l2c.ReadCleanReq_miss_latency::cpu1.inst 158684500 # number of ReadCleanReq miss cycles system.l2c.ReadCleanReq_miss_latency::cpu2.inst 437741000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu3.inst 503851499 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1100276999 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu3.inst 503847999 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1100273499 # number of ReadCleanReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.data 202807500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu2.data 178029000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3.data 392889000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 773725500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3.data 392888000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 773724500 # number of ReadSharedReq miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 97500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.inst 158684500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 1138873000 # number of demand (read+write) miss cycles @@ -2567,9 +2567,9 @@ system.l2c.demand_miss_latency::cpu2.inst 437741000 # n system.l2c.demand_miss_latency::cpu2.data 2453328000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu3.dtb.walker 6041500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu3.itb.walker 84000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 503851499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 4608645000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9309801999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 503847999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 4608644000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9309797499 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 97500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.inst 158684500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 1138873000 # number of overall miss cycles @@ -2579,9 +2579,9 @@ system.l2c.overall_miss_latency::cpu2.inst 437741000 # system.l2c.overall_miss_latency::cpu2.data 2453328000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu3.dtb.walker 6041500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu3.itb.walker 84000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 503851499 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 4608645000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9309801999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 503847999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 4608644000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9309797499 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 4243 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 2130 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 1539 # number of ReadReq accesses(hits+misses) @@ -2589,8 +2589,8 @@ system.l2c.ReadReq_accesses::cpu1.itb.walker 869 system.l2c.ReadReq_accesses::cpu2.dtb.walker 12536 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.itb.walker 1156 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.dtb.walker 20819 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.itb.walker 3758 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 47050 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.itb.walker 3774 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 47066 # number of ReadReq accesses(hits+misses) system.l2c.WritebackDirty_accesses::writebacks 692418 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackDirty_accesses::total 692418 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackClean_accesses::writebacks 1933833 # number of WritebackClean accesses(hits+misses) @@ -2631,10 +2631,10 @@ system.l2c.demand_accesses::cpu2.itb.walker 1156 # system.l2c.demand_accesses::cpu2.inst 473401 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.data 148206 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.dtb.walker 20819 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.itb.walker 3758 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.itb.walker 3774 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.inst 543125 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.data 240467 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2852690 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2852706 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 4243 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 2130 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.inst 743104 # number of overall (read+write) accesses @@ -2648,17 +2648,17 @@ system.l2c.overall_accesses::cpu2.itb.walker 1156 system.l2c.overall_accesses::cpu2.inst 473401 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.data 148206 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.dtb.walker 20819 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.itb.walker 3758 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.itb.walker 3774 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.inst 543125 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 240467 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2852690 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2852706 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001178 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000939 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000650 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.002234 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000865 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.dtb.walker 0.003362 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.itb.walker 0.000266 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.itb.walker 0.000265 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.002295 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.988382 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989605 # miss rate for UpgradeReq accesses @@ -2695,7 +2695,7 @@ system.l2c.demand_miss_rate::cpu2.itb.walker 0.000865 system.l2c.demand_miss_rate::cpu2.inst 0.011231 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.213878 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.dtb.walker 0.003362 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.itb.walker 0.000266 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.itb.walker 0.000265 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.inst 0.011137 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.230880 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.060515 # miss rate for demand accesses @@ -2711,7 +2711,7 @@ system.l2c.overall_miss_rate::cpu2.itb.walker 0.000865 system.l2c.overall_miss_rate::cpu2.inst 0.011231 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.data 0.213878 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.dtb.walker 0.003362 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.itb.walker 0.000266 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.itb.walker 0.000265 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.inst 0.011137 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.230880 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.060515 # miss rate for overall accesses @@ -2733,12 +2733,12 @@ system.l2c.ReadExReq_avg_miss_latency::cpu3.data 82527.572774 system.l2c.ReadExReq_avg_miss_latency::total 54101.590898 # average ReadExReq miss latency system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82691.245440 # average ReadCleanReq miss latency system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 82328.568742 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 83295.007274 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 52066.865370 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 83294.428666 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 52066.699744 # average ReadCleanReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 84047.865727 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 82573.747681 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 88568.304779 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 54835.258682 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 88568.079351 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 54835.187810 # average ReadSharedReq miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 97500 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 82691.245440 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 79491.379912 # average overall miss latency @@ -2748,9 +2748,9 @@ system.l2c.demand_avg_miss_latency::cpu2.inst 82328.568742 system.l2c.demand_avg_miss_latency::cpu2.data 77396.933560 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 86307.142857 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3.itb.walker 84000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 83295.007274 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 83010.230732 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 53928.911951 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 83294.428666 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 83010.212720 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 53928.885884 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 97500 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 82691.245440 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 79491.379912 # average overall miss latency @@ -2760,9 +2760,9 @@ system.l2c.overall_avg_miss_latency::cpu2.inst 82328.568742 system.l2c.overall_avg_miss_latency::cpu2.data 77396.933560 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 86307.142857 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.itb.walker 84000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 83295.007274 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 83010.230732 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 53928.911951 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 83294.428666 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 83010.212720 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 53928.885884 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2865,12 +2865,12 @@ system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 3704926000 system.l2c.ReadExReq_mshr_miss_latency::total 6501730500 # number of ReadExReq MSHR miss cycles system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 139494500 # number of ReadCleanReq MSHR miss cycles system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 384461500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 443095000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 967051000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 443091500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 967047500 # number of ReadCleanReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 178677500 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 155184000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 345817500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 679679000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 345816500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 679678000 # number of ReadSharedReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 87500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 139494500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 995603000 # number of demand (read+write) MSHR miss cycles @@ -2880,9 +2880,9 @@ system.l2c.demand_mshr_miss_latency::cpu2.inst 384461500 system.l2c.demand_mshr_miss_latency::cpu2.data 2135063000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker 5341500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.itb.walker 74000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 443095000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 4050743500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 8156129500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 443091500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 4050742500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 8156125000 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 87500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 139494500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 995603000 # number of overall MSHR miss cycles @@ -2892,9 +2892,9 @@ system.l2c.overall_mshr_miss_latency::cpu2.inst 384461500 system.l2c.overall_mshr_miss_latency::cpu2.data 2135063000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker 5341500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.itb.walker 74000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 443095000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 4050743500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 8156129500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 443091500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 4050742500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 8156125000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 558688000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1395919500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 1578780500 # number of ReadReq MSHR uncacheable cycles @@ -2907,8 +2907,8 @@ system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000650 system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.002234 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000865 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003362 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker 0.000266 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.002147 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker 0.000265 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.002146 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989605 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.981900 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.957143 # mshr miss rate for UpgradeReq accesses @@ -2935,7 +2935,7 @@ system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000865 system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011223 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.213736 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003362 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.000266 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.000265 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.inst 0.011128 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.230693 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.040262 # mshr miss rate for demand accesses @@ -2947,7 +2947,7 @@ system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000865 system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011223 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.213736 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003362 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.000266 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.000265 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.inst 0.011128 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.230693 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.040262 # mshr miss rate for overall accesses @@ -2969,12 +2969,12 @@ system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 72527.572774 system.l2c.ReadExReq_avg_mshr_miss_latency::total 70259.355515 # average ReadExReq mshr miss latency system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72691.245440 # average ReadCleanReq mshr miss latency system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72362.412949 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 73311.548643 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72842.045797 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 73310.969557 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72841.782163 # average ReadCleanReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74047.865727 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72685.714286 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 78755.978137 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76035.238841 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 78755.750399 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76035.126972 # average ReadSharedReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 87500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72691.245440 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69491.379912 # average overall mshr miss latency @@ -2984,9 +2984,9 @@ system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72362.412949 system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67401.048079 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 76307.142857 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 74000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 73311.548643 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 73020.577207 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 71012.402595 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 73310.969557 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 73020.559181 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 71012.363415 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 87500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72691.245440 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69491.379912 # average overall mshr miss latency @@ -2996,9 +2996,9 @@ system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72362.412949 system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67401.048079 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 76307.142857 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 74000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73311.548643 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 73020.577207 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 71012.402595 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73310.969557 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 73020.559181 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 71012.363415 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163168.224299 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 196193.886156 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202667.586650 # average ReadReq mshr uncacheable latency @@ -3142,8 +3142,8 @@ system.toL2Bus.snoop_filter.tot_snoops 306 # To system.toL2Bus.snoop_filter.hit_single_snoops 306 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 110707 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2619793 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 110723 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2619809 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 747367 # Transaction distribution @@ -3159,35 +3159,35 @@ system.toL2Bus.trans_dist::ReadSharedReq 537547 # Tr system.toL2Bus.trans_dist::InvalidateReq 4488 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5931996 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2625304 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 25197 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 25229 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 99111 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8681608 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8681640 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 252349880 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97897081 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 40804 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 40868 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 174056 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 350461821 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 350461885 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 123025 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4134634 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 4134650 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 0.021870 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0.146260 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4044208 97.81% 97.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4044224 97.81% 97.81% # Request fanout histogram system.toL2Bus.snoop_fanout::1 90426 2.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4134634 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3415021456 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4134650 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3415029456 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 230913 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 1843284752 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 768458163 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 768457664 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10591473 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10607473 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer3.occupancy 47113721 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index a6bd06312..5963d7bbb 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,98 +1,98 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.804583 # Number of seconds simulated -sim_ticks 2804582834000 # Number of ticks simulated -final_tick 2804582834000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.804580 # Number of seconds simulated +sim_ticks 2804580230500 # Number of ticks simulated +final_tick 2804580230500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172391 # Simulator instruction rate (inst/s) -host_op_rate 209235 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4135673798 # Simulator tick rate (ticks/s) -host_mem_usage 633896 # Number of bytes of host memory used -host_seconds 678.14 # Real time elapsed on the host +host_inst_rate 127171 # Simulator instruction rate (inst/s) +host_op_rate 154351 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3050845926 # Simulator tick rate (ticks/s) +host_mem_usage 593120 # Number of bytes of host memory used +host_seconds 919.28 # Real time elapsed on the host sim_insts 116905819 # Number of instructions simulated sim_ops 141891765 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 3968 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 685504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5035168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5032416 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 4288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 692224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4774856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 692288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4777544 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 11197032 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 685504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 692224 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1377728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8413760 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu1.inst 692288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1377792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8414016 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8431284 # Number of bytes written to this memory +system.physmem.bytes_written::total 8431540 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 62 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 10711 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 79193 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 79150 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 67 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74609 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10817 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 74651 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 175474 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131465 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 131469 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135846 # Number of write requests responded to by this memory +system.physmem.num_writes::total 135850 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 1415 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 244423 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1795336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1794356 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 1529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 246819 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1702519 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 246842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1703479 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3992406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3992409 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 244423 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 246819 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 491242 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3000004 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 246842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 491265 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3000098 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6245 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3006252 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3000004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3006347 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3000098 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 1415 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 244423 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1801581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1800602 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 1529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 246819 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1702522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 246842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1703482 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 342 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6998658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6998756 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 175475 # Number of read requests accepted -system.physmem.writeReqs 135846 # Number of write requests accepted +system.physmem.writeReqs 135850 # Number of write requests accepted system.physmem.readBursts 175475 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 135846 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writeBursts 135850 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 11220480 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 9920 # Total number of bytes read from write queue -system.physmem.bytesWritten 8444352 # Total number of bytes written to DRAM +system.physmem.bytesWritten 8444544 # Total number of bytes written to DRAM system.physmem.bytesReadSys 11197096 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8431284 # Total written bytes from the system interface side +system.physmem.bytesWrittenSys 8431540 # Total written bytes from the system interface side system.physmem.servicedByWrQ 155 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 11302 # Per bank write bursts -system.physmem.perBankRdBursts::1 11252 # Per bank write bursts -system.physmem.perBankRdBursts::2 11256 # Per bank write bursts -system.physmem.perBankRdBursts::3 10710 # Per bank write bursts -system.physmem.perBankRdBursts::4 11532 # Per bank write bursts -system.physmem.perBankRdBursts::5 11381 # Per bank write bursts -system.physmem.perBankRdBursts::6 12180 # Per bank write bursts -system.physmem.perBankRdBursts::7 12061 # Per bank write bursts +system.physmem.perBankRdBursts::1 11253 # Per bank write bursts +system.physmem.perBankRdBursts::2 11257 # Per bank write bursts +system.physmem.perBankRdBursts::3 10711 # Per bank write bursts +system.physmem.perBankRdBursts::4 11530 # Per bank write bursts +system.physmem.perBankRdBursts::5 11380 # Per bank write bursts +system.physmem.perBankRdBursts::6 12179 # Per bank write bursts +system.physmem.perBankRdBursts::7 12059 # Per bank write bursts system.physmem.perBankRdBursts::8 10232 # Per bank write bursts system.physmem.perBankRdBursts::9 10264 # Per bank write bursts -system.physmem.perBankRdBursts::10 10575 # Per bank write bursts -system.physmem.perBankRdBursts::11 9266 # Per bank write bursts +system.physmem.perBankRdBursts::10 10576 # Per bank write bursts +system.physmem.perBankRdBursts::11 9268 # Per bank write bursts system.physmem.perBankRdBursts::12 10585 # Per bank write bursts system.physmem.perBankRdBursts::13 11349 # Per bank write bursts system.physmem.perBankRdBursts::14 10873 # Per bank write bursts @@ -100,22 +100,22 @@ system.physmem.perBankRdBursts::15 10502 # Pe system.physmem.perBankWrBursts::0 8422 # Per bank write bursts system.physmem.perBankWrBursts::1 8567 # Per bank write bursts system.physmem.perBankWrBursts::2 8697 # Per bank write bursts -system.physmem.perBankWrBursts::3 8116 # Per bank write bursts +system.physmem.perBankWrBursts::3 8117 # Per bank write bursts system.physmem.perBankWrBursts::4 8443 # Per bank write bursts system.physmem.perBankWrBursts::5 8487 # Per bank write bursts -system.physmem.perBankWrBursts::6 9141 # Per bank write bursts -system.physmem.perBankWrBursts::7 9034 # Per bank write bursts +system.physmem.perBankWrBursts::6 9140 # Per bank write bursts +system.physmem.perBankWrBursts::7 9032 # Per bank write bursts system.physmem.perBankWrBursts::8 7740 # Per bank write bursts system.physmem.perBankWrBursts::9 7663 # Per bank write bursts -system.physmem.perBankWrBursts::10 7868 # Per bank write bursts -system.physmem.perBankWrBursts::11 6935 # Per bank write bursts +system.physmem.perBankWrBursts::10 7869 # Per bank write bursts +system.physmem.perBankWrBursts::11 6937 # Per bank write bursts system.physmem.perBankWrBursts::12 8081 # Per bank write bursts system.physmem.perBankWrBursts::13 8671 # Per bank write bursts -system.physmem.perBankWrBursts::14 8304 # Per bank write bursts +system.physmem.perBankWrBursts::14 8306 # Per bank write bursts system.physmem.perBankWrBursts::15 7774 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 2804582655500 # Total gap between requests +system.physmem.totGap 2804580052000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) @@ -129,11 +129,11 @@ system.physmem.writePktSize::2 4381 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 131465 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 103782 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1751 # What read queue length does an incoming req see +system.physmem.writePktSize::6 131469 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 103792 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1749 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -177,48 +177,48 @@ system.physmem.wrQLenPdf::11 81 # Wh system.physmem.wrQLenPdf::12 81 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 79 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7197 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 6902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 101 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 97 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 71 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 63 # What write queue length does an incoming req see @@ -226,50 +226,50 @@ system.physmem.wrQLenPdf::60 46 # Wh system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 36 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64935 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 302.837730 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.379870 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.140175 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24467 37.68% 37.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15703 24.18% 61.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6760 10.41% 72.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3722 5.73% 78.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2848 4.39% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1541 2.37% 84.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1091 1.68% 86.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1047 1.61% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7756 11.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64935 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6659 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.328127 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 478.808129 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6657 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 64931 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.859343 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.384089 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.204668 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24461 37.67% 37.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15710 24.19% 61.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6774 10.43% 72.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3704 5.70% 78.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2837 4.37% 82.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1544 2.38% 84.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1096 1.69% 86.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1046 1.61% 88.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7759 11.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64931 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6660 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.324024 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 478.772149 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6658 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-8191 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::36864-38911 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6659 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6659 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.814236 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.240992 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.368669 # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6660 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6660 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.811712 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.241865 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.351487 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::0-3 11 0.17% 0.17% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::4-7 8 0.12% 0.29% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::8-11 5 0.08% 0.36% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::12-15 7 0.11% 0.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5729 86.03% 86.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 143 2.15% 88.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 83 1.25% 89.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 58 0.87% 90.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 282 4.23% 95.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 54 0.81% 95.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 22 0.33% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 10 0.15% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 13 0.20% 96.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 9 0.14% 96.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.12% 96.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.08% 96.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 158 2.37% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.06% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 2 0.03% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5729 86.02% 86.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 144 2.16% 88.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 82 1.23% 89.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 58 0.87% 90.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 282 4.23% 94.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 56 0.84% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 22 0.33% 96.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.15% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 13 0.20% 96.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 9 0.14% 96.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.12% 96.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.08% 96.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 158 2.37% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.02% 99.28% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::80-83 9 0.14% 99.41% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::84-87 3 0.05% 99.46% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::88-91 1 0.02% 99.47% # Writes before turning the bus around for reads @@ -285,13 +285,13 @@ system.physmem.wrPerTurnAround::160-163 1 0.02% 99.95% # Wr system.physmem.wrPerTurnAround::172-175 1 0.02% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::188-191 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6659 # Writes before turning the bus around for reads -system.physmem.totQLat 2658321750 # Total ticks spent queuing -system.physmem.totMemAccLat 5945571750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.wrPerTurnAround::total 6660 # Writes before turning the bus around for reads +system.physmem.totQLat 2657846750 # Total ticks spent queuing +system.physmem.totMemAccLat 5945096750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 876600000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15162.68 # Average queueing delay per DRAM burst +system.physmem.avgQLat 15159.97 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33912.68 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 33909.97 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.00 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.01 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.99 # Average system read bandwidth in MiByte/s @@ -302,41 +302,41 @@ system.physmem.busUtilRead 0.03 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing system.physmem.avgWrQLen 11.41 # Average write queue length when enqueuing -system.physmem.readRowHits 144869 # Number of row buffer hits during reads -system.physmem.writeRowHits 97458 # Number of row buffer hits during writes +system.physmem.readRowHits 144865 # Number of row buffer hits during reads +system.physmem.writeRowHits 97469 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.63 # Row buffer hit rate for reads system.physmem.writeRowHitRate 73.86 # Row buffer hit rate for writes -system.physmem.avgGap 9008652.34 # Average gap between requests +system.physmem.avgGap 9008528.23 # Average gap between requests system.physmem.pageHitRate 78.86 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 258385680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 140984250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 715049400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 446517360 # Energy for write commands per rank (pJ) +system.physmem_0.actEnergy 258347880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 140963625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 715026000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 446504400 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 183181277760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 78012609390 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1614313697250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1877068521090 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.287723 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2685462700000 # Time in different power states +system.physmem_0.actBackEnergy 78001831260 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1614323151750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1877067102675 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.287218 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2685476419500 # Time in different power states system.physmem_0.memoryStateTime::REF 93650960000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 25469163500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 25452840500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 232522920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 126872625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 652438800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 408473280 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 232530480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 126876750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 652462200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 408505680 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 183181277760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 77055662610 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1615153124250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1876810372245 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.195678 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2686857596250 # Time in different power states +system.physmem_1.actBackEnergy 77069277630 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1615141181250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1876812111750 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.196298 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2686837815500 # Time in different power states system.physmem_1.memoryStateTime::REF 93650960000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 24067808750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 24087589500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 768 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 768 # Number of instructions bytes read from this memory @@ -349,30 +349,30 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 274 system.realview.nvmem.bw_inst_read::total 274 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 274 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 274 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 26563319 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13759388 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 495774 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 16214186 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 8026564 # Number of BTB hits +system.cpu0.branchPred.lookups 26564246 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13760083 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 495819 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 16217384 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 8027247 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 49.503342 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 6609603 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28316 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4513473 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 4401835 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 111638 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 31883 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 49.497792 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 6609804 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28343 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4513554 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 4401782 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 111772 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 31942 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -402,17 +402,17 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 59132 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 59132 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17796 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14691 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 26645 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 32487 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 741.511989 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 4828.940187 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-16383 32073 98.73% 98.73% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-32767 302 0.93% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 58733 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 58733 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17793 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14688 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 26252 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 32481 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 736.907731 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 4817.272185 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-16383 32071 98.74% 98.74% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-32767 298 0.92% 99.66% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::32768-49151 58 0.18% 99.83% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::49152-65535 24 0.07% 99.91% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::65536-81919 12 0.04% 99.94% # Table walker wait (enqueue to first request) latency @@ -420,72 +420,72 @@ system.cpu0.dtb.walker.walkWaitTime::81920-98303 5 0.02% 99. system.cpu0.dtb.walker.walkWaitTime::98304-114687 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::114688-131071 5 0.02% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::147456-163839 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 32487 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 12954 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 13356.453605 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11053.395474 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 8313.507092 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 9693 74.83% 74.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 2999 23.15% 97.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 232 1.79% 99.77% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkWaitTime::total 32481 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 12836 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 13407.876285 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11117.462243 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 8301.375847 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 9572 74.57% 74.57% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 3010 23.45% 98.02% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 224 1.75% 99.77% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::49152-65535 12 0.09% 99.86% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::65536-81919 3 0.02% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 11 0.08% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 11 0.09% 99.97% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.02% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 12954 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 80893447336 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.689246 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.490660 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 80809388336 99.90% 99.90% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 57018000 0.07% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 12830500 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 5059000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 2818000 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 1843000 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 1116000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 1980000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 463500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 218500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-21 179500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::22-23 36500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-25 167500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::26-27 41000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-29 27000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::30-31 261000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 80893447336 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3543 69.38% 69.38% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1564 30.62% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5107 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 59132 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 12836 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 80896428336 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.690430 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.489717 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 80813150336 99.90% 99.90% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 56853500 0.07% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 12740500 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 4914000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 2520000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 1766000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 1127000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 1985000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 442000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 216500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-21 182000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::22-23 37500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-25 158000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::26-27 42500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-29 16500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::30-31 277000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 80896428336 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3537 69.35% 69.35% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1563 30.65% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5100 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 58733 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 59132 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5107 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 58733 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5100 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5107 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 64239 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5100 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 63833 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 13759364 # DTB read hits -system.cpu0.dtb.read_misses 49716 # DTB read misses -system.cpu0.dtb.write_hits 10256387 # DTB write hits -system.cpu0.dtb.write_misses 9416 # DTB write misses +system.cpu0.dtb.read_hits 13760624 # DTB read hits +system.cpu0.dtb.read_misses 49633 # DTB read misses +system.cpu0.dtb.write_hits 10257954 # DTB write hits +system.cpu0.dtb.write_misses 9100 # DTB write misses system.cpu0.dtb.flush_tlb 182 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3461 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 822 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1317 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3389 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 823 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1310 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 673 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 13809080 # DTB read accesses -system.cpu0.dtb.write_accesses 10265803 # DTB write accesses +system.cpu0.dtb.perms_faults 671 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 13810257 # DTB read accesses +system.cpu0.dtb.write_accesses 10267054 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 24015751 # DTB hits -system.cpu0.dtb.misses 59132 # DTB misses -system.cpu0.dtb.accesses 24074883 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 24018578 # DTB hits +system.cpu0.dtb.misses 58733 # DTB misses +system.cpu0.dtb.accesses 24077311 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -515,62 +515,62 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 7852 # Table walker walks requested -system.cpu0.itb.walker.walksShort 7852 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2338 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 4601 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 913 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 6939 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1482.922611 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 5881.501681 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-8191 6495 93.60% 93.60% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-16383 232 3.34% 96.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-24575 124 1.79% 98.73% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-32767 39 0.56% 99.29% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-40959 13 0.19% 99.48% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::40960-49151 15 0.22% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::49152-57343 10 0.14% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::57344-65535 3 0.04% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 7862 # Table walker walks requested +system.cpu0.itb.walker.walksShort 7862 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2332 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 4618 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 912 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 6950 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1524.460432 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 6004.169915 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-8191 6494 93.44% 93.44% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-16383 241 3.47% 96.91% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-24575 125 1.80% 98.71% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-32767 34 0.49% 99.19% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-40959 18 0.26% 99.45% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-49151 15 0.22% 99.67% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::49152-57343 11 0.16% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::57344-65535 4 0.06% 99.88% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::65536-73727 4 0.06% 99.94% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::73728-81919 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::81920-90111 2 0.03% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 6939 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 3247 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12392.208192 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 10258.914411 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 7404.792558 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 1195 36.80% 36.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1373 42.29% 79.09% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 618 19.03% 98.12% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 36 1.11% 99.23% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 12 0.37% 99.60% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 8 0.25% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 3 0.09% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkWaitTime::total 6950 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 3241 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12408.053070 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 10260.895484 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 7472.988391 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 1196 36.90% 36.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1364 42.09% 78.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 617 19.04% 98.03% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 36 1.11% 99.14% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 13 0.40% 99.54% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 9 0.28% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 4 0.12% 99.94% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.03% 99.97% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 3247 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 29354741784 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.621127 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.485486 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 11126118428 37.90% 37.90% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 18225065856 62.09% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 2842500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 576000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 139000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 29354741784 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1743 74.68% 74.68% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 591 25.32% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2334 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 3241 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 29351792784 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.620704 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.485614 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 11137583928 37.95% 37.95% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 18210652356 62.04% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 2700500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 701500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 154500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 29351792784 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1739 74.67% 74.67% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 590 25.33% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2329 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 7852 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 7852 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 7862 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 7862 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2334 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2334 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 10186 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 19905461 # ITB inst hits -system.cpu0.itb.inst_misses 7852 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2329 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2329 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 10191 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 19906259 # ITB inst hits +system.cpu0.itb.inst_misses 7862 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -579,17 +579,17 @@ system.cpu0.itb.flush_tlb 182 # Nu system.cpu0.itb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2294 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2225 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1258 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1249 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 19913313 # ITB inst accesses -system.cpu0.itb.hits 19905461 # DTB hits -system.cpu0.itb.misses 7852 # DTB misses -system.cpu0.itb.accesses 19913313 # DTB accesses +system.cpu0.itb.inst_accesses 19914121 # ITB inst accesses +system.cpu0.itb.hits 19906259 # DTB hits +system.cpu0.itb.misses 7862 # DTB misses +system.cpu0.itb.accesses 19914121 # DTB accesses system.cpu0.numPwrStateTransitions 3146 # Number of power state transitions system.cpu0.pwrStateClkGateDist::samples 1573 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::mean 939647394.777495 # Distribution of time spent in the clock gated state @@ -601,104 +601,104 @@ system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.13% 100.00 system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 499976908600 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::total 1573 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 1326517482015 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::ON 1326514878515 # Cumulative time (in ticks) in various power states system.cpu0.pwrStateResidencyTicks::CLK_GATED 1478065351985 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 106457732 # number of cpu cycles simulated +system.cpu0.numCycles 106457810 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 39778104 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 102329331 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 26563319 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 19038002 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 62116027 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3105600 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 111146 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 3723 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 374 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 142117 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 123224 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 483 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 19903626 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 349456 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 4039 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 103827961 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.185750 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.289369 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 39783272 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 102334432 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 26564246 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 19038833 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 62110443 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3105656 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 111244 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 3727 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 375 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 142235 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 122947 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 487 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 19904431 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 349445 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 4054 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 103827521 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.185827 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.289430 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 75543673 72.76% 72.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 3812816 3.67% 76.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2351525 2.26% 78.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 7978907 7.68% 86.38% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1585659 1.53% 87.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 993143 0.96% 88.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 6063618 5.84% 94.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1017561 0.98% 95.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4481059 4.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 75541763 72.76% 72.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 3812950 3.67% 76.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2351578 2.26% 78.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 7979154 7.69% 86.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1585790 1.53% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 993286 0.96% 88.86% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 6064061 5.84% 94.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1017530 0.98% 95.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4481409 4.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 103827961 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.249520 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.961220 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 27448350 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 58255743 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 15281337 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1431455 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1410775 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1819074 # Number of times decode resolved a branch +system.cpu0.fetch.rateDist::total 103827521 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.249528 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.961267 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 27452745 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 58249830 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 15282230 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1431597 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1410818 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1819259 # Number of times decode resolved a branch system.cpu0.decode.BranchMispred 143809 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 84464795 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 475260 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1410775 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 28253865 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6710507 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 43964237 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 15899574 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 7588686 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 80835076 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 4210 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1036846 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 275223 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 5569610 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 83235701 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 372775200 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 90140763 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 7010 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 70379825 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 12855876 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1526723 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1432794 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8313035 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 14557991 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 11307773 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1955979 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2652434 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 77887971 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1057787 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 74749052 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 90659 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10605329 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 23152649 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 112514 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 103827961 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.719932 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.414021 # Number of insts issued each cycle +system.cpu0.decode.DecodedInsts 84470520 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 475057 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1410818 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 28258375 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6709685 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 43965251 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 15900516 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 7582559 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 80840782 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 4307 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1036576 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 275166 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 5563712 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 83242060 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 372803118 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 90148302 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 7047 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 70383329 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12858731 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1526779 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1432825 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8314563 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 14558964 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 11309450 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1956443 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2653694 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 77893392 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1057864 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 74754554 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 90317 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10606810 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 23150954 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 112541 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 103827521 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.719988 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.414103 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 73906111 71.18% 71.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10009384 9.64% 80.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 7640879 7.36% 88.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 6355260 6.12% 94.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2281294 2.20% 96.50% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1454406 1.40% 97.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 1486828 1.43% 99.33% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 476436 0.46% 99.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 217363 0.21% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 73904134 71.18% 71.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10009837 9.64% 80.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 7641807 7.36% 88.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 6354760 6.12% 94.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2280701 2.20% 96.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1455227 1.40% 97.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1486959 1.43% 99.33% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 476638 0.46% 99.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 217458 0.21% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 103827961 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 103827521 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 96059 8.82% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 96078 8.82% 8.82% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 1 0.00% 8.82% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.82% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.82% # attempts to use FU when none available @@ -727,13 +727,13 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.82% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.82% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.82% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 522555 47.96% 56.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 470896 43.22% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 523068 47.99% 56.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 470781 43.19% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2193 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 49733964 66.53% 66.54% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57150 0.08% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 49737115 66.53% 66.54% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57140 0.08% 66.61% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.61% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.61% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.61% # Type of FU issued @@ -761,95 +761,95 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 4360 0.01% 66.62% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.62% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 66.62% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 14140204 18.92% 85.54% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 10811178 14.46% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 14141290 18.92% 85.54% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 10812453 14.46% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 74749052 # Type of FU issued -system.cpu0.iq.rate 0.702148 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1089511 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.014576 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 254491359 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 89595521 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 72529451 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 14876 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 8869 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 6537 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 75828364 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 8006 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 352891 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 74754554 # Type of FU issued +system.cpu0.iq.rate 0.702199 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1089928 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.014580 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 254501968 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 89602389 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 72535350 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 14906 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 8959 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 6549 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 75834268 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 8021 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 353131 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2046517 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2081 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 54500 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1025754 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2046839 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2065 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 54488 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1026130 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 203183 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 83677 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 203254 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 83583 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1410775 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 5864401 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 637976 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 79069756 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 107726 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 14557991 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 11307773 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 551458 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 44492 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 582169 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 54500 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 204607 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 218688 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 423295 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 74201167 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 13921134 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 488864 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1410818 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 5863644 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 637671 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 79075081 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 107625 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 14558964 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 11309450 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 551514 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 44441 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 581945 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 54488 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 204716 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 218656 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 423372 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 74207157 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 13922405 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 488771 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 123998 # number of nop insts executed -system.cpu0.iew.exec_refs 24636404 # number of memory reference insts executed -system.cpu0.iew.exec_branches 14031471 # Number of branches executed -system.cpu0.iew.exec_stores 10715270 # Number of stores executed -system.cpu0.iew.exec_rate 0.697001 # Inst execution rate -system.cpu0.iew.wb_sent 73687563 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 72535988 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 37714943 # num instructions producing a value -system.cpu0.iew.wb_consumers 65670191 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.681360 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.574308 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 10562082 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 945273 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 353712 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 101401288 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.674752 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.564672 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 123825 # number of nop insts executed +system.cpu0.iew.exec_refs 24639289 # number of memory reference insts executed +system.cpu0.iew.exec_branches 14032526 # Number of branches executed +system.cpu0.iew.exec_stores 10716884 # Number of stores executed +system.cpu0.iew.exec_rate 0.697057 # Inst execution rate +system.cpu0.iew.wb_sent 73693634 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 72541899 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 37717472 # num instructions producing a value +system.cpu0.iew.wb_consumers 65674853 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.681415 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.574306 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 10563486 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 945323 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 353772 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 101400754 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.674795 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.564695 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 74703091 73.67% 73.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 12065534 11.90% 85.57% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 6043146 5.96% 91.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2565114 2.53% 94.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1263406 1.25% 95.30% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 840623 0.83% 96.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1825870 1.80% 97.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 394429 0.39% 98.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1700075 1.68% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 74701679 73.67% 73.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 12064783 11.90% 85.57% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 6043507 5.96% 91.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2566010 2.53% 94.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1263544 1.25% 95.30% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 840996 0.83% 96.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1825672 1.80% 97.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 394773 0.39% 98.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1699790 1.68% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 101401288 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 56174796 # Number of instructions committed -system.cpu0.commit.committedOps 68420730 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 101400754 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 56177531 # Number of instructions committed +system.cpu0.commit.committedOps 68424746 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 22793493 # Number of memory references committed -system.cpu0.commit.loads 12511474 # Number of loads committed -system.cpu0.commit.membars 380410 # Number of memory barriers committed -system.cpu0.commit.branches 13308961 # Number of branches committed +system.cpu0.commit.refs 22795445 # Number of memory references committed +system.cpu0.commit.loads 12512125 # Number of loads committed +system.cpu0.commit.membars 380426 # Number of memory barriers committed +system.cpu0.commit.branches 13309453 # Number of branches committed system.cpu0.commit.fp_insts 6093 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 59905864 # Number of committed integer instructions. -system.cpu0.commit.function_calls 2612225 # Number of function calls committed. +system.cpu0.commit.int_insts 59909497 # Number of committed integer instructions. +system.cpu0.commit.function_calls 2612274 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 45567261 66.60% 66.60% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55619 0.08% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 45569326 66.60% 66.60% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55618 0.08% 66.68% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.68% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.68% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.68% # Class of committed instruction @@ -877,215 +877,215 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 4357 0.01% 66.69% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.69% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.69% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.69% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 12511474 18.29% 84.97% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 10282019 15.03% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 12512125 18.29% 84.97% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 10283320 15.03% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 68420730 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1700075 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 166296828 # The number of ROB reads -system.cpu0.rob.rob_writes 160391499 # The number of ROB writes -system.cpu0.timesIdled 400345 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 2629771 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.commit.op_class_0::total 68424746 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1699790 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 166301969 # The number of ROB reads +system.cpu0.rob.rob_writes 160402388 # The number of ROB writes +system.cpu0.timesIdled 400481 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 2630289 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu0.quiesceCycles 2956130676 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 56094495 # Number of Instructions Simulated -system.cpu0.committedOps 68340429 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.897829 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.897829 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.526918 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.526918 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 80764362 # number of integer regfile reads -system.cpu0.int_regfile_writes 46165163 # number of integer regfile writes -system.cpu0.fp_regfile_reads 17106 # number of floating regfile reads +system.cpu0.committedInsts 56097231 # Number of Instructions Simulated +system.cpu0.committedOps 68344446 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.897737 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.897737 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.526943 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.526943 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 80771254 # number of integer regfile reads +system.cpu0.int_regfile_writes 46168447 # number of integer regfile writes +system.cpu0.fp_regfile_reads 17119 # number of floating regfile reads system.cpu0.fp_regfile_writes 13230 # number of floating regfile writes -system.cpu0.cc_regfile_reads 262463335 # number of cc regfile reads -system.cpu0.cc_regfile_writes 27226302 # number of cc regfile writes -system.cpu0.misc_regfile_reads 188101438 # number of misc regfile reads -system.cpu0.misc_regfile_writes 725062 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.cpu0.cc_regfile_reads 262483574 # number of cc regfile reads +system.cpu0.cc_regfile_writes 27229221 # number of cc regfile writes +system.cpu0.misc_regfile_reads 188104262 # number of misc regfile reads +system.cpu0.misc_regfile_writes 725122 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 852281 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.984445 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 42339308 # Total number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 42339944 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 852793 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 49.647814 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 49.648559 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 92671500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.071418 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 327.913027 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.359514 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.640455 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.072113 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 327.912332 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.359516 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.640454 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 189174355 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 189174355 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 12233622 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 12935174 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25168796 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 7652789 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 8245651 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15898440 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177697 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 185293 # number of SoftPFReq hits +system.cpu0.dcache.tags.tag_accesses 189174351 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 189174351 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 12234598 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 12933985 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25168583 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 7653509 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 8245795 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15899304 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177729 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 185261 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 362990 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 209982 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 236483 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 446465 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 216319 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 243020 # number of StoreCondReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 210001 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 236455 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 446456 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 216327 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 243012 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 459339 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 19886411 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 21180825 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41067236 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20064108 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21366118 # number of overall hits -system.cpu0.dcache.overall_hits::total 41430226 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 399335 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 433156 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 832491 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1953724 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1746335 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 3700059 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 79458 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 104494 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 183952 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13729 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14031 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 27760 # number of LoadLockedReq misses +system.cpu0.dcache.demand_hits::cpu0.data 19888107 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 21179780 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41067887 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 20065836 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 21365041 # number of overall hits +system.cpu0.dcache.overall_hits::total 41430877 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 399294 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 433443 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 832737 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1954214 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1744981 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 3699195 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 79447 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 104479 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 183926 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13728 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14033 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 27761 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 50 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 43 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 93 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2353059 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 2179491 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4532550 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2432517 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 2283985 # number of overall misses -system.cpu0.dcache.overall_misses::total 4716502 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5993164000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6602742500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 12595906500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 87678812214 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 78129188370 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 165808000584 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 179748500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 207520500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 387269000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 2353508 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 2178424 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4531932 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2432955 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 2282903 # number of overall misses +system.cpu0.dcache.overall_misses::total 4715858 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5995822000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6613305000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 12609127000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 87564281292 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 78191889675 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 165756170967 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 179746000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 207586500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 387332500 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 1029000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 788500 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 1817500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 93671976214 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 84731930870 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 178403907084 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 93671976214 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 84731930870 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 178403907084 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 12632957 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 13368330 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 26001287 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9606513 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9991986 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 93560103292 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 84805194675 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 178365297967 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 93560103292 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 84805194675 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 178365297967 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 12633892 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 13367428 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 26001320 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 9607723 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 9990776 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 19598499 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 257155 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 289787 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 546942 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 223711 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 250514 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 474225 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 216369 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 243063 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 257176 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 289740 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 546916 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 223729 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 250488 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 474217 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 216377 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 243055 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 459432 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 22239470 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 23360316 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 45599786 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 22496625 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 23650103 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 46146728 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031611 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032402 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.032017 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.203375 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.174774 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.188793 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.308989 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.360589 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.336328 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061369 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056009 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058538 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 22241615 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 23358204 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 45599819 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 22498791 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 23647944 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 46146735 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031605 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032425 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.032027 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.203400 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.174659 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.188749 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.308921 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.360596 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.336297 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061360 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056023 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058541 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000231 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000177 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000202 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.105806 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.093299 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.099398 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108128 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.096574 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.102207 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15007.860568 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15243.336119 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15130.381590 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44877.788374 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44738.946634 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44812.258557 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13092.614174 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14790.143254 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13950.612392 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.105816 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.093262 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.099385 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108137 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.096537 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.102193 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15016.058343 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15257.611727 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15141.787863 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44807.928554 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44809.593729 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44808.714049 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13093.385781 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14792.738545 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13952.397248 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20580 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 18337.209302 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 19543.010753 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39808.596475 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 38876.935427 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39360.604314 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 38508.251418 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 37098.286928 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 37825.470462 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1131320 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 188861 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 53104 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 2863 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.303857 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 65.966119 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 702476 # number of writebacks -system.cpu0.dcache.writebacks::total 702476 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 189142 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 219525 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 408667 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1797272 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1603201 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 3400473 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 9446 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 9040 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18486 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1986414 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1822726 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3809140 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1986414 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1822726 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3809140 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 210193 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 213631 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 423824 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 156452 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 143134 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 299586 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 55184 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 67813 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 122997 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4283 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4991 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39753.467289 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 38929.609055 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39357.452399 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 38455.336532 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 37147.962342 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 37822.448845 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1130917 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 188980 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 52756 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 2865 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.436747 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 65.961606 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 702484 # number of writebacks +system.cpu0.dcache.writebacks::total 702484 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 189081 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 219808 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 408889 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1797716 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1601889 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 3399605 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 9443 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 9044 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18487 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1986797 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1821697 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3808494 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1986797 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1821697 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3808494 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 210213 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 213635 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 423848 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 156498 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 143092 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 299590 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 55178 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 67787 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 122965 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4285 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4989 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9274 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 50 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 43 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 93 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 366645 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 356765 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 723410 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 421829 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 424578 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 846407 # number of overall MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 366711 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 356727 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 723438 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 421889 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 424514 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 846403 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16364 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 14763 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable @@ -1095,235 +1095,235 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27584 system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32319 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 26392 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2996485500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 3091984000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6088469500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7303847372 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6679350930 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13983198302 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 775558500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 966595500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1742154000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 55534500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 83841500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 139376000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2997028500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 3092354500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6089383000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7297289872 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6685283941 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13982573813 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 775081500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 964984500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1740066000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 55558500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 83818500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 139377000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 979000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 745500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1724500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10300332872 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9771334930 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 20071667802 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11075891372 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10737930430 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 21813821802 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3308436000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2995791000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6304227000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3308436000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2995791000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6304227000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016638 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015980 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016300 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016286 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014325 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10294318372 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9777638441 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 20071956813 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11069399872 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10742622941 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 21812022813 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3308422500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2995783000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6304205500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3308422500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2995783000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6304205500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016639 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015982 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016301 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016289 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014322 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015286 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.214594 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.234010 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224881 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.019145 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019923 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.214553 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.233958 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224833 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.019153 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019917 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019556 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000231 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000177 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000202 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016486 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016488 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015272 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015864 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018751 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017952 # mshr miss rate for overall accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015865 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018752 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017951 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.018342 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14255.876742 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14473.479972 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14365.560940 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46684.269757 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46665.019702 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46675.072607 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14054.046463 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14253.837760 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14164.199127 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12966.261966 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16798.537367 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15028.682338 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14257.103509 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14474.943244 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14366.902758 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46628.646194 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46720.179612 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46672.364942 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14046.929936 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14235.539263 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14150.904729 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12965.810968 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16800.661455 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15028.790166 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19580 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 17337.209302 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18543.010753 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28093.476993 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27388.715065 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27745.908685 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26256.827700 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25290.830966 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25772.260629 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 202177.707162 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 202925.624873 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202532.431651 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 102368.142579 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 113511.329191 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 107377.271721 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1934770 # number of replacements +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28072.019579 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27409.303027 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27745.234302 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26237.706771 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25305.697671 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25770.256973 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 202176.882180 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 202925.082978 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202531.740932 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 102367.724868 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 113511.026069 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 107376.905520 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1934891 # number of replacements system.cpu0.icache.tags.tagsinuse 511.556955 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 38706180 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1935282 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 20.000279 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 38705762 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1935403 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 19.998813 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 9780443500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 231.259013 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 280.297942 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.451678 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.547457 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 231.260597 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 280.296358 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.451681 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.547454 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999135 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 224 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 228 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 42724671 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 42724671 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 18869611 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 19836569 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 38706180 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 18869611 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 19836569 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 38706180 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 18869611 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 19836569 # number of overall hits -system.cpu0.icache.overall_hits::total 38706180 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1033343 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 1049727 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2083070 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1033343 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 1049727 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2083070 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1033343 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 1049727 # number of overall misses -system.cpu0.icache.overall_misses::total 2083070 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14011205485 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14271764988 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 28282970473 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14011205485 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 14271764988 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 28282970473 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14011205485 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 14271764988 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 28282970473 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 19902954 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 20886296 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 40789250 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 19902954 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 20886296 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 40789250 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 19902954 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 20886296 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 40789250 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051919 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.050259 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.051069 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051919 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.050259 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.051069 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051919 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.050259 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.051069 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13559.104271 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13595.692011 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13577.542028 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13559.104271 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13595.692011 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13577.542028 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13559.104271 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13595.692011 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13577.542028 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 12666 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 42724437 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 42724437 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 18870227 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 19835535 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 38705762 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 18870227 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 19835535 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 38705762 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 18870227 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 19835535 # number of overall hits +system.cpu0.icache.overall_hits::total 38705762 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1033532 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 1049601 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 2083133 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1033532 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 1049601 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 2083133 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1033532 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 1049601 # number of overall misses +system.cpu0.icache.overall_misses::total 2083133 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14014676985 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14269854487 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 28284531472 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14014676985 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 14269854487 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 28284531472 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14014676985 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 14269854487 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 28284531472 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 19903759 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 20885136 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 40788895 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 19903759 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 20885136 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 40788895 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 19903759 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 20885136 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 40788895 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051926 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.050256 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.051071 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051926 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.050256 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.051071 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051926 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.050256 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.051071 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13559.983614 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13595.503898 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13577.880756 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13559.983614 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13595.503898 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13577.880756 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13559.983614 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13595.503898 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13577.880756 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 12686 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 637 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 639 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.883830 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.852895 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1934770 # number of writebacks -system.cpu0.icache.writebacks::total 1934770 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 71468 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 76180 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 147648 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 71468 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 76180 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 147648 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 71468 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 76180 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 147648 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 961875 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 973547 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1935422 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 961875 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 973547 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1935422 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 961875 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 973547 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1935422 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1934891 # number of writebacks +system.cpu0.icache.writebacks::total 1934891 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 71394 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 76196 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 147590 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 71394 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 76196 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 147590 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 71394 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 76196 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 147590 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 962138 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 973405 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1935543 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 962138 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 973405 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1935543 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 962138 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 973405 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1935543 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 667 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 667 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 667 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 667 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12392823488 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 12603228992 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 24996052480 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12392823488 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 12603228992 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 24996052480 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12392823488 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 12603228992 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 24996052480 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12396442988 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 12601714991 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 24998157979 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12396442988 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 12601714991 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 24998157979 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12396442988 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 12601714991 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 24998157979 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 53482500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 53482500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 53482500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 53482500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.048328 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.046612 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047449 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.048328 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.046612 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.047449 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.048328 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046612 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.047449 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12884.027018 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12945.681094 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12915.039965 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12884.027018 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12945.681094 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12915.039965 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12884.027018 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12945.681094 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12915.039965 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.048340 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.046608 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047453 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.048340 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.046608 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.047453 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.048340 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046608 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.047453 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12884.267109 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12946.014240 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12915.320393 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12884.267109 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12946.014240 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12915.320393 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12884.267109 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12946.014240 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12915.320393 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80183.658171 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 80183.658171 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80183.658171 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 80183.658171 # average overall mshr uncacheable latency -system.cpu1.branchPred.lookups 27800734 # Number of BP lookups -system.cpu1.branchPred.condPredicted 14468017 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 520264 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 17357855 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 8537221 # Number of BTB hits +system.cpu1.branchPred.lookups 27798523 # Number of BP lookups +system.cpu1.branchPred.condPredicted 14466350 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 520194 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 17356776 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 8536168 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 49.183617 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 6851276 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 30109 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 4615749 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 4505317 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 110432 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 32773 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 49.180608 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 6850987 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 30102 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 4615656 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 4505334 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 110322 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 32790 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1353,93 +1353,93 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 58704 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 58704 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18787 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 14342 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 25575 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 33129 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 607.488907 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3928.944060 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-16383 32763 98.90% 98.90% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-32767 284 0.86% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-49151 53 0.16% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::49152-65535 14 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-81919 9 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 58687 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 58687 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18789 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 14348 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 25550 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 33137 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 617.587591 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3984.391967 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-16383 32762 98.87% 98.87% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-32767 289 0.87% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-49151 55 0.17% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::49152-65535 15 0.05% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-81919 10 0.03% 99.98% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::81920-98303 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::98304-114687 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::114688-131071 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::147456-163839 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 33129 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 12929 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 13107.123521 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10856.290186 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7818.028410 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 3814 29.50% 29.50% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 6003 46.43% 75.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 2605 20.15% 96.08% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 277 2.14% 98.22% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 121 0.94% 99.16% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 97 0.75% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkWaitTime::total 33137 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 12948 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 13117.547112 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10856.155685 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7835.700834 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 3825 29.54% 29.54% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 5982 46.20% 75.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 2634 20.34% 96.08% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 274 2.12% 98.20% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 123 0.95% 99.15% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 98 0.76% 99.91% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::49152-57343 6 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-73727 2 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::81920-90111 2 0.02% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 12929 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 90162765428 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.682767 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.486580 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 90084509428 99.91% 99.91% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 54607500 0.06% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 11537000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 4308000 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 2626500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 1272000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 860000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 1827500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 362000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 169500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-21 127500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::22-23 189000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-25 278500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::26-27 31000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-29 4000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::30-31 56000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 90162765428 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3736 69.71% 69.71% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1623 30.29% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5359 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 58704 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::total 12948 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 90160170928 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.682736 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.486637 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 90081870928 99.91% 99.91% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 54780000 0.06% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 11436000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 4223000 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 2627000 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 1276500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 880500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 1864000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 368000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 150000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-21 136000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::22-23 188500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-25 289500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::26-27 30000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-29 3500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::30-31 47500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 90160170928 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3742 69.76% 69.76% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1622 30.24% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5364 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 58687 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 58704 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5359 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 58687 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5364 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5359 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 64063 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5364 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 64051 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 14569453 # DTB read hits -system.cpu1.dtb.read_misses 50573 # DTB read misses -system.cpu1.dtb.write_hits 10639861 # DTB write hits -system.cpu1.dtb.write_misses 8131 # DTB write misses +system.cpu1.dtb.read_hits 14568202 # DTB read hits +system.cpu1.dtb.read_misses 50557 # DTB read misses +system.cpu1.dtb.write_hits 10638746 # DTB write hits +system.cpu1.dtb.write_misses 8130 # DTB write misses system.cpu1.dtb.flush_tlb 176 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 472 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3396 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 805 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1145 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 3340 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 811 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 1147 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 620 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 14620026 # DTB read accesses -system.cpu1.dtb.write_accesses 10647992 # DTB write accesses +system.cpu1.dtb.perms_faults 622 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 14618759 # DTB read accesses +system.cpu1.dtb.write_accesses 10646876 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 25209314 # DTB hits -system.cpu1.dtb.misses 58704 # DTB misses -system.cpu1.dtb.accesses 25268018 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 25206948 # DTB hits +system.cpu1.dtb.misses 58687 # DTB misses +system.cpu1.dtb.accesses 25265635 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1469,61 +1469,61 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 7547 # Table walker walks requested -system.cpu1.itb.walker.walksShort 7547 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2262 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4445 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 840 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 6707 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1590.577009 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 7723.778790 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-16383 6530 97.36% 97.36% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-32767 110 1.64% 99.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-49151 34 0.51% 99.51% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::49152-65535 14 0.21% 99.72% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-81919 4 0.06% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::81920-98303 4 0.06% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-114687 4 0.06% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 7567 # Table walker walks requested +system.cpu1.itb.walker.walksShort 7567 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2268 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4460 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 839 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 6728 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1599.137931 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 7818.499814 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-16383 6550 97.35% 97.35% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-32767 110 1.63% 98.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-49151 34 0.51% 99.49% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::49152-65535 14 0.21% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-81919 4 0.06% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::81920-98303 4 0.06% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-114687 5 0.07% 99.90% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::114688-131071 3 0.04% 99.94% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::131072-147455 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::147456-163839 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::163840-180223 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 6707 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 3150 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12187.460317 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 9947.804489 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 8166.759001 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-16383 2468 78.35% 78.35% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-32767 654 20.76% 99.11% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-49151 23 0.73% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkWaitTime::total 6728 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 3154 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12204.343691 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 9955.063689 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 8183.561503 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-16383 2464 78.12% 78.12% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-32767 661 20.96% 99.08% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-49151 24 0.76% 99.84% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::49152-65535 4 0.13% 99.97% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::180224-196607 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 3150 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 25738120488 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.844814 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.363091 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 3999711376 15.54% 15.54% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 21735062612 84.45% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 2190000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 624000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 246500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 151000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walkCompletionTime::total 3154 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 25735525988 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.805879 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.396479 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 5001469876 19.43% 19.43% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 20730637612 80.55% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 2251500 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 605500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 237500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 189000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::6 78500 0.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::7 56500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 25738120488 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1735 75.11% 75.11% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 575 24.89% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2310 # Table walker page sizes translated +system.cpu1.itb.walker.walksPending::total 25735525988 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1742 75.25% 75.25% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 573 24.75% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2315 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7547 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7547 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7567 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7567 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2310 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2310 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 9857 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 20888873 # ITB inst hits -system.cpu1.itb.inst_misses 7547 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2315 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2315 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 9882 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 20887699 # ITB inst hits +system.cpu1.itb.inst_misses 7567 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1532,21 +1532,21 @@ system.cpu1.itb.flush_tlb 176 # Nu system.cpu1.itb.flush_tlb_mva 472 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2235 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2181 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1381 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1369 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20896420 # ITB inst accesses -system.cpu1.itb.hits 20888873 # DTB hits -system.cpu1.itb.misses 7547 # DTB misses -system.cpu1.itb.accesses 20896420 # DTB accesses +system.cpu1.itb.inst_accesses 20895266 # ITB inst accesses +system.cpu1.itb.hits 20887699 # DTB hits +system.cpu1.itb.misses 7567 # DTB misses +system.cpu1.itb.accesses 20895266 # DTB accesses system.cpu1.numPwrStateTransitions 2930 # Number of power state transitions system.cpu1.pwrStateClkGateDist::samples 1465 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 831651178.963822 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 15817593716.503048 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 831651195.687372 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 15817593715.627289 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::underflows 1430 97.61% 97.61% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1000-5e+10 32 2.18% 99.80% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.07% 99.86% # Distribution of time spent in the clock gated state @@ -1555,139 +1555,139 @@ system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.07% 100.00 system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::max_value 499953823748 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::total 1465 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 1586213856818 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1218368977182 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 109807766 # number of cpu cycles simulated +system.cpu1.pwrStateResidencyTicks::ON 1586211228818 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1218369001682 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 109802096 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 40946708 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 108526504 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 27800734 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 19893814 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 64236038 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3213549 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 105759 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 7245 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 373 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 135453 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 122613 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 242 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20886297 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 363278 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3848 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 107161169 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.215637 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.316725 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 40943144 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 108514996 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 27798523 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 19892489 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 64235640 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3213335 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 105850 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 7199 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 370 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 133652 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 123170 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 245 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 20885138 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 363282 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3860 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 107155901 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.215568 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.316644 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 77416464 72.24% 72.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 3965095 3.70% 75.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2490829 2.32% 78.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 8243361 7.69% 85.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1613956 1.51% 87.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 1187147 1.11% 88.57% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 6283757 5.86% 94.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1186298 1.11% 95.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4774262 4.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 77413551 72.24% 72.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 3964796 3.70% 75.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2490827 2.32% 78.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 8243216 7.69% 85.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1613766 1.51% 87.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 1187087 1.11% 88.57% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 6283183 5.86% 94.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1186163 1.11% 95.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4773312 4.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 107161169 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.253176 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.988332 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 27964353 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 60068615 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15897753 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1769475 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1460665 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 2003148 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 148026 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 90335872 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 490325 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1460665 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 28918939 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 5241732 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 47181148 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 16705614 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 7652719 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 86492691 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2006 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1748729 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 211009 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 4894541 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 89713841 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 398185196 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 96380963 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6166 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 76287775 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13426050 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1604503 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1503333 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 10223805 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15401006 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 11773081 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 2213053 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 2955194 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 83360447 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1152123 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 80030097 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 91651 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10961230 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 24699895 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 103564 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 107161169 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.746820 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.429737 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 107155901 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.253169 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.988278 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 27961508 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 60068174 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15895892 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1769487 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1460540 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 2002899 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 148049 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 90324512 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 490358 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1460540 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 28915970 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 5237096 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 47181010 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 16703954 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 7656988 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 86483131 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 1983 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1745149 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 215112 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 4898057 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 89702997 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 398140635 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 96368391 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6135 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 76284271 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13418710 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1604439 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1503267 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 10222597 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15399417 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 11771402 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 2211738 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 2954385 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 83351812 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1152022 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 80024674 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 91529 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10956511 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 24682043 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 103513 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 107155901 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.746806 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.429727 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 74988145 69.98% 69.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10859318 10.13% 80.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 8183119 7.64% 87.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 6800302 6.35% 94.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2507101 2.34% 96.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1554442 1.45% 97.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1528270 1.43% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 490375 0.46% 99.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 250097 0.23% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 74986719 69.98% 69.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10856192 10.13% 80.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 8181836 7.64% 87.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 6800942 6.35% 94.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2507542 2.34% 96.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1554150 1.45% 97.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1528598 1.43% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 489898 0.46% 99.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 250024 0.23% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 107161169 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 107155901 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 115126 9.98% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 7 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 527227 45.72% 55.70% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 510910 44.30% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 115019 9.97% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 7 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 527702 45.75% 55.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 510821 44.28% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 144 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 53746905 67.16% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59075 0.07% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 53744043 67.16% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59080 0.07% 67.23% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.23% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued @@ -1715,95 +1715,95 @@ system.cpu1.iq.FU_type_0::SimdFloatMisc 4215 0.01% 67.24% # Ty system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 67.24% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 14959094 18.69% 85.93% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 11260652 14.07% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 14957838 18.69% 85.93% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 11259342 14.07% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 80030097 # Type of FU issued -system.cpu1.iq.rate 0.728820 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1153270 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014410 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 268452912 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 95516318 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 77725340 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 13372 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7575 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5790 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 81175982 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7241 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 353102 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 80024674 # Type of FU issued +system.cpu1.iq.rate 0.728808 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1153549 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.014415 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 268436998 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 95502900 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 77720615 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 13329 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7517 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5775 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 81170860 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7219 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 353138 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2112683 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1972 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 51148 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1017197 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2111745 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1994 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 51136 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1016819 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 193348 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 111717 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 193347 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 111137 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1460665 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 4238159 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 750598 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 84630100 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 109084 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15401006 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 11773081 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 582386 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 44757 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 693078 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 51148 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 222492 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 227539 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 450031 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 79465930 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 14732483 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 505630 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1460540 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 4234573 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 751343 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 84621300 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 108802 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15399417 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 11771402 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 582328 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 44713 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 693944 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 51136 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 222391 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 227484 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 449875 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 79460848 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 14731272 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 505307 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 117530 # number of nop insts executed -system.cpu1.iew.exec_refs 25895547 # number of memory reference insts executed -system.cpu1.iew.exec_branches 14804111 # Number of branches executed -system.cpu1.iew.exec_stores 11163064 # Number of stores executed -system.cpu1.iew.exec_rate 0.723682 # Inst execution rate -system.cpu1.iew.wb_sent 78901102 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 77731130 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 41032213 # num instructions producing a value -system.cpu1.iew.wb_consumers 71725825 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.707884 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.572070 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 10989958 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 1048559 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 374118 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 104645735 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.703573 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.592319 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 117466 # number of nop insts executed +system.cpu1.iew.exec_refs 25893193 # number of memory reference insts executed +system.cpu1.iew.exec_branches 14803387 # Number of branches executed +system.cpu1.iew.exec_stores 11161921 # Number of stores executed +system.cpu1.iew.exec_rate 0.723673 # Inst execution rate +system.cpu1.iew.wb_sent 78896446 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 77726390 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 41030059 # num instructions producing a value +system.cpu1.iew.wb_consumers 71721300 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.707877 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.572076 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 10985590 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 1048509 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 374030 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 104641106 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.703566 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.592412 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 76040779 72.66% 72.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 12759216 12.19% 84.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6569138 6.28% 91.14% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 2748147 2.63% 93.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1448865 1.38% 95.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 932135 0.89% 96.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1856823 1.77% 97.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 438122 0.42% 98.23% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1852510 1.77% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 76039975 72.67% 72.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12757270 12.19% 84.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6567840 6.28% 91.14% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 2747077 2.63% 93.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1449083 1.38% 95.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 932804 0.89% 96.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1855484 1.77% 97.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 438097 0.42% 98.23% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1853476 1.77% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 104645735 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 60885928 # Number of instructions committed -system.cpu1.commit.committedOps 73625940 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 104641106 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 60883193 # Number of instructions committed +system.cpu1.commit.committedOps 73621924 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 24044207 # Number of memory references committed -system.cpu1.commit.loads 13288323 # Number of loads committed -system.cpu1.commit.membars 433821 # Number of memory barriers committed -system.cpu1.commit.branches 14065730 # Number of branches committed +system.cpu1.commit.refs 24042255 # Number of memory references committed +system.cpu1.commit.loads 13287672 # Number of loads committed +system.cpu1.commit.membars 433805 # Number of memory barriers committed +system.cpu1.commit.branches 14065238 # Number of branches committed system.cpu1.commit.fp_insts 5335 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 64521424 # Number of committed integer instructions. -system.cpu1.commit.function_calls 2723504 # Number of function calls committed. +system.cpu1.commit.int_insts 64517791 # Number of committed integer instructions. +system.cpu1.commit.function_calls 2723455 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 49520111 67.26% 67.26% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 57410 0.08% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 49518046 67.26% 67.26% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 57411 0.08% 67.34% # Class of committed instruction system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.34% # Class of committed instruction system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.34% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.34% # Class of committed instruction @@ -1831,32 +1831,32 @@ system.cpu1.commit.op_class_0::SimdFloatMisc 4212 0.01% 67.34% system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.34% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.34% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 13288323 18.05% 85.39% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 10755884 14.61% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 13287672 18.05% 85.39% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 10754583 14.61% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 73625940 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1852510 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 174677688 # The number of ROB reads -system.cpu1.rob.rob_writes 171746746 # The number of ROB writes -system.cpu1.timesIdled 397244 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2646597 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2436737930 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 60811324 # Number of Instructions Simulated -system.cpu1.committedOps 73551336 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.805712 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.805712 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.553798 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.553798 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 86399425 # number of integer regfile reads -system.cpu1.int_regfile_writes 49556939 # number of integer regfile writes -system.cpu1.fp_regfile_reads 16634 # number of floating regfile reads +system.cpu1.commit.op_class_0::total 73621924 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1853476 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 174663739 # The number of ROB reads +system.cpu1.rob.rob_writes 171729340 # The number of ROB writes +system.cpu1.timesIdled 397158 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2646195 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2436737979 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 60808588 # Number of Instructions Simulated +system.cpu1.committedOps 73547319 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.805700 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.805700 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.553802 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.553802 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 86393465 # number of integer regfile reads +system.cpu1.int_regfile_writes 49554201 # number of integer regfile writes +system.cpu1.fp_regfile_reads 16619 # number of floating regfile reads system.cpu1.fp_regfile_writes 13036 # number of floating regfile writes -system.cpu1.cc_regfile_reads 280643076 # number of cc regfile reads -system.cpu1.cc_regfile_writes 29716175 # number of cc regfile writes -system.cpu1.misc_regfile_reads 196047925 # number of misc regfile reads -system.cpu1.misc_regfile_writes 794523 # number of misc regfile writes -system.iobus.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.cpu1.cc_regfile_reads 280625358 # number of cc regfile reads +system.cpu1.cc_regfile_writes 29714417 # number of cc regfile writes +system.cpu1.misc_regfile_reads 196041210 # number of misc regfile reads +system.cpu1.misc_regfile_writes 794463 # number of misc regfile writes +system.iobus.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30198 # Transaction distribution system.iobus.trans_dist::ReadResp 30198 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1941,9 +1941,9 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6430000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6424000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38405500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38406000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 187814627 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) @@ -1951,14 +1951,14 @@ system.iobus.respLayer0.occupancy 82688000 # La system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36409 # number of replacements -system.iocache.tags.tagsinuse 0.981814 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.981800 # Cycle average of tags in use system.iocache.tags.total_refs 30 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 234298498000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.981814 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 0.981800 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.061363 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.061363 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1966,7 +1966,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328227 # Number of tag accesses system.iocache.tags.data_accesses 328227 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits system.iocache.demand_hits::realview.ide 29 # number of demand (read+write) hits @@ -2053,21 +2053,21 @@ system.iocache.demand_avg_mshr_miss_latency::realview.ide 68271.921222 system.iocache.demand_avg_mshr_miss_latency::total 68271.921222 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 68271.921222 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 68271.921222 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 104354 # number of replacements -system.l2c.tags.tagsinuse 65128.327411 # Cycle average of tags in use -system.l2c.tags.total_refs 5134678 # Total number of references to valid blocks. +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 104355 # number of replacements +system.l2c.tags.tagsinuse 65128.328748 # Cycle average of tags in use +system.l2c.tags.total_refs 5134809 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 169609 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 30.273618 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 30.274390 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 49028.421881 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 45.557435 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 49028.426520 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 45.557440 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000253 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4778.981543 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2180.199494 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 47.031154 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5874.260795 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3173.874857 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4778.977549 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2180.200854 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 47.031162 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5874.261984 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3173.872988 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.748114 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000695 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy @@ -2078,250 +2078,250 @@ system.l2c.tags.occ_percent::cpu1.inst 0.089634 # Av system.l2c.tags.occ_percent::cpu1.data 0.048429 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.993779 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65177 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65176 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 78 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3224 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8984 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52582 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 371 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3222 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8987 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52579 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.001190 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994522 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 45398834 # Number of tag accesses -system.l2c.tags.data_accesses 45398834 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 35730 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6852 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 36375 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6496 # number of ReadReq hits -system.l2c.ReadReq_hits::total 85453 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 702476 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 702476 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1895131 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1895131 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 78 # number of UpgradeReq hits +system.l2c.tags.occ_task_id_percent::1024 0.994507 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 45400104 # Number of tag accesses +system.l2c.tags.data_accesses 45400104 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.l2c.ReadReq_hits::cpu0.dtb.walker 35642 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 6871 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 36349 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6520 # number of ReadReq hits +system.l2c.ReadReq_hits::total 85382 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 702484 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 702484 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 1895251 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1895251 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 77 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 55 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 133 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 132 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 34 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 35 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 69 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 82259 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 74230 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 156489 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 951585 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 962532 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1914117 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 262545 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 278213 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 540758 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 35730 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6852 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 951585 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 344804 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 36375 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6496 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 962532 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 352443 # number of demand (read+write) hits -system.l2c.demand_hits::total 2696817 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 35730 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6852 # number of overall hits -system.l2c.overall_hits::cpu0.inst 951585 # number of overall hits -system.l2c.overall_hits::cpu0.data 344804 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 36375 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6496 # number of overall hits -system.l2c.overall_hits::cpu1.inst 962532 # number of overall hits -system.l2c.overall_hits::cpu1.data 352443 # number of overall hits -system.l2c.overall_hits::total 2696817 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 82353 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 74147 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 156500 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 951848 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 962389 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1914237 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 262559 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 278192 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 540751 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 35642 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 6871 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 951848 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 344912 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 36349 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6520 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 962389 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 352339 # number of demand (read+write) hits +system.l2c.demand_hits::total 2696870 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 35642 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 6871 # number of overall hits +system.l2c.overall_hits::cpu0.inst 951848 # number of overall hits +system.l2c.overall_hits::cpu0.data 344912 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 36349 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6520 # number of overall hits +system.l2c.overall_hits::cpu1.inst 962389 # number of overall hits +system.l2c.overall_hits::cpu1.data 352339 # number of overall hits +system.l2c.overall_hits::total 2696870 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 62 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 67 # number of ReadReq misses system.l2c.ReadReq_misses::total 130 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1433 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1300 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2733 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1432 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1298 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2730 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 16 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 8 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 24 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 72695 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 67565 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140260 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 72649 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 67608 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140257 # number of ReadExReq misses system.l2c.ReadCleanReq_misses::cpu0.inst 10064 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 10823 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 20887 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 7102 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 8206 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 15308 # number of ReadSharedReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 10824 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 20888 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 7104 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 8203 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 15307 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 62 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 10064 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 79797 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 79753 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 67 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 10823 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 75771 # number of demand (read+write) misses -system.l2c.demand_misses::total 176585 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 10824 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 75811 # number of demand (read+write) misses +system.l2c.demand_misses::total 176582 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 62 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.inst 10064 # number of overall misses -system.l2c.overall_misses::cpu0.data 79797 # number of overall misses +system.l2c.overall_misses::cpu0.data 79753 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 67 # number of overall misses -system.l2c.overall_misses::cpu1.inst 10823 # number of overall misses -system.l2c.overall_misses::cpu1.data 75771 # number of overall misses -system.l2c.overall_misses::total 176585 # number of overall misses +system.l2c.overall_misses::cpu1.inst 10824 # number of overall misses +system.l2c.overall_misses::cpu1.data 75811 # number of overall misses +system.l2c.overall_misses::total 176582 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 5759000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 83500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 5729000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 11571500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 494500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 471000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 965500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 492500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 441500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 934000 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu0.data 285000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu1.data 200000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 485000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6150345000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5634905000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 11785250000 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 832598498 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 909265000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1741863498 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 619097000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 739733000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 1358830000 # number of ReadSharedReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6142757000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5641675000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 11784432000 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 833020998 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 909515500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1742536498 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 619108000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 739349500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 1358457500 # number of ReadSharedReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 5759000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 83500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 832598498 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 6769442000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 833020998 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 6761865000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 5729000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 909265000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 6374638000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 14897514998 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 909515500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 6381024500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 14896997498 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 5759000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 83500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 832598498 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 6769442000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 833020998 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 6761865000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 5729000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 909265000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 6374638000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 14897514998 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 35792 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 6853 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 36442 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6496 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 85583 # number of ReadReq accesses(hits+misses) -system.l2c.WritebackDirty_accesses::writebacks 702476 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 702476 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 1895131 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 1895131 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1511 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1355 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2866 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu1.inst 909515500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 6381024500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 14896997498 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 35704 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 6872 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 36416 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6520 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 85512 # number of ReadReq accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 702484 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 702484 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 1895251 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 1895251 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1509 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1353 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2862 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 50 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 43 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 93 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 154954 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 141795 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296749 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 961649 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 973355 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1935004 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 269647 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 286419 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 556066 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 35792 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6853 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 961649 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 424601 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 36442 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6496 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 973355 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 428214 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2873402 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 35792 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6853 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 961649 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 424601 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 36442 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6496 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 973355 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 428214 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2873402 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001732 # miss rate for ReadReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 155002 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 141755 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 296757 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 961912 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 973213 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1935125 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 269663 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 286395 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 556058 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 35704 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6872 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 961912 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 424665 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 36416 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6520 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 973213 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 428150 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2873452 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 35704 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6872 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 961912 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 424665 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 36416 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6520 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 973213 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 428150 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2873452 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001737 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000146 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001839 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.001519 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.948379 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.959410 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.953594 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001840 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.001520 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.948973 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.959350 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.953878 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.320000 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.186047 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.258065 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.469139 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.476498 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.472655 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.010465 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.011119 # miss rate for ReadCleanReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.468697 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.476936 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.472632 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.010462 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.011122 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::total 0.010794 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.026338 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.028650 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.027529 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001732 # miss rate for demand accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.026344 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.028642 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.027528 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001737 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000146 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.010465 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.187934 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001839 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.011119 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.176947 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.061455 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001732 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu0.inst 0.010462 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.187802 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001840 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.011122 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.177066 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.061453 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001737 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000146 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.010465 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.187934 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001839 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.011119 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.176947 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.061455 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.010462 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.187802 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001840 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.011122 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.177066 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.061453 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 92887.096774 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 83500 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 85507.462687 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 89011.538462 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 345.080251 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 362.307692 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 353.274790 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 343.924581 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 340.138675 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 342.124542 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17812.500000 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 25000 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 20208.333333 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84604.787124 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83399.763191 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 84024.311992 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82730.375397 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 84012.288645 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 83394.623354 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87172.205013 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90145.381428 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 88766.004703 # average ReadSharedReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84553.909896 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83446.855402 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 84020.277063 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82772.356717 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 84027.669993 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 83422.850345 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87149.211712 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90131.598196 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 88747.468478 # average ReadSharedReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 92887.096774 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 83500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 82730.375397 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 84833.289472 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 82772.356717 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 84785.086454 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85507.462687 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 84012.288645 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 84130.313708 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 84364.555302 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 84027.669993 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 84170.166599 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 84363.057945 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 92887.096774 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 83500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 82730.375397 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 84833.289472 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 82772.356717 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 84785.086454 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85507.462687 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 84012.288645 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 84130.313708 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 84364.555302 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 84027.669993 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 84170.166599 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 84363.057945 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 95305 # number of writebacks -system.l2c.writebacks::total 95305 # number of writebacks +system.l2c.writebacks::writebacks 95309 # number of writebacks +system.l2c.writebacks::total 95309 # number of writebacks system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 6 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 6 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits @@ -2342,37 +2342,37 @@ system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 62 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 67 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 130 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1433 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1300 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2733 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1432 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1298 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2730 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 16 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 8 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 24 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 72695 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 67565 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140260 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 72649 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 67608 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140257 # number of ReadExReq MSHR misses system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 10058 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 10817 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 20875 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 7028 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 8140 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 15168 # number of ReadSharedReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 10818 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 20876 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 7030 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 8137 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 15167 # number of ReadSharedReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 62 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.inst 10058 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 79723 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 79679 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 67 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 10817 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 75705 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 176433 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 10818 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 75745 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 176430 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 62 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.inst 10058 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 79723 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 79679 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 67 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 10817 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 75705 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 176433 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 10818 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 75745 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 176430 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 667 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16364 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14763 # number of ReadReq MSHR uncacheable @@ -2388,137 +2388,137 @@ system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5139000 system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 73500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 5059000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 10271500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 27285000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 24739000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 52024000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 27244500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 24670000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 51914500 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 360000 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 208500 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 568500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5423395000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4959255000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 10382650000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 731721998 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 800800501 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 1532522499 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 543441001 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 653257500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 1196698501 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5416267000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4965595000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 10381862000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 732144498 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 801041001 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1533185499 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 543432001 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 652904000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 1196336001 # number of ReadSharedReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 5139000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 73500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 731721998 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 5966836001 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 732144498 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 5959699001 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 5059000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 800800501 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 5612512500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 13122142500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 801041001 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 5618499000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 13121655000 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 5139000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 73500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 731721998 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 5966836001 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 732144498 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 5959699001 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 5059000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 800800501 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 5612512500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 13122142500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 801041001 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 5618499000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 13121655000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 43103498 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3103826000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2811200500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5958129998 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3103812500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2811194500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5958110498 # number of ReadReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 43103498 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3103826000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2811200500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5958129998 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001732 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3103812500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2811194500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5958110498 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001737 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000146 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001839 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.001519 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.948379 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.959410 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.953594 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001840 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.001520 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.948973 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.959350 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.953878 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.320000 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.186047 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.258065 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.469139 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.476498 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.472655 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.010459 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011113 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.468697 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.476936 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.472632 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.010456 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011116 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010788 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.026064 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.028420 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.027277 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001732 # mshr miss rate for demand accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.026070 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.028412 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.027276 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001737 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000146 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010459 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.187760 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001839 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011113 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.176792 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.061402 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001732 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010456 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.187628 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001840 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011116 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.176912 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.061400 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001737 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000146 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010459 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.187760 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001839 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011113 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.176792 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.061402 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010456 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.187628 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001840 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011116 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.176912 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.061400 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 82887.096774 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 73500 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75507.462687 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 79011.538462 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19040.474529 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19030 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19035.492133 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19025.488827 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19006.163328 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19016.300366 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 22500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 26062.500000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 23687.500000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74604.787124 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73399.763191 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 74024.311992 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72750.248360 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 74031.663215 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73414.251449 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77325.128201 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80252.764128 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 78896.261933 # average ReadSharedReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74553.909896 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73446.855402 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 74020.277063 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72792.254723 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 74047.051303 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73442.493725 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77301.849360 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80238.908689 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 78877.563196 # average ReadSharedReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82887.096774 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72750.248360 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74844.599438 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72792.254723 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74796.357899 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75507.462687 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74031.663215 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74136.615811 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 74374.649300 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74047.051303 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74176.500099 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 74373.150825 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82887.096774 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72750.248360 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74844.599438 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72792.254723 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74796.357899 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75507.462687 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74031.663215 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74136.615811 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 74374.649300 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74047.051303 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74176.500099 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 74373.150825 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64622.935532 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189674.040577 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190422.034817 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 187397.936655 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189673.215595 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190421.628395 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 187397.323331 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64622.935532 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96037.191745 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 106517.145347 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 100342.382667 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 356405 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 150205 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96036.774034 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 106516.918005 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 100342.054263 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 356400 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 150200 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 31794 # Transaction distribution system.membus.trans_dist::ReadResp 68215 # Transaction distribution system.membus.trans_dist::WriteReq 27584 # Transaction distribution system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::WritebackDirty 131465 # Transaction distribution -system.membus.trans_dist::CleanEvict 9298 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4631 # Transaction distribution +system.membus.trans_dist::WritebackDirty 131469 # Transaction distribution +system.membus.trans_dist::CleanEvict 9295 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4625 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 24 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 138363 # Transaction distribution @@ -2528,58 +2528,58 @@ system.membus.trans_dist::InvalidateReq 36194 # Tr system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 24 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 468976 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 576548 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 468971 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 576543 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72868 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72868 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 649416 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 649411 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 768 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17313116 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17477149 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17313372 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17477405 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315200 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2315200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19792349 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19792605 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 523 # Total snoops (count) -system.membus.snoop_fanout::samples 275014 # Request fanout histogram -system.membus.snoop_fanout::mean 0.019224 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.137313 # Request fanout histogram +system.membus.snoop_fanout::samples 275008 # Request fanout histogram +system.membus.snoop_fanout::mean 0.019225 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.137315 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 269727 98.08% 98.08% # Request fanout histogram +system.membus.snoop_fanout::0 269721 98.08% 98.08% # Request fanout histogram system.membus.snoop_fanout::1 5287 1.92% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 275014 # Request fanout histogram -system.membus.reqLayer0.occupancy 95656500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 275008 # Request fanout histogram +system.membus.reqLayer0.occupancy 95651000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18156 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1704498 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1701498 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 922039711 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 922033211 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1008874750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1008880500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 1321623 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -2611,84 +2611,84 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5615551 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2827345 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 47668 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 5615830 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2827503 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 47677 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 189 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 189 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 149135 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2640787 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 149204 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2640969 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 797781 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1934770 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 158854 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2867 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 797793 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1934891 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 158843 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2863 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 93 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2959 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296749 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296749 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1935422 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 556302 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2955 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296757 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296757 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1935543 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 556294 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 4761 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5806529 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2681416 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 36041 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 166883 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8690869 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 247708160 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99732253 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 53396 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 288936 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 347782745 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 141693 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3081386 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.027688 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.164077 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5806892 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2681408 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 36148 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 166774 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8691222 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 247723648 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99732765 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 53568 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 288480 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 347798461 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 141834 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3081573 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.027702 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.164119 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2996069 97.23% 97.23% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 85317 2.77% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2996206 97.23% 97.23% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 85367 2.77% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3081386 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5532635383 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3081573 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5532917883 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 308377 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2905951347 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2906129853 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1326155926 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1326155422 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 22725930 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 22791427 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 95104578 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 95110077 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3038 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index e65448f88..f2d1708bd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 47.355903 # Nu sim_ticks 47355903328000 # Number of ticks simulated final_tick 47355903328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 277163 # Simulator instruction rate (inst/s) -host_op_rate 325991 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14856975599 # Simulator tick rate (ticks/s) -host_mem_usage 813232 # Number of bytes of host memory used -host_seconds 3187.45 # Real time elapsed on the host +host_inst_rate 170836 # Simulator instruction rate (inst/s) +host_op_rate 200933 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9157476763 # Simulator tick rate (ticks/s) +host_mem_usage 772600 # Number of bytes of host memory used +host_seconds 5171.28 # Real time elapsed on the host sim_insts 883443630 # Number of instructions simulated sim_ops 1039082168 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -483,7 +483,7 @@ system.cpu0.dtb.flush_tlb 14 # Nu system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 39156 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 39092 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 2185 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 10307 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -574,7 +574,7 @@ system.cpu0.itb.flush_tlb 14 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 28333 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 28269 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1496,7 +1496,7 @@ system.cpu1.dtb.flush_tlb 14 # Nu system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 35846 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 35782 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 839 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 6709 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1587,7 +1587,7 @@ system.cpu1.itb.flush_tlb 14 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25383 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 25319 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 1618cff36..d15bd2bbc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.660653 # Nu sim_ticks 51660652947000 # Number of ticks simulated final_tick 51660652947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 288085 # Simulator instruction rate (inst/s) -host_op_rate 338513 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16013200726 # Simulator tick rate (ticks/s) -host_mem_usage 724944 # Number of bytes of host memory used -host_seconds 3226.13 # Real time elapsed on the host +host_inst_rate 170651 # Simulator instruction rate (inst/s) +host_op_rate 200523 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9485631865 # Simulator tick rate (ticks/s) +host_mem_usage 683504 # Number of bytes of host memory used +host_seconds 5446.20 # Real time elapsed on the host sim_insts 929398934 # Number of instructions simulated sim_ops 1092086880 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -438,7 +438,7 @@ system.cpu.dtb.flush_tlb 11 # Nu system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 78994 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 78930 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 1361 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 14910 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -524,7 +524,7 @@ system.cpu.itb.flush_tlb 11 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 56590 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 56526 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt index c78c1552c..fb27e7fcb 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.327140 # Nu sim_ticks 51327139864000 # Number of ticks simulated final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139208 # Simulator instruction rate (inst/s) -host_op_rate 163572 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8424230073 # Simulator tick rate (ticks/s) -host_mem_usage 729304 # Number of bytes of host memory used -host_seconds 6092.80 # Real time elapsed on the host +host_inst_rate 87448 # Simulator instruction rate (inst/s) +host_op_rate 102753 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5291966495 # Simulator tick rate (ticks/s) +host_mem_usage 687348 # Number of bytes of host memory used +host_seconds 9699.07 # Real time elapsed on the host sim_insts 848164321 # Number of instructions simulated sim_ops 996610207 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -423,7 +423,7 @@ system.cpu.checker.dtb.flush_tlb 20 # Nu system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 71788 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 71724 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.dtb.prefetch_faults 6683 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -493,7 +493,7 @@ system.cpu.checker.itb.flush_tlb 20 # Nu system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.itb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.itb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 51713 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_entries 51649 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -609,7 +609,7 @@ system.cpu.dtb.flush_tlb 20 # Nu system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 72102 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 72038 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 9776 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -718,7 +718,7 @@ system.cpu.itb.flush_tlb 20 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 52913 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 52849 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 10b007358..bdfed319a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 47.384315 # Nu sim_ticks 47384315163000 # Number of ticks simulated final_tick 47384315163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 162093 # Simulator instruction rate (inst/s) -host_op_rate 190619 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8503081814 # Simulator tick rate (ticks/s) -host_mem_usage 814268 # Number of bytes of host memory used -host_seconds 5572.60 # Real time elapsed on the host +host_inst_rate 151085 # Simulator instruction rate (inst/s) +host_op_rate 177673 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7925620115 # Simulator tick rate (ticks/s) +host_mem_usage 773240 # Number of bytes of host memory used +host_seconds 5978.63 # Real time elapsed on the host sim_insts 903281747 # Number of instructions simulated sim_ops 1062243320 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -471,7 +471,7 @@ system.cpu0.dtb.flush_tlb 14 # Nu system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 35541 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 35477 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 482 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 6442 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -582,7 +582,7 @@ system.cpu0.itb.flush_tlb 14 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25342 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 25278 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1797,7 +1797,7 @@ system.cpu1.dtb.flush_tlb 14 # Nu system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 40949 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 40885 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 397 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 6052 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1905,7 +1905,7 @@ system.cpu1.itb.flush_tlb 14 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 29991 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 29927 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index 7f31e0119..3c37d97cb 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.327140 # Nu sim_ticks 51327139864000 # Number of ticks simulated final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 184861 # Simulator instruction rate (inst/s) -host_op_rate 217215 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11186950873 # Simulator tick rate (ticks/s) -host_mem_usage 729056 # Number of bytes of host memory used -host_seconds 4588.13 # Real time elapsed on the host +host_inst_rate 138298 # Simulator instruction rate (inst/s) +host_op_rate 162502 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8369157499 # Simulator tick rate (ticks/s) +host_mem_usage 688884 # Number of bytes of host memory used +host_seconds 6132.89 # Real time elapsed on the host sim_insts 848164321 # Number of instructions simulated sim_ops 996610207 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -465,7 +465,7 @@ system.cpu.dtb.flush_tlb 10 # Nu system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 72102 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 72038 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 9776 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -574,7 +574,7 @@ system.cpu.itb.flush_tlb 10 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 52913 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 52849 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt index 037f2a987..e0d2d1c95 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111167 # Nu sim_ticks 51111167216500 # Number of ticks simulated final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1565564 # Simulator instruction rate (inst/s) -host_op_rate 1839875 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 81467630636 # Simulator tick rate (ticks/s) -host_mem_usage 722252 # Number of bytes of host memory used -host_seconds 627.38 # Real time elapsed on the host +host_inst_rate 974606 # Simulator instruction rate (inst/s) +host_op_rate 1145373 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50715816566 # Simulator tick rate (ticks/s) +host_mem_usage 678940 # Number of bytes of host memory used +host_seconds 1007.80 # Real time elapsed on the host sim_insts 982203438 # Number of instructions simulated sim_ops 1154301153 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -138,7 +138,7 @@ system.cpu.dtb.flush_tlb 11 # Nu system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 82503 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 82439 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 9079 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -208,7 +208,7 @@ system.cpu.itb.flush_tlb 11 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 58073 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 58009 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 3835eafd1..613ee48d7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 47.216815 # Nu sim_ticks 47216814802000 # Number of ticks simulated final_tick 47216814802000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1563637 # Simulator instruction rate (inst/s) -host_op_rate 1839381 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75563871924 # Simulator tick rate (ticks/s) -host_mem_usage 737620 # Number of bytes of host memory used -host_seconds 624.86 # Real time elapsed on the host +host_inst_rate 917426 # Simulator instruction rate (inst/s) +host_op_rate 1079212 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44335256452 # Simulator tick rate (ticks/s) +host_mem_usage 692848 # Number of bytes of host memory used +host_seconds 1064.99 # Real time elapsed on the host sim_insts 977053655 # Number of instructions simulated sim_ops 1149354696 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -169,7 +169,7 @@ system.cpu0.dtb.flush_tlb 16 # Nu system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 36369 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 36305 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 5198 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -239,7 +239,7 @@ system.cpu0.itb.flush_tlb 16 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25117 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 25053 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -725,7 +725,7 @@ system.cpu1.dtb.flush_tlb 16 # Nu system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 44858 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 44794 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 4450 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -795,7 +795,7 @@ system.cpu1.itb.flush_tlb 16 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 31512 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 31448 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index fa34e1384..95caaea31 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111167 # Nu sim_ticks 51111167216500 # Number of ticks simulated final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1675396 # Simulator instruction rate (inst/s) -host_op_rate 1968952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 87182982694 # Simulator tick rate (ticks/s) -host_mem_usage 718784 # Number of bytes of host memory used -host_seconds 586.25 # Real time elapsed on the host +host_inst_rate 967952 # Simulator instruction rate (inst/s) +host_op_rate 1137552 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50369548013 # Simulator tick rate (ticks/s) +host_mem_usage 676592 # Number of bytes of host memory used +host_seconds 1014.72 # Real time elapsed on the host sim_insts 982203438 # Number of instructions simulated sim_ops 1154301153 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -138,7 +138,7 @@ system.cpu.dtb.flush_tlb 11 # Nu system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 82503 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 82439 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 9079 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -208,7 +208,7 @@ system.cpu.itb.flush_tlb 11 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 58073 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 58009 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 7618e4e0a..7576c0a8a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 47.522770 # Nu sim_ticks 47522770414500 # Number of ticks simulated final_tick 47522770414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 967829 # Simulator instruction rate (inst/s) -host_op_rate 1138446 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52174728436 # Simulator tick rate (ticks/s) -host_mem_usage 796444 # Number of bytes of host memory used -host_seconds 910.84 # Real time elapsed on the host +host_inst_rate 594104 # Simulator instruction rate (inst/s) +host_op_rate 698838 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32027606991 # Simulator tick rate (ticks/s) +host_mem_usage 752504 # Number of bytes of host memory used +host_seconds 1483.81 # Real time elapsed on the host sim_insts 881535802 # Number of instructions simulated sim_ops 1036940641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -477,7 +477,7 @@ system.cpu0.dtb.flush_tlb 14 # Nu system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 37476 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 37412 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 4693 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -563,7 +563,7 @@ system.cpu0.itb.flush_tlb 14 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26626 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 26562 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1478,7 +1478,7 @@ system.cpu1.dtb.flush_tlb 14 # Nu system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 37178 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 37114 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 4820 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1570,7 +1570,7 @@ system.cpu1.itb.flush_tlb 14 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25875 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 25811 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index 86046cc23..04a520211 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.759374 # Nu sim_ticks 51759374264500 # Number of ticks simulated final_tick 51759374264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1051370 # Simulator instruction rate (inst/s) -host_op_rate 1235514 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65021013988 # Simulator tick rate (ticks/s) -host_mem_usage 718040 # Number of bytes of host memory used -host_seconds 796.04 # Real time elapsed on the host +host_inst_rate 622194 # Simulator instruction rate (inst/s) +host_op_rate 731170 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38479042536 # Simulator tick rate (ticks/s) +host_mem_usage 677104 # Number of bytes of host memory used +host_seconds 1345.13 # Real time elapsed on the host sim_insts 836933434 # Number of instructions simulated sim_ops 983519389 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -432,7 +432,7 @@ system.cpu.dtb.flush_tlb 10 # Nu system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 71001 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 70937 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 6932 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -520,7 +520,7 @@ system.cpu.itb.flush_tlb 10 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 50677 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 50613 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index 2c9d73210..505f419d1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111166 # Nu sim_ticks 51111166190000 # Number of ticks simulated final_tick 51111166190000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1663860 # Simulator instruction rate (inst/s) -host_op_rate 1955365 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 86501229007 # Simulator tick rate (ticks/s) -host_mem_usage 721112 # Number of bytes of host memory used -host_seconds 590.87 # Real time elapsed on the host +host_inst_rate 942692 # Simulator instruction rate (inst/s) +host_op_rate 1107850 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49008962729 # Simulator tick rate (ticks/s) +host_mem_usage 679656 # Number of bytes of host memory used +host_seconds 1042.89 # Real time elapsed on the host sim_insts 983128290 # Number of instructions simulated sim_ops 1155370468 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -156,7 +156,7 @@ system.cpu0.dtb.flush_tlb 51122 # Nu system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 25185 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 570 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 56806 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 56742 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 4849 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -226,7 +226,7 @@ system.cpu0.itb.flush_tlb 51122 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 25185 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 570 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 40500 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 40436 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -560,7 +560,7 @@ system.cpu1.dtb.flush_tlb 51111 # Nu system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 24586 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 569 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 56691 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 56630 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 4731 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -630,7 +630,7 @@ system.cpu1.itb.flush_tlb 51111 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 24586 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 569 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 41078 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 41017 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt index d32885727..d111f5f05 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.316243 # Nu sim_ticks 51316242679000 # Number of ticks simulated final_tick 51316242679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 414274 # Simulator instruction rate (inst/s) -host_op_rate 486791 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24763727262 # Simulator tick rate (ticks/s) -host_mem_usage 734172 # Number of bytes of host memory used -host_seconds 2072.23 # Real time elapsed on the host +host_inst_rate 261245 # Simulator instruction rate (inst/s) +host_op_rate 306975 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15616250138 # Simulator tick rate (ticks/s) +host_mem_usage 693224 # Number of bytes of host memory used +host_seconds 3286.08 # Real time elapsed on the host sim_insts 858473131 # Number of instructions simulated sim_ops 1008744567 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -373,10 +373,10 @@ system.physmem_1.preEnergy 539141625 # En system.physmem_1.readEnergy 1669683600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 1531975680 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3312965298240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1172484635445 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29689595916750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34179777578340 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.615263 # Core power per rank (mW) +system.physmem_1.actBackEnergy 1172482833105 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29689600432500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34179780291750 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.615252 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 48917806002648 # Time in different power states system.physmem_1.memoryStateTime::REF 1693745040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states @@ -470,7 +470,7 @@ system.cpu0.dtb.flush_tlb 1192 # Nu system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 16238 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 399 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 41149 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 41085 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 2806 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -542,7 +542,7 @@ system.cpu0.itb.flush_tlb 1192 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 16238 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 399 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 28999 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 28935 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1294,7 +1294,7 @@ system.cpu1.dtb.flush_tlb 1184 # Nu system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 5343 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 135 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 18131 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 18070 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 972 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1382,7 +1382,7 @@ system.cpu1.itb.flush_tlb 1184 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 5343 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 135 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 13509 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 13448 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1555,7 +1555,7 @@ system.cpu2.dtb.flush_tlb 1184 # Nu system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 6949 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 188 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 22306 # Number of entries that have been flushed from TLB +system.cpu2.dtb.flush_entries 22245 # Number of entries that have been flushed from TLB system.cpu2.dtb.align_faults 80 # Number of TLB faults due to alignment restrictions system.cpu2.dtb.prefetch_faults 2280 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1644,7 +1644,7 @@ system.cpu2.itb.flush_tlb 1184 # Nu system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 6949 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 188 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 16608 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 16547 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1849,7 +1849,7 @@ system.cpu3.dtb.flush_tlb 1184 # Nu system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu3.dtb.flush_tlb_mva_asid 11562 # Number of times TLB was flushed by MVA & ASID system.cpu3.dtb.flush_tlb_asid 307 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 29776 # Number of entries that have been flushed from TLB +system.cpu3.dtb.flush_entries 29715 # Number of entries that have been flushed from TLB system.cpu3.dtb.align_faults 81 # Number of TLB faults due to alignment restrictions system.cpu3.dtb.prefetch_faults 5087 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1958,7 +1958,7 @@ system.cpu3.itb.flush_tlb 1184 # Nu system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu3.itb.flush_tlb_mva_asid 11562 # Number of times TLB was flushed by MVA & ASID system.cpu3.itb.flush_tlb_asid 307 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 22881 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_entries 22821 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index b739037f9..b5baf9b71 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.317219 # Nu sim_ticks 51317219225000 # Number of ticks simulated final_tick 51317219225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 203116 # Simulator instruction rate (inst/s) -host_op_rate 238662 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11427931870 # Simulator tick rate (ticks/s) -host_mem_usage 741344 # Number of bytes of host memory used -host_seconds 4490.51 # Real time elapsed on the host +host_inst_rate 237803 # Simulator instruction rate (inst/s) +host_op_rate 279419 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13379498708 # Simulator tick rate (ticks/s) +host_mem_usage 700916 # Number of bytes of host memory used +host_seconds 3835.51 # Real time elapsed on the host sim_insts 912094204 # Number of instructions simulated sim_ops 1071714405 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -485,7 +485,7 @@ system.cpu0.dtb.flush_tlb 1081 # Nu system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 22090 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 55450 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 55386 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 172 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 9899 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -592,7 +592,7 @@ system.cpu0.itb.flush_tlb 1081 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 22090 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 40899 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 40835 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1491,7 +1491,7 @@ system.cpu1.dtb.flush_tlb 1089 # Nu system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 21973 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 55426 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 55362 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 199 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 9714 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1603,7 +1603,7 @@ system.cpu1.itb.flush_tlb 1089 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 21973 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 40809 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 40745 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt index 272c6e9a4..e35d19105 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.821000 # Nu sim_ticks 51820999867500 # Number of ticks simulated final_tick 51820999867500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1076689 # Simulator instruction rate (inst/s) -host_op_rate 1265246 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62402323103 # Simulator tick rate (ticks/s) -host_mem_usage 722120 # Number of bytes of host memory used -host_seconds 830.43 # Real time elapsed on the host +host_inst_rate 622691 # Simulator instruction rate (inst/s) +host_op_rate 731741 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36089691928 # Simulator tick rate (ticks/s) +host_mem_usage 680680 # Number of bytes of host memory used +host_seconds 1435.89 # Real time elapsed on the host sim_insts 894119248 # Number of instructions simulated sim_ops 1050702892 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -457,7 +457,7 @@ system.cpu0.dtb.flush_tlb 51828 # Nu system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 21506 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 536 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 73288 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 73224 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 4644 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -543,7 +543,7 @@ system.cpu0.itb.flush_tlb 51828 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 21506 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 536 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 53811 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 53747 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1158,7 +1158,7 @@ system.cpu1.dtb.flush_tlb 51822 # Nu system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 21521 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 531 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 74029 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 73965 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 4498 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1250,7 +1250,7 @@ system.cpu1.itb.flush_tlb 51822 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 21521 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 531 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 53985 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 53921 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |