diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-03-17 10:32:53 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-03-17 10:32:53 -0700 |
| commit | d7c083864c85c3ab24b40fc85ef3cae8031c5912 (patch) | |
| tree | ae575d831de5d67596ca3aae5e87a71f9c9fd1cd /tests/long | |
| parent | 9b4249410ec18cac9df2c7e9c0a4a6ce5459233d (diff) | |
| download | gem5-d7c083864c85c3ab24b40fc85ef3cae8031c5912.tar.xz | |
stats: update stats for ld.so support
Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
Diffstat (limited to 'tests/long')
16 files changed, 3705 insertions, 3723 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 67ec871cc..a4234efc5 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2016 19:53:43 -gem5 started Mar 15 2016 21:14:27 -gem5 executing on dinar2c11, pid 11560 +gem5 compiled Mar 16 2016 23:07:21 +gem5 started Mar 16 2016 23:48:20 +gem5 executing on dinar2c11, pid 25963 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -70,4 +70,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 233975583000 because target called exit() +Exiting @ tick 234067145000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 8f47426de..d56531c9c 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.233976 # Number of seconds simulated -sim_ticks 233975583000 # Number of ticks simulated -final_tick 233975583000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.234067 # Number of seconds simulated +sim_ticks 234067145000 # Number of ticks simulated +final_tick 234067145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86832 # Simulator instruction rate (inst/s) -host_op_rate 94070 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40212079 # Simulator tick rate (ticks/s) -host_mem_usage 330216 # Number of bytes of host memory used -host_seconds 5818.54 # Real time elapsed on the host -sim_insts 505237724 # Number of instructions simulated -sim_ops 547350945 # Number of ops (including micro ops) simulated +host_inst_rate 77703 # Simulator instruction rate (inst/s) +host_op_rate 84180 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35998538 # Simulator tick rate (ticks/s) +host_mem_usage 329176 # Number of bytes of host memory used +host_seconds 6502.13 # Real time elapsed on the host +sim_insts 505234934 # Number of instructions simulated +sim_ops 547348155 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 519680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10101184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16452992 # Number of bytes read from this memory -system.physmem.bytes_read::total 27073856 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 519680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 519680 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18693440 # Number of bytes written to this memory -system.physmem.bytes_written::total 18693440 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8120 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 157831 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 257078 # Number of read requests responded to by this memory -system.physmem.num_reads::total 423029 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292085 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292085 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2221086 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 43171958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 70319269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 115712313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2221086 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2221086 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 79894832 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 79894832 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 79894832 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2221086 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 43171958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 70319269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 195607146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 423029 # Number of read requests accepted -system.physmem.writeReqs 292085 # Number of write requests accepted -system.physmem.readBursts 423029 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292085 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26921664 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 152192 # Total number of bytes read from write queue -system.physmem.bytesWritten 18690816 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27073856 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18693440 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2378 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 12 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 528384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10113344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16488320 # Number of bytes read from this memory +system.physmem.bytes_read::total 27130048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 528384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 528384 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18753344 # Number of bytes written to this memory +system.physmem.bytes_written::total 18753344 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8256 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158021 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 257630 # Number of read requests responded to by this memory +system.physmem.num_reads::total 423907 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293021 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293021 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2257404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 43207021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70442693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 115907117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2257404 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2257404 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 80119506 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 80119506 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 80119506 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2257404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 43207021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70442693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 196026623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 423907 # Number of read requests accepted +system.physmem.writeReqs 293021 # Number of write requests accepted +system.physmem.readBursts 423907 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 293021 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26979584 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 150464 # Total number of bytes read from write queue +system.physmem.bytesWritten 18751744 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27130048 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18753344 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2351 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26587 # Per bank write bursts -system.physmem.perBankRdBursts::1 25566 # Per bank write bursts -system.physmem.perBankRdBursts::2 25266 # Per bank write bursts -system.physmem.perBankRdBursts::3 32149 # Per bank write bursts -system.physmem.perBankRdBursts::4 27127 # Per bank write bursts -system.physmem.perBankRdBursts::5 28227 # Per bank write bursts -system.physmem.perBankRdBursts::6 25084 # Per bank write bursts -system.physmem.perBankRdBursts::7 24199 # Per bank write bursts -system.physmem.perBankRdBursts::8 25413 # Per bank write bursts -system.physmem.perBankRdBursts::9 25760 # Per bank write bursts -system.physmem.perBankRdBursts::10 25321 # Per bank write bursts -system.physmem.perBankRdBursts::11 26053 # Per bank write bursts -system.physmem.perBankRdBursts::12 27496 # Per bank write bursts -system.physmem.perBankRdBursts::13 25872 # Per bank write bursts -system.physmem.perBankRdBursts::14 24848 # Per bank write bursts -system.physmem.perBankRdBursts::15 25683 # Per bank write bursts -system.physmem.perBankWrBursts::0 18549 # Per bank write bursts -system.physmem.perBankWrBursts::1 18359 # Per bank write bursts -system.physmem.perBankWrBursts::2 17952 # Per bank write bursts -system.physmem.perBankWrBursts::3 17851 # Per bank write bursts -system.physmem.perBankWrBursts::4 18559 # Per bank write bursts -system.physmem.perBankWrBursts::5 18328 # Per bank write bursts -system.physmem.perBankWrBursts::6 17864 # Per bank write bursts -system.physmem.perBankWrBursts::7 17725 # Per bank write bursts -system.physmem.perBankWrBursts::8 17897 # Per bank write bursts -system.physmem.perBankWrBursts::9 17869 # Per bank write bursts -system.physmem.perBankWrBursts::10 18218 # Per bank write bursts -system.physmem.perBankWrBursts::11 18760 # Per bank write bursts -system.physmem.perBankWrBursts::12 18894 # Per bank write bursts -system.physmem.perBankWrBursts::13 18283 # Per bank write bursts -system.physmem.perBankWrBursts::14 18348 # Per bank write bursts -system.physmem.perBankWrBursts::15 18588 # Per bank write bursts +system.physmem.perBankRdBursts::0 26590 # Per bank write bursts +system.physmem.perBankRdBursts::1 25594 # Per bank write bursts +system.physmem.perBankRdBursts::2 25276 # Per bank write bursts +system.physmem.perBankRdBursts::3 32211 # Per bank write bursts +system.physmem.perBankRdBursts::4 27176 # Per bank write bursts +system.physmem.perBankRdBursts::5 28517 # Per bank write bursts +system.physmem.perBankRdBursts::6 25342 # Per bank write bursts +system.physmem.perBankRdBursts::7 24044 # Per bank write bursts +system.physmem.perBankRdBursts::8 25598 # Per bank write bursts +system.physmem.perBankRdBursts::9 25550 # Per bank write bursts +system.physmem.perBankRdBursts::10 25481 # Per bank write bursts +system.physmem.perBankRdBursts::11 26074 # Per bank write bursts +system.physmem.perBankRdBursts::12 27377 # Per bank write bursts +system.physmem.perBankRdBursts::13 26182 # Per bank write bursts +system.physmem.perBankRdBursts::14 25062 # Per bank write bursts +system.physmem.perBankRdBursts::15 25482 # Per bank write bursts +system.physmem.perBankWrBursts::0 18771 # Per bank write bursts +system.physmem.perBankWrBursts::1 18326 # Per bank write bursts +system.physmem.perBankWrBursts::2 17966 # Per bank write bursts +system.physmem.perBankWrBursts::3 17954 # Per bank write bursts +system.physmem.perBankWrBursts::4 18603 # Per bank write bursts +system.physmem.perBankWrBursts::5 18522 # Per bank write bursts +system.physmem.perBankWrBursts::6 18156 # Per bank write bursts +system.physmem.perBankWrBursts::7 17645 # Per bank write bursts +system.physmem.perBankWrBursts::8 18039 # Per bank write bursts +system.physmem.perBankWrBursts::9 17820 # Per bank write bursts +system.physmem.perBankWrBursts::10 18389 # Per bank write bursts +system.physmem.perBankWrBursts::11 18735 # Per bank write bursts +system.physmem.perBankWrBursts::12 18802 # Per bank write bursts +system.physmem.perBankWrBursts::13 18436 # Per bank write bursts +system.physmem.perBankWrBursts::14 18499 # Per bank write bursts +system.physmem.perBankWrBursts::15 18333 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 233975530500 # Total gap between requests +system.physmem.totGap 234067092500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 423029 # Read request sizes (log2) +system.physmem.readPktSize::6 423907 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292085 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 323238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 49503 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12846 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6055 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 74 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 36 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293021 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 324297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 49438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12772 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8887 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6051 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 79 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 41 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -148,34 +148,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 19060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 14936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 19091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -197,112 +197,111 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 321539 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 141.852976 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 99.721857 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 179.991773 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 202400 62.95% 62.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 79393 24.69% 87.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15074 4.69% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7330 2.28% 94.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4928 1.53% 96.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2561 0.80% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1887 0.59% 97.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1542 0.48% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6424 2.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 321539 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17050 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.666979 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 143.647395 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17048 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 323145 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 141.515567 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 99.534760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 179.780407 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 203801 63.07% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 79524 24.61% 87.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15124 4.68% 92.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7403 2.29% 94.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4958 1.53% 96.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2458 0.76% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1821 0.56% 97.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1542 0.48% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6514 2.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 323145 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17117 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.623824 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 142.773249 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17115 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17050 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17050 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.128680 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.068427 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.524733 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 9277 54.41% 54.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 307 1.80% 56.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5331 31.27% 87.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1349 7.91% 95.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 375 2.20% 97.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 167 0.98% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 95 0.56% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 68 0.40% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 36 0.21% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 15 0.09% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 9 0.05% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 5 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 3 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 2 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 3 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17117 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17117 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.117252 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.059352 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.476775 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 9319 54.44% 54.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 336 1.96% 56.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5339 31.19% 87.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1368 7.99% 95.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 375 2.19% 97.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 151 0.88% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 90 0.53% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 54 0.32% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 43 0.25% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 14 0.08% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 11 0.06% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 3 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 5 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 2 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.01% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::35 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17050 # Writes before turning the bus around for reads -system.physmem.totQLat 8699002486 # Total ticks spent queuing -system.physmem.totMemAccLat 16586208736 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2103255000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20679.86 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::36 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 2 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17117 # Writes before turning the bus around for reads +system.physmem.totQLat 8655442270 # Total ticks spent queuing +system.physmem.totMemAccLat 16559617270 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2107780000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20532.13 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39429.86 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 115.06 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 79.88 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 115.71 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 79.89 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39282.13 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 115.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 80.11 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 115.91 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 80.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.52 # Data bus utilization in percentage +system.physmem.busUtil 1.53 # Data bus utilization in percentage system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.61 # Average write queue length when enqueuing -system.physmem.readRowHits 305767 # Number of row buffer hits during reads -system.physmem.writeRowHits 85381 # Number of row buffer hits during writes -system.physmem.readRowHitRate 72.69 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.23 # Row buffer hit rate for writes -system.physmem.avgGap 327186.34 # Average gap between requests -system.physmem.pageHitRate 54.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1223691840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 667689000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1670487000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 940811760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15281719440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 82095857685 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 68367661500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 170247918225 # Total energy per rank (pJ) -system.physmem_0.averagePower 727.650714 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 113204918849 # Time in different power states -system.physmem_0.memoryStateTime::REF 7812740000 # Time in different power states +system.physmem.avgWrQLen 21.74 # Average write queue length when enqueuing +system.physmem.readRowHits 306165 # Number of row buffer hits during reads +system.physmem.writeRowHits 85234 # Number of row buffer hits during writes +system.physmem.readRowHitRate 72.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 29.09 # Row buffer hit rate for writes +system.physmem.avgGap 326486.19 # Average gap between requests +system.physmem.pageHitRate 54.77 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1230881400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 671611875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1674738000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 945710640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15287822160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 82093251645 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 68426008500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 170330024220 # Total energy per rank (pJ) +system.physmem_0.averagePower 727.711031 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 113299566780 # Time in different power states +system.physmem_0.memoryStateTime::REF 7815860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 112953795651 # Time in different power states +system.physmem_0.memoryStateTime::ACT 112947723720 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1207044720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 658605750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1610044800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 951633360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15281719440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79725813930 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 70446639000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 169881501000 # Total energy per rank (pJ) -system.physmem_1.averagePower 726.084666 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 116677189668 # Time in different power states -system.physmem_1.memoryStateTime::REF 7812740000 # Time in different power states +system.physmem_1.actEnergy 1211996520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 661307625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1612860600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 952903440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15287822160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 79567358490 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 70641696000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 169935944835 # Total energy per rank (pJ) +system.physmem_1.averagePower 726.027425 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 117000888833 # Time in different power states +system.physmem_1.memoryStateTime::REF 7815860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 109482083332 # Time in different power states +system.physmem_1.memoryStateTime::ACT 109246895167 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 175127231 # Number of BP lookups -system.cpu.branchPred.condPredicted 131371482 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7444734 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90531038 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83892410 # Number of BTB hits +system.cpu.branchPred.lookups 175180766 # Number of BP lookups +system.cpu.branchPred.condPredicted 131398582 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7457767 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90448674 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83962981 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.667014 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12111505 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104166 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.829422 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12120591 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 103810 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -421,129 +420,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 467951167 # number of cpu cycles simulated +system.cpu.numCycles 468134291 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7807571 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 731933483 # Number of instructions fetch has processed -system.cpu.fetch.Branches 175127231 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 96003915 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 452021991 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14942209 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5420 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 243 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 11591 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 236759344 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34037 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 467317920 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.696233 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.181442 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7820267 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 732116673 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175180766 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 96083572 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 452171073 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14968467 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 4602 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 73 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 11985 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 236801931 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34000 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 467492233 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.696108 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.181518 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95319924 20.40% 20.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132721002 28.40% 48.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57871857 12.38% 61.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 181405137 38.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95390302 20.40% 20.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132755119 28.40% 48.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57878050 12.38% 61.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 181468762 38.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 467317920 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.374243 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.564124 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32360208 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 118941905 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 286956233 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22076930 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6982644 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24050421 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 496163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 715840292 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 30013840 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6982644 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63442941 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 55755110 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40375220 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276571280 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24190725 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 686624983 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13341882 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9442632 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2386991 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1673870 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1900758 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 831052151 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3019309313 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 723953553 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 176928400 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1544708 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1535125 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42420493 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 143531079 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67984063 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12865529 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11219958 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 668189770 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2978336 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 610255971 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5862329 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 123817161 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 319322709 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 704 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 467317920 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.305869 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.102065 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 467492233 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.374210 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.563903 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32386715 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 118994468 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 287021244 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22094342 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6995464 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24069927 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 496423 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 716090334 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 30070891 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6995464 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63523233 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 55798726 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40379426 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276600311 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24195073 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 686795271 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13387267 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9456751 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2380300 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1659301 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1902126 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 831315383 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3020004146 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 724106734 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 424 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 177219709 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1544715 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1534907 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42449008 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 143548530 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67987102 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12901487 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11312004 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 668319179 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2978345 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 610345579 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5883396 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 123949369 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 319552681 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 713 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 467492233 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.305574 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.102144 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 150163836 32.13% 32.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 101159501 21.65% 53.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145796763 31.20% 84.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63288828 13.54% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6908500 1.48% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 492 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 150289114 32.15% 32.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 101200175 21.65% 53.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145769872 31.18% 84.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63327215 13.55% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6905270 1.48% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 587 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 467317920 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 467492233 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71905236 52.96% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44555950 32.82% 85.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19306846 14.22% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71934630 52.97% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44579938 32.83% 85.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19275701 14.20% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413151233 67.70% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 351795 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413246027 67.71% 67.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 352054 0.06% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued @@ -571,94 +570,94 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 134217204 21.99% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62535736 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 134225887 21.99% 89.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62521608 10.24% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 610255971 # Type of FU issued -system.cpu.iq.rate 1.304102 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135768062 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222477 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1829459960 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 795013485 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594984726 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 610345579 # Type of FU issued +system.cpu.iq.rate 1.303783 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135790299 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222481 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1829856789 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 795275233 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 595043365 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 297 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 322 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 746023856 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7274448 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 746135699 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 179 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7278929 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27646323 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25541 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28976 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11123586 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27665247 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25667 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29087 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11126882 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 225332 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22431 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 224857 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22662 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6982644 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22928683 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 924923 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 672655804 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6995464 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22964751 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 919913 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 672785382 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 143531079 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67984063 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1489794 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 258689 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 530260 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28976 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3822816 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3731718 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7554534 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599400071 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129576716 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10855900 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 143548530 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67987102 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1489803 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 257985 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 525401 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29087 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3817186 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3742282 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7559468 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599464871 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129581939 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10880708 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1487698 # number of nop insts executed -system.cpu.iew.exec_refs 190533409 # number of memory reference insts executed -system.cpu.iew.exec_branches 131373584 # Number of branches executed -system.cpu.iew.exec_stores 60956693 # Number of stores executed -system.cpu.iew.exec_rate 1.280903 # Inst execution rate -system.cpu.iew.wb_sent 596279806 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594984742 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349898988 # num instructions producing a value -system.cpu.iew.wb_consumers 570632014 # num instructions consuming a value -system.cpu.iew.wb_rate 1.271468 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.613178 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 110042423 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1487858 # number of nop insts executed +system.cpu.iew.exec_refs 190527023 # number of memory reference insts executed +system.cpu.iew.exec_branches 131393815 # Number of branches executed +system.cpu.iew.exec_stores 60945084 # Number of stores executed +system.cpu.iew.exec_rate 1.280540 # Inst execution rate +system.cpu.iew.wb_sent 596341042 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 595043381 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349946127 # num instructions producing a value +system.cpu.iew.wb_consumers 570674546 # num instructions consuming a value +system.cpu.iew.wb_rate 1.271095 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.613215 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 110160125 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6956274 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 450200687 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.218778 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.886375 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6968998 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 450355888 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.218352 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.886219 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 221166453 49.13% 49.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116327626 25.84% 74.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43750418 9.72% 84.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23323090 5.18% 89.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11527236 2.56% 92.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7779283 1.73% 94.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8247237 1.83% 95.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4226436 0.94% 96.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13852908 3.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 221337598 49.15% 49.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116324478 25.83% 74.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43749692 9.71% 84.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23265748 5.17% 89.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11567595 2.57% 92.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7783316 1.73% 94.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8242109 1.83% 95.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4251497 0.94% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13833855 3.07% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 450200687 # Number of insts commited each cycle -system.cpu.commit.committedInsts 506581608 # Number of instructions committed -system.cpu.commit.committedOps 548694829 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 450355888 # Number of insts commited each cycle +system.cpu.commit.committedInsts 506578818 # Number of instructions committed +system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 172745233 # Number of memory references committed -system.cpu.commit.loads 115884756 # Number of loads committed +system.cpu.commit.refs 172743503 # Number of memory references committed +system.cpu.commit.loads 115883283 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 121548302 # Number of branches committed +system.cpu.commit.branches 121552863 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 448454354 # Number of committed integer instructions. +system.cpu.commit.int_insts 448447003 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 375610374 68.46% 68.46% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 375609314 68.46% 68.46% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction @@ -687,398 +686,394 @@ system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 56860220 10.36% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 548694829 # Class of committed instruction -system.cpu.commit.bw_lim_events 13852908 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1095077893 # The number of ROB reads -system.cpu.rob.rob_writes 1334621527 # The number of ROB writes -system.cpu.timesIdled 12496 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 633247 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 505237724 # Number of Instructions Simulated -system.cpu.committedOps 547350945 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.926200 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.926200 # CPI: Total CPI of All Threads -system.cpu.ipc 1.079680 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.079680 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 611089815 # number of integer regfile reads -system.cpu.int_regfile_writes 328120494 # number of integer regfile writes +system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction +system.cpu.commit.bw_lim_events 13833855 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1095367059 # The number of ROB reads +system.cpu.rob.rob_writes 1334871218 # The number of ROB writes +system.cpu.timesIdled 12751 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 642058 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 505234934 # Number of Instructions Simulated +system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.926568 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.926568 # CPI: Total CPI of All Threads +system.cpu.ipc 1.079252 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.079252 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 611137722 # number of integer regfile reads +system.cpu.int_regfile_writes 328167949 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2170189724 # number of cc regfile reads -system.cpu.cc_regfile_writes 376542500 # number of cc regfile writes -system.cpu.misc_regfile_reads 217973496 # number of misc regfile reads +system.cpu.cc_regfile_reads 2170388141 # number of cc regfile reads +system.cpu.cc_regfile_writes 376631000 # number of cc regfile writes +system.cpu.misc_regfile_reads 217967292 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2820720 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.629803 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 169353985 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2821232 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 60.028379 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2817526 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.629948 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169361200 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2818038 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 60.098977 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 500883000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.629803 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.629948 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 356246516 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 356246516 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114648880 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114648880 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51725160 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51725160 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2783 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2783 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 356245262 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 356245262 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114657971 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114657971 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51723280 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51723280 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2781 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2781 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488558 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488558 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 166374040 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166374040 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 166376823 # number of overall hits -system.cpu.dcache.overall_hits::total 166376823 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4844495 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4844495 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2514146 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2514146 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 166381251 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166381251 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 166384032 # number of overall hits +system.cpu.dcache.overall_hits::total 166384032 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4836633 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4836633 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2515769 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2515769 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 67 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 67 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7358641 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7358641 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7358653 # number of overall misses -system.cpu.dcache.overall_misses::total 7358653 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57544876000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57544876000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18904875439 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18904875439 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 941000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 941000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 76449751439 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 76449751439 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 76449751439 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 76449751439 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119493375 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119493375 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2795 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2795 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7352402 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7352402 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7352414 # number of overall misses +system.cpu.dcache.overall_misses::total 7352414 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57448748500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57448748500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18924298425 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18924298425 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 887000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 887000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 76373046925 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 76373046925 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 76373046925 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 76373046925 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119494604 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119494604 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2793 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2793 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173732681 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173732681 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173735476 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173735476 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040542 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040542 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046353 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046353 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004293 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.004293 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173733653 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173733653 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173736446 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173736446 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040476 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040476 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046383 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046383 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004296 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.004296 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000045 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000045 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042356 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042356 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042356 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042356 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11878.405489 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11878.405489 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7519.402389 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7519.402389 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14044.776119 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14044.776119 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10389.112805 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10389.112805 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10389.095863 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10389.095863 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 904831 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.042320 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042320 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042319 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042319 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11877.839088 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11877.839088 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7522.271888 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7522.271888 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13238.805970 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13238.805970 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10387.496076 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10387.496076 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10387.479123 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10387.479123 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 910856 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221213 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.090316 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 221280 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.116305 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2820720 # number of writebacks -system.cpu.dcache.writebacks::total 2820720 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2542826 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2542826 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1994565 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1994565 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2817526 # number of writebacks +system.cpu.dcache.writebacks::total 2817526 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2538406 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2538406 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1995936 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1995936 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 67 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 67 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4537391 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4537391 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4537391 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4537391 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301669 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2301669 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519581 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519581 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4534342 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4534342 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4534342 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4534342 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2298227 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2298227 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519833 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519833 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2821250 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2821250 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2821260 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2821260 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29551116000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29551116000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4600493494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4600493494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 704500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 704500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34151609494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 34151609494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34152313994 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 34152313994 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019262 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019262 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009579 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009579 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003578 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003578 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016239 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016239 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016239 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016239 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12838.994660 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12838.994660 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8854.237345 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8854.237345 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70450 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70450 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12105.134070 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12105.134070 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12105.340874 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12105.340874 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_misses::cpu.data 2818060 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2818060 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2818070 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2818070 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29530364500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29530364500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603208492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4603208492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 671000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 671000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34133572992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 34133572992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34134243992 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 34134243992 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019233 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019233 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009584 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009584 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003580 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003580 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016221 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016221 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016220 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016220 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12849.193966 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12849.193966 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8855.167894 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8855.167894 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 67100 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 67100 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12112.436567 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12112.436567 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12112.631692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12112.631692 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 73492 # number of replacements -system.cpu.icache.tags.tagsinuse 466.319606 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 236677467 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 74004 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3198.171275 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 115561804500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 466.319606 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.910780 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.910780 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu.icache.tags.replacements 73421 # number of replacements +system.cpu.icache.tags.tagsinuse 466.150305 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 236720018 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 73932 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3201.861413 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 115595672500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 466.150305 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.910450 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.910450 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 16 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 473592523 # Number of tag accesses -system.cpu.icache.tags.data_accesses 473592523 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 236677467 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 236677467 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 236677467 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 236677467 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 236677467 # number of overall hits -system.cpu.icache.overall_hits::total 236677467 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 81779 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 81779 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 81779 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 81779 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 81779 # number of overall misses -system.cpu.icache.overall_misses::total 81779 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1323960223 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1323960223 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1323960223 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1323960223 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1323960223 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1323960223 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 236759246 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 236759246 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 236759246 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 236759246 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 236759246 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 236759246 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000345 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000345 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000345 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000345 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000345 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000345 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16189.489025 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16189.489025 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16189.489025 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16189.489025 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16189.489025 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16189.489025 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 155623 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6523 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 23.857581 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 23.750000 # average number of cycles each access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 473677631 # Number of tag accesses +system.cpu.icache.tags.data_accesses 473677631 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 236720018 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 236720018 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 236720018 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 236720018 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 236720018 # number of overall hits +system.cpu.icache.overall_hits::total 236720018 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 81816 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 81816 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 81816 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 81816 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 81816 # number of overall misses +system.cpu.icache.overall_misses::total 81816 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1337252702 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1337252702 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1337252702 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1337252702 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1337252702 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1337252702 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 236801834 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 236801834 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 236801834 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 236801834 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 236801834 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 236801834 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000346 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000346 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000346 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000346 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000346 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000346 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16344.635548 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16344.635548 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16344.635548 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16344.635548 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16344.635548 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16344.635548 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 158150 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 252 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6634 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 23.839313 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 50.400000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 73492 # number of writebacks -system.cpu.icache.writebacks::total 73492 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7746 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 7746 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 7746 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 7746 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 7746 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 7746 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74033 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 74033 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 74033 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 74033 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 74033 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 74033 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1098365314 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1098365314 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1098365314 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1098365314 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1098365314 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1098365314 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14836.158389 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14836.158389 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14836.158389 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14836.158389 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14836.158389 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14836.158389 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 73421 # number of writebacks +system.cpu.icache.writebacks::total 73421 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7851 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 7851 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 7851 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 7851 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 7851 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 7851 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 73965 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 73965 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 73965 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 73965 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 73965 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 73965 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1106045298 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1106045298 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1106045298 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1106045298 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1106045298 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1106045298 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000312 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000312 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000312 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000312 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000312 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000312 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14953.630744 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14953.630744 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14953.630744 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14953.630744 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14953.630744 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14953.630744 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 8513149 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 8514588 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 439 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 8512826 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 8514409 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 561 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 743612 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 395043 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15130.846704 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3180527 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 410976 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.738960 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 170568441000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 13790.709252 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 0.000317 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1340.137135 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.841718 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.081795 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.923514 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 1071 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14862 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 25 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 244 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 802 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4899 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6238 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3369 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.065369 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.907104 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 94912633 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 94912633 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 2358534 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2358534 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 511979 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 511979 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 516918 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 516918 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 65874 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 65874 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2140936 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 2140936 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 65874 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2657854 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2723728 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 65874 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2657854 # number of overall hits -system.cpu.l2cache.overall_hits::total 2723728 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 27 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 27 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 5055 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 5055 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8128 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 8128 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 158323 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 158323 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 8128 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 163378 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 171506 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 8128 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 163378 # number of overall misses -system.cpu.l2cache.overall_misses::total 171506 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 60000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 60000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 483012500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 483012500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 589814000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 589814000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12070914500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 12070914500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 589814000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12553927000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13143741000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 589814000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12553927000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13143741000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2358534 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2358534 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 511979 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 511979 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 28 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 28 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 521973 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 521973 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 74002 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 74002 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2299259 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 2299259 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 74002 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2821232 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2895234 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 74002 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2821232 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2895234 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.964286 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.964286 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009684 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.009684 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.109835 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.109835 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.068858 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.068858 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.109835 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.057910 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.059237 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.109835 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.057910 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.059237 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2222.222222 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2222.222222 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95551.434224 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95551.434224 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72565.698819 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72565.698819 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76242.330552 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76242.330552 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72565.698819 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76839.764228 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76637.208028 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72565.698819 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76839.764228 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76637.208028 # average overall miss latency +system.cpu.l2cache.prefetcher.pfSpanPage 743711 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 395988 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15132.629454 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3179530 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 411918 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.718842 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 170668253000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 13783.431676 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1349.197778 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.841274 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.082348 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.923622 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 1007 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 14923 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 36 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 235 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 736 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4874 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6268 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3420 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.061462 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.910828 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 94799517 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 94799517 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 2352015 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2352015 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 515062 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 515062 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 517153 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 517153 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 65667 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 65667 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2137304 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 2137304 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 65667 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2654457 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2720124 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 65667 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2654457 # number of overall hits +system.cpu.l2cache.overall_hits::total 2720124 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 32 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 32 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 5060 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 5060 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8262 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 8262 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 158521 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 158521 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 8262 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 163581 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 171843 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 8262 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 163581 # number of overall misses +system.cpu.l2cache.overall_misses::total 171843 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 104000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 104000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 481607500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 481607500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 598906500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 598906500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12080001500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 12080001500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 598906500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12561609000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13160515500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 598906500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12561609000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13160515500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2352015 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2352015 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 515062 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 515062 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 32 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 32 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 522213 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 522213 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 73929 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 73929 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295825 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 2295825 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 73929 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2818038 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2891967 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 73929 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2818038 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2891967 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009690 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.009690 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.111756 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.111756 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.069048 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.069048 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.111756 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.058048 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.059421 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.111756 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.058048 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.059421 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 3250 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 3250 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95179.347826 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95179.347826 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72489.288308 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72489.288308 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76204.424020 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76204.424020 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72489.288308 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76791.369413 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76584.530647 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72489.288308 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76791.369413 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76584.530647 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1087,158 +1082,158 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 292085 # number of writebacks -system.cpu.l2cache.writebacks::total 292085 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1398 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1398 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 7 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4146 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4146 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 7 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 5544 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 5551 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 7 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 5544 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 5551 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 351023 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 351023 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 27 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 27 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3657 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3657 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8121 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8121 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 154177 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 154177 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 8121 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 157834 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165955 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 8121 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 157834 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 351023 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 516978 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18646833753 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18646833753 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 389000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 389000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 334746500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 334746500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 540727000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 540727000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10842464500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10842464500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 540727000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11177211000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11717938000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 540727000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11177211000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18646833753 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30364771753 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 293021 # number of writebacks +system.cpu.l2cache.writebacks::total 293021 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1390 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1390 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4166 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4166 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 5556 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 5561 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 5556 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 5561 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 350786 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 350786 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 32 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 32 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3670 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3670 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8257 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8257 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 154355 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 154355 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8257 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158025 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166282 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8257 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158025 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 350786 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 517068 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18631455358 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18631455358 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 467000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 467000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 333539000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 333539000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 549061000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 549061000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10851655500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10851655500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 549061000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11185194500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11734255500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 549061000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11185194500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18631455358 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30365710858 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.964286 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.964286 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007006 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007006 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.109740 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.109740 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067055 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067055 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.109740 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055945 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.057320 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.109740 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055945 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007028 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007028 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.111688 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.111688 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067233 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067233 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.111688 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056076 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.057498 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.111688 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056076 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.178562 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53121.401598 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53121.401598 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14407.407407 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14407.407407 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91535.821712 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91535.821712 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66583.795099 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66583.795099 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70324.785798 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70324.785798 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66583.795099 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70816.243648 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70609.128981 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66583.795099 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70816.243648 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53121.401598 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58735.133319 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.178795 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53113.451956 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53113.451956 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14593.750000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14593.750000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 90882.561308 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 90882.561308 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66496.427274 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66496.427274 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70303.232807 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70303.232807 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66496.427274 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70781.170701 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70568.404878 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66496.427274 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70781.170701 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53113.451956 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58726.726191 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5789505 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894253 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23731 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 260682 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244671 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16011 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 2373290 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2650619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 535678 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 265254 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 392218 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 5782982 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2890992 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 260193 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244256 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15937 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 2369788 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2645036 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 538932 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 265577 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 391986 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 28 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 28 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 521973 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 521973 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 74033 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299259 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 221525 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8463241 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8684766 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9439488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361084992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 370524480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 949589 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3844850 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.078147 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.283493 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 32 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 32 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 522213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 522213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 73965 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295825 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 221313 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8453667 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8674980 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9430272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360676160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 370106432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 950621 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3842619 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.078093 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.283354 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3560398 92.60% 92.60% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 268441 6.98% 99.58% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 16011 0.42% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3558474 92.61% 92.61% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 268208 6.98% 99.59% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 15937 0.41% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3844850 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5788964505 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3842619 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5782438005 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 111128336 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 111022344 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4231881960 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4227098948 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.trans_dist::ReadResp 419375 # Transaction distribution -system.membus.trans_dist::WritebackDirty 292085 # Transaction distribution -system.membus.trans_dist::CleanEvict 98517 # Transaction distribution -system.membus.trans_dist::UpgradeReq 31 # Transaction distribution -system.membus.trans_dist::ReadExReq 3653 # Transaction distribution -system.membus.trans_dist::ReadExResp 3653 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 419376 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1236690 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1236690 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45767232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45767232 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 420240 # Transaction distribution +system.membus.trans_dist::WritebackDirty 293021 # Transaction distribution +system.membus.trans_dist::CleanEvict 98541 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36 # Transaction distribution +system.membus.trans_dist::ReadExReq 3666 # Transaction distribution +system.membus.trans_dist::ReadExResp 3666 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 420241 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1239411 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1239411 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45883328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45883328 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 813662 # Request fanout histogram +system.membus.snoop_fanout::samples 815505 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 813662 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 815505 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 813662 # Request fanout histogram -system.membus.reqLayer0.occupancy 2208946039 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 815505 # Request fanout histogram +system.membus.reqLayer0.occupancy 2215026289 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2237977923 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2242814920 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 60c8e3478..f75c6f447 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -656,9 +656,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/parser +executable=/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false max_stack_size=67108864 output=cout diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr index 341b479f7..f9e2ef3b2 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr @@ -1,2 +1 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 0edda5875..48af414dd 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -3,17 +3,29 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2016 21:27:50 -gem5 started Mar 15 2016 21:35:29 -gem5 executing on phenom, pid 15976 -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing +gem5 compiled Mar 16 2016 22:57:26 +gem5 started Mar 16 2016 22:58:58 +gem5 executing on dinar2c11, pid 24771 +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: **info: Increasing stack size by one page. *******info: Increasing stack size by one page. -**************************************** +******************************info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +********** 58924 words stored in 3784810 bytes @@ -25,28 +37,8 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -86,9 +78,11 @@ info: Increasing stack size by one page. the man with whom I play tennis is here there is a dog in the park this is not the man we know and love +info: Increasing stack size by one page. +info: Increasing stack size by one page. we like to eat at restaurants , usually on weekends what did John say he thought you should do about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 403557300500 because target called exit() +Exiting @ tick 404911731500 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 4eb720ad3..080fc4b8f 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.403557 # Number of seconds simulated -sim_ticks 403557300500 # Number of ticks simulated -final_tick 403557300500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.404912 # Number of seconds simulated +sim_ticks 404911731500 # Number of ticks simulated +final_tick 404911731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114335 # Simulator instruction rate (inst/s) -host_op_rate 211418 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55801045 # Simulator tick rate (ticks/s) -host_mem_usage 368712 # Number of bytes of host memory used -host_seconds 7232.07 # Real time elapsed on the host -sim_insts 826877109 # Number of instructions simulated -sim_ops 1528988701 # Number of ops (including micro ops) simulated +host_inst_rate 59948 # Simulator instruction rate (inst/s) +host_op_rate 110933 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29356650 # Simulator tick rate (ticks/s) +host_mem_usage 419644 # Number of bytes of host memory used +host_seconds 13792.85 # Real time elapsed on the host +sim_insts 826847303 # Number of instructions simulated +sim_ops 1530082520 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 163584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24544448 # Number of bytes read from this memory -system.physmem.bytes_read::total 24708032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 163584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 163584 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18888768 # Number of bytes written to this memory -system.physmem.bytes_written::total 18888768 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2556 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 383507 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386063 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 295137 # Number of write requests responded to by this memory -system.physmem.num_writes::total 295137 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 405355 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60820230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 61225585 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 405355 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 405355 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 46805665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 46805665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 46805665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 405355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60820230 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 108031251 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386063 # Number of read requests accepted -system.physmem.writeReqs 295137 # Number of write requests accepted -system.physmem.readBursts 386063 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 295137 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24688384 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue -system.physmem.bytesWritten 18886848 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24708032 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18888768 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 162176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24538048 # Number of bytes read from this memory +system.physmem.bytes_read::total 24700224 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 162176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 162176 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18887104 # Number of bytes written to this memory +system.physmem.bytes_written::total 18887104 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2534 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383407 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385941 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295111 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295111 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 400522 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60600981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 61001502 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 400522 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 400522 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 46644991 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 46644991 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 46644991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 400522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60600981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 107646493 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385941 # Number of read requests accepted +system.physmem.writeReqs 295111 # Number of write requests accepted +system.physmem.readBursts 385941 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295111 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24680320 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue +system.physmem.bytesWritten 18885056 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24700224 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18887104 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24073 # Per bank write bursts -system.physmem.perBankRdBursts::1 26429 # Per bank write bursts -system.physmem.perBankRdBursts::2 24836 # Per bank write bursts -system.physmem.perBankRdBursts::3 24494 # Per bank write bursts -system.physmem.perBankRdBursts::4 23227 # Per bank write bursts -system.physmem.perBankRdBursts::5 23706 # Per bank write bursts -system.physmem.perBankRdBursts::6 24492 # Per bank write bursts -system.physmem.perBankRdBursts::7 24304 # Per bank write bursts -system.physmem.perBankRdBursts::8 23632 # Per bank write bursts -system.physmem.perBankRdBursts::9 23534 # Per bank write bursts -system.physmem.perBankRdBursts::10 24801 # Per bank write bursts -system.physmem.perBankRdBursts::11 23978 # Per bank write bursts -system.physmem.perBankRdBursts::12 23332 # Per bank write bursts -system.physmem.perBankRdBursts::13 22938 # Per bank write bursts -system.physmem.perBankRdBursts::14 24084 # Per bank write bursts -system.physmem.perBankRdBursts::15 23896 # Per bank write bursts -system.physmem.perBankWrBursts::0 18613 # Per bank write bursts -system.physmem.perBankWrBursts::1 19937 # Per bank write bursts -system.physmem.perBankWrBursts::2 19197 # Per bank write bursts -system.physmem.perBankWrBursts::3 19026 # Per bank write bursts -system.physmem.perBankWrBursts::4 18109 # Per bank write bursts -system.physmem.perBankWrBursts::5 18508 # Per bank write bursts -system.physmem.perBankWrBursts::6 19135 # Per bank write bursts -system.physmem.perBankWrBursts::7 19091 # Per bank write bursts -system.physmem.perBankWrBursts::8 18652 # Per bank write bursts -system.physmem.perBankWrBursts::9 17959 # Per bank write bursts -system.physmem.perBankWrBursts::10 18920 # Per bank write bursts -system.physmem.perBankWrBursts::11 17762 # Per bank write bursts -system.physmem.perBankWrBursts::12 17406 # Per bank write bursts -system.physmem.perBankWrBursts::13 17012 # Per bank write bursts -system.physmem.perBankWrBursts::14 17899 # Per bank write bursts -system.physmem.perBankWrBursts::15 17881 # Per bank write bursts +system.physmem.perBankRdBursts::0 24031 # Per bank write bursts +system.physmem.perBankRdBursts::1 26423 # Per bank write bursts +system.physmem.perBankRdBursts::2 24936 # Per bank write bursts +system.physmem.perBankRdBursts::3 24514 # Per bank write bursts +system.physmem.perBankRdBursts::4 23470 # Per bank write bursts +system.physmem.perBankRdBursts::5 23659 # Per bank write bursts +system.physmem.perBankRdBursts::6 24566 # Per bank write bursts +system.physmem.perBankRdBursts::7 24334 # Per bank write bursts +system.physmem.perBankRdBursts::8 23673 # Per bank write bursts +system.physmem.perBankRdBursts::9 23472 # Per bank write bursts +system.physmem.perBankRdBursts::10 24737 # Per bank write bursts +system.physmem.perBankRdBursts::11 23939 # Per bank write bursts +system.physmem.perBankRdBursts::12 23178 # Per bank write bursts +system.physmem.perBankRdBursts::13 22917 # Per bank write bursts +system.physmem.perBankRdBursts::14 23861 # Per bank write bursts +system.physmem.perBankRdBursts::15 23920 # Per bank write bursts +system.physmem.perBankWrBursts::0 18617 # Per bank write bursts +system.physmem.perBankWrBursts::1 19947 # Per bank write bursts +system.physmem.perBankWrBursts::2 19213 # Per bank write bursts +system.physmem.perBankWrBursts::3 19024 # Per bank write bursts +system.physmem.perBankWrBursts::4 18187 # Per bank write bursts +system.physmem.perBankWrBursts::5 18473 # Per bank write bursts +system.physmem.perBankWrBursts::6 19133 # Per bank write bursts +system.physmem.perBankWrBursts::7 19079 # Per bank write bursts +system.physmem.perBankWrBursts::8 18679 # Per bank write bursts +system.physmem.perBankWrBursts::9 17947 # Per bank write bursts +system.physmem.perBankWrBursts::10 18901 # Per bank write bursts +system.physmem.perBankWrBursts::11 17752 # Per bank write bursts +system.physmem.perBankWrBursts::12 17391 # Per bank write bursts +system.physmem.perBankWrBursts::13 17019 # Per bank write bursts +system.physmem.perBankWrBursts::14 17841 # Per bank write bursts +system.physmem.perBankWrBursts::15 17876 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 403557258500 # Total gap between requests +system.physmem.totGap 404911622500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386063 # Read request sizes (log2) +system.physmem.readPktSize::6 385941 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 295137 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 303 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295111 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 380814 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,46 +144,46 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17615 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see @@ -193,733 +193,733 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146836 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.749026 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 175.460690 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.805815 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54147 36.88% 36.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39842 27.13% 64.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13777 9.38% 73.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7669 5.22% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5515 3.76% 82.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3906 2.66% 85.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2997 2.04% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2808 1.91% 88.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16175 11.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146836 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17510 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.029754 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 217.905540 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17500 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 147028 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 296.294039 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.908610 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.351914 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54375 36.98% 36.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40100 27.27% 64.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13677 9.30% 73.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7439 5.06% 78.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5510 3.75% 82.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3768 2.56% 84.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3010 2.05% 86.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2924 1.99% 88.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16225 11.04% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147028 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17521 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.008789 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 217.166856 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17511 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 3 0.02% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17510 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17510 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.853626 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.775847 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.814458 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17322 98.93% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 130 0.74% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 32 0.18% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 9 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 3 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17521 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17521 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.841447 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.770042 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.569197 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17331 98.92% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 134 0.76% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 31 0.18% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 4 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 3 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 3 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 4 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17510 # Writes before turning the bus around for reads -system.physmem.totQLat 4294664500 # Total ticks spent queuing -system.physmem.totMemAccLat 11527589500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1928780000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11133.11 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::116-119 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17521 # Writes before turning the bus around for reads +system.physmem.totQLat 4288044250 # Total ticks spent queuing +system.physmem.totMemAccLat 11518606750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1928150000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11119.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29883.11 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 61.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 46.80 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 61.23 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 46.81 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29869.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 60.95 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 46.64 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 61.00 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 46.64 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.84 # Data bus utilization in percentage system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.37 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.17 # Average write queue length when enqueuing -system.physmem.readRowHits 318250 # Number of row buffer hits during reads -system.physmem.writeRowHits 215762 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.11 # Row buffer hit rate for writes -system.physmem.avgGap 592421.11 # Average gap between requests -system.physmem.pageHitRate 78.43 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 567929880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 309882375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1525258800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 982361520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26358156240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 62125312320 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 187636398750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 279505299885 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.609739 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 311602147750 # Time in different power states -system.physmem_0.memoryStateTime::REF 13475540000 # Time in different power states +system.physmem.avgWrQLen 21.53 # Average write queue length when enqueuing +system.physmem.readRowHits 317942 # Number of row buffer hits during reads +system.physmem.writeRowHits 215725 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.45 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.10 # Row buffer hit rate for writes +system.physmem.avgGap 594538.48 # Average gap between requests +system.physmem.pageHitRate 78.40 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 570719520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 311404500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1528168200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 982685520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26446645680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62100381375 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 188471152500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 280411157295 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.529485 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 312985847250 # Time in different power states +system.physmem_0.memoryStateTime::REF 13520780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 78476140500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 78402005250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 541832760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 295642875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1483138800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 929594880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26358156240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 60415771455 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 189135996000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 279160133010 # Total energy per rank (pJ) -system.physmem_1.averagePower 691.754421 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 314107658000 # Time in different power states -system.physmem_1.memoryStateTime::REF 13475540000 # Time in different power states +system.physmem_1.actEnergy 540562680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 294949875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1479324600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 929082960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26446645680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 59763827970 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 190520760750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 279975154515 # Total energy per rank (pJ) +system.physmem_1.averagePower 691.452692 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 316410940750 # Time in different power states +system.physmem_1.memoryStateTime::REF 13520780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 75970627000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 74976935500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 219252380 # Number of BP lookups -system.cpu.branchPred.condPredicted 219252380 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 8528271 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 123973177 # Number of BTB lookups -system.cpu.branchPred.BTBHits 121800120 # Number of BTB hits +system.cpu.branchPred.lookups 219859048 # Number of BP lookups +system.cpu.branchPred.condPredicted 219859048 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 8758546 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 124148256 # Number of BTB lookups +system.cpu.branchPred.BTBHits 121897688 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.247156 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 27061903 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1407355 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.187193 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 27156156 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1403906 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 807114602 # number of cpu cycles simulated +system.cpu.numCycles 809823464 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 175891157 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1208567118 # Number of instructions fetch has processed -system.cpu.fetch.Branches 219252380 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 148862023 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 621375374 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17762469 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 208 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 90709 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 718160 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1191 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 170755406 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2320013 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 806958068 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.786744 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.368251 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 176591288 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1214997993 # Number of instructions fetch has processed +system.cpu.fetch.Branches 219859048 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 149053844 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 622702021 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 18219345 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 230 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 91157 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 715943 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 449274 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 171574494 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2309765 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 809659613 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.796039 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.371227 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 417094848 51.69% 51.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32452037 4.02% 55.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31902781 3.95% 59.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32612026 4.04% 63.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26524373 3.29% 66.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 26910367 3.33% 70.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 35157617 4.36% 74.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31335613 3.88% 78.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 172968406 21.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 417404830 51.55% 51.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 32671589 4.04% 55.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 32039233 3.96% 59.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32726753 4.04% 63.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26705475 3.30% 66.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 26911183 3.32% 70.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 35262840 4.36% 74.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31547344 3.90% 78.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174390366 21.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 806958068 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.271650 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.497392 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 120421699 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 370368413 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 225215938 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82070784 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8881234 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2132047991 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 8881234 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 152579592 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 150649676 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 43646 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 271398208 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 223405712 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2088421237 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 135982 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 138413157 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24833190 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 50057898 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2190635347 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5277929489 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3356932236 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 59989 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 576594493 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3330 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3150 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 422929221 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 507109788 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 200805340 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 229274294 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 68310404 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2023046060 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27646 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1788955161 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 413315 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 494085005 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 832817551 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 27094 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 806958068 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.216912 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.070634 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 809659613 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.271490 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.500325 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 121391489 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 370091708 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 226645475 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82421269 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9109672 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2145160206 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 9109672 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 153539670 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 151301355 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 41989 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 272974154 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 222692773 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2099917751 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 135565 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 138360760 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24932221 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 49265464 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2208208417 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5316744595 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3383996279 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 60226 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 591246845 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3675 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3497 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 423124310 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 508481889 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 201115971 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 229749012 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 68249944 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2031398692 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 54143 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1792547451 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 420919 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 501370315 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 849083500 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 53591 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 809659613 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.213952 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.069729 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 238363650 29.54% 29.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 123779759 15.34% 44.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 118420990 14.67% 59.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 107850309 13.37% 72.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 89928227 11.14% 84.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60113985 7.45% 91.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 42280336 5.24% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 18948850 2.35% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7271962 0.90% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 239429764 29.57% 29.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 124356019 15.36% 44.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 119082530 14.71% 59.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 108043901 13.34% 72.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 89929088 11.11% 84.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 60282735 7.45% 91.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 42261465 5.22% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 18997036 2.35% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7277075 0.90% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 806958068 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 809659613 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11501801 42.82% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12260611 45.64% 88.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3099977 11.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11520020 42.79% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12317290 45.76% 88.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3082634 11.45% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2718189 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1183067002 66.13% 66.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 368893 0.02% 66.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881187 0.22% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 137 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 38 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 395 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 428511642 23.95% 90.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170407678 9.53% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2934339 0.16% 0.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1185141409 66.11% 66.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 369471 0.02% 66.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4797462 0.27% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 190 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 20 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 21 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 479 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 428879813 23.93% 90.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170424247 9.51% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1788955161 # Type of FU issued -system.cpu.iq.rate 2.216482 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26862389 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015016 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4412114486 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2517408815 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1762314892 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 29608 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 69342 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 5559 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1813086388 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12973 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 185891278 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1792547451 # Type of FU issued +system.cpu.iq.rate 2.213504 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26919944 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015018 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4422066274 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2533070112 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1765468749 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 29104 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 69216 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 5504 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1816520301 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12755 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 185916260 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 123009946 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 214354 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 373061 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 51645154 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 124400743 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 210576 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 369684 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 51957776 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 23005 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1152 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 22915 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1100 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8881234 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 97675937 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6156450 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2023073706 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 372553 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 507112103 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 200805340 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 12025 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1859445 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3396246 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 373061 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4843605 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4134020 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8977625 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1769939059 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 423109380 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19016102 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 9109672 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 98354510 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6118608 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2031452835 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 404669 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 508484056 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 201115971 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 41229 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1818362 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3401419 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 369684 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4846207 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4373880 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 9220087 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1773318465 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 423351838 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19228986 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590326143 # number of memory reference insts executed -system.cpu.iew.exec_branches 168971977 # Number of branches executed -system.cpu.iew.exec_stores 167216763 # Number of stores executed -system.cpu.iew.exec_rate 2.192922 # Inst execution rate -system.cpu.iew.wb_sent 1766810354 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1762320451 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1339786199 # num instructions producing a value -system.cpu.iew.wb_consumers 2050074397 # num instructions consuming a value -system.cpu.iew.wb_rate 2.183482 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.653531 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 494145922 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 590572450 # number of memory reference insts executed +system.cpu.iew.exec_branches 169222012 # Number of branches executed +system.cpu.iew.exec_stores 167220612 # Number of stores executed +system.cpu.iew.exec_rate 2.189759 # Inst execution rate +system.cpu.iew.wb_sent 1769957940 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1765474253 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1342270213 # num instructions producing a value +system.cpu.iew.wb_consumers 2056372436 # num instructions consuming a value +system.cpu.iew.wb_rate 2.180073 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.652737 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 501430525 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8608481 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 739768084 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.066849 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.575796 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 8839580 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 741419902 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.063719 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.574359 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 275719169 37.27% 37.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 172002982 23.25% 60.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 56035372 7.57% 68.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86287676 11.66% 79.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25889173 3.50% 83.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26492883 3.58% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9844270 1.33% 88.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9007252 1.22% 89.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 78489307 10.61% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 276552385 37.30% 37.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 172772725 23.30% 60.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 55960386 7.55% 68.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86390933 11.65% 79.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25906280 3.49% 83.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26508569 3.58% 86.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9812132 1.32% 88.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8956469 1.21% 89.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 78560023 10.60% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 739768084 # Number of insts commited each cycle -system.cpu.commit.committedInsts 826877109 # Number of instructions committed -system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 741419902 # Number of insts commited each cycle +system.cpu.commit.committedInsts 826847303 # Number of instructions committed +system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 533262343 # Number of memory references committed -system.cpu.commit.loads 384102157 # Number of loads committed +system.cpu.commit.refs 533241508 # Number of memory references committed +system.cpu.commit.loads 384083313 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 149758583 # Number of branches committed +system.cpu.commit.branches 149981740 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions. +system.cpu.commit.int_insts 1527470225 # Number of committed integer instructions. system.cpu.commit.function_calls 17673145 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 1819099 0.12% 0.12% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 989721889 64.73% 64.85% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.87% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 3878536 0.25% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::No_OpClass 2048202 0.13% 0.13% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 989691028 64.68% 64.82% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.84% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 4794948 0.31% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 384083313 25.10% 90.25% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 78489307 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2684413400 # The number of ROB reads -system.cpu.rob.rob_writes 4113633509 # The number of ROB writes -system.cpu.timesIdled 1975 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 156534 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 826877109 # Number of Instructions Simulated -system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.976100 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.976100 # CPI: Total CPI of All Threads -system.cpu.ipc 1.024485 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.024485 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2722552264 # number of integer regfile reads -system.cpu.int_regfile_writes 1435774618 # number of integer regfile writes -system.cpu.fp_regfile_reads 5765 # number of floating regfile reads -system.cpu.fp_regfile_writes 491 # number of floating regfile writes -system.cpu.cc_regfile_reads 596650045 # number of cc regfile reads -system.cpu.cc_regfile_writes 405459285 # number of cc regfile writes -system.cpu.misc_regfile_reads 971600702 # number of misc regfile reads +system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction +system.cpu.commit.bw_lim_events 78560023 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2694372924 # The number of ROB reads +system.cpu.rob.rob_writes 4131439321 # The number of ROB writes +system.cpu.timesIdled 2207 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 163851 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 826847303 # Number of Instructions Simulated +system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.979411 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.979411 # CPI: Total CPI of All Threads +system.cpu.ipc 1.021022 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.021022 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2730823256 # number of integer regfile reads +system.cpu.int_regfile_writes 1440512155 # number of integer regfile writes +system.cpu.fp_regfile_reads 5926 # number of floating regfile reads +system.cpu.fp_regfile_writes 463 # number of floating regfile writes +system.cpu.cc_regfile_reads 599968810 # number of cc regfile reads +system.cpu.cc_regfile_writes 405913106 # number of cc regfile writes +system.cpu.misc_regfile_reads 971975039 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2530810 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.810337 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 382026213 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2534906 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.706264 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2532888 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.837732 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 382237058 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2536984 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.665932 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.810337 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998001 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998001 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.837732 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998007 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998007 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 867 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3177 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 870 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3173 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 773143076 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 773143076 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 233377627 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 233377627 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148173651 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148173651 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 381551278 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 381551278 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 381551278 # number of overall hits -system.cpu.dcache.overall_hits::total 381551278 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2766256 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2766256 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 986551 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 986551 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3752807 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3752807 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3752807 # number of overall misses -system.cpu.dcache.overall_misses::total 3752807 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58648858500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58648858500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 30791929995 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 30791929995 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 89440788495 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 89440788495 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 89440788495 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 89440788495 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 236143883 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 236143883 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 385304085 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 385304085 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 385304085 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 385304085 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011714 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011714 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006614 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006614 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009740 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009740 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009740 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009740 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21201.529613 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21201.529613 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31211.696096 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31211.696096 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23833.037109 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23833.037109 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23833.037109 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23833.037109 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10234 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 15 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1094 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.354662 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.500000 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 773578930 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 773578930 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 233596304 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 233596304 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148199808 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148199808 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 381796112 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 381796112 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 381796112 # number of overall hits +system.cpu.dcache.overall_hits::total 381796112 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2766458 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2766458 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 958403 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 958403 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3724861 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3724861 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3724861 # number of overall misses +system.cpu.dcache.overall_misses::total 3724861 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58572979000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58572979000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 29883028996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 29883028996 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 88456007996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 88456007996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 88456007996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 88456007996 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 236362762 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 236362762 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 385520973 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 385520973 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 385520973 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 385520973 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011704 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011704 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006425 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006425 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009662 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009662 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009662 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009662 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21172.553135 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21172.553135 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31180.024474 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31180.024474 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23747.465475 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23747.465475 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23747.465475 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23747.465475 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9959 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 9 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1047 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.511939 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 9 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330455 # number of writebacks -system.cpu.dcache.writebacks::total 2330455 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1001445 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1001445 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19420 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 19420 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1020865 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1020865 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1020865 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1020865 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764811 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764811 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 967131 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 967131 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2731942 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2731942 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2731942 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2731942 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33568096500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33568096500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29570460997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 29570460997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63138557497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 63138557497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63138557497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 63138557497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007473 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007473 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006484 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006484 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007090 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.007090 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007090 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.007090 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19020.788345 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19020.788345 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30575.445309 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30575.445309 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23111.236438 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23111.236438 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23111.236438 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23111.236438 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2332013 # number of writebacks +system.cpu.dcache.writebacks::total 2332013 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999668 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 999668 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19404 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 19404 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1019072 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1019072 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1019072 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1019072 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766790 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1766790 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 938999 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 938999 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2705789 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2705789 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2705789 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2705789 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33605058000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33605058000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 28689647497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 28689647497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62294705497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 62294705497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62294705497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 62294705497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007475 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007475 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006295 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006295 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007019 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.007019 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007019 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.007019 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19020.403104 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19020.403104 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30553.437753 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30553.437753 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23022.750664 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23022.750664 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23022.750664 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23022.750664 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 6689 # number of replacements -system.cpu.icache.tags.tagsinuse 1037.520443 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 170544686 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8296 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20557.459740 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 6016 # number of replacements +system.cpu.icache.tags.tagsinuse 1043.380208 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 171393952 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 7637 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22442.575881 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1037.520443 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.506602 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.506602 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1607 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 323 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1154 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.784668 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 341716240 # Number of tag accesses -system.cpu.icache.tags.data_accesses 341716240 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 170547776 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 170547776 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 170547776 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 170547776 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 170547776 # number of overall hits -system.cpu.icache.overall_hits::total 170547776 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 207629 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 207629 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 207629 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 207629 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 207629 # number of overall misses -system.cpu.icache.overall_misses::total 207629 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1204990000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1204990000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1204990000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1204990000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1204990000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1204990000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 170755405 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 170755405 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 170755405 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 170755405 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 170755405 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 170755405 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001216 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001216 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001216 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001216 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001216 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001216 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5803.572719 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 5803.572719 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 5803.572719 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 5803.572719 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 5803.572719 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 5803.572719 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 923 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1043.380208 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.509463 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.509463 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1621 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1224 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.791504 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 343325473 # Number of tag accesses +system.cpu.icache.tags.data_accesses 343325473 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 171395976 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 171395976 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 171395976 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 171395976 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 171395976 # number of overall hits +system.cpu.icache.overall_hits::total 171395976 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 178518 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 178518 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 178518 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 178518 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 178518 # number of overall misses +system.cpu.icache.overall_misses::total 178518 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1062576000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1062576000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1062576000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1062576000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1062576000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1062576000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 171574494 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 171574494 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 171574494 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 171574494 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 171574494 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 171574494 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001040 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001040 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001040 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001040 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001040 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001040 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5952.206500 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 5952.206500 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 5952.206500 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 5952.206500 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 5952.206500 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 5952.206500 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 613 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 68.111111 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 6689 # number of writebacks -system.cpu.icache.writebacks::total 6689 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2197 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2197 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2197 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2197 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2197 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2197 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205432 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 205432 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 205432 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 205432 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 205432 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 205432 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 915620000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 915620000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 915620000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 915620000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915620000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 915620000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001203 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001203 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001203 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4457.046614 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4457.046614 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4457.046614 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4457.046614 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4457.046614 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4457.046614 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 6016 # number of writebacks +system.cpu.icache.writebacks::total 6016 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2032 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2032 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2032 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2032 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2032 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2032 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 176486 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 176486 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 176486 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 176486 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 176486 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 176486 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 805089500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 805089500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 805089500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 805089500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 805089500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 805089500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001029 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001029 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001029 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001029 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001029 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001029 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4561.775438 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4561.775438 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4561.775438 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4561.775438 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4561.775438 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4561.775438 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 355320 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29620.939989 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3892489 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 387653 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.041168 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 189331361500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21024.490956 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.822585 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8409.626448 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.641617 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005701 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.256641 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.903959 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32333 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu.l2cache.tags.replacements 355100 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29624.391257 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3897105 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 387449 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.058369 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 189360575500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21018.110892 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 185.534699 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8420.745667 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.641422 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005662 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.256981 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.904065 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32349 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13412 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18612 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986725 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 43293695 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 43293695 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 2330455 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2330455 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 6282 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 6282 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1842 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1842 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 563562 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 563562 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5713 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 5713 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587786 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1587786 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5713 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2151348 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2157061 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 5713 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2151348 # number of overall hits -system.cpu.l2cache.overall_hits::total 2157061 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 195194 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 195194 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206925 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206925 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2558 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2558 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176633 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 176633 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2558 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 383558 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 386116 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2558 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 383558 # number of overall misses -system.cpu.l2cache.overall_misses::total 386116 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 12720000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 12720000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16418152000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16418152000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 210152000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 210152000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14200919500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 14200919500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 210152000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 30619071500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30829223500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 210152000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 30619071500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30829223500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2330455 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2330455 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 6282 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 6282 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 197036 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 197036 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 770487 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 770487 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8271 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 8271 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1764419 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1764419 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 8271 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2534906 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2543177 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 8271 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2534906 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2543177 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990651 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990651 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268564 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.268564 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.309273 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.309273 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100108 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100108 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.309273 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.151311 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151824 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.309273 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.151311 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151824 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 65.165937 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 65.165937 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79343.491603 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79343.491603 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82154.808444 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82154.808444 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80397.884314 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80397.884314 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82154.808444 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79829.051930 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79844.459955 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82154.808444 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79829.051930 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79844.459955 # average overall miss latency +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13364 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18670 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987213 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 43097417 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 43097417 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 2332013 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2332013 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 5708 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 5708 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1488 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1488 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 563712 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 563712 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5057 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 5057 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1589822 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1589822 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5057 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2153534 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2158591 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5057 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2153534 # number of overall hits +system.cpu.l2cache.overall_hits::total 2158591 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 167317 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 167317 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206886 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206886 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2535 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2535 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176564 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 176564 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2535 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 383450 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 385985 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2535 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 383450 # number of overall misses +system.cpu.l2cache.overall_misses::total 385985 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 8361500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 8361500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16391900500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16391900500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 208226000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 208226000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14213856500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 14213856500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 208226000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 30605757000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30813983000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 208226000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 30605757000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30813983000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2332013 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2332013 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 5708 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 5708 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 168805 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 168805 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 770598 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 770598 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 7592 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 7592 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1766386 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1766386 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 7592 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2536984 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2544576 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 7592 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2536984 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2544576 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991185 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991185 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268475 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.268475 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.333904 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.333904 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099958 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099958 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.333904 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.151144 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151689 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.333904 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.151144 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151689 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49.974001 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49.974001 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79231.559893 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79231.559893 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82140.433925 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82140.433925 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80502.574137 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80502.574137 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82140.433925 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79816.813144 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79832.073785 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82140.433925 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79816.813144 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79832.073785 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -928,142 +928,136 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 295137 # number of writebacks -system.cpu.l2cache.writebacks::total 295137 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.l2cache.writebacks::writebacks 295111 # number of writebacks +system.cpu.l2cache.writebacks::total 295111 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 7 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 7 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 195194 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 195194 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206925 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206925 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2557 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2557 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176633 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176633 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2557 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 383558 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 386115 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2557 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 383558 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 386115 # number of overall MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3766618491 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3766618491 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14348902000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14348902000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 184524501 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 184524501 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12434572036 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12434572036 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184524501 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26783474036 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26967998537 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184524501 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26783474036 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26967998537 # number of overall MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 167317 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 167317 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206886 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206886 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2535 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2535 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176564 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176564 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2535 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 383450 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 385985 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2535 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 383450 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 385985 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3236471489 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3236471489 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14323040500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14323040500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 182885002 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 182885002 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12448203030 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12448203030 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 182885002 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26771243530 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26954128532 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 182885002 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26771243530 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26954128532 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990651 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990651 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268564 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268564 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.309152 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.309152 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100108 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100108 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.309152 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151311 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151824 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.309152 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151311 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151824 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19296.794425 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19296.794425 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69343.491603 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69343.491603 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72164.450919 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72164.450919 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70397.785442 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70397.785442 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72164.450919 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69829.006398 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69844.472598 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72164.450919 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69829.006398 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69844.472598 # average overall mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991185 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991185 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268475 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268475 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.333904 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.333904 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099958 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099958 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.333904 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151144 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151689 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.333904 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151144 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151689 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19343.351178 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19343.351178 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69231.559893 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69231.559893 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72143.985010 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72143.985010 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70502.497848 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70502.497848 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72143.985010 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69816.778015 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69832.062210 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72143.985010 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69816.778015 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69832.062210 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5474873 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2731236 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 212343 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3595 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3595 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5421179 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2705952 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 181282 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3493 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3493 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 1969849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2625592 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6689 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 260538 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 197036 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 197036 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 770487 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 770487 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 205432 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764419 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220390 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7994694 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8215084 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 957312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311383104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312340416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 552481 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3292694 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.124385 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.330020 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 1942871 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2627124 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6016 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 260864 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 168805 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 168805 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 770598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 770598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 176486 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766386 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 190093 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7944466 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8134559 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 870848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311615808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312486656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 523994 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3237375 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.108652 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.311202 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2883132 87.56% 87.56% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 409562 12.44% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2885627 89.13% 89.13% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 351748 10.87% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3292694 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5103271503 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3237375 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5077578963 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 308149990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 264736482 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3900879073 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3889880082 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 179188 # Transaction distribution -system.membus.trans_dist::WritebackDirty 295137 # Transaction distribution -system.membus.trans_dist::CleanEvict 56656 # Transaction distribution -system.membus.trans_dist::UpgradeReq 195245 # Transaction distribution -system.membus.trans_dist::ReadExReq 206874 # Transaction distribution -system.membus.trans_dist::ReadExResp 206874 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 179189 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1319163 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1319163 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1319163 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43596736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43596736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43596736 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 179098 # Transaction distribution +system.membus.trans_dist::WritebackDirty 295111 # Transaction distribution +system.membus.trans_dist::CleanEvict 56587 # Transaction distribution +system.membus.trans_dist::UpgradeReq 167360 # Transaction distribution +system.membus.trans_dist::ReadExReq 206843 # Transaction distribution +system.membus.trans_dist::ReadExResp 206843 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 179098 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1290940 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1290940 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1290940 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43587328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43587328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43587328 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 933101 # Request fanout histogram +system.membus.snoop_fanout::samples 904999 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 933101 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 904999 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 933101 # Request fanout histogram -system.membus.reqLayer0.occupancy 2242999911 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2042259250 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 904999 # Request fanout histogram +system.membus.reqLayer0.occupancy 2207449441 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 2041679000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout index ff0a5c91f..ff993af56 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 16 2016 15:38:19 -gem5 started Mar 16 2016 15:38:59 -gem5 executing on dinar2c11, pid 14361 +gem5 compiled Mar 16 2016 22:57:26 +gem5 started Mar 16 2016 22:58:08 +gem5 executing on dinar2c11, pid 24736 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -72,4 +72,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 885256008500 because target called exit() +Exiting @ tick 885772926000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index a821d05f5..0e4a177c3 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,127 +1,127 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.885256 # Number of seconds simulated -sim_ticks 885256008500 # Number of ticks simulated -final_tick 885256008500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.885773 # Number of seconds simulated +sim_ticks 885772926000 # Number of ticks simulated +final_tick 885772926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 362789 # Simulator instruction rate (inst/s) -host_op_rate 670835 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 388389023 # Simulator tick rate (ticks/s) -host_mem_usage 304128 # Number of bytes of host memory used -host_seconds 2279.30 # Real time elapsed on the host -sim_insts 826906380 # Number of instructions simulated -sim_ops 1529035683 # Number of ops (including micro ops) simulated +host_inst_rate 376226 # Simulator instruction rate (inst/s) +host_op_rate 696207 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 403037674 # Simulator tick rate (ticks/s) +host_mem_usage 304140 # Number of bytes of host memory used +host_seconds 2197.74 # Real time elapsed on the host +sim_insts 826847304 # Number of instructions simulated +sim_ops 1530082521 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 8547061720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2285750420 # Number of bytes read from this memory -system.physmem.bytes_read::total 10832812140 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 8547061720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 8547061720 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 991875282 # Number of bytes written to this memory -system.physmem.bytes_written::total 991875282 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1068382715 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 384117854 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1452500569 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 149164510 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149164510 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 9654903935 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2582021921 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12236925856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 9654903935 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 9654903935 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1120438915 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1120438915 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 9654903935 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3702460837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13357364772 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 8546485088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2285527276 # Number of bytes read from this memory +system.physmem.bytes_read::total 10832012364 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 8546485088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 8546485088 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 991837474 # Number of bytes written to this memory +system.physmem.bytes_written::total 991837474 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1068310636 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 384083342 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1452393978 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 149158211 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149158211 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 9648618554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2580263190 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12228881744 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 9648618554 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 9648618554 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1119742368 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1119742368 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 9648618554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3700005559 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13348624112 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 1770512018 # number of cpu cycles simulated +system.cpu.numCycles 1771545853 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 826906380 # Number of instructions committed -system.cpu.committedOps 1529035683 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1526653037 # Number of integer alu accesses +system.cpu.committedInsts 826847304 # Number of instructions committed +system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 35346287 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 92662756 # number of instructions that are conditional controls -system.cpu.num_int_insts 1526653037 # number of integer instructions +system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls +system.cpu.num_int_insts 1527470226 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3293861747 # number of times the integer registers were read -system.cpu.num_int_register_writes 1237389453 # number of times the integer registers were written +system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read +system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 561356848 # number of times the CC registers were read -system.cpu.num_cc_register_writes 376698535 # number of times the CC registers were written -system.cpu.num_mem_refs 533282319 # number of memory refs -system.cpu.num_load_insts 384117825 # Number of load instructions -system.cpu.num_store_insts 149164494 # Number of store instructions +system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read +system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written +system.cpu.num_mem_refs 533241508 # number of memory refs +system.cpu.num_load_insts 384083313 # Number of load instructions +system.cpu.num_store_insts 149158195 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1770512017.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1771545852.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 149762544 # Number of branches fetched -system.cpu.op_class::No_OpClass 1818553 0.12% 0.12% # Class of executed instruction -system.cpu.op_class::IntAlu 989751625 64.73% 64.85% # Class of executed instruction -system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction -system.cpu.op_class::IntDiv 3876352 0.25% 65.12% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::MemRead 384117825 25.12% 90.24% # Class of executed instruction -system.cpu.op_class::MemWrite 149164494 9.76% 100.00% # Class of executed instruction +system.cpu.Branches 149981740 # Number of branches fetched +system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction +system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction +system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction +system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction +system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1529035683 # Class of executed instruction -system.membus.trans_dist::ReadReq 1452500569 # Transaction distribution -system.membus.trans_dist::ReadResp 1452500569 # Transaction distribution -system.membus.trans_dist::WriteReq 149164510 # Transaction distribution -system.membus.trans_dist::WriteResp 149164510 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136765430 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 2136765430 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066564728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 1066564728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3203330158 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8547061720 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 8547061720 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277625702 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 3277625702 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 11824687422 # Cumulative packet size per connected master and slave (bytes) +system.cpu.op_class::total 1530082521 # Class of executed instruction +system.membus.trans_dist::ReadReq 1452393978 # Transaction distribution +system.membus.trans_dist::ReadResp 1452393978 # Transaction distribution +system.membus.trans_dist::WriteReq 149158211 # Transaction distribution +system.membus.trans_dist::WriteResp 149158211 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136621272 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 2136621272 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066483106 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 1066483106 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3203104378 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546485088 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 8546485088 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277364750 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 3277364750 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 11823849838 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1601665079 # Request fanout histogram -system.membus.snoop_fanout::mean 0.667045 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.471271 # Request fanout histogram +system.membus.snoop_fanout::samples 1601552189 # Request fanout histogram +system.membus.snoop_fanout::mean 0.667047 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 533282364 33.30% 33.30% # Request fanout histogram -system.membus.snoop_fanout::1 1068382715 66.70% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 533241553 33.30% 33.30% # Request fanout histogram +system.membus.snoop_fanout::1 1068310636 66.70% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1601665079 # Request fanout histogram +system.membus.snoop_fanout::total 1601552189 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index cd12e9ca0..ded960c36 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 16 2016 15:38:19 -gem5 started Mar 16 2016 15:38:49 -gem5 executing on dinar2c11, pid 14355 +gem5 compiled Mar 16 2016 22:57:26 +gem5 started Mar 16 2016 22:57:56 +gem5 executing on dinar2c11, pid 24718 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -72,4 +72,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 1650600522500 because target called exit() +Exiting @ tick 1650501252500 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 58e8c99ef..aee130b35 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,111 +1,111 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.650601 # Number of seconds simulated -sim_ticks 1650600522500 # Number of ticks simulated -final_tick 1650600522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.650501 # Number of seconds simulated +sim_ticks 1650501252500 # Number of ticks simulated +final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 236277 # Simulator instruction rate (inst/s) -host_op_rate 436901 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 471636555 # Simulator tick rate (ticks/s) -host_mem_usage 314152 # Number of bytes of host memory used -host_seconds 3499.73 # Real time elapsed on the host -sim_insts 826906380 # Number of instructions simulated -sim_ops 1529035683 # Number of ops (including micro ops) simulated +host_inst_rate 239314 # Simulator instruction rate (inst/s) +host_op_rate 442851 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 477703969 # Simulator tick rate (ticks/s) +host_mem_usage 314168 # Number of bytes of host memory used +host_seconds 3455.07 # Real time elapsed on the host +sim_insts 826847304 # Number of instructions simulated +sim_ops 1530082521 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24258880 # Number of bytes read from this memory -system.physmem.bytes_read::total 24374656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory +system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18765184 # Number of bytes written to this memory -system.physmem.bytes_written::total 18765184 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory +system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 379045 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380854 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293206 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293206 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 70142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14697002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14767144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 70142 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 70142 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11368701 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11368701 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11368701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 70142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14697002 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 26135845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 70146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14697925 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14768071 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 70146 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 70146 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11369424 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11369424 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11369424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3301201045 # number of cpu cycles simulated +system.cpu.numCycles 3301002505 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 826906380 # Number of instructions committed -system.cpu.committedOps 1529035683 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1526653037 # Number of integer alu accesses +system.cpu.committedInsts 826847304 # Number of instructions committed +system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 35346287 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 92662756 # number of instructions that are conditional controls -system.cpu.num_int_insts 1526653037 # number of integer instructions +system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls +system.cpu.num_int_insts 1527470226 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3293861747 # number of times the integer registers were read -system.cpu.num_int_register_writes 1237389453 # number of times the integer registers were written +system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read +system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 561356848 # number of times the CC registers were read -system.cpu.num_cc_register_writes 376698535 # number of times the CC registers were written -system.cpu.num_mem_refs 533282319 # number of memory refs -system.cpu.num_load_insts 384117825 # Number of load instructions -system.cpu.num_store_insts 149164494 # Number of store instructions +system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read +system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written +system.cpu.num_mem_refs 533241508 # number of memory refs +system.cpu.num_load_insts 384083313 # Number of load instructions +system.cpu.num_store_insts 149158195 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 3301201044.998000 # Number of busy cycles +system.cpu.num_busy_cycles 3301002504.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 149762544 # Number of branches fetched -system.cpu.op_class::No_OpClass 1818553 0.12% 0.12% # Class of executed instruction -system.cpu.op_class::IntAlu 989751625 64.73% 64.85% # Class of executed instruction -system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction -system.cpu.op_class::IntDiv 3876352 0.25% 65.12% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::MemRead 384117825 25.12% 90.24% # Class of executed instruction -system.cpu.op_class::MemWrite 149164494 9.76% 100.00% # Class of executed instruction +system.cpu.Branches 149981740 # Number of branches fetched +system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction +system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction +system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction +system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction +system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1529035683 # Class of executed instruction -system.cpu.dcache.tags.replacements 2515885 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.387052 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 530762383 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2519981 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 210.621581 # Average number of references to valid blocks. +system.cpu.op_class::total 1530082521 # Class of executed instruction +system.cpu.dcache.tags.replacements 2517016 # number of replacements +system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.387052 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386474 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -115,56 +115,56 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1069084709 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1069084709 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 382389020 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 382389020 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148373363 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148373363 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 530762383 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 530762383 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 530762383 # number of overall hits -system.cpu.dcache.overall_hits::total 530762383 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1728834 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1728834 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791147 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791147 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2519981 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2519981 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2519981 # number of overall misses -system.cpu.dcache.overall_misses::total 2519981 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 30936646500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 30936646500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20396358500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20396358500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 51333005000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 51333005000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 51333005000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 51333005000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 384117854 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 384117854 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149164510 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149164510 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 533282364 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 533282364 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 533282364 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 533282364 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004501 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004501 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005304 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005304 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004725 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004725 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004725 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004725 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17894.515321 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17894.515321 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25780.744286 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25780.744286 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20370.393666 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20370.393666 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20370.393666 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20370.393666 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148366841 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 530720441 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 530720441 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 530720441 # number of overall hits +system.cpu.dcache.overall_hits::total 530720441 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1729742 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1729742 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791370 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791370 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2521112 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2521112 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2521112 # number of overall misses +system.cpu.dcache.overall_misses::total 2521112 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 30948499500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 30948499500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20399257500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20399257500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 51347757000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 51347757000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 51347757000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 51347757000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 384083342 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 533241553 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 533241553 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 533241553 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 533241553 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004504 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004504 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004728 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004728 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004728 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17891.974352 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17891.974352 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25777.142803 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25777.142803 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20367.106658 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20367.106658 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,50 +173,50 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2324237 # number of writebacks -system.cpu.dcache.writebacks::total 2324237 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1728834 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1728834 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791147 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 791147 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2519981 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2519981 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2519981 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2519981 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29207812500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29207812500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19605211500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19605211500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48813024000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 48813024000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48813024000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 48813024000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004501 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004501 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005304 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005304 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004725 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.004725 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004725 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.004725 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16894.515321 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16894.515321 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24780.744286 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24780.744286 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19370.393666 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19370.393666 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19370.393666 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19370.393666 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2325221 # number of writebacks +system.cpu.dcache.writebacks::total 2325221 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1729742 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 791370 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2521112 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2521112 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2521112 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2521112 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29218757500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29218757500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19607887500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19607887500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48826645000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 48826645000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48826645000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 48826645000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005306 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.004728 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16891.974352 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16891.974352 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24777.142803 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24777.142803 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1253 # number of replacements -system.cpu.icache.tags.tagsinuse 881.377882 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1068379901 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 379665.920753 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 881.377882 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.430360 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.430360 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 881.361687 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id @@ -224,44 +224,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 7 system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2136768244 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2136768244 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1068379901 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1068379901 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1068379901 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1068379901 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1068379901 # number of overall hits -system.cpu.icache.overall_hits::total 1068379901 # number of overall hits +system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1068307822 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1068307822 # number of overall hits +system.cpu.icache.overall_hits::total 1068307822 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 125256000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 125256000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 125256000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 125256000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 125256000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 125256000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1068382715 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1068382715 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1068382715 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1068382715 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1068382715 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1068382715 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 125255000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 125255000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 125255000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 125255000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 125255000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 125255000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1068310636 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1068310636 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1068310636 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1068310636 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1068310636 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1068310636 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.727079 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44511.727079 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.727079 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44511.727079 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.727079 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44511.727079 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.371713 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44511.371713 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44511.371713 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44511.371713 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -278,126 +278,126 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814 system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122442000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 122442000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122442000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 122442000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122442000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 122442000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122441000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 122441000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122441000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 122441000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122441000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 122441000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.727079 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.727079 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.727079 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.727079 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.727079 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.727079 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.371713 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.371713 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 348437 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29288.556947 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3849932 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 380797 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.110195 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 348438 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.115473 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 20940.547795 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.260188 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.748964 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.639055 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 20940.857984 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.259734 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.616448 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.639064 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004006 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.250755 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.893816 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.250751 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.893821 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8218 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24062 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41491408 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41491408 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 2324237 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2324237 # number of WritebackDirty hits +system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 41509728 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 2325221 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2325221 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 584791 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 584791 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 585014 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 585014 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1005 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1005 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1556145 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1556145 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1557052 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1557052 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 1005 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2140936 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2141941 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2142066 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2143071 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1005 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2140936 # number of overall hits -system.cpu.l2cache.overall_hits::total 2141941 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2142066 # number of overall hits +system.cpu.l2cache.overall_hits::total 2143071 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 206356 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 206356 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1809 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 1809 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172689 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 172689 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172690 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 172690 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 1809 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 379045 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 380854 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 379046 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 380855 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 1809 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 379045 # number of overall misses -system.cpu.l2cache.overall_misses::total 380854 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 379046 # number of overall misses +system.cpu.l2cache.overall_misses::total 380855 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12278185500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 12278185500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 107657000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 107657000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10275036000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 10275036000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 107657000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22553221500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22660878500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 107657000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22553221500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22660878500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2324237 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2324237 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 107656000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 107656000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10275095500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 10275095500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 107656000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22553281000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22660937000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 107656000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22553281000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22660937000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2325221 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2325221 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 791147 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 791147 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 791370 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 791370 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 2814 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1728834 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1728834 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1729742 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1729742 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2519981 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2522795 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2521112 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2523926 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2519981 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2522795 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260831 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.260831 # miss rate for ReadExReq accesses +system.cpu.l2cache.overall_accesses::cpu.data 2521112 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2523926 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260758 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.260758 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.642857 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.642857 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099888 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099888 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099836 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099836 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.642857 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150416 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.150965 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150349 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.150898 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.642857 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150416 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.150965 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150349 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.150898 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.016961 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.016961 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.885019 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.885019 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234526 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234526 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.885019 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.332228 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.332228 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234524 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234524 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59500.171982 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.885019 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59500.169356 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59500.171982 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59500.169356 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -406,125 +406,125 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 293207 # number of writebacks -system.cpu.l2cache.writebacks::total 293207 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 293208 # number of writebacks +system.cpu.l2cache.writebacks::total 293208 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206356 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 206356 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1809 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1809 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172689 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172689 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172690 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172690 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 379045 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 380854 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 379046 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 380855 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 379045 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 380854 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 379046 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 380855 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214625500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214625500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89567000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89567000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548146000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548146000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89567000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762771500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18852338500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89567000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762771500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18852338500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89566000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89566000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548195500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548195500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89566000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762821000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18852387000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89566000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762821000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18852387000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260831 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260831 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260758 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260758 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099888 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099888 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099836 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099836 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150416 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.150965 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.150898 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150416 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.150965 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.150898 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.016961 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.016961 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.885019 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.885019 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234526 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234526 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.885019 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.332228 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.332228 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.171982 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.885019 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.171982 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5039933 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2517138 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 1731648 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2617444 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 246878 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 791147 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 791147 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 247025 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1728834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7555847 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7562728 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7566121 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310029952 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 310290240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 348437 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2871232 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310165312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 310425600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 348438 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2872364 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.024532 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.024527 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2869503 99.94% 99.94% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2870635 99.94% 99.94% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2871232 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4845456500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2872364 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4847571500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3779971500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 174498 # Transaction distribution -system.membus.trans_dist::WritebackDirty 293206 # Transaction distribution +system.membus.trans_dist::ReadResp 174499 # Transaction distribution +system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution system.membus.trans_dist::CleanEvict 53507 # Transaction distribution system.membus.trans_dist::ReadExReq 206356 # Transaction distribution system.membus.trans_dist::ReadExResp 206356 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 174498 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108421 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108421 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1108421 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43139840 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 727567 # Request fanout histogram +system.membus.snoop_fanout::samples 727569 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 727567 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 727567 # Request fanout histogram -system.membus.reqLayer0.occupancy 1900421500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 727569 # Request fanout histogram +system.membus.reqLayer0.occupancy 1900428000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1904270000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout index 7ed803ee9..f8e2a4c4d 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 16 2016 15:51:04 -gem5 started Mar 16 2016 17:19:39 -gem5 executing on dinar2c11, pid 17050 +gem5 compiled Mar 16 2016 23:07:21 +gem5 started Mar 16 2016 23:13:40 +gem5 executing on dinar2c11, pid 25474 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -16,4 +16,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.510000 -Exiting @ tick 517287152500 because target called exit() +Exiting @ tick 517291025500 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 7d459034e..f4880fcc0 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.517287 # Number of seconds simulated -sim_ticks 517287152500 # Number of ticks simulated -final_tick 517287152500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517291 # Number of seconds simulated +sim_ticks 517291025500 # Number of ticks simulated +final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131506 # Simulator instruction rate (inst/s) -host_op_rate 157879 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 249419657 # Simulator tick rate (ticks/s) -host_mem_usage 307088 # Number of bytes of host memory used -host_seconds 2073.96 # Real time elapsed on the host -sim_insts 272737951 # Number of instructions simulated -sim_ops 327435116 # Number of ops (including micro ops) simulated +host_inst_rate 222408 # Simulator instruction rate (inst/s) +host_op_rate 267009 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 421830266 # Simulator tick rate (ticks/s) +host_mem_usage 307072 # Number of bytes of host memory used +host_seconds 1226.30 # Real time elapsed on the host +sim_insts 272739286 # Number of instructions simulated +sim_ops 327433744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 269696 # Number of bytes read from this memory -system.physmem.bytes_read::total 436672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4214 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6823 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 322792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 521366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 844158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 322792 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 322792 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 322792 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 521366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 844158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory +system.physmem.bytes_read::total 437248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,33 +147,33 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1034574305 # number of cpu cycles simulated +system.cpu.numCycles 1034582051 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 272737951 # Number of instructions committed -system.cpu.committedOps 327435116 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 258332236 # Number of integer alu accesses +system.cpu.committedInsts 272739286 # Number of instructions committed +system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses -system.cpu.num_func_calls 12449970 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15800021 # number of instructions that are conditional controls -system.cpu.num_int_insts 258332236 # number of integer instructions +system.cpu.num_func_calls 12448615 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls +system.cpu.num_int_insts 258331537 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 1215886434 # number of times the integer registers were read -system.cpu.num_int_register_writes 162499715 # number of times the integer registers were written +system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read +system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_cc_register_reads 1242911540 # number of times the CC registers were read -system.cpu.num_cc_register_writes 76355719 # number of times the CC registers were written -system.cpu.num_mem_refs 168105830 # number of memory refs -system.cpu.num_load_insts 85730232 # Number of load instructions -system.cpu.num_store_insts 82375598 # Number of store instructions +system.cpu.num_cc_register_reads 1242915503 # number of times the CC registers were read +system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written +system.cpu.num_mem_refs 168107847 # number of memory refs +system.cpu.num_load_insts 85732248 # Number of load instructions +system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1034574304.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 30566209 # Number of branches fetched +system.cpu.Branches 30563503 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 104315933 31.82% 31.82% # Class of executed instruction +system.cpu.op_class::IntAlu 104312544 31.82% 31.82% # Class of executed instruction system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction @@ -198,79 +198,79 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Cl system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 19652356 5.99% 44.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.67% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction -system.cpu.op_class::MemRead 85730232 26.15% 74.87% # Class of executed instruction -system.cpu.op_class::MemWrite 82375598 25.13% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction +system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 327813586 # Class of executed instruction -system.cpu.dcache.tags.replacements 1326 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.339297 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168357609 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4469 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37672.322443 # Average number of references to valid blocks. +system.cpu.op_class::total 327812214 # Class of executed instruction +system.cpu.dcache.tags.replacements 1332 # number of replacements +system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.339297 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.751548 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.751548 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3143 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 678 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2434 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.767334 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336728627 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336728627 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86231946 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86231946 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82049814 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82049814 # number of WriteReq hits +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168281760 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168281760 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168335819 # number of overall hits -system.cpu.dcache.overall_hits::total 168335819 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1605 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1605 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2862 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2862 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits +system.cpu.dcache.overall_hits::total 168337827 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 4467 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4467 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4470 # number of overall misses -system.cpu.dcache.overall_misses::total 4470 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88066000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88066000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 176802500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 176802500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 264868500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 264868500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 264868500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 264868500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86233551 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86233551 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 82052676 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 82052676 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses +system.cpu.dcache.overall_misses::total 4479 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168286227 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168286227 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168340289 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168340289 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses @@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54869.781931 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54869.781931 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61775.856045 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61775.856045 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59294.492948 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59294.492948 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59254.697987 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59254.697987 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -297,34 +297,34 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 997 # number of writebacks -system.cpu.dcache.writebacks::total 997 # number of writebacks +system.cpu.dcache.writebacks::writebacks 998 # number of writebacks +system.cpu.dcache.writebacks::total 998 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1604 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1604 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2862 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2862 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4466 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4466 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4469 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4469 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86415000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 86415000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 173940500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 173940500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260355500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 260355500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260538500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 260538500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -335,71 +335,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53874.688279 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53874.688279 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60775.856045 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60775.856045 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58297.245858 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58297.245858 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58299.060192 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58299.060192 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13798 # number of replacements -system.cpu.icache.tags.tagsinuse 1765.947853 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 348643415 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15605 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22341.776033 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13796 # number of replacements +system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1765.947853 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 163 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1522 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 697333645 # Number of tag accesses -system.cpu.icache.tags.data_accesses 697333645 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 348643415 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 348643415 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 348643415 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 348643415 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 348643415 # number of overall hits -system.cpu.icache.overall_hits::total 348643415 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15605 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15605 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15605 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15605 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15605 # number of overall misses -system.cpu.icache.overall_misses::total 15605 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 338522000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 338522000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 338522000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 338522000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 338522000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 338522000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 348659020 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 348659020 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 348659020 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 348659020 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 348659020 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 348659020 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses +system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 348644750 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 348644750 # number of overall hits +system.cpu.icache.overall_hits::total 348644750 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses +system.cpu.icache.overall_misses::total 15603 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 348660353 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 348660353 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 348660353 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21693.175264 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21693.175264 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21693.175264 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21693.175264 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21693.175264 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21693.175264 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -408,42 +408,42 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 13798 # number of writebacks -system.cpu.icache.writebacks::total 13798 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15605 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15605 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15605 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15605 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15605 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15605 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322917000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 322917000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322917000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 322917000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322917000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 322917000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 13796 # number of writebacks +system.cpu.icache.writebacks::total 13796 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20693.175264 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20693.175264 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20693.175264 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20693.175264 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20693.175264 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20693.175264 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3487.616981 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 341.600605 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.332701 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 738.683674 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy @@ -451,92 +451,92 @@ system.cpu.l2cache.tags.occ_percent::total 0.106434 # system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1233 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 228016 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 228016 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 997 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 997 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 6213 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 6213 # number of WritebackClean hits +system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12996 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 12996 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 239 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 239 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12996 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13251 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12996 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits -system.cpu.l2cache.overall_hits::total 13251 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 2846 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2846 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2609 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2609 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 238 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 238 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 12995 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 254 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12995 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 254 # number of overall hits +system.cpu.l2cache.overall_hits::total 13249 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2608 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2608 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1368 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 1368 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2609 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 4214 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 6823 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 4214 # number of overall misses -system.cpu.l2cache.overall_misses::total 6823 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 169475500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 169475500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155351500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 155351500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.demand_misses::cpu.inst 2608 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 4224 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses +system.cpu.l2cache.overall_misses::total 6832 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 170070500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 170070500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155292000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 155292000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 155351500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 251066500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 406418000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 155351500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 251066500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 406418000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 997 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 997 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 6213 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 6213 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2862 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2862 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15605 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 15605 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1607 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1607 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 15605 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4469 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 20074 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15605 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4469 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 20074 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994410 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.994410 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167190 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167190 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851276 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851276 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167190 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.942940 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.339892 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167190 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.942940 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.339892 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.664793 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.664793 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.461479 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.461479 # average ReadCleanReq miss latency +system.cpu.l2cache.demand_miss_latency::cpu.inst 155292000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 251661500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 406953500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 155292000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 251661500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 406953500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 998 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 998 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 6212 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15603 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 15603 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1606 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1606 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167147 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167147 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851806 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851806 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167147 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.943278 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.461479 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59579.140959 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59565.880111 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.461479 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59579.140959 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59565.880111 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -545,115 +545,115 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2846 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2846 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2609 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2609 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2609 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 4214 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 6823 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 4214 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 6823 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141015500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141015500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129261500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129261500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129261500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 208926500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 338188000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129261500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 208926500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 338188000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994410 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994410 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167190 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851276 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851276 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942940 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.339892 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942940 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.339892 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.664793 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.664793 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.461479 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.461479 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167147 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851806 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.461479 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49579.140959 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.880111 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.461479 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49579.140959 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.880111 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 35198 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 15220 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7664 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 17212 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 997 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13798 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 329 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2862 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2862 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15605 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1607 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45008 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10264 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 55272 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 349824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2231616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 55290 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2232000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 20074 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.386570 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.486976 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 12314 61.34% 61.34% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 7760 38.66% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 20074 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 32394000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 23407500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6703500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3977 # Transaction distribution -system.membus.trans_dist::ReadExReq 2846 # Transaction distribution -system.membus.trans_dist::ReadExResp 2846 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3977 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13646 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13646 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 436672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 436672 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3976 # Transaction distribution +system.membus.trans_dist::ReadExReq 2856 # Transaction distribution +system.membus.trans_dist::ReadExResp 2856 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3976 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6824 # Request fanout histogram +system.membus.snoop_fanout::samples 6833 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6824 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6824 # Request fanout histogram -system.membus.reqLayer0.occupancy 7272500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 6833 # Request fanout histogram +system.membus.reqLayer0.occupancy 7281500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 34115000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 34160000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 2b7c8fd88..dc097b928 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2016 19:53:43 -gem5 started Mar 15 2016 20:34:58 -gem5 executing on dinar2c11, pid 10996 +gem5 compiled Mar 16 2016 23:07:21 +gem5 started Mar 16 2016 23:41:21 +gem5 executing on dinar2c11, pid 25849 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -27,4 +27,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 767874998000 because target called exit() +Exiting @ tick 767851412000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index d2ad49fd9..659d2c639 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.767875 # Number of seconds simulated -sim_ticks 767874998000 # Number of ticks simulated -final_tick 767874998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.767851 # Number of seconds simulated +sim_ticks 767851412000 # Number of ticks simulated +final_tick 767851412000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97609 # Simulator instruction rate (inst/s) -host_op_rate 105159 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48526138 # Simulator tick rate (ticks/s) -host_mem_usage 342328 # Number of bytes of host memory used -host_seconds 15823.95 # Real time elapsed on the host +host_inst_rate 96147 # Simulator instruction rate (inst/s) +host_op_rate 103584 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47797800 # Simulator tick rate (ticks/s) +host_mem_usage 342312 # Number of bytes of host memory used +host_seconds 16064.58 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 235361472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63663872 # Number of bytes read from this memory -system.physmem.bytes_read::total 299090176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104698048 # Number of bytes written to this memory -system.physmem.bytes_written::total 104698048 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3677523 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 994748 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4673284 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1635907 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1635907 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 84430 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 306510139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 82909161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 389503730 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 84430 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 84430 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136347776 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136347776 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136347776 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 84430 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 306510139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 82909161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 525851506 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4673284 # Number of read requests accepted -system.physmem.writeReqs 1635907 # Number of write requests accepted -system.physmem.readBursts 4673284 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1635907 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 298596928 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 493248 # Total number of bytes read from write queue -system.physmem.bytesWritten 104694592 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 299090176 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104698048 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7707 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 24 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 64960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 235334976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63685504 # Number of bytes read from this memory +system.physmem.bytes_read::total 299085440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64960 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64960 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104625984 # Number of bytes written to this memory +system.physmem.bytes_written::total 104625984 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1015 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3677109 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 995086 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4673210 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1634781 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1634781 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 84600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 306485047 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 82939880 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 389509527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 84600 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 84600 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136258112 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136258112 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136258112 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 84600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 306485047 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 82939880 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 525767639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4673210 # Number of read requests accepted +system.physmem.writeReqs 1634781 # Number of write requests accepted +system.physmem.readBursts 4673210 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1634781 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 298595648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 489792 # Total number of bytes read from write queue +system.physmem.bytesWritten 104623680 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 299085440 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104625984 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7653 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 16 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 300421 # Per bank write bursts -system.physmem.perBankRdBursts::1 298937 # Per bank write bursts -system.physmem.perBankRdBursts::2 284574 # Per bank write bursts -system.physmem.perBankRdBursts::3 288248 # Per bank write bursts -system.physmem.perBankRdBursts::4 288002 # Per bank write bursts -system.physmem.perBankRdBursts::5 284734 # Per bank write bursts -system.physmem.perBankRdBursts::6 280770 # Per bank write bursts -system.physmem.perBankRdBursts::7 278050 # Per bank write bursts -system.physmem.perBankRdBursts::8 293697 # Per bank write bursts -system.physmem.perBankRdBursts::9 299275 # Per bank write bursts -system.physmem.perBankRdBursts::10 291592 # Per bank write bursts -system.physmem.perBankRdBursts::11 297756 # Per bank write bursts -system.physmem.perBankRdBursts::12 299138 # Per bank write bursts -system.physmem.perBankRdBursts::13 298570 # Per bank write bursts -system.physmem.perBankRdBursts::14 293356 # Per bank write bursts -system.physmem.perBankRdBursts::15 288457 # Per bank write bursts -system.physmem.perBankWrBursts::0 103823 # Per bank write bursts -system.physmem.perBankWrBursts::1 101786 # Per bank write bursts -system.physmem.perBankWrBursts::2 99158 # Per bank write bursts -system.physmem.perBankWrBursts::3 99952 # Per bank write bursts -system.physmem.perBankWrBursts::4 99094 # Per bank write bursts -system.physmem.perBankWrBursts::5 98779 # Per bank write bursts -system.physmem.perBankWrBursts::6 102513 # Per bank write bursts -system.physmem.perBankWrBursts::7 104359 # Per bank write bursts -system.physmem.perBankWrBursts::8 105182 # Per bank write bursts -system.physmem.perBankWrBursts::9 104512 # Per bank write bursts -system.physmem.perBankWrBursts::10 101930 # Per bank write bursts -system.physmem.perBankWrBursts::11 102694 # Per bank write bursts -system.physmem.perBankWrBursts::12 102904 # Per bank write bursts -system.physmem.perBankWrBursts::13 102694 # Per bank write bursts -system.physmem.perBankWrBursts::14 104057 # Per bank write bursts -system.physmem.perBankWrBursts::15 102416 # Per bank write bursts +system.physmem.perBankRdBursts::0 301092 # Per bank write bursts +system.physmem.perBankRdBursts::1 298585 # Per bank write bursts +system.physmem.perBankRdBursts::2 284412 # Per bank write bursts +system.physmem.perBankRdBursts::3 287553 # Per bank write bursts +system.physmem.perBankRdBursts::4 288019 # Per bank write bursts +system.physmem.perBankRdBursts::5 285340 # Per bank write bursts +system.physmem.perBankRdBursts::6 281024 # Per bank write bursts +system.physmem.perBankRdBursts::7 277791 # Per bank write bursts +system.physmem.perBankRdBursts::8 293545 # Per bank write bursts +system.physmem.perBankRdBursts::9 299289 # Per bank write bursts +system.physmem.perBankRdBursts::10 291195 # Per bank write bursts +system.physmem.perBankRdBursts::11 297241 # Per bank write bursts +system.physmem.perBankRdBursts::12 298946 # Per bank write bursts +system.physmem.perBankRdBursts::13 298565 # Per bank write bursts +system.physmem.perBankRdBursts::14 293948 # Per bank write bursts +system.physmem.perBankRdBursts::15 289012 # Per bank write bursts +system.physmem.perBankWrBursts::0 103815 # Per bank write bursts +system.physmem.perBankWrBursts::1 101663 # Per bank write bursts +system.physmem.perBankWrBursts::2 99081 # Per bank write bursts +system.physmem.perBankWrBursts::3 99729 # Per bank write bursts +system.physmem.perBankWrBursts::4 98947 # Per bank write bursts +system.physmem.perBankWrBursts::5 98825 # Per bank write bursts +system.physmem.perBankWrBursts::6 102537 # Per bank write bursts +system.physmem.perBankWrBursts::7 104314 # Per bank write bursts +system.physmem.perBankWrBursts::8 105187 # Per bank write bursts +system.physmem.perBankWrBursts::9 104412 # Per bank write bursts +system.physmem.perBankWrBursts::10 101681 # Per bank write bursts +system.physmem.perBankWrBursts::11 102588 # Per bank write bursts +system.physmem.perBankWrBursts::12 102740 # Per bank write bursts +system.physmem.perBankWrBursts::13 102708 # Per bank write bursts +system.physmem.perBankWrBursts::14 104126 # Per bank write bursts +system.physmem.perBankWrBursts::15 102392 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 767874956500 # Total gap between requests +system.physmem.totGap 767851370500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4673284 # Read request sizes (log2) +system.physmem.readPktSize::6 4673210 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1635907 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2762422 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1028983 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 325435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 231330 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 148884 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 81578 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 37725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23665 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18045 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4249 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1720 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 827 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 441 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1634781 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2763298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1028318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 325143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 231238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 149204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 81551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 37590 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23700 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18069 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4228 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1700 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 28320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 72944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 84862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 100110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 107311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 108333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 109501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 111075 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 111603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 103835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 101089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 100454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 25895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 28601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 73237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 99991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 107211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 108036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 109230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 110922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 111311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 103575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 100806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 100214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -197,116 +197,116 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4243203 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 95.043673 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.954417 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 102.715127 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3379213 79.64% 79.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 666153 15.70% 95.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 95338 2.25% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35101 0.83% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 23158 0.55% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12215 0.29% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7169 0.17% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5140 0.12% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19716 0.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4243203 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 97801 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.704328 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 99.639805 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 95408 97.55% 97.55% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1143 1.17% 98.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 693 0.71% 99.43% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 419 0.43% 99.86% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 4241219 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 95.071143 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.963204 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 102.762534 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3377855 79.64% 79.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 665363 15.69% 95.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 95455 2.25% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35191 0.83% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22820 0.54% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12430 0.29% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7284 0.17% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5212 0.12% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19609 0.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4241219 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 97672 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.767497 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 100.584321 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 95276 97.55% 97.55% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 1151 1.18% 98.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 710 0.73% 99.45% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 401 0.41% 99.86% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1279 104 0.11% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 21 0.02% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 6 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-2047 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 19 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2304-2559 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2816-3071 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-3839 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-4863 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 97801 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 97801 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.726342 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.683389 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.248647 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 68568 70.11% 70.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 2029 2.07% 72.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18244 18.65% 90.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5739 5.87% 96.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1897 1.94% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 745 0.76% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 303 0.31% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 146 0.15% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 72 0.07% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 32 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 13 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 4 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 97801 # Writes before turning the bus around for reads -system.physmem.totQLat 128464947947 # Total ticks spent queuing -system.physmem.totMemAccLat 215944516697 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23327885000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27534.63 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::4096-4351 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-4863 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 97672 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 97672 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.737089 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.693249 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.262570 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 68211 69.84% 69.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 2039 2.09% 71.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18248 18.68% 90.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5781 5.92% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 2040 2.09% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 736 0.75% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 303 0.31% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 177 0.18% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 71 0.07% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 35 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 22 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 97672 # Writes before turning the bus around for reads +system.physmem.totQLat 128403949042 # Total ticks spent queuing +system.physmem.totMemAccLat 215883142792 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23327785000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27521.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46284.63 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 388.86 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 136.34 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 389.50 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 136.35 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46271.68 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 388.87 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 136.26 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 389.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 136.26 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 4.10 # Data bus utilization in percentage system.physmem.busUtilRead 3.04 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.07 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.91 # Average write queue length when enqueuing -system.physmem.readRowHits 1710553 # Number of row buffer hits during reads -system.physmem.writeRowHits 347662 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 21.25 # Row buffer hit rate for writes -system.physmem.avgGap 121707.36 # Average gap between requests -system.physmem.pageHitRate 32.66 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15942837960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8698969125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 17968828800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5245261920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50153678640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 415022318100 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 96668804250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 609700698795 # Total energy per rank (pJ) -system.physmem_0.averagePower 794.012990 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 158294269639 # Time in different power states -system.physmem_0.memoryStateTime::REF 25640940000 # Time in different power states +system.physmem.avgWrQLen 24.90 # Average write queue length when enqueuing +system.physmem.readRowHits 1711348 # Number of row buffer hits during reads +system.physmem.writeRowHits 347723 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 21.27 # Row buffer hit rate for writes +system.physmem.avgGap 121726.77 # Average gap between requests +system.physmem.pageHitRate 32.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 15936283440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8695392750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 17969468400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5241691440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50152152960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 414929915685 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 96735845250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 609660749925 # Total energy per rank (pJ) +system.physmem_0.averagePower 793.985115 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 158402074288 # Time in different power states +system.physmem_0.memoryStateTime::REF 25640160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 583937331861 # Time in different power states +system.physmem_0.memoryStateTime::ACT 583806871462 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16135663320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8804181375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18422297400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5354961840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 50153678640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 410145276690 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 100946910750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 609962970015 # Total energy per rank (pJ) -system.physmem_1.averagePower 794.354545 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 165441923935 # Time in different power states -system.physmem_1.memoryStateTime::REF 25640940000 # Time in different power states +system.physmem_1.actEnergy 16127249040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8799590250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18421525200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5351352480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50152152960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 410152468095 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 100926587250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 609930925275 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.336977 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 165409997970 # Time in different power states +system.physmem_1.memoryStateTime::REF 25640160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 576789598565 # Time in different power states +system.physmem_1.memoryStateTime::ACT 576799157530 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 286279645 # Number of BP lookups -system.cpu.branchPred.condPredicted 223407155 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14631310 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157715633 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150347717 # Number of BTB hits +system.cpu.branchPred.lookups 286283871 # Number of BP lookups +system.cpu.branchPred.condPredicted 223409198 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14630000 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157660833 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150354422 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.328354 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16640366 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 95.365741 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16641462 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -425,128 +425,128 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1535749997 # number of cpu cycles simulated +system.cpu.numCycles 1535702825 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13928863 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067540877 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286279645 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166988083 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1507099451 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29287501 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 190 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 976 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656956376 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 928 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1535673230 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.442364 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228170 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13928194 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067545272 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286283871 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166995884 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1507053814 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29284843 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 194 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 878 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656961352 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 924 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1535625501 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.442414 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228162 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 453232887 29.51% 29.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465446694 30.31% 59.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101428513 6.60% 66.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515565136 33.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 453179554 29.51% 29.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465452437 30.31% 59.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101425758 6.60% 66.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515567752 33.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1535673230 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.186410 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.346274 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74702692 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 538196786 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849939330 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58191372 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14643050 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42203099 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 740 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037258767 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52502216 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14643050 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139798596 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 457232788 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14060 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837861639 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 86123097 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976450357 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26748217 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45311443 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 127280 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1601349 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 25060230 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985922281 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9128467759 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432961586 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 131 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1535625501 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.186419 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.346319 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74705832 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 538167437 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849914387 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58196125 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14641720 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42203366 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 738 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037249572 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52491206 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14641720 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139798655 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 457197163 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14177 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837846796 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 86126990 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976444651 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26741715 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45304447 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 126733 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1592000 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 25068959 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985917884 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128448478 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432959376 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 137 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 311023336 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 153 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 144 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111484275 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542573994 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199309930 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26884095 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29108781 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1948029821 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 211 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857521274 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13507542 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283997616 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647442130 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1535673230 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.209581 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150633 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 311018939 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 156 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 147 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111499439 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542575800 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199311764 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26984794 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29485637 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1948029914 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 213 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857440521 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13485383 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283997711 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647527066 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 43 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1535625501 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.209566 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150575 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 582693827 37.94% 37.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 326116884 21.24% 59.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378188392 24.63% 83.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219675077 14.30% 98.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28992875 1.89% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6175 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 582643896 37.94% 37.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 326148429 21.24% 59.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378192784 24.63% 83.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219661214 14.30% 98.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28973008 1.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6170 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1535673230 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1535625501 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166036820 40.98% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1982 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191468502 47.25% 88.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47685170 11.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166041601 41.02% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1966 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191453028 47.29% 88.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47322574 11.69% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138261186 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800987 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138257310 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800951 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -568,88 +568,88 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 30 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532140310 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186318740 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532072663 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186309545 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857521274 # Type of FU issued -system.cpu.iq.rate 1.209521 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405192474 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218136 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5669415557 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2232040499 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805727122 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 228 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262713615 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17816594 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857440521 # Type of FU issued +system.cpu.iq.rate 1.209505 # Inst issue rate +system.cpu.iq.fu_busy_cnt 404819169 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.217945 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5668810855 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2232040657 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805715757 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 240 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 240 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262259556 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 134 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17798811 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84267660 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66369 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13310 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24462885 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84269466 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66606 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13290 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24464719 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4528039 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4867222 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4470256 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4868274 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14643050 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25368203 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1322817 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1948030107 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14641720 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25371637 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1306573 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1948030205 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542573994 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199309930 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 149 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159427 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1161958 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13310 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7700527 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8706121 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16406648 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827850066 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516960251 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29671208 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 542575800 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199311764 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 151 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 159252 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1145955 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13290 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7700252 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8704527 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16404779 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827784428 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516894749 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29656093 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 75 # number of nop insts executed -system.cpu.iew.exec_refs 698714373 # number of memory reference insts executed -system.cpu.iew.exec_branches 229541828 # Number of branches executed -system.cpu.iew.exec_stores 181754122 # Number of stores executed -system.cpu.iew.exec_rate 1.190200 # Inst execution rate -system.cpu.iew.wb_sent 1808757098 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805727191 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169214999 # num instructions producing a value -system.cpu.iew.wb_consumers 1689608003 # num instructions consuming a value -system.cpu.iew.wb_rate 1.175795 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692004 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 258092940 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 78 # number of nop insts executed +system.cpu.iew.exec_refs 698647521 # number of memory reference insts executed +system.cpu.iew.exec_branches 229543891 # Number of branches executed +system.cpu.iew.exec_stores 181752772 # Number of stores executed +system.cpu.iew.exec_rate 1.190194 # Inst execution rate +system.cpu.iew.wb_sent 1808752237 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805715827 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169206310 # num instructions producing a value +system.cpu.iew.wb_consumers 1689633446 # num instructions consuming a value +system.cpu.iew.wb_rate 1.175824 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.691988 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 258099424 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14630610 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1496181220 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.112186 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.028021 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14629299 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1496131949 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.112223 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.027889 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 915888142 61.22% 61.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250644385 16.75% 77.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110066561 7.36% 85.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55290971 3.70% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29288855 1.96% 90.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34073264 2.28% 93.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24725039 1.65% 94.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18121984 1.21% 96.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58082019 3.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 915820639 61.21% 61.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250646763 16.75% 77.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110056209 7.36% 85.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55261288 3.69% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29350080 1.96% 90.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34099698 2.28% 93.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24719772 1.65% 94.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18148053 1.21% 96.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58029447 3.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1496181220 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1496131949 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -695,76 +695,76 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58082019 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3360223976 # The number of ROB reads -system.cpu.rob.rob_writes 3883747904 # The number of ROB writes -system.cpu.timesIdled 828 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 76767 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58029447 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3360233761 # The number of ROB reads +system.cpu.rob.rob_writes 3883762364 # The number of ROB writes +system.cpu.timesIdled 834 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 77324 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.994294 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.994294 # CPI: Total CPI of All Threads -system.cpu.ipc 1.005739 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.005739 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175836515 # number of integer regfile reads -system.cpu.int_regfile_writes 1261593461 # number of integer regfile writes +system.cpu.cpi 0.994264 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.994264 # CPI: Total CPI of All Threads +system.cpu.ipc 1.005769 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.005769 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175773439 # number of integer regfile reads +system.cpu.int_regfile_writes 1261589366 # number of integer regfile writes system.cpu.fp_regfile_reads 40 # number of floating regfile reads -system.cpu.fp_regfile_writes 51 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965846001 # number of cc regfile reads -system.cpu.cc_regfile_writes 551857157 # number of cc regfile writes -system.cpu.misc_regfile_reads 675854889 # number of misc regfile reads +system.cpu.fp_regfile_writes 52 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965635020 # number of cc regfile reads +system.cpu.cc_regfile_writes 551858996 # number of cc regfile writes +system.cpu.misc_regfile_reads 675848866 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.replacements 17003582 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.964809 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638071493 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17004094 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.524580 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 17003597 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.964807 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638080633 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17004109 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.525085 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 77932500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.964809 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.964807 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 408 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335716396 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335716396 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 469352988 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469352988 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168718360 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168718360 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335734207 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335734207 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469362265 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469362265 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168718228 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168718228 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638071348 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638071348 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638071348 # number of overall hits -system.cpu.dcache.overall_hits::total 638071348 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17416992 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17416992 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3867687 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3867687 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638080493 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638080493 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638080493 # number of overall hits +system.cpu.dcache.overall_hits::total 638080493 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17416613 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17416613 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3867819 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3867819 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21284679 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21284679 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21284681 # number of overall misses -system.cpu.dcache.overall_misses::total 21284681 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 412160487500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 412160487500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 148823410876 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 148823410876 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 21284432 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21284432 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21284434 # number of overall misses +system.cpu.dcache.overall_misses::total 21284434 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 412110560500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 412110560500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 148910053049 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 148910053049 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 196500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 196500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 560983898376 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 560983898376 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 560983898376 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 560983898376 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486769980 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486769980 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 561020613549 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 561020613549 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 561020613549 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 561020613549 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486778878 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486778878 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -773,74 +773,74 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659356027 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659356027 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659356029 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659356029 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035781 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035781 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022410 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022410 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659364925 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659364925 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659364927 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659364927 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035779 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035779 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022411 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022411 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032281 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032281 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032281 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032281 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23664.274951 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23664.274951 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38478.659435 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38478.659435 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.032280 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032280 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032280 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032280 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23661.923274 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23661.923274 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38499.747028 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38499.747028 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49125 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26356.230149 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26356.230149 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26356.227673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26356.227673 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20486404 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3408907 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 942205 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67188 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.743043 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50.736843 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26358.260984 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26358.260984 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26358.258507 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26358.258507 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20478587 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3417945 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 942442 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67202 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.729281 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50.860763 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 17003582 # number of writebacks -system.cpu.dcache.writebacks::total 17003582 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3150438 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3150438 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130143 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1130143 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 17003597 # number of writebacks +system.cpu.dcache.writebacks::total 17003597 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3150032 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3150032 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130287 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1130287 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4280581 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4280581 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4280581 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4280581 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266554 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14266554 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737544 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737544 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4280319 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4280319 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4280319 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4280319 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266581 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14266581 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737532 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737532 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17004098 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17004098 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17004099 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17004099 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331835130000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 331835130000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115624975794 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 115624975794 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 17004113 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17004113 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17004114 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17004114 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331850986000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 331850986000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115586978404 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 115586978404 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447460105794 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 447460105794 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447460173794 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 447460173794 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029309 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029309 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447437964404 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 447437964404 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447438032404 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 447438032404 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses @@ -849,393 +849,393 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23259.655415 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23259.655415 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42236.755206 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42236.755206 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23260.722804 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23260.722804 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42223.060189 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42223.060189 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26314.839270 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26314.839270 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26314.841721 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26314.841721 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26313.513937 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26313.513937 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26313.516388 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26313.516388 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 590 # number of replacements -system.cpu.icache.tags.tagsinuse 444.554720 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656954786 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1076 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 610552.775093 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 586 # number of replacements +system.cpu.icache.tags.tagsinuse 444.620453 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656959766 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1072 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 612835.602612 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 444.554720 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.868271 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.868271 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 444.620453 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.868399 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.868399 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 440 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313913824 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313913824 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 656954786 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656954786 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656954786 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656954786 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656954786 # number of overall hits -system.cpu.icache.overall_hits::total 656954786 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1588 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1588 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1588 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1588 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1588 # number of overall misses -system.cpu.icache.overall_misses::total 1588 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 98682987 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 98682987 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 98682987 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 98682987 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 98682987 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 98682987 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656956374 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656956374 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656956374 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656956374 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656956374 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656956374 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 1313923770 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313923770 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 656959766 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656959766 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656959766 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656959766 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656959766 # number of overall hits +system.cpu.icache.overall_hits::total 656959766 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1583 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1583 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1583 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1583 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1583 # number of overall misses +system.cpu.icache.overall_misses::total 1583 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 101448987 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 101448987 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 101448987 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 101448987 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 101448987 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 101448987 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656961349 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656961349 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656961349 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656961349 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656961349 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656961349 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62142.938917 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62142.938917 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62142.938917 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62142.938917 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62142.938917 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62142.938917 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 17933 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 176 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 194 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 92.438144 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 29.333333 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64086.536323 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 64086.536323 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 64086.536323 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 64086.536323 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 64086.536323 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 64086.536323 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 16918 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 173 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 189 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 89.513228 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 34.600000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 590 # number of writebacks -system.cpu.icache.writebacks::total 590 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 510 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 510 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 510 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 510 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 510 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 510 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1078 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1078 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1078 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1078 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1078 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1078 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74485990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 74485990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74485990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 74485990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74485990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 74485990 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 586 # number of writebacks +system.cpu.icache.writebacks::total 586 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 509 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 509 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 509 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 509 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 509 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 509 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1074 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1074 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1074 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1074 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1074 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1074 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74582990 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 74582990 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74582990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 74582990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74582990 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 74582990 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69096.465677 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69096.465677 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69096.465677 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69096.465677 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69096.465677 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69096.465677 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69444.124767 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69444.124767 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69444.124767 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69444.124767 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69444.124767 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69444.124767 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 11607933 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 11636199 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 19107 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 11607728 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 11635838 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 19050 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4655601 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 4705755 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16099.742972 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 22830947 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4721680 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.835344 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfRemovedFull 5 # number of prefetches dropped due to prefetch queue size +system.cpu.l2cache.prefetcher.pfSpanPage 4655842 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 4705864 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16099.842459 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 22826032 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4721788 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.834192 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 54104143500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 13103.742170 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 2.284694 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2993.716107 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.799789 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000139 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.182722 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.982650 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 804 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15121 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 13102.285184 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 2.119304 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2995.437971 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.799700 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000129 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.182827 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.982656 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 773 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15151 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 610 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 192 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 461 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2942 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4257 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5586 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1875 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.049072 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.922913 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 552235013 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 552235013 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 4829213 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 4829213 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 12153673 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 12153673 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1758045 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1758045 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 63 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 63 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11520714 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 11520714 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 63 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 13278759 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13278822 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 63 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 13278759 # number of overall hits -system.cpu.l2cache.overall_hits::total 13278822 # number of overall hits +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 599 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 172 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 469 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2950 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4343 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5551 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1838 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.047180 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.924744 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 552240776 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 552240776 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 4834377 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 4834377 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 12148517 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 12148517 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1758217 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1758217 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 57 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 57 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11520794 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 11520794 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 57 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 13279011 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13279068 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 57 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 13279011 # number of overall hits +system.cpu.l2cache.overall_hits::total 13279068 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 979533 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 979533 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1015 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1015 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2745802 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 2745802 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1015 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3725335 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3726350 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1015 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3725335 # number of overall misses -system.cpu.l2cache.overall_misses::total 3726350 # number of overall misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 979355 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 979355 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1017 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1017 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2745743 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 2745743 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1017 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3725098 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3726115 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1017 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3725098 # number of overall misses +system.cpu.l2cache.overall_misses::total 3726115 # number of overall misses system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 100500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 100500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 98972728500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 98972728500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72952500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 72952500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234172325000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 234172325000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 72952500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 333145053500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 333218006000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 72952500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 333145053500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 333218006000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 4829213 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 4829213 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 12153673 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 12153673 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 98934121000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 98934121000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 73094500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 73094500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234186702000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 234186702000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 73094500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 333120823000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 333193917500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 73094500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 333120823000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 333193917500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 4834377 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 4834377 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 12148517 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 12148517 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2737578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1078 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1078 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266516 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 14266516 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1078 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 17004094 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 17005172 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1078 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 17004094 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 17005172 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737572 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2737572 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1074 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1074 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266537 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 14266537 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1074 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 17004109 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 17005183 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1074 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 17004109 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 17005183 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.357810 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.357810 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.941558 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.941558 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.192465 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.192465 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.941558 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.219085 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.219130 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.941558 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.219085 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.219130 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.357746 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.357746 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.946927 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.946927 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.192460 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.192460 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.946927 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.219070 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.219116 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.946927 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.219070 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.219116 # miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20100 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20100 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101040.729103 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101040.729103 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 71874.384236 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 71874.384236 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85283.762267 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85283.762267 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71874.384236 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89426.871275 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 89422.090249 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71874.384236 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89426.871275 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 89422.090249 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 879 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101019.672131 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101019.672131 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 71872.664700 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 71872.664700 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85290.830934 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85290.830934 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71872.664700 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89426.056174 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 89421.265178 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71872.664700 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89426.056174 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 89421.265178 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 398 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 146.500000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1635907 # number of writebacks -system.cpu.l2cache.writebacks::total 1635907 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3910 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3910 # number of ReadExReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 1634781 # number of writebacks +system.cpu.l2cache.writebacks::total 1634781 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3953 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 3953 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45136 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45136 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45302 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45302 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 49046 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 49047 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 49255 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 49256 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 49046 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 49047 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1143496 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 1143496 # number of HardPFReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 49255 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 49256 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1144188 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1144188 # number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 975623 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 975623 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1014 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1014 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2700666 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2700666 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1014 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3676289 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3677303 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3676289 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1143496 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 4820799 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72430896209 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72430896209 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 975402 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 975402 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1016 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1016 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2700441 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2700441 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1016 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3675843 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3676859 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1016 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3675843 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1144188 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4821047 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72422793987 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72422793987 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 70500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 70500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92751563000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92751563000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 66801500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 66801500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215184233000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215184233000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66801500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307935796000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 308002597500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66801500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307935796000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72430896209 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 380433493709 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92707545500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92707545500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 66931500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 66931500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215168959000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215168959000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66931500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307876504500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 307943436000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66931500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307876504500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72422793987 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 380366229987 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356382 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356382 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.940631 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.940631 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189301 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189301 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.940631 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216200 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216246 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.940631 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216200 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356302 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356302 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.945996 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.945996 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189285 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189285 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.945996 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216174 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216220 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.945996 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216174 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.283490 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63341.626214 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63341.626214 # average HardPFReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.283505 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63296.236271 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63296.236271 # average HardPFReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14100 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14100 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95069.061512 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95069.061512 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65879.191321 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65879.191321 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79678.210116 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79678.210116 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65879.191321 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83762.673718 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83757.742427 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65879.191321 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83762.673718 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63341.626214 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78915.029170 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95045.474071 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95045.474071 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65877.460630 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65877.460630 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79679.192769 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79679.192769 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65877.460630 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83756.706829 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83751.766385 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65877.460630 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83756.706829 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63296.236271 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78897.017595 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 34009349 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004186 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21286 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2918754 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899783 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18971 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 14267592 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 6465120 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 12174959 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 5771526 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1434255 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 34009371 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004197 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21289 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2918881 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2900097 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18784 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 14267609 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 6469158 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 12169806 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 5772538 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1435459 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737578 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737578 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1078 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266516 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2744 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011789 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 51014533 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176491840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2176598464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 8841697 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 25846865 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.114483 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.320694 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 2737572 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737572 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1074 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266537 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2732 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011834 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 51014566 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176493760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2176599872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 8842787 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 25847966 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.114476 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.320662 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 22906816 88.63% 88.63% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2921078 11.30% 99.93% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 18971 0.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 22907787 88.63% 88.63% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2921395 11.30% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 18784 0.07% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 25846865 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 34008846525 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 25847966 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 34008868522 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 13536 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 13530 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1615497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1609497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25506147987 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 25506170491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3697520 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1635907 # Transaction distribution -system.membus.trans_dist::CleanEvict 3001520 # Transaction distribution +system.membus.trans_dist::ReadResp 3697667 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1634781 # Transaction distribution +system.membus.trans_dist::CleanEvict 3002759 # Transaction distribution system.membus.trans_dist::UpgradeReq 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 975763 # Transaction distribution -system.membus.trans_dist::ReadExResp 975763 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3697521 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13983999 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13983999 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403788160 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 403788160 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 975542 # Transaction distribution +system.membus.trans_dist::ReadExResp 975542 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3697668 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13983964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13983964 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403711360 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 403711360 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 9310716 # Request fanout histogram +system.membus.snoop_fanout::samples 9310755 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9310716 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 9310755 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9310716 # Request fanout histogram -system.membus.reqLayer0.occupancy 17657125833 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 9310755 # Request fanout histogram +system.membus.reqLayer0.occupancy 17653458992 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 25413031627 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 25411663187 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 96efea7df..965d23114 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 16 2016 15:38:19 -gem5 started Mar 16 2016 15:38:50 -gem5 executing on dinar2c11, pid 14357 +gem5 compiled Mar 16 2016 22:57:26 +gem5 started Mar 16 2016 22:58:08 +gem5 executing on dinar2c11, pid 24733 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index a8124019a..ed3dbc17c 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.079141 # Nu sim_ticks 79140979500 # Number of ticks simulated final_tick 79140979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48369 # Simulator instruction rate (inst/s) -host_op_rate 81071 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28984226 # Simulator tick rate (ticks/s) -host_mem_usage 336892 # Number of bytes of host memory used -host_seconds 2730.48 # Real time elapsed on the host +host_inst_rate 47467 # Simulator instruction rate (inst/s) +host_op_rate 79560 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28443866 # Simulator tick rate (ticks/s) +host_mem_usage 336904 # Number of bytes of host memory used +host_seconds 2782.36 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -231,10 +231,10 @@ system.physmem_0.actBackEnergy 2477527515 # En system.physmem_0.preBackEnergy 45310553250 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 52987315485 # Total energy per rank (pJ) system.physmem_0.averagePower 669.541483 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 75375284500 # Time in different power states +system.physmem_0.memoryStateTime::IDLE 75375284000 # Time in different power states system.physmem_0.memoryStateTime::REF 2642640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1122707500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1122708000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 3470040 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 1893375 # Energy for precharge commands per rank (pJ) @@ -250,13 +250,13 @@ system.physmem_1.memoryStateTime::REF 2642640000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 884606250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 20604097 # Number of BP lookups -system.cpu.branchPred.condPredicted 20604097 # Number of conditional branches predicted +system.cpu.branchPred.lookups 20604101 # Number of BP lookups +system.cpu.branchPred.condPredicted 20604101 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1328804 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 12707128 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12016947 # Number of BTB hits +system.cpu.branchPred.BTBHits 12016946 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.568552 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 94.568545 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1442846 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 16873 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -265,32 +265,32 @@ system.cpu.workload.num_syscalls 400 # Nu system.cpu.numCycles 158281960 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25261186 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227540228 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20604097 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13459793 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 131194120 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 25261178 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227540211 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20604101 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13459792 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 131194128 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 3196201 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 20 # Number of cycles fetch has spent waiting for tlb system.cpu.fetch.MiscStallCycles 1974 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 21216 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24267792 # Number of cache lines fetched +system.cpu.fetch.CacheLines 24267790 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 266999 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 158076676 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.380152 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.324971 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.324972 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95737539 60.56% 60.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95737541 60.56% 60.56% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 4758449 3.01% 63.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3804663 2.41% 65.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3804662 2.41% 65.98% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 4365114 2.76% 68.74% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 4234763 2.68% 71.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4816061 3.05% 74.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4706874 2.98% 77.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4816060 3.05% 74.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4706873 2.98% 77.45% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 3702906 2.34% 79.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31950307 20.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31950308 20.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) @@ -298,61 +298,61 @@ system.cpu.fetch.rateDist::total 158076676 # Nu system.cpu.fetch.branchRate 0.130173 # Number of branch fetches per cycle system.cpu.fetch.rate 1.437563 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 15410588 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96165479 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 23286259 # Number of cycles decode is running +system.cpu.decode.BlockedCycles 96165480 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 23286258 # Number of cycles decode is running system.cpu.decode.UnblockCycles 21616250 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1598100 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336629364 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 336629357 # Number of instructions handled by decode system.cpu.rename.SquashCycles 1598100 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 23294905 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 31785654 # Number of cycles rename is blocking +system.cpu.rename.IdleCycles 23294906 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 31785653 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 30420 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 36005072 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 65362525 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 328266719 # Number of instructions processed by rename +system.cpu.rename.RunCycles 36005070 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 65362527 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 328266704 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 1575 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 57713162 # Number of times rename has blocked due to IQ full +system.cpu.rename.IQFullEvents 57713164 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 7745606 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 167786 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 380441368 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 910027762 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 600617825 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 380441390 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 910027714 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 600617838 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4182134 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 121011918 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 121011940 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 1942 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 1920 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 120996232 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 82787391 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 29790688 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 59618216 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 20385329 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 317847109 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 120996238 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 82787388 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 29790681 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59618218 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 20385333 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 317847098 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 5129 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 259397692 # Number of instructions issued +system.cpu.iq.iqInstsIssued 259397684 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 74444 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 96488854 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 197170724 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 96488843 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 197170698 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 3884 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 158076676 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.640961 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.524821 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40037944 25.33% 25.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 47502917 30.05% 55.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40037945 25.33% 25.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 47502914 30.05% 55.38% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 33077309 20.92% 76.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17993681 11.38% 87.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10964078 6.94% 94.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4766946 3.02% 97.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2459939 1.56% 99.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 882458 0.56% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17993682 11.38% 87.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10964082 6.94% 94.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4766949 3.02% 97.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2459936 1.56% 99.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 882455 0.56% 99.75% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 391404 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 158076676 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 232299 7.31% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 232294 7.31% 7.31% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 7.31% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 7.31% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.31% # attempts to use FU when none available @@ -386,7 +386,7 @@ system.cpu.iq.fu_full::MemWrite 383461 12.07% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1212757 0.47% 0.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 161810982 62.38% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 161810976 62.38% 62.85% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 789695 0.30% 63.15% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 7037932 2.71% 65.86% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 1186383 0.46% 66.32% # Type of FU issued @@ -415,40 +415,40 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.32% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 64896242 25.02% 91.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22463701 8.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 64896241 25.02% 91.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22463700 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 259397692 # Type of FU issued +system.cpu.iq.FU_type_0::total 259397684 # Type of FU issued system.cpu.iq.rate 1.638833 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3176512 # FU busy when requested +system.cpu.iq.fu_busy_cnt 3176507 # FU busy when requested system.cpu.iq.fu_busy_rate 0.012246 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 675268347 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 410944123 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 253662320 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 675268326 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 410944101 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 253662317 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4854669 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 3693735 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2339703 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 258916836 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 258916823 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2444611 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18724074 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 18724072 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26137804 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 26137801 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 13130 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 303242 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9274971 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 9274964 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49888 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 49887 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1598100 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12496396 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 12496395 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 489060 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 317852238 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 317852227 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 92568 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 82787391 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 29790688 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 82787388 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 29790681 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 2962 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 383739 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 63074 # Number of times the LSQ has become full, causing a stall @@ -456,41 +456,41 @@ system.cpu.iew.memOrderViolationEvents 303242 # Nu system.cpu.iew.predictedTakenIncorrect 551670 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 826736 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1378406 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 257339863 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64084690 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2057829 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 257339859 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64084689 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2057825 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 86369702 # number of memory reference insts executed +system.cpu.iew.exec_refs 86369700 # number of memory reference insts executed system.cpu.iew.exec_branches 14330688 # Number of branches executed -system.cpu.iew.exec_stores 22285012 # Number of stores executed +system.cpu.iew.exec_stores 22285011 # Number of stores executed system.cpu.iew.exec_rate 1.625832 # Inst execution rate -system.cpu.iew.wb_sent 256690837 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 256002023 # cumulative count of insts written-back -system.cpu.iew.wb_producers 204396158 # num instructions producing a value -system.cpu.iew.wb_consumers 369708068 # num instructions consuming a value +system.cpu.iew.wb_sent 256690834 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 256002020 # cumulative count of insts written-back +system.cpu.iew.wb_producers 204396152 # num instructions producing a value +system.cpu.iew.wb_consumers 369708063 # num instructions consuming a value system.cpu.iew.wb_rate 1.617380 # insts written-back per cycle system.cpu.iew.wb_fanout 0.552858 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 96496531 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 96496520 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1330625 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 144920748 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 144920750 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.527479 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.956907 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 45508636 31.40% 31.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57312376 39.55% 70.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14158342 9.77% 80.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11991162 8.27% 88.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4086517 2.82% 91.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2858053 1.97% 93.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 45508635 31.40% 31.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57312379 39.55% 70.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14158343 9.77% 80.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11991163 8.27% 88.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4086516 2.82% 91.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2858052 1.97% 93.79% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 923800 0.64% 94.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1073191 0.74% 95.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7008671 4.84% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1073190 0.74% 95.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7008672 4.84% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 144920748 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 144920750 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -536,9 +536,9 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 7008671 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 455771992 # The number of ROB reads -system.cpu.rob.rob_writes 648913303 # The number of ROB writes +system.cpu.commit.bw_lim_events 7008672 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 455771982 # The number of ROB reads +system.cpu.rob.rob_writes 648913279 # The number of ROB writes system.cpu.timesIdled 2665 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 205284 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated @@ -547,19 +547,19 @@ system.cpu.cpi 1.198459 # CP system.cpu.cpi_total 1.198459 # CPI: Total CPI of All Threads system.cpu.ipc 0.834405 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.834405 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 448575238 # number of integer regfile reads +system.cpu.int_regfile_reads 448575240 # number of integer regfile reads system.cpu.int_regfile_writes 232602901 # number of integer regfile writes system.cpu.fp_regfile_reads 3212636 # number of floating regfile reads system.cpu.fp_regfile_writes 1997796 # number of floating regfile writes -system.cpu.cc_regfile_reads 102540240 # number of cc regfile reads -system.cpu.cc_regfile_writes 59516414 # number of cc regfile writes -system.cpu.misc_regfile_reads 132474845 # number of misc regfile reads +system.cpu.cc_regfile_reads 102540235 # number of cc regfile reads +system.cpu.cc_regfile_writes 59516419 # number of cc regfile writes +system.cpu.misc_regfile_reads 132474842 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes system.cpu.dcache.tags.replacements 51 # number of replacements system.cpu.dcache.tags.tagsinuse 1429.115986 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 65747317 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 65747319 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1995 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32956.048622 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32956.049624 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 1429.115986 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.348905 # Average percentage of cache occupancy @@ -571,40 +571,40 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 498 system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1394 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.474609 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 131501473 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 131501473 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 45233028 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45233028 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513911 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513911 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 65746939 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 65746939 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 65746939 # number of overall hits -system.cpu.dcache.overall_hits::total 65746939 # number of overall hits +system.cpu.dcache.tags.tag_accesses 131501477 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 131501477 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 45233030 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45233030 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513912 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513912 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 65746942 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 65746942 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 65746942 # number of overall hits +system.cpu.dcache.overall_hits::total 65746942 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 980 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 980 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1820 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1820 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2800 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2800 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2800 # number of overall misses -system.cpu.dcache.overall_misses::total 2800 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 65148000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65148000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 128547000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 128547000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 193695000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 193695000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 193695000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 193695000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45234008 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45234008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 1819 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1819 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2799 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2799 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2799 # number of overall misses +system.cpu.dcache.overall_misses::total 2799 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65149000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65149000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 128515000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 128515000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 193664000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 193664000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 193664000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 193664000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45234010 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45234010 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 65749739 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 65749739 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 65749739 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 65749739 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 65749741 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 65749741 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 65749741 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 65749741 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses @@ -613,14 +613,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66477.551020 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66477.551020 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70630.219780 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70630.219780 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69176.785714 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69176.785714 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69176.785714 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69176.785714 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66478.571429 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66478.571429 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70651.456844 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70651.456844 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69190.425152 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69190.425152 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69190.425152 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69190.425152 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 656 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 70 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked @@ -641,20 +641,20 @@ system.cpu.dcache.overall_mshr_hits::cpu.data 528 system.cpu.dcache.overall_mshr_hits::total 528 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 454 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 454 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1818 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1818 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2272 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2272 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2272 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2272 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36063000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36063000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126583000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 126583000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162646000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 162646000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 162646000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 162646000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1817 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1817 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2271 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2271 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2271 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2271 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36063500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36063500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126552000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 126552000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162615500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 162615500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 162615500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 162615500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -663,24 +663,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79433.920705 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79433.920705 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69627.612761 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69627.612761 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71587.147887 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71587.147887 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71587.147887 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71587.147887 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79435.022026 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79435.022026 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69648.871767 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69648.871767 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71605.239982 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71605.239982 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71605.239982 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71605.239982 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 5017 # number of replacements -system.cpu.icache.tags.tagsinuse 1636.801929 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 24258361 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1636.805094 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24258360 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6993 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3468.949092 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3468.948949 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1636.801929 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.799220 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.799220 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1636.805094 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.799221 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.799221 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1976 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id @@ -688,44 +688,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 869 system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 788 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.964844 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 48542851 # Number of tag accesses -system.cpu.icache.tags.data_accesses 48542851 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 24258362 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24258362 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24258362 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24258362 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24258362 # number of overall hits -system.cpu.icache.overall_hits::total 24258362 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9429 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9429 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9429 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9429 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9429 # number of overall misses -system.cpu.icache.overall_misses::total 9429 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 409019999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 409019999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 409019999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 409019999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 409019999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 409019999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24267791 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24267791 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24267791 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24267791 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24267791 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24267791 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000389 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000389 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000389 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000389 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000389 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000389 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43378.937215 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43378.937215 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43378.937215 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43378.937215 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43378.937215 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43378.937215 # average overall miss latency +system.cpu.icache.tags.tag_accesses 48542846 # Number of tag accesses +system.cpu.icache.tags.data_accesses 48542846 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 24258361 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24258361 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24258361 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24258361 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24258361 # number of overall hits +system.cpu.icache.overall_hits::total 24258361 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9428 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9428 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9428 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9428 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9428 # number of overall misses +system.cpu.icache.overall_misses::total 9428 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 409015499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 409015499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 409015499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 409015499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 409015499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 409015499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24267789 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24267789 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24267789 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24267789 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24267789 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24267789 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000388 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000388 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000388 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000388 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000388 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000388 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43383.060989 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43383.060989 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43383.060989 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43383.060989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43383.060989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43383.060989 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 793 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked @@ -742,30 +742,30 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 2159 system.cpu.icache.demand_mshr_hits::total 2159 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 2159 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 2159 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7270 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7270 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7270 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7270 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7270 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7270 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 311109999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 311109999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 311109999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 311109999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 311109999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 311109999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7269 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7269 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7269 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7269 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7269 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7269 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 311106499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 311106499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 311106499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 311106499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 311106499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 311106499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000300 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000300 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000300 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42793.672490 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42793.672490 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42793.672490 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 42793.672490 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42793.672490 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 42793.672490 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42799.078140 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42799.078140 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42799.078140 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 42799.078140 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42799.078140 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 42799.078140 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 2581.252539 # Cycle average of tags in use @@ -787,8 +787,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 999 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 41 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2611 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118378 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 119261 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 119261 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 119253 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 119253 # Number of data accesses system.cpu.l2cache.WritebackDirty_hits::writebacks 10 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 10 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 4917 # number of WritebackClean hits @@ -807,8 +807,8 @@ system.cpu.l2cache.demand_hits::total 3572 # nu system.cpu.l2cache.overall_hits::cpu.inst 3531 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 41 # number of overall hits system.cpu.l2cache.overall_hits::total 3572 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 276 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 276 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 275 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 275 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 1535 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1535 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3460 # number of ReadCleanReq misses @@ -823,22 +823,22 @@ system.cpu.l2cache.overall_misses::cpu.data 1954 # system.cpu.l2cache.overall_misses::total 5414 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 115784500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 115784500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262406500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 262406500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34977000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 34977000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 262406500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 150761500 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262406000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 262406000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34977500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 34977500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 262406000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 150762000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 413168000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 262406500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 150761500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 262406000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 150762000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 413168000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 10 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 10 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 4917 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 4917 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 277 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 277 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 276 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 276 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1541 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1541 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6991 # number of ReadCleanReq accesses(hits+misses) @@ -851,8 +851,8 @@ system.cpu.l2cache.demand_accesses::total 8986 # n system.cpu.l2cache.overall_accesses::cpu.inst 6991 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1995 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 8986 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.996390 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.996390 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.996377 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.996377 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996106 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.996106 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.494922 # miss rate for ReadCleanReq accesses @@ -867,15 +867,15 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.979449 system.cpu.l2cache.overall_miss_rate::total 0.602493 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75429.641694 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75429.641694 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75840.028902 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75840.028902 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83477.326969 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83477.326969 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75840.028902 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77155.322416 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75839.884393 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75839.884393 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83478.520286 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83478.520286 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75839.884393 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77155.578301 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 76314.739564 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75840.028902 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77155.322416 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75839.884393 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77155.578301 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 76314.739564 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -885,8 +885,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 276 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 276 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 275 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 275 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1535 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1535 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3460 # number of ReadCleanReq MSHR misses @@ -899,22 +899,22 @@ system.cpu.l2cache.demand_mshr_misses::total 5414 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3460 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1954 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5414 # number of overall MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5237000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5237000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5217500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5217500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100434500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100434500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 227816500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 227816500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30787000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30787000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 227816500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131221500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 227816000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 227816000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30787500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30787500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 227816000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131222000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 359038000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 227816500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131221500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 227816000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131222000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 359038000 # number of overall MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.996390 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.996390 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.996377 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.996377 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996106 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996106 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.494922 # mshr miss rate for ReadCleanReq accesses @@ -927,84 +927,84 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.602493 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.494922 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.979449 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.602493 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18974.637681 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18974.637681 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18972.727273 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18972.727273 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65429.641694 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65429.641694 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65842.919075 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65842.919075 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73477.326969 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73477.326969 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65842.919075 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67155.322416 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65842.774566 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65842.774566 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73478.520286 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73478.520286 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65842.774566 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67155.578301 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66316.586627 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65842.919075 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67155.322416 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65842.774566 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67155.578301 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66316.586627 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 14610 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5368 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 377 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 14608 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5367 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 376 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7723 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7722 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 10 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 5017 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 41 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 276 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 276 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1541 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7270 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7269 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 454 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19277 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4595 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23872 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4593 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23869 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 768448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128320 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 896768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 279 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 9542 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.070845 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.256579 # Request fanout histogram +system.cpu.toL2Bus.snoops 278 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 9540 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.070650 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.256253 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 8866 92.92% 92.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 676 7.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 8866 92.94% 92.94% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 674 7.06% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9542 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12332000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 9540 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12331000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10903500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10902000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3131998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3131498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadResp 3878 # Transaction distribution -system.membus.trans_dist::UpgradeReq 276 # Transaction distribution +system.membus.trans_dist::UpgradeReq 275 # Transaction distribution system.membus.trans_dist::ReadExReq 1535 # Transaction distribution system.membus.trans_dist::ReadExResp 1535 # Transaction distribution system.membus.trans_dist::ReadSharedReq 3878 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11102 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11102 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11101 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11101 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11101 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 346432 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::total 346432 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 346432 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5689 # Request fanout histogram +system.membus.snoop_fanout::samples 5688 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5689 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5688 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5689 # Request fanout histogram -system.membus.reqLayer0.occupancy 6955500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5688 # Request fanout histogram +system.membus.reqLayer0.occupancy 6954000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 28681250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) |